Thin-film transistor and method for manufacturing thin-film transistor

The present invention is a thin film transistor suitable for a pixel display switching element of an active matrix type display panel.<u style="single">And its manufacturing method</u>Regarding.

[0002] FIG. 7 is a cross-sectional view showing the structure of a bottom gate type thin film transistor. A gate electrode 2 made of a refractory metal such as tungsten or chromium is arranged on the surface of the insulating transparent substrate 1. The gate electrode 2 has a tapered shape in which both ends are widened on the transparent substrate 1 side. A silicon oxide film 4 is laminated on the transparent substrate 1 on which the gate electrode 2 is arranged via the silicon nitride film 3. The silicon nitride film 3 prevents impurities contained in the transparent substrate 1 from infiltrating into the active region described later, and the silicon oxide film 4 acts as a gate insulating film. A polycrystalline silicon film 5 is laminated on the silicon oxide film 4 across the gate electrode 2. This polycrystalline silicon film 5 serves as an active region of the thin film transistor.

[0003] A stopper 6 made of an insulating material such as silicon oxide is arranged on the polycrystalline silicon film 5. The polycrystalline silicon film 5 covered with the stopper 6 becomes the channel region 5c, and the other polycrystalline silicon film 5 becomes the source region 5s and the drain region 5d. A silicon oxide film 7 and a silicon nitride film 8 are laminated on the polycrystalline silicon film 5 on which the stopper 6 is formed. The silicon oxide film 7 and the silicon nitride film 8 serve as an interlayer insulating film that protects the polycrystalline silicon film 5 including the source region 5s and the drain region 5d.

[0004] Contact holes 9 are formed at predetermined positions of the silicon oxide film 7 and the silicon nitride film 8 on the source region 5s and the drain region 5d. A source electrode 10s and a drain electrode 10d connected to the source region 5s and the drain region 5d are arranged in the contact hole 9 portion. An acrylic resin layer 11 transparent to visible light is laminated on the silicon nitride film 8 on which the source electrode 10s and the drain electrode 10d are arranged. The acrylic resin layer 11 fills the irregularities generated by the gate electrode 2 and the stopper 6 to flatten the surface.

[0005] A contact hole 12 is formed in the acrylic resin layer 11 on the source electrode 10s. Then, the transparent electrode 13 made of ITO (indium tin oxide) or the like connected to the source electrode 10s through the contact hole 12 is arranged so as to spread on the acrylic resin layer 11. The transparent electrode 13 constitutes a display electrode of the liquid crystal display panel.

[0006] A plurality of the above thin film transistors are arranged in a matrix on the transparent substrate 1 together with the display electrode, and in response to the scanning control signal applied to the gate electrode 2, the image information supplied to the drain electrode 10d is displayed on the display electrode. Is applied to each. By the way, the polycrystalline silicon film 5 is formed to have a sufficiently large crystal grain size so as to function as an active region of the thin film transistor. A laser annealing method using an excimer laser is known as a method for forming a large crystal grain size of the polycrystalline silicon film 5. In this laser annealing method, amorphous silicon is laminated on the silicon oxide film 4 to be the gate insulating film, and first, hydrogen contained in the amorphous silicon film is discharged to the outside of the film by low-temperature heat treatment, and then the film is discharged. The silicon is crystallized by irradiating the silicon with an excima laser to melt the silicon once. By using such a laser annealing method, since the portion of the transparent substrate 1 that becomes hot is local, a glass substrate having a low melting point can be adopted as the transparent substrate 1.

[0007] [Problem to be Solved by the Invention] Since the polycrystalline silicon film 5 crystallized by the laser annealing method has many crystal defects, electrons moving in the film are easily captured and used as an active region of a transistor. Is not preferable. Therefore, an insulating film containing a large amount of hydrogen ions is formed on the polycrystalline silicon film 5 once formed, and the crystal defects are filled with hydrogen ions by heat treatment together with the insulating film.

[0008] As an insulating film containing a large amount of hydrogen ions, a silicon nitride film is known. The hydrogen ion concentration of the silicon nitride film formed by the plasma CVD method is usually about 10 ^ 22 / cm ^ 3 (^ represents the power), and the hydrogen ion of the silicon oxide film formed by the same plasma CVD method. It is about two orders of magnitude higher than the concentration (10 ^ 20 / cm ^ 3). When such a silicon nitride film is formed directly on the active region, the transistor characteristics are deteriorated. Therefore, as shown in FIG. 7, a silicon oxide film is formed between the active region and the silicon nitride film.

[0009] However, in the interlayer insulating film in which the silicon nitride film 8 is laminated on the silicon oxide film 7, when the contact hole 9 is formed by etching with a hydrofluoric acid-based etching solution, the contact hole is formed due to the difference in etching rate. There is a problem that 9 becomes wider on the bottom side. That is, since the etching rate of the silicon oxide film 7 with respect to the phosphoric acid-based etching solution is faster than that of the silicon nitride film 8, the contact hole 9 has the silicon nitride film 8 at the silicon oxide film 7 portion as shown in FIG. It will be wider than the part. Therefore, the source electrode 10s or the drain electrode 10d formed in the contact hole 9 portion is likely to be disconnected, resulting in poor contact.

[0010] Therefore, an object of the present invention is to improve the shape of the contact hole formed in the interlayer insulating film.

[Means for Solving Problems] In the method for manufacturing a thin film film of the present invention, a first step of laminating a semiconductor film on one main surface of a substrate and a gate insulating film made of a first silicon oxide film in contact with the semiconductor film are formed on the semiconductor film. A second step of laminating and forming a gate electrode on the gate insulating film, a third step of covering the gate electrode on the gate insulating film and laminating an interlayer insulating film, the gate insulating film and the said A fourth step of forming a contact hole reaching the semiconductor film by etching the interlayer insulating film with a hydrofluoric acid-based etching solution and penetrating the interlayer insulating film, and a first step of forming an electrode connected to the semiconductor film through the contact hole. The third step comprises a silicon nitride film and a second and third silicon oxide films on the first silicon oxide film laminated in contact with the semiconductor film. The interlayer insulating film is formed by sequentially laminating a second silicon oxide film, a silicon nitride film, and a third silicon oxide film, and in the fourth step, the gate insulating film and the interlayer insulating film are insulated from each other. The silicon nitride film is continuously isotropically etched from the surface of the film until it reaches the semiconductor film to form a tapered contact hole in which the silicon nitride film expands toward the upper layer side, and the second and third films are formed. The silicon oxide film is made of a silicon oxide film having a faster etching rate with respect to a phosphoric acid-based etching solution than the silicon nitride film, and the size of the contact hole formed by etching with the phosphoric acid-based etching solution. Is characterized in that the difference between the second silicon oxide film portion and the silicon nitride film portion is reduced.

[0014] Further, the first step of forming the gate electrode on one main surface of the substrate and the second step of covering the gate electrode on the substrate and laminating the gate insulating film and laminating the semiconductor film on the gate insulating film. And the third step of laminating the interlayer insulating film on the semiconductor film, and the interlayer insulating film is etched with a phosphoric acid-based etching solution and penetrated to form a contact hole reaching the semiconductor film. It has a fourth step and a fifth step of forming an electrode connected to the semiconductor film through the contact hole, and the third step comprises a silicon nitride film and the silicon nitride film on the semiconductor film. The second and third silicon oxide films having a faster etching rate with respect to the phosphoric acid-based etching solution than the silicon nitride film were laminated in this order in the order of the second silicon oxide film, the silicon nitride film, and the third silicon oxide film. The second silicon oxide film that forms the interlayer insulating film and constitutes the interlayer insulating film is laminated in contact with the semiconductor film, and in the fourth step, the interlayer insulating film is formed from the surface. The silicon nitride film is continuously and isotropically etched until it reaches the semiconductor film to form a contact hole having a tapered shape in which the silicon nitride film expands toward the upper layer side, and by etching with the hydrofluoric acid-based etching solution. The size of the formed contact hole is characterized in that the difference between the second silicon oxide film portion and the silicon nitride film portion is reduced.

[0015] According to the present invention, when etching to form a contact hole, since the uppermost layer has a silicon oxide film having a faster etching rate than the silicon nitride film, etching from the upper layer side becomes dominant. Therefore, the shape of the silicon nitride film itself becomes a tapered shape that expands toward the upper layer side, and a contact hole with good step coverage is formed in electrode formation.

[Embodiment of the Invention] FIG. 1 is a cross-sectional view showing a first embodiment of the thin film transistor of the present invention. In this figure, the transparent substrate 21, the gate electrode 22, the silicon nitride film 23, the silicon oxide film 24, and the polycrystalline silicon film 25 are the transparent substrate 1, the gate electrode 2, the silicon nitride film 3, and silicon oxide of the thin film transistor shown in FIG. It is the same as the film 4 and the polycrystalline silicon film 5.

A gate electrode 22 is arranged on the surface of the transparent substrate 21, and a silicon nitride film 23 and a silicon oxide film 24 as a gate insulating film are laminated so as to cover the gate electrode 22. Then, the polycrystalline silicon film 25 as a semiconductor film serving as an active region is laminated on the silicon oxide film 24. A stopper 26 made of silicon oxide is arranged on the polycrystalline silicon film 25. The polycrystalline silicon film 25 covered with the stopper 26 becomes the channel region 25c, and the other polycrystalline silicon film 25 becomes the source region 25s and the drain region 25d. On the polycrystalline silicon film 25 on which the stopper 26 is formed, the silicon oxide film 27, which has little adverse effect even if it comes into contact with the polycrystalline silicon film 25, is laminated. Then, a silicon nitride film 28, which contains a larger amount of hydrogen ions than the silicon oxide film 27 and is a main source of hydrogen ions, is laminated on the silicon oxide film 27. Further, the silicon oxide film 29 is laminated on the silicon nitride film 28. The silicon oxide film 27, the silicon nitride film 28, and the silicon oxide film 29 form an interlayer insulating film that protects the polycrystalline silicon film 25.

The interlayer insulating film composed of the three layers of the silicon oxide film 27, the silicon nitride film 28, and the silicon oxide film 29 is provided with a contact hole 30 reaching the polycrystalline silicon film 25. Then, the source electrode 31s and the drain electrode 31d connected to the source region 25s and the drain region 25d are arranged in the contact hole 30 portion. Further, an acrylic resin layer 32 that covers the source electrode 31s and the drain electrode 31d to flatten the surface is laminated on the interlayer insulating film. Further, the acrylic resin layer 32 is provided with a contact hole 33 reaching the source electrode 31s, and the transparent electrode 34 connected to the source electrode 31s is arranged so as to spread on the acrylic resin layer 32. The source electrode 31s, the drain electrode 31d, and the transparent electrode 34 are the same as the source electrode 10s, the drain electrode 10d, and the transparent electrode 13 of the thin film transistor shown in FIG.

[0019] In the above thin film transistor, the interlayer insulating film is formed of the silicon nitride film 28 and the silicon oxide films 27 and 29 having a higher etching rate with respect to the phosphoric acid-based etching solution than the silicon nitride film 28. Therefore, when the contact hole 30 is formed by etching with a hydrofluoric acid-based etching solution, the size of the contact hole 30 is the same as that of the silicon oxide film 27 portion and the silicon nitride film 28 portion, as shown in FIG. The difference becomes smaller. Therefore, it is possible to prevent contact failure of the source electrode 31s or the drain electrode 31d formed through the contact hole 30.

[0020] FIG. 3 is a cross-sectional view showing a second embodiment of the thin film transistor of the present invention. In this figure, the top gate type is shown. A silicon nitride film 42 and a silicon oxide film 43 are laminated on the surface of the insulating transparent substrate 41. The silicon nitride film 42 prevents precipitation of impurity ions such as sodium contained in the transparent substrate 41, and the silicon oxide film 43 enables lamination of the polycrystalline silicon film 44 which is an active region. A polycrystalline silicon film 44 as a semiconductor film serving as an active region of a thin film transistor is laminated on a predetermined region on the silicon oxide film 43.

[0021] A silicon oxide film 45 serving as a gate insulating film is laminated on the silicon oxide film 43 on which the polycrystalline silicon film 44 is laminated. Then, a gate electrode 46 made of a refractory metal such as tungsten or chromium is arranged on the silicon oxide film 45. The gate electrodes 46 are arranged so as to intersect in the extending direction of the polycrystalline silicon film 44. The polycrystalline silicon film 44 covered by the gate electrode 46 serves as a channel region 44c, and the other polycrystalline silicon film 44 serves as a source region 44s and a drain region 44d.

[0022] The silicon oxide film 47 is laminated on the silicon oxide film 45 on which the gate electrode 46 is arranged. Then, the silicon nitride film 48 is laminated on the silicon oxide film 47, and the silicon oxide film 49 is further laminated on the silicon nitride film 48. The silicon oxide film 47, the silicon nitride film 48, and the silicon oxide film 49 form an interlayer insulating film that protects the polycrystalline silicon film 44.

The interlayer insulating film is provided with a contact hole 50 reaching the polycrystalline silicon film 44, and a source electrode 51s and a drain electrode 51d connected to the source region 45s and the drain region 45d are arranged. Then, an acrylic resin layer 52 that covers the source electrode 51s and the drain electrode 51d to flatten the surface is laminated on the interlayer insulating film. Further, the acrylic resin layer 52 is provided with a contact hole 53 reaching the source electrode 51s, and the transparent electrode 54 connected to the source electrode 51s is arranged so as to spread over the acrylic resin layer 52. The source electrode 51s, the drain electrode 51d, and the transparent electrode 54 are the same as in the case of the bottom gate type.

[0024] Even in the above thin film transistor, when the contact hole 50 is formed by etching with a hydrofluoric acid-based etching solution, the size of the contact hole 50 is oxidized as in the case of the top gate type (FIG. 2). The difference between the 47 parts of the silicon film and the 48 parts of the silicon nitride film is small. 4 (a) to 4 (c) and 5 (d) to 5 (f) are cross-sectional views for each process for explaining the method for manufacturing the thin film transistor according to the first embodiment. In these figures, the same parts as in FIG. 1 are shown. (a) First step A refractory metal such as chromium or molybdenum is laminated on an insulating transparent substrate 21 to a film thickness of 1000 Å by a sputtering method to form a refractory metal film 35. The refractory metal film 35 is patterned into a predetermined shape to form a gate electrode 22. In this patterning process, both ends of the gate electrode 22 are formed into a tapered shape so as to be wider on the transparent substrate 21 side by taper etching. (b) Second step Silicon nitride is laminated on the transparent substrate 21 to a film thickness of 500 Å or more by the plasma CVD method, and silicon oxide is continuously laminated to a film thickness of 1300 Å or more. As a result, the silicon nitride film 23 that prevents the precipitation of impurity ions from the transparent substrate 21 and the silicon oxide film 24 that serves as the gate insulating film are formed. Then, silicon is laminated on the silicon oxide film 23 to a film thickness of 400 Å by the plasma CVD method to form an amorphous silicon film 25'. Then, the hydrogen in the silicon film 25'is discharged to the outside of the film by heat treatment at about 430 ° C for 1 hour or more to reduce the hydrogen concentration to 1% or less, and then the excimer laser is applied to the silicon film 25'. And heat until the amorphous silicon melts. As a result, silicon crystallizes and becomes a polycrystalline silicon film 25. (c) Third step Silicon oxide is laminated on the polycrystalline silicon film 25 to a film thickness of 1000 Å to form the silicon oxide film 35. Then, the silicon oxide film 35 is patterned according to the shape of the gate electrode 22 to form a stopper 26 that overlaps the gate electrode 22. In the formation of the stopper 26, the mask displacement can be eliminated by covering the silicon oxide film 35 to form a resist layer and exposing the resist layer from the transparent substrate side with the gate electrode 22 as a mask. (d) Fourth step P-type or N-type ions corresponding to the type of transistor to be formed are injected into the polycrystalline silicon film 25 on which the stopper 26 is formed. That is, when forming a P-channel type transistor, P-type ions such as boron are injected, and when forming an N-channel type transistor, N-type ions such as phosphorus are injected. By this injection, a region exhibiting P-type or N-type conductivity is formed on the polycrystalline silicon film 25 except for the region covered by the stopper 26. These regions serve as a source region 25s and a drain region 25d on both sides of the stopper 26. (e) Step 5 The polycrystalline silicon film 25 in which the source region 25s and the drain region 25d are formed is irradiated with an excimer laser and heated to the extent that the silicon does not melt. As a result, the impurity ions in the source region 25s and the drain region 25d are activated. Then, the polycrystalline silicon film 25 is patterned in an island shape while leaving a predetermined width on both sides of the stopper 26 (gate electrode 22), and the transistors are separated and made independent. (f) Step 6 Silicon oxide is laminated on the polycrystalline silicon film 25 to a film thickness of 1000 Å by the plasma CVD method, and silicon nitride is continuously laminated to a film thickness of 3000 Å and silicon oxide to a film thickness of 500 Å. To do. As a result, an interlayer insulating film composed of three layers, a silicon oxide film 27, a silicon nitride film 28, and a silicon oxide layer 29, is formed. In the process, the mask displacement can be eliminated by covering the silicon oxide film 35 to form a resist layer and exposing the resist layer from the transparent substrate side using the gate electrode 22 as a mask. (d) Fourth step P-type or N-type ions corresponding to the type of transistor to be formed are injected into the polycrystalline silicon film 25 on which the stopper 26 is formed. That is, when forming a P-channel type transistor, P-type ions such as boron are injected, and when forming an N-channel type transistor, N-type ions such as phosphorus are injected. By this injection, a region exhibiting P-type or N-type conductivity is formed on the polycrystalline silicon film 25 except for the region covered by the stopper 26. These regions serve as a source region 25s and a drain region 25d on both sides of the stopper 26. (e) Step 5 The polycrystalline silicon film 25 in which the source region 25s and the drain region 25d are formed is irradiated with an excimer laser and heated to the extent that the silicon does not melt. As a result, the impurity ions in the source region 25s and the drain region 25d are activated. Then, the polycrystalline silicon film 25 is patterned in an island shape while leaving a predetermined width on both sides of the stopper 26 (gate electrode 22), and the transistors are separated and made independent. (f) Step 6 Silicon oxide is laminated on the polycrystalline silicon film 25 to a film thickness of 1000 Å by the plasma CVD method, and silicon nitride is continuously laminated to a film thickness of 3000 Å and silicon oxide to a film thickness of 500 Å. To do. As a result, an interlayer insulating film composed of three layers, a silicon oxide film 27, a silicon nitride film 28, and a silicon oxide layer 29, is formed. In the process, the mask displacement can be eliminated by covering the silicon oxide film 35 to form a resist layer and exposing the resist layer from the transparent substrate side using the gate electrode 22 as a mask. (d) Fourth step P-type or N-type ions corresponding to the type of transistor to be formed are injected into the polycrystalline silicon film 25 on which the stopper 26 is formed. That is, when forming a P-channel type transistor, P-type ions such as boron are injected, and when forming an N-channel type transistor, N-type ions such as phosphorus are injected. By this injection, a region exhibiting P-type or N-type conductivity is formed on the polycrystalline silicon film 25 except for the region covered by the stopper 26. These regions serve as a source region 25s and a drain region 25d on both sides of the stopper 26. (e) Step 5 The polycrystalline silicon film 25 in which the source region 25s and the drain region 25d are formed is irradiated with an excimer laser and heated to the extent that the silicon does not melt. As a result, the impurity ions in the source region 25s and the drain region 25d are activated. Then, the polycrystalline silicon film 25 is patterned in an island shape while leaving a predetermined width on both sides of the stopper 26 (gate electrode 22), and the transistors are separated and made independent. (f) Step 6 Silicon oxide is laminated on the polycrystalline silicon film 25 to a film thickness of 1000 Å by the plasma CVD method, and silicon nitride is continuously laminated to a film thickness of 3000 Å and silicon oxide to a film thickness of 500 Å. To do. As a result, an interlayer insulating film composed of three layers, a silicon oxide film 27, a silicon nitride film 28, and a silicon oxide layer 29, is formed. When injecting to form an N-channel type transistor, N-type ions such as phosphorus are injected. By this injection, a region exhibiting P-type or N-type conductivity is formed on the polycrystalline silicon film 25 except for the region covered by the stopper 26. These regions serve as a source region 25s and a drain region 25d on both sides of the stopper 26. (e) Step 5 The polycrystalline silicon film 25 in which the source region 25s and the drain region 25d are formed is irradiated with an excimer laser and heated to the extent that the silicon does not melt. As a result, the impurity ions in the source region 25s and the drain region 25d are activated. Then, the polycrystalline silicon film 25 is patterned in an island shape while leaving a predetermined width on both sides of the stopper 26 (gate electrode 22), and the transistors are separated and made independent. (f) Step 6 Silicon oxide is laminated on the polycrystalline silicon film 25 to a film thickness of 1000 Å by the plasma CVD method, and silicon nitride is continuously laminated to a film thickness of 3000 Å and silicon oxide to a film thickness of 500 Å. To do. As a result, an interlayer insulating film composed of three layers, a silicon oxide film 27, a silicon nitride film 28, and a silicon oxide layer 29, is formed. When injecting to form an N-channel type transistor, N-type ions such as phosphorus are injected. By this injection, a region exhibiting P-type or N-type conductivity is formed on the polycrystalline silicon film 25 except for the region covered by the stopper 26. These regions serve as a source region 25s and a drain region 25d on both sides of the stopper 26. (e) Step 5 The polycrystalline silicon film 25 in which the source region 25s and the drain region 25d are formed is irradiated with an excimer laser and heated to the extent that the silicon does not melt. As a result, the impurity ions in the source region 25s and the drain region 25d are activated. Then, the polycrystalline silicon film 25 is patterned in an island shape while leaving a predetermined width on both sides of the stopper 26 (gate electrode 22), and the transistors are separated and made independent. (f) Step 6 Silicon oxide is laminated on the polycrystalline silicon film 25 to a film thickness of 1000 Å by the plasma CVD method, and silicon nitride is continuously laminated to a film thickness of 3000 Å and silicon oxide to a film thickness of 500 Å. To do. As a result, an interlayer insulating film composed of three layers, a silicon oxide film 27, a silicon nitride film 28, and a silicon oxide layer 29, is formed. Is laminated to a film thickness of 3000 Å and silicon oxide is laminated to a film thickness of 500 Å. As a result, an interlayer insulating film composed of three layers, a silicon oxide film 27, a silicon nitride film 28, and a silicon oxide layer 29, is formed. Is laminated to a film thickness of 3000 Å and silicon oxide is laminated to a film thickness of 500 Å. As a result, an interlayer insulating film composed of three layers, a silicon oxide film 27, a silicon nitride film 28, and a silicon oxide layer 29, is formed.

After forming the interlayer insulating film, it is heated in a nitrogen atmosphere to introduce hydrogen ions contained in the silicon nitride film 28 into the polycrystalline silicon film 25. The temperature of this heat treatment needs to be within a range in which the movement of hydrogen ions is sufficient and the transparent substrate 21 is not damaged, and a range of 350 to 450 ° C is appropriate. Hydrogen ions contained in the silicon nitride film 28 are introduced into the polycrystalline silicon film 25 through the silicon oxide film 27 formed thinly according to the thickness of the silicon nitride film 28, which is necessary for the polycrystalline silicon film 25. The quantity is reliably supplied. As a result, the crystal defects in the polycrystalline silicon film 25 are filled with hydrogen ions.

[0026] After the replenishment of the crystal defects in the polycrystalline silicon film 25 by hydrogen ions is completed, a contact hole 30 penetrating the interlayer insulating film is formed corresponding to the source region 25s and the drain region 25d, and this contact is formed. A source electrode 31s and a drain electrode 31d made of a metal such as aluminum are formed in the hole 30 portion. The source electrode 31s and the drain electrode 31d are formed, for example, by patterning the sputtered aluminum on the interlayer insulating film in which the contact hole 30 is formed.

[0027] Subsequently, the acrylic resin solution is applied onto the interlayer insulating film on which the source electrode 31s and the drain electrode 31d are formed, and fired to form the acrylic resin layer 32. The acrylic resin layer 32 flattens the surface by filling the irregularities formed by the stopper 26, the source electrode 31s, and the drain electrode 31d. Further, a contact hole 33 penetrating the acrylic resin layer 32 is formed on the source electrode 31s, and a transparent electrode 34 made of ITO or the like connected to the source electrode 31s is formed in the contact hole 33 portion. The transparent electrode 34 is formed, for example, by patterning a sputtered ITO on the acrylic resin layer 32 on which the contact hole 33 is formed.

[0028] By the above first to sixth steps, a bottom gate type thin film transistor having the structure shown in FIG. 1 is formed. 6 (a) to 6 (d) are cross-sectional views for each process for explaining the method for manufacturing the thin film transistor according to the second embodiment. In these figures, the same parts as in FIG. 3 are shown. (a) First step Silicon nitride is laminated to a film thickness of 500 Å or more on an insulating transparent substrate 41 by a plasma CVD method, and silicon oxide is continuously laminated to a film thickness of 500 Å or more. As a result, the silicon oxide film 43 that enables the lamination of the silicon nitride film 42 and the polycrystalline silicon film 44 that prevent the precipitation of impurity ions from the transparent substrate 41 is formed. Further, silicon is laminated to a film thickness of 400 Å by the plasma CVD method to form an amorphous silicon film 44'. Then, the hydrogen in the silicon film 44'is discharged to the outside of the film by heat treatment at about 430 ° C for 1 hour or more to reduce the hydrogen concentration to 1% or less, and then the excimer laser is applied to the silicon film 44'. And heat until the amorphous silicon melts. As a result, silicon crystallizes and becomes a polycrystalline silicon film 44. (b) Second step The polycrystalline silicon film 44 is patterned into a predetermined shape corresponding to the formation position of the transistor, and separated for each transistor. After separating the polycrystalline silicon film 44, silicon oxide is laminated to a film thickness of 1000 Å by a plasma CVD method to form a silicon oxide film 45 to be a gate insulating film. Then, a metal such as chromium or molybdenum is laminated to a film thickness of 1000 Å by a sputtering method to form a metal film 54. The metal film 54 is patterned into a predetermined shape across the polycrystalline silicon film 45 to form the gate electrode 46. (c) Third step Using the gate electrode 46 as a mask, P-type or N-type ions corresponding to the type of transistor to be formed are injected into the polycrystalline silicon film 44. In this injection, a region exhibiting P-type or N-type conductivity is formed on the polycrystalline silicon film 44 except for the region covered by the gate electrode 46. These regions are the source region 44s and the drain region 44d. Then, the polycrystalline silicon film 44 into which the predetermined conductive impurity ions are injected is irradiated with an excimer laser and heated to such an extent that the silicon does not melt. As a result, the impurity ions in the source region 44s and the drain region 44d are activated. (d) Step 4 Silicon oxide was laminated on the silicon oxide film 45 on which the gate electrode 46 was formed by the plasma CVD method to a film thickness of 1000 Å, and silicon nitride was continuously coated with a film thickness of 3000 Å and silicon oxide with a film thickness of 500 Å. Laminate sequentially to the film thickness of. As a result, an interlayer insulating film composed of three layers of the silicon oxide film 47, the silicon nitride film 48, and the silicon oxide film 49 is formed. Silicon oxide is laminated on the silicon oxide film 45 to a film thickness of 1000 Å by the plasma CVD method, and silicon nitride is continuously laminated to a film thickness of 3000 Å and silicon oxide to a film thickness of 500 Å. As a result, an interlayer insulating film composed of three layers of the silicon oxide film 47, the silicon nitride film 48, and the silicon oxide film 49 is formed. Silicon oxide is laminated on the silicon oxide film 45 to a film thickness of 1000 Å by the plasma CVD method, and silicon nitride is continuously laminated to a film thickness of 3000 Å and silicon oxide to a film thickness of 500 Å. As a result, an interlayer insulating film composed of three layers of the silicon oxide film 47, the silicon nitride film 48, and the silicon oxide film 49 is formed.

[0029] After forming the interlayer insulating film, it is heated in a nitrogen atmosphere to introduce hydrogen ions contained in the silicon nitride film 48 into the polycrystalline silicon film 44. This heat treatment itself is the same as the heat treatment in the sixth step of the method for manufacturing a bottom gate type thin film transistor shown in FIG. 5 (f). By the way, between the polycrystalline silicon film 44 and the gate electrode 46, hydrogen ions are easily diffused through the interface as a diffusion path. Therefore, in the portion of the polycrystalline silicon film 44 covered with the gate electrode 46, from the side surface of the gate electrode 46. Hydrogen ions wrap around and infiltrate. Therefore, there is no problem even if the gate electrode 46 made of the refractory metal does not allow hydrogen ions to pass through. As a result, the crystal defects in the polycrystalline silicon film 44 are filled with hydrogen ions.

[0030] After introducing hydrogen ions into the polycrystalline silicon film 4, a contact hole 50 penetrating the silicon oxide film 45 and the interlayer insulating film is formed corresponding to the source region 44s and the drain region 44d. Then, a source electrode 51s and a drain electrode 51d made of a metal such as aluminum are formed in the contact hole 50 portion. Subsequently, the acrylic resin solution is applied onto the interlayer insulating film on which the source electrode 51s and the drain electrode 51d are formed, and fired to form the acrylic resin layer 52. The acrylic resin layer 52 flattens the surface by filling the irregularities formed by the gate electrode 46, the source electrode 51s, and the drain electrode 51d. Further, a contact hole 53 penetrating the acrylic resin layer 52 is formed on the source electrode 51s, and a transparent electrode 53 made of ITO or the like connected to the source electrode 51s is formed in the contact hole 53 portion.

By the above first to fourth steps, a top gate type thin film transistor having the structure shown in FIG. 3 is formed. The film thickness of each part illustrated in each of the above-described embodiments is an optimum value under specific conditions, and is not necessarily limited to these values.

[Effect of the Invention] According to the present invention, it is possible to improve the shape of a contact hole that penetrates an interlayer insulating film and reaches a semiconductor film. As a result, it is possible to prevent the occurrence of poor contact between the electrode and the semiconductor film and prevent the deterioration of the operating characteristics of the transistor, and as a result, the manufacturing yield can be expected to be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a first embodiment of a thin film transistor of the present invention.

FIG. 2 is a cross-sectional view showing the shape of a contact hole of the thin film transistor of the present invention.

FIG. 3 is a cross-sectional view showing a second embodiment of the thin film transistor of the present invention.

FIG. 4 is a cross-sectional view of each step showing the first half steps of the manufacturing method according to the first embodiment.

FIG. 5 is a cross-sectional view of each step showing the latter half of the manufacturing method according to the first embodiment.

FIG. 6 is a cross-sectional view of each process showing the manufacturing method according to the second embodiment.

FIG. 7 is a cross-sectional view showing the structure of a conventional thin film transistor.

FIG. 8 is a cross-sectional view showing the shape of a contact hole of a conventional thin film transistor.

[Description of Code] 1, 21, 41 Transparent Substrate 2, 22, 46 Gate Electrode 3, 8, 23, 28, 42, 48 Silicon Nitride Film 4, 7, 24, 27, 29, 43, 47, 49 Silicon Oxidation Membranes 5, 25, 44 Polycrystalline Silicon Membranes 5c, 25c, 44c Channel Regions 5s, 25s, 44s Source Regions 5d, 25d, 44d Drain Regions 6, 26 Stoppers 9, 12, 30, 33, 50, 53 Contact Holes 10s, 31s, 51s Source electrode 10d, 31d, 51d Drain electrode 11, 32, 52 Acrylic resin layer 12, 34, 54 Transparent electrode