Semiconductor device and manufacture thereof

[Technical Field to which the Invention Affected] In the present invention, silicon as a semiconductor and a conductive film are laminated via an interlayer insulating film having a contact hole, and the silicon and the conductive film are sintered inside the contact hole. The present invention relates to a silicide contact structure connected via, and particularly relates to a semiconductor device suitable for preventing delamination between VDD and silicon, and a method for manufacturing the same.

PROBLEM TO BE SOLVED: In recent years, semiconductor devices have become highly integrated and miniaturized, and it is strongly desired to improve the performance of each part of the semiconductor device. For example, in order to realize high-speed operation, it is desired to reduce the contact resistance of a metal wiring made of a conductive film, silicon which is a semiconductor, and a connection portion.

[0003] As a conventional technique for reducing the resistance of the contact portion that electrically connects the surface of the silicon substrate and the metal wiring, as shown in Japanese Patent Application Laid-Open No. 07-78821, the silicon substrate and the substrate thereof It is known that a titanium silicide film is formed between the metal wiring and the metal wiring laminated on the top.

[0004] [Problems to be Solved by the Invention] In order to obtain a low contact resistance by forming a titanium silicide film at an interface between silicon and a metal, the thickness of the titanium silicide (TiSiX, X 2) film is adjusted. It is empirically known that it needs to be thickened to some extent. On the other hand, there is a problem that the thicker the thickness of the titanium silicide film, the more easily peeling occurs at the interface between the titanium silicide film and silicon. This is because the titanium silicide film is formed by depositing a titanium film on silicon and then heat-treating it to react silicon with titanium, so that stress is applied to the inside of the film due to the volume change of the film that occurs during the reaction. This is because it occurs.

[0005] Due to the stress generated inside the titanium silicide film, a high stress is also generated in the vicinity of the interface between the titanium silicide film and silicon, but the higher the film thickness of the titanium silicide film is, the higher the stress is. The higher the internal stress of the conductive film in contact with the film (internal stress generated after the film is formed of the conductive film), the greater the stress. The large stress generated near the interface between the titanium silicide film and silicon causes the titanium silicide film to peel off.

[0006] That is, the thicker the thickness of the titanium silicide film, the easier it is to peel off, which is an obstacle to the high integration and miniaturization of the semiconductor device.

[0007] An object of the present invention is a semiconductor capable of preventing peeling of a titanium silicide film when silicon and a conductive film are connected via a titanium silicide film in a contact hole provided in the insulating film. The purpose is to provide an apparatus and a method for manufacturing the apparatus.

[Means for Solving the Problems] In order to achieve the above object, according to the present invention, a silicon layer and a conductive film are laminated via an insulating film, and a contact hole is provided in the insulating film. In a semiconductor device in which the silicon layer and the conductive film are connected via a titanium silicide film inside the contact hole, the thickness of the titanium silicide film.<u style="single">t (nm)</u>The upper limit of is the internal stress of the conductive film after film formation.<u style="single">By σ (MPa), at t = 150-0.03σ</u>Provided is a semiconductor device characterized by having a specified value.

[0009] In the present invention configured as described above, the thickness of the titanium silicide film is taken into consideration in consideration of the correlation between the film thickness of the titanium silicide film and the internal stress of the conductive film in contact with the titanium silicide film. The upper limit of is set to a value specified corresponding to the internal stress of the conductive film. That is, the thickness of the titanium silicide film is set to a value corresponding to the internal stress of the conductive film that does not cause peeling. As a result, the stress generated in the vicinity of the interface between the titanium silicide film and silicon can be reduced, and the titanium silicide film can be prevented from peeling off.

[0010] Here, preferably, in the above-mentioned semiconductor device, the silicon layer forms a silicon substrate of the semiconductor device on which the insulating film and the conductive film are laminated.

[0011] Further, a polycrystalline silicon layer is deposited on the silicon substrate inside the contact hole, and the titanium silicide film is formed between the polycrystalline silicon layer and the conductive film. May be good.

[0013] Further, according to the present invention, a contact hole is provided with a stacked capacitor structure in which a capacitive element for storing information is arranged above the MOS transistor, and the diffusion layer of the MOS transistor and a bit wire are connected to each other. A polycrystalline silicon layer is deposited inside, and the electrical wiring connected to the diffusion layer of the MOS transistor of the peripheral circuit and the bit wire are composed of the same W / TiN / Ti wiring layer, and the bit wire is formed. And in a semiconductor device in which the electrical wiring is connected to the polycrystalline silicon layer and the diffusion layer of the peripheral circuit via a titanium film, the thickness of the titanium silicide film.<u style="single">t (nm)</u>The upper limit of<u style="single">Bit line</u>Internal stress<u style="single">By σ (MPa), at t = 150-0.03σ</u>Provided is a semiconductor device characterized by having a specified value.

[0015] Further, the upper limit of the hole diameter of the contact hole is preferably 0.4 μm.

[0016] Further, in order to achieve the above-mentioned object, an insulating film is provided on the silicon substrate, a contact hole is opened in the insulating film, and a titanium film is deposited at least inside the contact hole so as to abut the silicon substrate. The conductive film is deposited so as to abut the titanium film, and then the titanium film and the silicon substrate on which the conductive film is deposited are heat-treated to determine the selection material between the titanium film and the silicon substrate. In a method for manufacturing a semiconductor device that forms a titanium silicide film by a reaction, the thickness of the titanium film<u style="single">y (nm)</u>The upper limit of is the internal stress of the conductive film after film formation.<u style="single">By σ (MPa), at y = 60-0.012σ</u>Provided is a method for manufacturing a semiconductor device, characterized in that the value is set to a specified value.

[0017] In such a method for manufacturing a semiconductor device of the present invention, the upper limit of the thickness of the titanium film is set in consideration of the correlation between the film thickness of the titanium film and the internal stress of the conductive film. The value should be specified according to the internal stress of the conductive film. That is, the thickness of the titanium film is set to a value corresponding to the internal stress of the conductive film so as not to cause peeling of the titanium silicide film. As a result, the stress generated in the vicinity of the interface between the titanium silicide film and silicon can be made equal to or less than the peeling generation stress value, and peeling of the titanium silicide film can be prevented.

[0019] Also in the method for manufacturing a semiconductor device of the present invention, it is preferable that the upper limit of the hole diameter of the contact hole is 0.4 μm.

[Embodiments of the Invention] Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 5. 1 and 2 are diagrams showing a contact structure (structure near a contact hole) and a manufacturing method thereof in the semiconductor device of the present embodiment, respectively.

[0021] As shown in FIG. 1, the semiconductor device includes a silicon substrate 1, a gate oxide film 11 and a gate electrode 12 formed on the silicon substrate 1, and an insulating film (interlayer) formed on the surface of the silicon substrate 1. The insulating film) 4 is provided, and the insulating film 4 is provided with a contact hole 5. Further, the element separation region 2 and the diffusion layers 3a and 3b are formed on the silicon substrate 1, and the titanium film 7 and the conductive film 7 and the conductive film 7 are formed on the inner surface of the contact hole 5, the surface of the diffusion layer 3a on the bottom surface of the contact hole 5, and the surface of the insulating film 4. The sex membrane 8 is formed. Further, inside the contact hole 5, a titanium silicide film 6 is formed between the diffusion layer 3a and the titanium film 7, and the diffusion layer 3a and the conductive film (for example, TiN film) 8 are connected via the titanium silicide film 6. It has a structure that has been set.

The contact structure of the semiconductor device shown in FIG. 1 is manufactured by the manufacturing method shown in FIG. That is, (1) the element separation region 2 is formed on the silicon substrate 1, and the gate oxide film 11 and the gate electrode 12 are formed on the exposed portion of the silicon substrate 1. Next, impurities are injected into the silicon substrate 1 using the gate electrode 12 and the element separation region 2 as masks to form diffusion layers 3a and 3b. This situation is shown in a cross-sectional view in FIG. 2 (a).

(2) An insulating film 4 made of, for example, silicon oxide is formed on the upper surface of the silicon substrate 1 on which each element as described above is formed. Then, the contact hole 5 is provided in the insulating film 4. This situation is shown in a cross-sectional view in FIG. 2 (b). The upper limit of the hole diameter of the contact hole 5 is preferably 0.4 μm.

(3) A titanium film 7 is deposited so as to be in contact with the upper surface of the insulating film 4, the side wall of the insulating film 4 inside the contact hole 5, and the upper surface of the diffusion layer 3a on the bottom surface of the contact hole, and further to be in contact with the titanium film 7. The conductive film 8 is deposited on the surface. This situation is shown in a cross-sectional view in FIG. 2 (c).

(4) After the above, heat treatment is performed to cause the titanium film 7 and the silicon of the diffusion layer 3a to undergo a silicide reaction to form the titanium silicide film 6 at the interface between the titanium film 7 and the diffusion layer 3a. This situation is shown in a cross-sectional view in FIG. 2 (d). The heat treatment temperature for causing the silicide reaction is preferably 550 ° C. or higher.

[0026] After the steps (1) to (4) above, a desired step (not shown) is performed to complete the semiconductor device. For example, after forming the wiring and the insulating film of the first layer, the wiring and the insulating film of the second and subsequent layers are formed as needed, and the MOS transistor structure and the like are completed.

[0027] However, the manufacturing procedure of the semiconductor device is not limited to the above description, and the number of wiring layers is not limited to one layer. Further, the semiconductor device can be used for DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), a microcomputer, or the like.

[0028] Here, the upper limit of the film thickness y (nm) of the titanium film 7 is defined by y = 60-0.012σ using the film internal stress σ (MPa) of the conductive film 8 in contact with the titanium film 7. Value. For example, when the conductive film 8 has a film internal stress (tensile stress) of 1000 MPa, the thickness of the titanium film 7 is set to about 50 nm or less. By reacting the titanium film 7 having a thickness of 50 nm or less with the VDD reaction, the film thickness of the titanium silicide 6 becomes 125 nm or less. This is because, theoretically, assuming that the thickness of the titanium film 7 is 1, silicon having a thickness of about 2.3 is consumed and the titanium silicide film 6 having a thickness of about 2.5 is formed.

[0029] Next, the effects of the present embodiment will be described with reference to FIGS. 3 to 5. FIG. 3 is a diagram showing the internal stress (measured value in the experiment) of the titanium silicide film 6 due to the silicide reaction. As can be seen from FIG. 3, when the heat treatment temperature is 550 ° C or higher, the internal stress of the film increases sharply. This is because the silicide reaction occurs at 550 ° C or higher, and it is experimentally clear that a tensile stress of up to 1000 MPa is generated inside the titanium silicide film 6.

[0030] Fig. 4 shows the result of analyzing the stress (shear stress) generated at the interface between titanium silicide and silicon by the finite element method in consideration of the maximum value of 1000 MPa of the generated stress obtained from FIG. 3 and the contact structure. It is a figure which shows. As can be seen from FIG. 4, the stress generated at the interface increases as the thickness of the titanium silicide film 6 increases and as the internal stress of the conductive film 8 in contact with the titanium silicide film 6 increases. In order to prevent the titanium silicide film 6 from peeling, the film thickness of the titanium silicide film 6 and the internal stress of the conductive film 8 are designed so that the stress generated at the interface is equal to or less than the critical stress value at which the peeling occurs. (Regulation) should be done.

FIG. 5 is a diagram showing the relationship between the film thickness of the titanium silicide film 6 and the internal stress of the film of the conductive film (TiN film) 8 so as not to cause peeling of the titanium silicide film 6. As can be seen from FIG. 5, the smaller the internal stress of the conductive film 8, the thicker the limit film thickness of the titanium silicide film 6 in which peeling does not occur. At this time, it is clear from experiments and analysis that the relationship between the critical film thickness t (nm) of the titanium silicide film 6 and the film internal stress σ (MPa) of the conductive film 8 is shown by t = 150-0.03σ. Became. From this, considering the reaction from the titanium film 7 to the titanium silicide film 6, the relationship between the film thickness y (nm) of the titanium film 7 to be deposited and the film internal stress σ (MPa) of the conductive film is described above. As shown by y = 60-0.012σ. That is, in order to prevent the titanium silicide film 6 from peeling off, the upper limit of the film thickness y of the titanium film 7 deposited on silicon (on the diffusion layer 3a) depends on the internal stress σ (MPa) of the conductive film 8. It is necessary to set the value to be determined by the above equation. Further, the internal stress of the conductive film 8 can be easily obtained by measuring the strain of the crystal lattice (that is, the lattice constant of the crystal) using, for example, X-ray diffraction.

By the way, it has been empirically confirmed that the contact resistance between the conductive film and silicon via the titanium silicide film increases when the thickness of the titanium silicide film is 20 nm or less, and therefore the titanium silicide film is used. The film thickness of 6 needs to be 20 nm or more. When the thickness of the titanium silicide film 6 is 20 nm, the internal stress of the conductive film 8 that does not cause peeling is 4300 MPa as shown in FIG. 5, so that a contact structure with low contact resistance and no peeling can be realized. Therefore, the internal stress of the conductive film 8 must be 4300 MPa or less. In particular, in order to promote low resistance, the internal stress σ of the conductive film 8 is set to 1000 MPa or less, the film thickness of the titanium film 7 to be deposited is about 50 nm, and the film thickness of the titanium silicide film 6 to be formed is 125 nm. It is preferable to secure the degree.

[0033] According to the present embodiment as described above, the upper limit of the thickness of the titanium film 7 and the titanium silicide film 6 is set to a value defined in accordance with the internal stress of the film of the conductive film 8. Therefore, the stress generated in the vicinity of the interface between the titanium silicide film 6 and the diffusion layer 3a on the silicon substrate 1 can be made equal to or less than the peeling generation stress value, and therefore the peeling of the titanium silicide film 6 can be prevented.

[0034] In the above description, the case where the unreacted titanium film 7 that was not used in the silicide reaction exists between the conductive film 8 and the titanium silicide film 6, but the unreacted titanium film is not necessarily present. It is not necessary that the titanium film 6 is present, and all the titanium films may be used for the VDD reaction so that the titanium silicide film 6 and the conductive film 8 are in direct contact with each other. Further, the titanium film 7 may contain a component other than titanium.

Next, a second embodiment of the present invention will be described with reference to FIGS. 6 to 8. 6 and 7 are diagrams showing the contact structure (structure near the contact hole) and the manufacturing method thereof in the semiconductor device of the present embodiment, respectively, and FIG. 8 is a modification of FIG. However, for the sake of simplicity, in FIGS. 6 to 8, the same members as those in FIGS. 1 and 2 are designated by the same reference numerals.

As shown in FIG. 6, the semiconductor device includes a silicon substrate 1, a gate oxide film 11 and a gate electrode 12 formed on the silicon substrate 1, and an insulating film (interlayer) formed on the surface of the silicon substrate 1. The insulating film) 4 is provided, and the insulating film 4 is provided with a contact hole 5. Further, the element separation region 2 and the diffusion layers 3a and 3b are formed on the silicon substrate 1, and the polycrystalline silicon 10 is deposited on the diffusion layer 3a inside the contact hole 5, and the inner surface of the contact hole 5 and the bottom surface of the contact hole 5 are deposited. A titanium film 7 and a conductive film 8 are formed on the surface of the polycrystalline silicon 10 and the surface of the insulating film 4. Further, inside the contact hole 5, a titanium silicide film 6 is formed between the polycrystalline silicon 10 and the titanium film 7, and the polycrystalline silicon 10 and the conductive film 8 are connected via the titanium silicide film 6. It has become.

The contact structure of the semiconductor device shown in FIG. 6 is manufactured by the manufacturing method shown in FIG. 7. That is, (5) the element separation region 2 is formed on the silicon substrate 1, and the gate oxide film 11 and the gate electrode 12 are formed on the exposed portion of the silicon substrate 1. Next, impurities are injected into the silicon substrate 1 using the gate electrode 12 and the element separation region 2 as masks to form diffusion layers 3a and 3b. This situation is shown in a cross-sectional view in FIG. 7 (a).

(6) An insulating film 4 made of, for example, silicon oxide is formed on the upper surface of the silicon substrate 1 on which each element is formed as described above, and a contact hole 5 is provided in the insulating film 4. Then, polycrystalline silicon is formed by, for example, a CVD method (Chemical Vapor Deposition) so as to be in contact with the upper surface of the insulating film 4, the side wall of the insulating film 4 inside the contact hole 5, and the upper surface of the diffusion layer 3a on the bottom surface of the contact hole 5. 10 is deposited and the inside of the contact hole 5 is filled with polycrystalline silicon. After that, the excess polycrystalline silicon deposited on the upper surface of the insulating film 4 is removed by etching or the like. At this stage, as shown in the cross-sectional view in FIG. 7 (b), the polycrystalline silicon 10 is in a state of being deposited inside the contact hole 5. The upper limit of the hole diameter of the contact hole 5 is preferably 0.4 μm.

(7) A titanium film 7 is deposited so as to be in contact with the upper surface of the insulating film 4, the side wall of the insulating film 4 inside the contact hole 5, and the upper surface of the polycrystalline silicon 10 on the bottom surface of the contact hole, and further in contact with the titanium film 7. As a result, the conductive film 8 is deposited. This situation is shown in a cross-sectional view in FIG. 7 (c).

(8) After the above, heat treatment is performed to cause the titanium film 7 and the silicon of the polycrystalline silicon 10 to undergo a silicide reaction to form the titanium silicide film 6 at the interface between the titanium film 7 and the polycrystalline silicon 10. This situation is shown in a cross-sectional view in FIG. 7 (d). The heat treatment temperature for causing the silicide reaction is preferably 550 ° C. or higher.

[0041] After the steps (5) to (8) above, a desired step (not shown) is performed to complete the semiconductor device. For example, after forming the wiring and the insulating film of the first layer, the wiring and the insulating film of the second and subsequent layers are formed as needed, and the MOS transistor structure and the like are completed.

[0042] However, the manufacturing procedure of the semiconductor device is not limited to the above description, and the number of wiring layers is not limited to one layer. Further, the semiconductor device can be used for DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), a microcomputer, or the like.

At this time as well, as in the first embodiment, the upper limit of the film thickness y (nm) of the titanium film 7 is set to the internal stress σ of the conductive film 8 (for example, TiN film) in contact with the titanium film 7. Using (MPa), set the value specified by y = 60-0.012σ, and set the upper limit of the film thickness t (nm) of the titanium silicide film 6 at this time to the film internal stress σ (of the conductive film 8). MPa) is used to set the value specified by t = 150-0.03σ.

[0044] As a modification of the present embodiment, the configuration shown in FIG. 8 can be realized. That is, a tungsten (W) film 9 is further laminated on the conductive film (for example, TiN film) 8 of the semiconductor device shown in FIG. 6, and the titanium film 7, the conductive film 8, and the tungsten film 9 form 3 The layered electrical wiring 13 is configured.

[0045] According to the present embodiment as described above, the same action and effect as those of the first embodiment can be obtained, and the peeling of the titanium silicide film 6 can be prevented. Further, in the present embodiment, although a step of depositing the polycrystalline silicon 10 is required, the contact hole 5 is filled with the polycrystalline silicon 10 and the depth becomes shallow, and the titanium film 7 and the conductivity which are the next steps are made. It also has the effect of facilitating the deposition of the sex membrane 8.

[0046] Also in the present embodiment, the unreacted titanium film does not necessarily exist, and all the titanium films are used for the silicide reaction so that the titanium silicide film 6 and the conductive film 8 are in direct contact with each other. The composition may be used, and the titanium film 7 may contain a component other than titanium.

Next, a third embodiment of the present invention will be described with reference to FIGS. 9 and 10. The present embodiment relates to the contact structure of the gate electrode of the MOS (Metal Oxide Semiconductor) transistor, and FIGS. 9 and 10 show the contact structure (structure near the contact hole) and the contact structure in the semiconductor device of the present embodiment, respectively. It is a figure which shows the manufacturing method. However, for the sake of simplicity, in FIGS. 9 and 10, the same members as those in FIGS. 1 and 2 are designated by the same reference numerals.

[0048] As shown in FIG. 9, the semiconductor device includes a silicon substrate 1, a gate oxide film 11 and a gate electrode 12 formed on the silicon substrate 1, and an insulating film (interlayer) formed on the surface of the silicon substrate 1. An insulating film) 4 is provided, and a contact hole 5 is provided on the gate electrode 12 of the insulating film 4. A titanium film 7 and a conductive film 8 are formed on the inner surface of the contact hole 5, the surface of the gate electrode 12 on the bottom surface of the contact hole 5, and the surface of the insulating film 4. Further, inside the contact hole 5, a titanium silicide film 6 is formed between the diffusion layer 3a and the titanium film 7, and the gate electrode 12 and the conductive film (for example, TiN film) 8 are connected via the titanium silicide film 6. It has a structure that has been set.

The contact structure of the semiconductor device shown in FIG. 9 is manufactured by the manufacturing method shown in FIG. That is, (9) a silicon oxide film having a thickness of about 15 nm is formed on the silicon substrate 1, then a polycrystalline silicon film is formed on the silicon oxide film by a CVD method or the like, and a resist pattern is formed by a photolithography method. Then, using the resist pattern as a mask, the polycrystalline silicon film and the silicon oxide film are patterned by a dry etching method to form a gate electrode 12 made of a gate oxide film 11 and a polycrystalline silicon. This situation is shown in a cross-sectional view in FIG. 10 (a).

(10) An insulating film 4 made of, for example, silicon oxide is formed on the upper surface of the silicon substrate 1. Then, a contact hole 5 that reaches the gate electrode 12 is provided in the insulating film 4. This situation is shown in a cross-sectional view in FIG. 10 (b). The upper limit of the hole diameter of the contact hole 5 is preferably 0.4 μm.

(11) A titanium film 7 is deposited so as to be in contact with the upper surface of the insulating film 4, the side wall of the insulating film 4 inside the contact hole 5, and the upper surface of the gate electrode 12 on the bottom surface of the contact hole, and further to be in contact with the titanium film 7. The conductive film 8 is deposited on the surface. This situation is shown in a cross-sectional view in FIG. 10 (c).

(12) After the above, heat treatment is performed to cause the titanium film 7 and the silicon of the gate electrode 12 to undergo a silicide reaction to form the titanium silicide film 6 at the interface between the titanium film 7 and the gate electrode 12. This situation is shown in a cross-sectional view in FIG. 10 (d). The heat treatment temperature for causing the silicide reaction is preferably 550 ° C. or higher.

[0053] After the steps (9) to (12) above, a desired step (not shown) is performed to complete the semiconductor device. For example, after forming the wiring and the insulating film of the first layer, the wiring and the insulating film of the second and subsequent layers are formed as needed, and the MOS transistor structure and the like are completed.

[0054] However, the manufacturing procedure of the semiconductor device is not limited to the above description, and the number of wiring layers is not limited to one layer. Further, the semiconductor device can be used for DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), a microcomputer, or the like.

[0055] Also at this time, similarly to the first embodiment, the upper limit of the thickness y (nm) of the titanium film 7 and the upper limit of the film thickness t (nm) of the titanium silicide film 6 are in contact with the titanium film 7. The internal stress σ (MPa) of the conductive film 8 (for example, TiN film) is used to set the value specified by the above formula. According to the present embodiment as described above, the same effect as that of the first embodiment can be obtained, and the peeling of the titanium silicide film 6 can be prevented.

[0056] Also in the present embodiment, the unreacted titanium film does not necessarily exist, and all the titanium films are used for the silicide reaction so that the titanium silicide film 6 and the conductive film 8 are in direct contact with each other. The composition may be used, and the titanium film 7 may contain a component other than titanium.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. 11 and 12. The present embodiment relates to the contact structure of the gate electrode of the MOS (Metal Oxide Semiconductor) transistor, and FIGS. 11 and 12 show the contact structure (structure near the contact hole) and the contact structure in the semiconductor device of the present embodiment, respectively. It is a figure which shows the manufacturing method. However, for the sake of simplicity, in FIGS. 11 and 12, the same members as those in FIGS. 1 and 2 are designated by the same reference numerals.

As shown in FIG. 11, the semiconductor device includes a silicon substrate 1, a gate oxide film 11 and a gate electrode 12 formed on the silicon substrate 1, and an insulating film (interlayer) formed on the surface of the silicon substrate 1. An insulating film) 4 is provided, and a contact hole 5 is provided on the gate electrode 12 of the insulating film 4. In addition, polycrystalline silicon 10 is deposited on the gate electrode 12 inside the contact hole 5, and the titanium film 7 and the conductive film 7 are deposited on the inner surface of the contact hole 5, the surface of the polycrystalline silicon 10 on the bottom surface of the contact hole 5, and the surface of the insulating film 4. Membrane 8 is formed. Further, inside the contact hole 5, a titanium silicide film 6 is formed between the polycrystalline silicon 10 and the titanium film 7, and the polycrystalline silicon 10 and the conductive film (for example, TiN film) 8 pass through the titanium silicide film 6. It is a connected configuration.

The contact structure of the semiconductor device shown in FIG. 11 is manufactured by the manufacturing method shown in FIG. That is, (13) a silicon oxide film having a thickness of about 15 nm is formed on the silicon substrate 1, then a polycrystalline silicon film is formed on the silicon oxide film by a CVD method or the like, and a resist pattern is formed by a photolithography method. Then, using the resist pattern as a mask, the polycrystalline silicon film and the silicon oxide film are patterned by a dry etching method to form a gate electrode 12 made of a gate oxide film 11 and a polycrystalline silicon. This situation is shown in a cross-sectional view in FIG. 12 (a).

(14) An insulating film 4 made of, for example, silicon oxide is formed on the upper surface of the silicon substrate 1, and a contact hole 5 reaching the gate electrode 12 is provided in the insulating film 4. Then, polycrystalline silicon 10 is deposited on the upper surface of the insulating film 4, the side wall of the insulating film 4 inside the contact hole 5, and the upper surface of the diffusion layer 3a on the bottom surface of the contact hole 5, for example, by the CVD method, and the inside of the contact hole 5 is increased. Fill with crystalline silicon. After that, the excess polycrystalline silicon deposited on the upper surface of the insulating film 4 is removed by etching or the like. At this stage, as shown in the cross-sectional view in FIG. 12 (b), the polycrystalline silicon 10 is in a state of being deposited inside the contact hole 5. The upper limit of the hole diameter of the contact hole 5 is preferably 0.4 μm.

(15) A titanium film 7 is deposited so as to be in contact with the upper surface of the insulating film 4, the side wall of the insulating film 4 inside the contact hole 5, and the upper surface of the polycrystalline silicon 10 on the bottom surface of the contact hole, and further in contact with the titanium film 7. As a result, the conductive film 8 is deposited. This situation is shown in a cross-sectional view in FIG. 12 (c).

[0062] (16) After the above, heat treatment is performed to cause the titanium film 7 and the silicon of the polycrystalline silicon 10 to undergo a silicide reaction to form the titanium silicide film 6 at the interface between the titanium film 7 and the polycrystalline silicon 10. This situation is shown in a cross-sectional view in FIG. 12 (d). The heat treatment temperature for causing the silicide reaction is preferably 550 ° C. or higher.

[0063] After the steps (13) to (16) above, a desired step (not shown) is performed to complete the semiconductor device. For example, after forming the wiring and the insulating film of the first layer, the wiring and the insulating film of the second and subsequent layers are formed as needed, and the MOS transistor structure and the like are completed.

[0064] However, the manufacturing procedure of the semiconductor device is not limited to the above description, and the number of wiring layers is not limited to one layer. Further, the semiconductor device can be used for DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), a microcomputer, or the like.

[0065] At this time as well, as in the first embodiment, the upper limit of the film thickness y (nm) of the titanium film 7 and the upper limit of the film thickness t (nm) of the titanium silicide film 6 are in contact with the titanium film 7. The internal stress σ (MPa) of the conductive film 8 (for example, TiN film) is used to set the value specified by the above formula. According to the present embodiment as described above, the same effect as that of the first embodiment can be obtained, and the peeling of the titanium silicide film 6 can be prevented. Further, in the present embodiment, although a step of depositing the polycrystalline silicon 10 is required, the contact hole 5 is filled with the polycrystalline silicon 10 and the depth becomes shallow, and the titanium film 7 and the conductivity which are the next steps are made. It also has the effect of facilitating the deposition of the sex membrane 8.

[0066] Also in the present embodiment, the unreacted titanium film does not necessarily exist, and all the titanium films are used for the silicide reaction so that the titanium silicide film 6 and the conductive film 8 are in direct contact with each other. The composition may be used, and the titanium film 7 may contain a component other than titanium.

[0067] A fifth embodiment of the present invention will be described with reference to FIG. The present embodiment relates to a contact structure of a main part (a part of a memory array and peripheral circuits) of a semiconductor substrate on which a DRAM is formed, and has both configurations of the first embodiment and the second embodiment. It is a form.

A memory array 100A (on the right side of the center of the figure) and a peripheral circuit area 100B (on the left side of the center of the figure) are formed on the main surface of the silicon substrate 101 shown in FIG. A plurality of DRAM memory cells are formed in the active area of the memory array 100A, and each memory cell has one memory selection MOS transistor Qt and one information storage capacitance element C arranged above the MOS transistor Qt. It is composed of. That is, the memory cell 100A is composed of a stacked capacitor structure in which the information storage capacitance element C is arranged above the memory selection MOS transistor Qt, and each MOS transistor Qt is separated by the field oxide film 102. Has been done.

[0069] The MOS transistor Qt for selecting a memory cell in the memory cell 100A is composed of a gate oxide film 111, a gate electrode 112a, and a pair of diffusion layers 103a and 103b (source and drain regions). .. The gate electrode 112a is made of, for example, a polycrystalline silicon film, and is integrally formed with the word wire WL.

[0070] A plurality of MOS transistors Q1, Q2, ... Are formed in the active region of the peripheral circuit region 100B. The peripheral circuit area 100B of this DRAM may be composed of a CMOS circuit in which an n-channel type MOS transistor and a p-channel type MOS transistor are combined. The MOS transistors Q1, Q2, ... In the peripheral circuit region 100B are composed of a gate oxide film 111, a gate electrode 112b, and a pair of diffusion layers 103c, 103d (source and drain regions).

[0071] Silicon oxide films are formed on the upper and side walls of the gate electrode 112a of the MOS transistor Qt in the memory cell 100A and the gate electrode 112b of the MOS transistors Q1, Q2, ... In the peripheral circuit region 100B. 105 is formed. Further, an information storage capacitance element C is formed on the upper part of the silicon oxide film 105 covering the memory cell selection MOS transistor Qt, and the information storage capacitance element C is one of the memory cell selection MOS transistors Qt. It is connected to the diffusion layer 103a. An insulating film 104 such as a BPSG (Boron doped Phospho Silicate Glass) film is formed on the entire upper surface of the information storage capacitance element C of the memory cell 100A and the MOS transistors Q1, Q2, ... In the peripheral circuit area 100B. Each is formed.

[0072] Above the other diffusion layer 103b of the memory cell selection MOS transistor Qt, a contact hole 201 is opened in the insulating film 104, and polycrystalline silicon 110 is embedded inside the contact hole 201. The bit wire BL is connected to the diffusion layer 103b via the polycrystalline silicon 110 in the contact hole 201.

[0073] In the peripheral circuit region 100B, a contact hole 202 is opened in the insulating film 104 above one diffusion layer 103c of the MOS transistor Q1, and a bit wire BL is connected via the contact hole 202. Has been done. Further, a contact hole 203 is opened in the insulating film 104 above the other diffusion layer 103d of the MOS transistor Q1, and the wiring 113a of the first layer is connected via the contact hole 203. Further, a contact hole 204 is opened in the insulating film 104 above the diffusion layer 103c of the MOS transistor Q2, the first layer wiring 113a is connected via the contact hole 204, and the MOS transistor Q2 A contact hole 205 is opened in the insulating film 104 above the diffusion layer 103d of the above, and the wiring 113b of the first layer is connected via the contact hole 205.

[0074] The above-mentioned bit wire BL and the wirings 113a and 113b of the first layer have a structure in which Ti film 107, TiN film 108, and W film 109 are laminated in this order from the lower layer side, and these have the same structure. Wiring layer.

[0075] In the memory cell 100A, a titanium silicide layer 106a is formed at the interface between the polycrystalline silicon 110 above the diffusion layer 103b of the memory cell selection MOS transistor Qt and the Ti film 107 forming a part of the bit line BL. Has been done. Further, at the interface between the diffusion layers 103c, 103d of the MOS transistors Q1, Q2, ... In the peripheral circuit region 100B and the Ti film 107 forming a part of the bit line BL or the wiring 113a, 113b of the first layer. Is formed with a titanium silicide layer 106b.

[0076] Also in the present embodiment as described above, similarly to the first embodiment, the upper limit of the film thickness y (nm) of the Ti film 107 and the film thickness t (nm) of the titanium silicide films 106a and 106b The upper limit is the value specified by the above formula using the internal stress σ (MPa) of the TiN film (conductive film) 8. According to the present embodiment as described above, the same effects as those of the first and second embodiments can be obtained, and the peeling of the titanium silicide films 106a and 106b can be prevented.

[Effectiveness of the Invention] According to the present invention, in a semiconductor device in which silicon and a conductive film are connected via a titanium silicide film inside a contact hole provided in the insulating film, the titanium silicide film is used. Since each of the upper limit of the thickness and the upper limit of the titanium film is set to a value specified corresponding to the internal stress of the conductive film, peeling at the interface between silicon and titanium silicide can be prevented. Further, the contact resistance between the silicon and the conductive film can be reduced by controlling the thickness of the titanium silicide film. Therefore, it is possible to provide a semiconductor device having a good contact structure.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a contact structure (structure near a contact hole) of a semiconductor device according to the first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing method of the semiconductor device shown in FIG.

FIG. 3 is a diagram showing a film internal stress (measured value in an experiment) of a titanium silicide film due to a silicide reaction.

FIG. 4 is a diagram showing the relationship between the interfacial stress generated at the interface between the silicon substrate and the titanium silicide film and the internal stress of the conductive film.

FIG. 5 is a diagram showing the relationship between the film thickness of the titanium silicide film for preventing peeling and the internal stress of the conductive film (TiN film).

FIG. 6 is a cross-sectional view showing a contact structure (structure near a contact hole) of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing method of the semiconductor device shown in FIG.

8 is a diagram showing a modification of the semiconductor device of FIG. 6. FIG.

FIG. 9 is a cross-sectional view showing a contact structure (structure near a contact hole) of a semiconductor device according to a third embodiment of the present invention.

10 is a diagram showing a manufacturing method of the semiconductor device shown in FIG. 9. FIG.

FIG. 11 is a cross-sectional view showing a contact structure (structure near a contact hole) of a semiconductor device according to a fourth embodiment of the present invention.

12 is a diagram showing a method of manufacturing the semiconductor device shown in FIG. 11. FIG.

FIG. 13 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

[Code description] 1 Silicon substrate 2 Element separation region 3a, 3b Diffusion layer 4 Insulating film 5 Contact hole 6 Titanium silicide film 7 Titanium film 8 Conductive film (TiN film) 9 Tungsten film 10 Polycrystalline silicon 11 Gate oxide film 12 Gate electrode 13 Electrical wiring 100A Memory array 100B Peripheral circuit area 101 Silicon substrate 102 Field oxide film 103a, 103b, 103c, 103d Diffusion layer 104 Insulation film 105 Silicon oxide film 106a, 106b Titanium silicide film 107 Ti film 108 TiN film ( (Conductive film) 109 W film 110 Polycrystalline silicon 111 Gate oxide film 112a, 112b Gate electrode 113a, 113b First layer wiring 201,202,203,204 Contact hole Qt (for memory selection) MOS transistor Q1, Q2 MOS transistor BL Bit wire C Information Capacitive element for storage WL word wire