Semiconductor integrated circuit

The present invention relates to semiconductor integrated circuits, particularly semiconductor integrated circuits having at least two logic device elements and voltage level conversion circuits operating at different values of power supply voltage.

PROBLEM TO BE SOLVED: To reduce a power supply voltage in order to secure reliability of an internal circuit element and reduce power consumption with the miniaturization of a semiconductor integrated circuit. However, with a low power supply voltage, it is not possible to operate the internal circuit at high speed or sufficiently write to the memory cell. Therefore, the reliability and low power consumption requirements can be achieved by supplying a high power supply voltage to a necessary portion of the semiconductor integrated circuit to operate the semiconductor integrated circuit.

[0003] That is, since power supply voltages having different values are supplied to the same semiconductor integrated circuit and circuits having different signal levels for performing logic processing are mixedly mounted, a level conversion circuit for converting the signal level is required between the two. Is.

[0004] In a semiconductor integrated circuit including a conventional level conversion circuit, a level conversion in which an output signal from a logic circuit to which a lower power supply voltage is supplied is supplied with two types of power supply voltages, a higher voltage and a lower power supply voltage. It is input to the circuit, further converted from the amplitude of the lower power supply voltage to the amplitude of the higher power supply voltage in the level conversion circuit, and output to the circuit operating at the lower power supply voltage (for example, Patent Document). See 1.).

[0005] [Patent Document 1] US Pat. No. 6,067,257 (1st page, 7th figure) Further, semiconductor integrated circuits having such different power supply voltage levels have been introduced in recent years with the mobilization of electronic devices. The specified voltage may be constantly supplied because the power supply may be supplied from a battery that has been discharged and consumed, or may be supplied from a charging power source for the battery, or the power supply circuit including the battery may be shocked or vibrated. It may not be done. That is, the higher power supply voltage becomes unstable and becomes lower than the lower power supply voltage, or the contact of the connection terminal of the low voltage power supply becomes unstable, resulting in a state such as a momentary power supply stop or stop. Sometimes.

[0006] Therefore, as a result of supplying a power supply voltage equal to or lower than the minimum level voltage required for determining the logic to the logic circuit, the logic operation of the logic circuit element becomes indefinite, for example, an inverter transistor composed of a CMOS circuit. The continuity state of the inverter becomes indefinite, and a through current may flow between the power supply terminals of this inverter via a CMOS circuit. As described above, through currents flow in various parts of the semiconductor integrated circuit due to the unstable power supply voltage, and it is not possible to prevent malfunction and increase in power consumption.

[0007] Hereinafter, a conventional example of a semiconductor integrated circuit including a level conversion circuit will be described with reference to FIG. FIG. 8A shows a block of a semiconductor integrated circuit having a level conversion circuit 83 between the logic circuit 81 to which the lower power supply voltage VL is supplied and the logic circuit 82 to which the higher power supply voltage VH is supplied. It is a figure.

[0008] This semiconductor integrated circuit is connected to a logic circuit 81 to which a power supply voltage VL is supplied and outputs a signal S1 having an amplitude of the power supply voltage VL, and is connected to the logic circuit 81 to supply power supply voltages VL and VH. A level conversion circuit 83 that converts the input signal S1 from the amplitude of the power supply voltage VL to the signal S2 having the amplitude of the power supply voltage VH and outputs the signal S2, and a signal to which the power supply voltage VH is supplied and has the amplitude of the power supply voltage VH. It has a logic circuit 82 that outputs S3. Further, in the front stage of the logic circuit 81, a simple logic element (not shown) such as an inverter, a NAND circuit, or a NOR circuit that converts the level of the input signal S3 from the amplitude of the power supply voltage VH to the signal having the amplitude of the power supply voltage VL ( Hereinafter, it is referred to as an H / L conversion logic element.) Is connected.

[0009] Here, the logic circuits 81 and 82 are logic circuits including a CMOS inverter which is composed of a MOSFET transistor and an NMOS transistor and in which an input signal is supplied to a commonly connected gate.

[0010] Further, FIG. 8B is a circuit diagram showing an example of the level conversion circuit 83. The level conversion circuit 83 includes a latch circuit, in which the power supply voltage VH is supplied to the source terminal, and the gate terminals and the drain terminals are cross-connected to each other in the MOSFET transistors P84 and P85, and the source. The terminal is connected to the drain terminal of the MIMO transistor P84 and the gate terminal of the MOSFET transistor P85 at node 86, and the drain terminal is connected to the ground. It is composed of an NMOS transistor N85 which is connected to the gate terminal of the transistor P84 and whose drain terminal is connected to the ground.

[0011] Further, the level conversion circuit 83 is supplied with a power supply voltage VL, a gate terminal of the MIMO transistor N84 and an input terminal of the inverter 89 are connected to the output terminal side, and an inverter that outputs a signal in which the logic of the input signal S1 is inverted. 88, an inverter 89 that outputs a signal in which the logic of the input signal from the inverter 88 is inverted to the gate terminal of the MIMO transistor N85, and a signal S2 in which the power supply voltage VH is supplied and the logic of the input signal from the node 87 is inverted. It is composed of an inverter 810 that outputs.

Next, the operation of the semiconductor integrated circuit including the level conversion circuit shown in FIG. 8 will be described.

First, the conversion from the signal S1 having the amplitude of the power supply voltage VL to the signal S2 having the amplitude of the power supply voltage VH (hereinafter referred to as LH conversion) will be described with reference to FIG. 8B. When a signal S1 having a high level of the amplitude of the power supply voltage VL (hereinafter referred to as logic H) is input to the level conversion circuit 83, the signal S1 of logic H is low level (hereinafter referred to as logic L) by the inverter 88. It is inverted to the signal with, and is output to the MIMO transistor N84 and the inverter 89. The signal of the logic L input to the gate terminal of the NMOS transistor N84 turns off the NMOS transistor N84.

On the other hand, the signal of the logic L input to the inverter 89 is inverted to the signal of the logic H having the amplitude VL, is input to the gate terminal of the NMOS transistor N85, and turns on the NMOS transistor N85. Then, the node 87 is pulled down to the low level, and the PCOS transistor P84 at which the potential of the node 87 is gate-input is turned on. Therefore, the potential of the node 86 becomes a high level, and the PCOS transistor P85 having the potential of the node 86 as the gate input is turned off. Therefore, the signal of logic L is input to the inverter 810 to which the node 87 is connected to the input terminal, and the inverter 810 outputs a high level signal having an amplitude of the inverted power supply voltage VH.

[0015] Instead, when the signal S1 of the logic L having the amplitude of the power supply voltage VL is input to the level conversion circuit 83, the signal S1 of the logic L is inverted to the signal of the logic H by the inverter 88, and the MIMO transistor N84 and the inverter. It is output to 89. The signal of the logic H input to the gate terminal of the NMOS transistor N84 turns on the NMOS transistor N84. On the other hand, the signal of the logic H input to the inverter 89 is inverted to the signal of the logic L and input to the gate terminal of the NMOS transistor N85, and the NMOS transistor N85 is turned off.

[0016] Then, the potential of the node 87 becomes high level, and the potential of the node 87 turns off the MIMO transistor P84 to which the potential is input to the gate. Therefore, the potential of the node 86 is pulled down to the low level, and the MIMO transistor P85 whose gate input is the potential of the node 86 is turned on. Therefore, a high level is input to the inverter 810 to which the node 87 is connected to the input terminal, and the inverter 810 outputs a low level signal S2 having an inverted VH amplitude.

On the other hand, the conversion from the amplitude of the power supply voltage VH to the amplitude of the power supply voltage VL will be described. The power supply voltage VH has a higher voltage than VL, and the amplitude of the signal input to the logic circuit 81 operating at a lower voltage VL is also sufficiently large. Therefore, in the logic circuit 81, since a sufficient signal level is secured by the input signal, a latch circuit for fixing the logic is unnecessary. Therefore, since the H / L conversion logic element connected to the first stage of the logic circuit 81 is sufficient, the power supply voltages VL and VH are normal even if the level conversion circuit 83 as shown in FIG. 8 (b) is not used. If there is, accurate logical operation can be expected.

[0018] Here, the operation when the power supply voltage VH supplying the higher voltage is unstable and temporarily becomes lower than the power supply voltage VL will be described. In the level conversion circuit 83, since the signal S1 from the logic circuit 81 to which the power supply voltage VL is supplied is input to the inverter 88, the signal S1 having the amplitude of the power supply voltage VL having a normal logic level is input. .. However, since the power supply voltage VH supplied to the latch circuit is unstable, the potential of the node 87 to which the unstable power supply voltage VH is supplied is indefinite. Therefore, a signal with undefined logic is supplied to the inverter 810 to which the node 87 and the input terminal side are connected. As a result, a through current may flow through the inverter 810 composed of a CMOS circuit. Further, since the power supply voltage VH supplied to the inverter 810 is unstable, the potential state of the output signal S2 is not determined, and the signal S2 whose logic is undefined may be output.

[0019] The signal S2 whose logic is indefinite is input to the logic circuit 82. Therefore, a through current flows through the CMOS inverter or the like even in the logic circuit 82. Moreover, since the unstable power supply voltage VH is supplied, the potential state of the output signal is not determined, and the signal S3 whose logic is indefinite is output.

The signal S3 whose logic is indefinite is input to the H / L conversion logic element connected to the first stage of the logic circuit 81. For example, if this logic circuit element is a CMOS inverter, a signal S3 having an indefinite logic is input, so that a through current may flow. Further, the signal S3 whose logic is indefinite is output to the inside of the logic circuit 81, and a through current also flows in the logic circuit 81.

[0021] In this way, a through current flows through each of the level conversion circuit 83, the logic circuit 82, the H / L conversion logic element, and the logic circuit 81, and the power consumption of the entire semiconductor integrated circuit increases.

[0022] Further, the operation when the lower power supply voltage VL is unstable and the power supply voltage is momentarily stopped or stopped will be described. In this case, the logic circuit 81 outputs a signal S1 whose logic is indefinite because the unstable power supply voltage VL is supplied. The signal S1 whose logic is indefinite is input to the level conversion circuit 83. Since this logic-undefined signal S1 is input, a through current flows through the inverter 88, and an unstable power supply voltage VL is supplied, so that a logic-undefined signal is output. A signal whose logic is indefinite is input to the gate terminal of the NMOS transistor N84, and the conduction state of the NMOS transistor N84 becomes indefinite.

On the other hand, since the inverter 89 is also supplied with the unstable power supply voltage VL, it outputs a signal with undefined logic. This logic indefinite signal is input to the gate terminal of the NMOS transistor N85, and the conduction state of the NMOS transistor N85 is also indefinite. That is, the relationship between the conduction states of the NMOS transistors N84 and N85 is not determined, and a state occurs in which they are turned on at the same time. As a result, the node 86 or the node 87 may be in a floating state, and both the MIMO transistors P84 and P85 may be turned on at the same time, and a through current flows through the latch circuit. Further, since a signal with undefined logic can be input to the inverter 810, a through current flows and a signal S2 with undefined logic is output.

[0024] Since this logic indefinite signal S2 is input to the logic circuit 82, a through current flows through the logic circuit 82, and the logic indefinite signal S3 is output.

Further, as a result, a through current flows through a simple logic circuit element to which the power supply voltage VL connected to the first stage of the logic circuit 81 is supplied, and a signal with undefined logic is output. Then, a through current also flows through the logic circuit 81.

[0026] In particular, the amount of power consumed by the through current generated in the element supplied with the higher power supply voltage VH as the operating voltage becomes large.

[0027] As described above, since a through current may be generated in the entire semiconductor integrated circuit, the circuit corresponding to the mobilization should be a low power consumption circuit, but conversely, a through current flows in the entire circuit. was there.

[0028] The present invention relates to a semiconductor integrated circuit capable of suppressing power consumption by supplying different voltages according to an object. However, in an actual usage environment, for example, in the use mounted on a mobile device, the supplied power supply voltage may be unstable. At this time, as described above, a through current is generated in the entire semiconductor integrated circuit, and power consumption cannot be suppressed.

[0029] Therefore, according to the present invention, at least two different power supply voltages are supplied, and even when one of the power supply voltages becomes unstable, a signal having an amplitude of this power supply voltage is input and output. It is an object of the present invention to provide a semiconductor integrated circuit capable of preventing an increase in power consumption due to a through current in a logic circuit and a voltage level conversion circuit, and also preventing a malfunction.

[Means for Solving the Problems] According to one aspect of the present invention, a first power supply voltage having an amplitude of a first voltage level is supplied, and a first voltage having an amplitude of the first voltage level is provided. A first logic circuit that outputs one signal and a second power supply voltage having an amplitude of the first power supply voltage and a second voltage level different from the first power supply voltage are supplied, and the first power supply voltage is supplied. The first level conversion circuit that converts the signal level of the first voltage level from the amplitude of the first voltage level to the amplitude of the second voltage level and outputs the second signal, and the amplitude of the second voltage level. The second power supply voltage to be supplied is supplied, and the second logic circuit for outputting the third signal having the amplitude of the second voltage level is connected between the first and second logic circuits, and the above-mentioned The first and second power supply voltages are supplied, and the third signal of the second voltage level output from the second logic circuit is level-converted to the first voltage level and the fourth signal. Can be provided with a second level conversion circuit that outputs the above to the first logic circuit.

[0031] According to another aspect of the present invention, a first power supply voltage having a first voltage level amplitude is supplied and a first signal having the first voltage level amplitude is output. And a second power supply voltage having an amplitude of the first power supply voltage and a second voltage level higher than the first power supply voltage, and the level of the first and second power supply voltages A power supply voltage detection circuit that outputs a detection signal indicating a state and a first signal to which the first and second power supply voltages are supplied and input from the first logic circuit are used to obtain the amplitude of the second voltage level. A level conversion circuit unit that converts to a second signal to have and outputs a switch control signal based on the detection signal, an internal circuit that operates by the first power supply voltage, and a power supply terminal of the first power supply voltage. A switching circuit that is connected in series with the internal circuit and operates by the switch control signal from the level conversion circuit unit is provided between them, and the detection signals output from the power supply voltage detection circuit are the first and second detection signals. When expressing the fluctuation of the level of any one of the power supply voltages of the above, it is possible to provide a semiconductor integrated circuit characterized in that the level conversion circuit unit outputs a signal for opening the switching circuit.

[0032] With this configuration, even when one of the first and second power supply voltages becomes unstable, the penetration in the logic circuit for inputting / outputting a signal having the amplitude of this power supply voltage and in the voltage level conversion circuit. It is possible to provide a semiconductor integrated circuit that can prevent an increase in power consumption due to an electric current and also prevent a malfunction.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0034] FIG. 1 is a block diagram showing a configuration of a first embodiment. Similarly to FIG. 8, in FIGS. 1 to 7, for ease of explanation, the power supply terminal to which the power supply voltage VL having a low voltage is supplied is indicated by a horizontal bar - and has a high voltage. The power supply terminals to which the power supply voltage VH is supplied are indicated by white circles. Further, in FIG. 4, it has a power supply terminal to which an intermediate voltage VM is supplied, and is indicated by a black circle.

As shown in FIG. 1, the semiconductor integrated circuit of the first embodiment is, for example, a DRAM macro 10 formed on a silicon substrate, and power supply voltages VL and VH are supplied from the outside. This DRAM macro 10 supplies a logic circuit 11 to which a power supply voltage VL is supplied and outputs a signal S1 having an amplitude of the power supply voltage VL, and a signal S1 to which a power supply voltage VL and VH are supplied and input from the logic circuit 11. A level conversion circuit 13 that converts the amplitude of the power supply voltage VL into a signal S2 with an amplitude of the power supply voltage VH, a logic circuit 12 that is supplied with the power supply voltage VH and outputs a signal S3 with an amplitude of the power supply voltage VH, and a power supply voltage. VL and VH are supplied, and it is composed of a level conversion circuit 14 that converts the signal S3 output from the logic circuit 12 from the amplitude of the power supply voltage VH to the signal S4 having the amplitude of the power supply voltage VL.

[0036] Further, outside the DRAM macro 10, a lower power supply voltage VL is supplied to the same semiconductor substrate, and a logic circuit 15 that is directly connected to the logic circuit 11 to exchange signals is formed. ..

The logic circuit 11 includes, for example, a control circuit for controlling the DRAM macro 10, a decoding circuit for decoding the address of the memory device, and the like, and the logic circuit 12 includes, for example, an internal power generation circuit and a sense amplifier. Etc. may be included.

[0038] The logic circuit 15 includes, for example, an address buffer circuit.

[0039] FIG. 2 is a circuit diagram showing an example of the circuit configuration of the level conversion circuit 13 that performs L / H conversion. The full latch circuit included in the level conversion circuit 13 is composed of two MOSFET transistors P21 and P22 and two NMOS transistors N21 and N22. That is, the high voltage side power supply terminal of the power supply voltage VH is connected to the sources of the MIMO transistors P21 and P22. At node 25, the gate of the NMOS transistor N22 and the MIMO transistor P22, the drain of the MOSFET transistor P21, and the drain of the NMOS transistor N21 are connected. Further, at node 26, the gate of the NMOS transistor N21 and the MIMO transistor P21, the drain of the MOSFET transistor P22, and the drain of the NMOS transistor N22 are connected, and the source of the NMOS transistors N21 and N22 is connected to the ground potential.

[0040] Further, the node 25 side of this full latch circuit is connected to the source of the NMOS transistor N23. The gate of this transistor N23 is connected to the output terminal of the inverter 27 to which the signal S1 is input from the input terminal.

Further, the output terminal of the inverter 27 to which the power supply voltage VL is supplied is connected to the input terminal of the inverter 28 to which the power supply voltage VL is also supplied. The output terminal of the inverter 28 is connected to the gate of the NMOS transistor N24, the drain of the transistor N24 is connected to the node 26, and the source is grounded. This node 26 is connected to the input terminal of the inverter 29 to which the power supply voltage VH is supplied.

On the other hand, FIG. 3 is an example of a circuit diagram of the level conversion circuit 14 that performs H / L conversion. The full-latch circuit included in the level conversion circuit 14 is composed of MIMO transistors P31 and P32 and NMOS transistors N31 and N32.

[0043] A high-voltage power supply terminal having a power supply voltage of VL is connected to the source of the MIMO transistors P31 and P32, and at node 35, the gate of the NMOS transistor N32 and the MIMO transistor P32, the drain of the MIMO transistor P31, and the drain of the NMOS transistor N31 are connected. Is connected. Further, at the node 36, the gate of the NMOS transistor N31 and the MIMO transistor P31, the drain of the MOSFET transistor P32, and the drain of the NMOS transistor N32 are connected, and the sources of the MIMO transistors N31 and N32 are connected to the power supply terminal of the ground potential. There is.

[0044] Further, the node 35 side of this full latch circuit is connected to the drain of the NMOS transistor N33. The gate of this NMOS transistor N33 is connected to the output terminal of the inverter 37 to which the signal S3 is input from the input terminal.

Further, the output terminal of the inverter 37 to which the power supply voltage VH is supplied is connected to the input terminal of the inverter 38 to which the power supply voltage VH is supplied. The output terminal of this inverter 38 is connected to the gate of the NMOS transistor N34, its drain is connected to node 36, and its source is grounded. This node 36 is connected to the input terminal of the inverter 39 to which the power supply voltage VL is supplied.

Next, the operation of the semiconductor integrated circuit according to the first embodiment will be described with reference to FIGS. 1 to 3.

First, when the high-level signal S1 having the amplitude of the power supply voltage VL, which describes the operation of the L / H conversion, is input from the logic circuit 11 to the level conversion circuit 13 using the level conversion circuit 13 of FIG. , The signal inverted to the logic L by the inverter 27 is supplied to the MIMO transistor N23 and the inverter 28. The signal of the logic L input to the gate of the NMOS transistor N23 turns off the NMOS transistor N23.

[0048] On the other hand, the signal of the logic L input to the input terminal of the inverter 28 is inverted to the signal of the logic H, input to the gate of the NMOS transistor N24, and the NMOS transistor N24 is turned on. Then, the node 26 connected to the drain of the NMOS transistor N24 is pulled down to the low level, and the MOSFET P21 having the potential of the node 26 as the gate input is turned on. At the same time, the NMOS transistor N21 whose gate input is the potential of the node 26 is turned off.

Further, the potential of the node 25 is raised to a high level of the power supply voltage VH. Therefore, the MIMO transistor P22 whose gate input is the potential of the node 25 is turned off. At the same time, the NMOS transistor N22 whose gate input is the potential of the node 25 is turned on. Therefore, a low-level signal having an amplitude of the power supply voltage VH is supplied to the inverter 29 to which the node 26 is connected to the input terminal, and the inverter 29 outputs the inverted logic H signal S2.

[0050] Next, when a low-level signal S1 having an amplitude of the power supply voltage VL is input from the logic circuit 11 to the level conversion circuit 13, the signal inverted to the logic H by the inverter 27 is sent to the MIMO transistor N23 and the inverter 28. Be entered. The signal of the logic H input to the gate of the NMOS transistor N23 turns this transistor N23 on.

On the other hand, the signal of the logic H input to the input terminal of the inverter 28 is inverted to the logic L and input to the gate of the NMOS transistor N24 to turn off the NMOS transistor N24. Then, the potential of the node 26 connected to the drain of the transistor N24 is raised to a high level of the power supply voltage VH. Therefore, the MIMO transistor P21 whose gate input is the potential of the node 26 is turned off. At the same time, the NMOS transistor N21 whose gate input is the potential of the node 26 is turned on.

Further, the node 25 is pulled down to the low level, and the MIMO transistor P22 whose gate input is the potential of the node 25 is turned on. At the same time, the NMOS transistor N22 whose gate input is the potential of the node 25 is turned off. Therefore, the high level of the amplitude of the power supply voltage VH is output to the inverter 29 to which the node 26 is connected to the input terminal, and the inverter 29 outputs the signal S2 of the inverted logic L.

Next, when the high-level signal S3 having the amplitude of the power supply voltage VH, which describes the H / L conversion operation, is input from the logic circuit 12 to the level conversion circuit 14 using the level conversion circuit 14 of FIG. , The signal inverted to the logic L by the inverter 37 is supplied to the MIMO transistor N33 and the inverter 38. The NMOS transistor N33 is turned off by the signal of the logic L input to its gate.

On the other hand, the signal of the logic L input to the input terminal of the inverter 38 is inverted to the signal of the logic H, input to the gate of the NMOS transistor N34, and the NMOS transistor N34 is turned on. Then, the node 36 connected to the drain of the NMOS transistor N34 is pulled down to the low level, and the MOSFET P31 whose gate input is the potential of the node 36 is turned on. At the same time, the NMOS transistor N31 whose gate input is the potential of the node 36 is turned off.

Further, the potential of the node 35 is raised to a high level of the power supply voltage VL. Therefore, the MIMO transistor P32 whose gate input is the potential of the node 35 is turned off. At the same time, the NMOS transistor N32 whose gate input is the potential of the node 35 is turned on. Therefore, a low-level signal having an amplitude of the power supply voltage VL is supplied to the inverter 39 to which the node 36 is connected to the input terminal, and the inverter 39 outputs the inverted logic H signal S4.

Next, when a low-level signal S3 having an amplitude of the power supply voltage VH is input from the logic circuit 12 to the level conversion circuit 14, the signal inverted to the logic H by the inverter 37 is sent to the MIMO transistor N33 and the inverter 38. Be entered. The NMOS transistor N33 is turned on by the signal of the logic H input to its gate.

On the other hand, the signal of the logic H input to the input terminal of the inverter 38 is inverted to the logic L and input to the gate of the NMOS transistor N34, and the NMOS transistor N34 is turned off. Then, the potential of the node 36 connected to the drain of the NMOS transistor N34 is raised to a high level of the power supply voltage VL. Therefore, the MIMO transistor P31 having the potential of the node 36 as the gate input is turned off. At the same time, the NMOS transistor N31 whose gate input is the potential of the node 36 is turned on.

Further, the node 35 is pulled down to the low level, and the MIMO transistor P32 having the potential of the node 35 as the gate input is turned on. At the same time, the NMOS transistor N32 whose gate input is the potential of the node 35 is turned off. Therefore, the high level of the amplitude of the power supply voltage VL is output to the inverter 39 to which the node 36 is connected to the input terminal, and the inverter 39 outputs the inverted logic L signal S4.

[0059] Hereinafter, the operation when either the value of the power supply voltage VH or VL fluctuates will be described.

[0060] First, when the power supply voltage VL is unstable and a fluctuation such as a momentary power failure or stop occurs, the logic circuit 11 to which the power supply voltage VL is supplied outputs a logic indefinite signal S1 and is a level conversion circuit. Enter in 13. Inverters 27 and 28 are also supplied with an unstable power supply voltage VL, so they output signals with undefined logic. Therefore, the conduction state of the NMOS transistors N23 and N24 is indefinite, and the potentials of the nodes 25 and 26 are also indefinite. However, since the full latch circuit of the level conversion circuit 13 can converge the potential difference in an expanded manner if there is a small potential difference between the nodes 25 and 26, the nodes 25 and 26 are in potential states in opposite directions. Can be maintained.

The operation of this full latch circuit will be described. For example, when the NMOS transistors N24 and N23 are turned on at the same time, the node 26 is pulled down to the low level by the MOSFET transistor N24 on the output side, so that a low-level signal with the amplitude of the power supply voltage VH is output to the inverter 29. ..

[0062] Further, when the NMOS transistors N24 and N23 are turned off at the same time, the nodes 25 and 26 are both in the floating state. In this case, if there is a slight difference in the potentials of the nodes 25 and 26, in the full latch circuit, the potential difference converges in the direction of expansion, and the node 26 sets either H or L of the amplitude of the power supply voltage VH level. The possessed signal is output to the inverter 29. Since the inverter 29 is supplied with the normal specified voltage VH, it operates normally, so that the level conversion circuit 13 is not affected by the fluctuation of the power supply voltage, and the logic is fixed to either H or L level. Output signal S2.

[0063] Next, when the power supply voltage VH is unstable and a fluctuation occurs that causes the voltage to be lower than the power supply voltage VL, the logic circuit 12 to which the power supply voltage VH is supplied has a logically undefined signal S3. Is output, and this signal S3 is input to the level conversion circuit 14. Inverters 37 and 38 are also supplied with an unstable power supply voltage VH, so they output signals with undefined logic. Therefore, the conduction state of the NMOS transistors N33 and N34 is indefinite, and the potentials of the nodes 35 and 36 are also indefinite. However, the full latch circuit constituting the level conversion circuit 14 can converge the potential difference between the two nodes 35 and 36 in the direction in which the difference increases as long as the nodes 35 and 36 have a small potential difference. Can maintain potential states in opposite directions.

[0064] The operation of this full latch circuit will be described. For example, when the NMOS transistors N33N34 are turned on at the same time, the node 36 is pulled down to the low level by the MOSFET transistor N34 on the output side, so that the logic L on the low voltage side of the VL level amplitude is output to the inverter 39. ..

[0065] Further, when the NMOS transistors N33 and N34 are turned off at the same time, the nodes 35 and 36 are both in the floating state. At this time, if there is a slight potential difference between the two, the potential difference between the nodes 35 and 36 converges in the direction of expansion, and the node 36 outputs a signal having either the amplitude of the power supply voltage VL level. .. Since the inverter 39 is supplied with the normal specified voltage, it operates normally, so that the level conversion circuit 14 outputs the signal S4 whose logic is fixed.

[0066] Hereinafter, the operation of the semiconductor integrated circuit shown in FIG. 1 will be described in more detail. When both the supplied power supply voltages VL and VH are normal, the signal S1 having the amplitude of the power supply voltage VL output from the logic circuit 11 is input to the level conversion circuit 13, and the level conversion circuit 13 is L / H. The conversion operation is performed, the amplitude of the power supply voltage VL is converted into a signal having the amplitude of the power supply voltage VH, and the signal S2 is output. This signal S2 is input to the logic circuit 12, and the logic circuit 12 performs a predetermined logic process.

On the other hand, the signal S3 having the amplitude of the power supply voltage VH output from the logic circuit 12 is input to the level conversion circuit 14. The level conversion circuit 14 performs the above H / L conversion operation, converts the amplitude of the power supply voltage VH into a signal having the amplitude of the power supply voltage VL, and outputs the signal S4. This signal S4 is input to the logic circuit 11, and the logic circuit 11 performs a predetermined logic process.

[0068] Here, when either one of the power supply voltage VL and VH fluctuates, it becomes as follows.

[0069] For example, when the power supply voltage VL is unstable and fluctuates such that it momentarily stops or stops, the logic circuit 11 to which the power supply voltage VL is supplied first converts the signal S1 whose logic is indefinite into a level conversion circuit. Output to 13. Since the level conversion circuit 13 uses the full latch circuit shown in FIG. 2 above, it is possible to prevent the through current flowing through the full latch circuit to which the power supply voltage VH is supplied. Further, since a logically fixed signal having an amplitude of the power supply voltage VH is input to the inverter 29 in FIG. 2, there is no possibility that a through current will flow through the inverter 29 as well. Since the normal specified voltage VH is supplied to the inverter 29, a signal with a fixed logic is output. Therefore, no through current flows through the logic circuit 12 that operates at the power supply voltage VH. Further, since the logic circuit 12 is supplied with the normal power supply voltage VH, the logic-defined signal S3 is output to the level conversion circuit 14.

On the other hand, the level conversion circuit 14 shown in FIG. 3 will be described. Since the power supply voltage VH is supplied to the inverters 37 and 38 attached to the full latch circuit of the level conversion circuit 14, a signal having a normal logic level is output. For example, if the signal S3 is a logic L, the NMOS transistor N33 is in the ON state and N34 is in the OFF state. In this case, since the node 35 is surely at the ground potential, the MIMO transistor N32 is in the off state and the MOSFET transistor P32 is in the on state.

[0071] Here, considering that the unstable state of the power supply voltage VL is a momentary power failure or a stop state, the potential of the node 36 is slightly lower than that, if not lower than the ground potential equal to the potential of the node 35. It is considered to be a high degree. Therefore, it can be said that there is an extremely high possibility that the NMOS transistor N31 will also be turned off.

On the contrary, when the signal S3 is a logic H, the NMOS transistor N33 is turned off and N34 is turned on. In this case, the node 36 is surely at the ground potential, and the NMOS transistor N31 is turned off. In this case, the potential of the node 35 becomes unstable, but for the same reason as described above, there is a high possibility that the NMOS transistor N32 will also be turned off.

[0073] As described above, even when the power supply voltage VL is unstable, almost no through current flows through the level conversion circuit 14.

Further, when the NMOS transistor N34 is in the ON state due to the output of the H level of the inverter 38, the potential of the node 36 becomes low level. However, since the power supply voltage VL of the inverter 39 is unstable, the output signal S4 becomes indefinite. On the other hand, when the NMOS transistor N34 is in the off state, the node 36 is supplied with an unstable power supply voltage VL, and therefore outputs a signal having this unstable amplitude VL. That is, when a logic circuit is provided in front of the output of the level conversion circuit and the power supply voltage supplied to the logic circuit fluctuates, the output has an unstable amplitude VL regardless of the output signal of the full latch circuit in the previous stage. A signal is output.

However, in most cases, such an unstable state is a momentary power failure or stop, the power supply voltage VL is an extremely low voltage, and it can be said that the output signal is often at a low level. .. That is, this full latch circuit outputs a signal at a level close to the low level of the power supply voltage VL.

[0076] In the inverter 39 and the logic circuit 11, even if a signal having an indefinite logic is input, a through current does not flow in the inverter 39 and the logic circuit 11 because the supplied power supply voltage VL is low.

[0077] Therefore, even if one of the power supply voltages VL becomes unstable, it is possible to reliably prevent the through current flowing through the logic circuit or the like to which the power supply voltage VH maintaining the normal specified voltage is supplied, and the semiconductor. Since the through current can be prevented in the integrated circuit as a whole, wasteful power consumption can be reduced.

At this time, an unstable power supply voltage VL is supplied to the logic circuit 15, but since it is considered that the power supply voltage VL is in an unstable state in most cases, it is considered to be in a momentary power failure or a stop state. Outputs a signal with a low-level logic level of voltage VL. In addition, there is no risk of a through current flowing.

[0079] On the other hand, when the power supply voltage VH is unstable and a momentary power failure occurs and the voltage becomes lower than the normal power supply voltage VL, the logic circuit to which the power supply voltage VH is supplied first occurs. 12 outputs a signal S3 whose logic is indefinite to the level conversion circuit 14. Since the level conversion circuit 14 uses the full latch circuit shown in FIG. 3 above, it is possible to prevent the through current flowing through the full latch circuit to which the power supply voltage VL is supplied. Further, since a logically fixed signal having an amplitude of the power supply voltage VL is input to the inverter 39 of FIG. 3, there is no possibility that a through current will flow through the inverter 39 as well. Since the power supply voltage VL having a normal specified voltage is supplied to the inverter 39, the signal S4 whose logic is determined is output. Therefore, no through current flows through the logic circuit 11 that operates at the power supply voltage VL.

Further, since the logic circuit 11 is supplied with the normal power supply voltage VL, the logic-determined signal S1 is output to the level conversion circuit 13.

Next, the level conversion circuit 13 shown in FIG. 2 will be described. Since the power supply voltage VL is supplied to the inverters 27 and 28 attached to the full latch circuit of the level conversion circuit 13, a signal having a normal logic level is output. For example, if the signal S1 is a logic L, the NMOS transistor N23 is in the ON state and N24 is in the OFF state. In this case, since the node 25 is surely at the ground potential, the MIMO transistor N22 is in the off state and the MOSFET transistor P22 is in the on state.

[0082] Here, as a factor that makes the power supply voltage VH unstable, considering a momentary power failure or a stop state as in the case of the power supply voltage VL, the potential of the node 26 is up to the same ground potential as the potential of the node 25. If not low, it is considered to be slightly higher. Therefore, it can be said that there is an extremely high possibility that the NMOS transistor N21 will also be turned off.

[0083] On the contrary, when the signal S1 is a logic H, the NMOS transistor N23 is turned off and N24 is turned on. In this case, the node 26 is surely at the ground potential, and the NMOS transistor N21 is turned off. In this case, the potential of the node 25 becomes unstable, but for the same reason as described above, there is a high possibility that the NMOS transistor N22 will also be turned off.

[0084] As described above, even when the power supply voltage VH is unstable, almost no through current flows through the level conversion circuit 13.

[0085] Further, when the NMOS transistor N24 is in the ON state due to the output of the H level of the inverter 28, the potential of the node 26 becomes low level. However, since the power supply voltage VH of the inverter 29 is unstable, the output signal S2 becomes indefinite. On the other hand, when the NMOS transistor N24 is in the off state, the node 26 is supplied with an unstable power supply voltage VH, and therefore outputs a signal having this unstable amplitude VH. That is, when a logic circuit is provided in front of the output of the level conversion circuit and the power supply voltage supplied to the logic circuit fluctuates, the output has an unstable amplitude VL regardless of the output signal of the full latch circuit in the previous stage. A signal is output. That is, when a logic circuit is provided in front of the output of the level conversion circuit and the power supply voltage supplied to the logic circuit fluctuates, the output has an unstable amplitude VH regardless of the output signal of the full latch circuit in the previous stage. A signal is output.

[0086] However, in most cases, such an unstable state is a momentary power failure or stop, the power supply voltage VH is an extremely low voltage, and it can be said that the output signal is often at a low level. .. In other words, this full latch circuit outputs a signal with a level close to the low level of the power supply voltage VH.

[0087] In the inverter 29 and the logic circuit 12, even if a signal with undefined logic is input, it is considered that most of the unstable states of the supplied power supply voltage VL are momentary power failure or stop, and the power supply voltage VL. Is very low voltage and low, so there is no risk of through current flowing.

[0088] As described above, even if one of the power supply voltages VH becomes unstable, it is possible to reliably prevent the through current flowing through the logic circuit or the like to which the power supply voltage VL that maintains the normal specified voltage is supplied. As a result, the through current can be reduced for the entire semiconductor integrated circuit, so that wasteful power consumption can be reduced.

At this time, the logic circuit 11 has an input from the logic circuit 15, but since the normal power supply voltage VL is supplied, there is no possibility that a through current will flow. Further, a signal having a normal logic level can be output from the logic circuit 15 to the logic circuit 11.

[0090] Even if one of the two power supply voltages VL and VH becomes unstable in this way, if a normal specified voltage is supplied from the other power supply, the normal power supply voltage is supplied. Since the logic circuit and the level conversion circuit having a full latch circuit that supplies the level conversion output to this logic circuit operate by the signal of the normal logic level, the through current in these circuits is surely prevented, and the entire semiconductor integrated circuit is prevented. Since the through current flowing through the circuit can be significantly reduced, the power consumption can be reduced.

FIG. 4 is a block diagram showing the configuration of the second embodiment. In this embodiment, a power supply voltage VM intermediate between the power supply voltage VL and the power supply voltage VH is supplied to the logic circuit 42, and this power supply voltage is shown as being supplied from the black circle power supply terminal in FIG. There is.

As shown in FIG. 4, in the semiconductor integrated circuit of this embodiment, the power supply voltages VL and VH are supplied from the outside to the DRAM macro 10A formed on the silicon substrate. This DRAM macro 10A is supplied with an internal voltage generation circuit 40 that generates an internal voltage VM that is lower than the power supply voltage VH and higher than VL, and a power supply voltage VL, which is the amplitude of the level of the voltage VL. The logic circuit 41 that outputs the signal S5 with the power supply voltage VL and the power supply voltage VL and the internal voltage VM are supplied, and the output signal S5 from this logic circuit 41 is converted from the amplitude of the power supply voltage VL to the signal S6 having the amplitude of the internal voltage VM. Level conversion circuit 43 to be supplied, a logic circuit 42 to which an internal voltage VM is supplied and outputs a signal S7 having the amplitude of the internal voltage VM, and a power supply voltage VL and an internal voltage VM to be supplied and an output signal S7 from the logic circuit 42. Is formed with a level conversion circuit 44 that converts the voltage from the amplitude of the internal voltage VM to the signal S8 having the amplitude of the voltage VL.

Further, a power supply voltage VL is supplied to the outside of the DRAM macro 10A and in the same semiconductor substrate, and a logic circuit 45 directly connected to the logic circuit 41 is formed.

The level conversion circuit 43 corresponds to the level conversion circuit 13 shown in FIG. 2, and the level conversion circuit 44 corresponds to the level conversion circuit 14 shown in FIG. However, with respect to the operation description and the reference drawing, the description is omitted because the configuration and operation are the same as described above except that the power supply voltage VM is supplied instead of the power supply voltage VH. Further, the logic circuit 41 whose operating voltage is the power supply voltage VL on the low voltage side includes, for example, a control circuit for controlling the DRAM macro 10A, a decoding circuit for decoding the address of the memory cell array, and the like, and the power supply voltage on the high voltage side. The logic circuit 42 having a VM as an operating voltage includes, for example, a sense amplifier and the like. Further, the logic circuit 45 connected to the previous stage of the logic circuit 41 includes, for example, an address buffer circuit.

Next, the operation of the semiconductor integrated circuit of the second embodiment shown in FIG. 4 will be described with reference to FIGS. 2 to 4.

[0096] The internal voltage generation circuit 40 is supplied with the power supply voltage VH and generates an internal voltage VM higher than the power supply voltage VL and lower than the power supply voltage VH. The logic circuit 42 to which this internal voltage VM is supplied outputs a signal S7 having the amplitude of the internal voltage VM to the level conversion circuit 44. This level conversion circuit 44 converts the signal S7 from the amplitude of the internal voltage VM to the amplitude of the power supply voltage VL, and outputs the signal S8.

[0097] On the contrary, the logic circuit 41 outputs the signal S5 having the amplitude of the power supply voltage VL to the level conversion circuit 43. This level conversion circuit 43 converts the signal S5 from the amplitude of the power supply voltage VL to the amplitude of the internal voltage VM, and outputs the signal S6.

[0098] Further, the logic circuit 45 formed outside the DRAM macro 10A outputs a signal having an amplitude of the power supply voltage VL to the logic circuit 41.

Next, the operation of the semiconductor integrated circuit of the present embodiment when either the power supply voltage VM or VL fluctuates will be described.

[0100] First, when the power supply voltage VL is unstable and fluctuates such that it momentarily stops or stops, the logic circuit 41 to which the power supply voltage VL is supplied outputs a logic indefinite signal S5, and this signal. S5 is input to the level conversion circuit 43. The level conversion circuit 43 differs only in that the internal voltage VM is supplied instead of the power supply voltage VH supplied to the full latch circuit and the inverter 29 in FIG. 2, and detailed explanation of its configuration and operation is omitted. To do. Therefore, as described in FIG. 2, since this level conversion circuit 43 also uses a full latch circuit inside, the through current flowing through the full latch circuit despite the unstable power supply voltage VL being supplied. Can be prevented. Moreover, since a stable power supply voltage VM is supplied, no through current flows through the inverter 29. Since the inverter 29 is supplied with the specified voltage VM, it outputs the signal S6 whose logic is fixed. Therefore, no through current flows through the logic circuit 42. Further, the logic circuit 42 is supplied with a normal internal voltage VM, and outputs a signal S7 having a fixed logic to the level conversion circuit 44.

Therefore, the operation of each transistor of the full latch circuit of the level conversion circuit 44 is normal. However, since the supplied power supply voltage VL is unstable, a low-level signal is output to the node 36 when the NMOS transistor N34 in FIG. 3 is in the on state, and an unstable power supply voltage is output when it is in the off state. Outputs a signal with VL amplitude. However, at this time, the power supply voltage VL is in a momentary power failure or stop state and is an extremely low voltage, and the output signal S8 can always be said to be at a low level. That is, the full latch circuit of this level conversion circuit 44 outputs a low level signal of the power supply voltage VL.

Further, in the inverter 39 in FIG. 3 and the logic circuit 41 in FIG. 4, even if a signal having an undefined logic is input, the supplied power supply voltage VL is low and no through current flows. Also, since the logic circuit 45 is also supplied with an unstable power supply voltage VL, the signal inside it is also a signal with an indefinite logic level, but since the supplied power supply voltage VL is very low, the penetration current is inside it. Not flowing.

Therefore, even in the embodiment of FIG. 4, even if the power supply voltage VL is unstable, the through current flowing through the logic circuit 42 or the like to which the power supply voltage VM maintaining the specified voltage is supplied is surely prevented. This makes it possible to significantly reduce the through current of the semiconductor integrated circuit as a whole, so that wasteful power consumption can be reduced.

At this time, an unstable power supply voltage VL is supplied to the logic circuit 45, but since it is considered that the power supply voltage VL is in an unstable state in most cases, it is considered to be in a momentary power failure or a stop state. Outputs a signal with a low-level logic level of voltage VL. In addition, there is no risk of a through current flowing.

Next, a case where the amplitude level of the internal voltage VM also fluctuates as the power supply voltage VH fluctuates will be described. An unstable power supply voltage VH is supplied to the internal voltage generation circuit 40. Therefore, the internal voltage generation circuit 40 outputs an unstable internal voltage VM. This unstable internal voltage VM is supplied to the logic circuit 42, so that the logic circuit 42 outputs a logic indefinite signal S7 and inputs it to the level conversion circuit 44. The level conversion circuit 44 has the same configuration and operation except that the power supply voltage VH supplied to the inverter 37 and the inverter 38 shown in FIG. 3 is replaced by the internal voltage VM.

[0106] Since the level conversion circuit 44 uses the full latch circuit as described with reference to FIG. 3, it is possible to prevent the through current flowing through the full latch circuit to which the normal power supply voltage VL is supplied. Further, since a signal having a stable logic level due to the power supply voltage VL is input to the inverter 39, no through current flows through the inverter 39. Therefore, since the inverter 39 is supplied with the power supply voltage VL having the specified voltage, the signal S8 having the correct logic is output. Therefore, the logic circuit 41 performs a normal logic operation, and no through current flows through the logic circuit 41. Further, the logic circuit 41 is supplied with the normal power supply voltage VL, and the signal S5 of the correct logic level is output. Therefore, no through current flows through the level conversion circuit 43.

[0107] As described above, the penetration current flowing through the logic circuit 41 or the like to which the power supply voltage VL maintaining the specified voltage is supplied can be reliably prevented, and the penetration current of the entire semiconductor integrated circuit can be reduced. Therefore, wasteful power consumption can be reduced.

The logic circuit 41 has an input from the logic circuit 45, which is a signal having a stable power supply voltage VL amplitude with a fixed logic level. Therefore, neither the logic circuit 45 nor the logic circuit 41 receives a signal having a stable logic level, so that no through current flows. Further, since the supplied power supply voltage VL also holds the specified voltage, the logic circuit 41 outputs a signal with a fixed logic.

[0109] As described above, even if the power supply voltage of one of the two power supply voltages becomes unstable, the logical operation of the circuit to which the power supply voltage of the other power supply is supplied is normal, so that the power supply voltage is this power supply voltage. In the logic circuit to which is supplied, the through current can be reliably prevented, and the through current flowing through the entire semiconductor integrated circuit can be reduced, so that the power consumption can be reduced.

[0110] Hereinafter, a third embodiment in which the present invention is applied to a sense amplifier unit used in a dynamic RAM will be described with reference to FIG.

[0111] In FIG. 5, for example, the DRAM macro 10B on the semiconductor substrate is supplied with a power supply voltage VL having a low voltage and a power supply voltage VH having a voltage higher than the power supply voltage VL in order to suppress power consumption. ..

As shown in FIG. 5, the semiconductor integrated circuit of the present embodiment includes a logic circuit 50 and a power supply voltage detection circuit 51 to which a power supply voltage VL is supplied and an output signal S11 is output to level conversion circuits 531 and 532,533. Have. The power supply voltages VL and VH are supplied to the power supply voltage detection circuit 51. When the specified power supply voltages VL and VH are supplied, the power supply voltage detection circuit 51 outputs a high-level signal of the amplitude of the power supply voltage VL, and one of the supplied power supply voltages VL and VH is used. When it fluctuates, it detects this and outputs a low-level detection signal with an amplitude of the power supply voltage VL level to the level conversion circuit 531,532,533 connected to the output terminal side.

[0113] The level conversion circuit 531,532,533 is supplied with the logic output signal S11 from the logic circuit 50, and is also supplied with the detection signal S10 from the power supply voltage detection circuit 51. Here, the logic output signal S11 of the logic circuit 50 is supplied as an inverting signal via the inverter 57 only when it is supplied to the level conversion circuit 532.

The power supply voltages VH and VL are supplied to these level conversion circuits 531, 532, and 533, respectively, and the level of the signal S11 input from the logic circuit 50 is changed from the value corresponding to the amplitude of the power supply voltage VL to the power supply voltage VH. It is converted into a signal with a value corresponding to the amplitude of. As will be described in detail later, these level conversion circuits 531,532,533 are used to output a signal having one level of the amplitude of the power supply voltage VH when the level of either the power supply voltage VH or VL fluctuates. It is configured.

[0115] An output signal S12 is output from the level conversion circuit 531. This signal S12 is supplied to an inverter 56 driven by a power supply voltage VH, its logic is inverted, and a signal S13 having an amplitude of voltage VH is output. To.

[0116] The inverter 56 is connected to the gate terminal of the PMOS transistor P54. The source terminal of this PCOS transistor P54 is connected to the power supply voltage VL, and the drain terminal is connected to one power supply terminal of the sense amplifier 52. The PCOS transistor P54 is turned off by a signal of logic level H having a level of power supply voltage VH supplied to its gate terminal, and turned on by a signal of logic level L.

[0117] A signal S14 is output from the output terminal of the level conversion circuit 533, and this output terminal is connected to the gate terminal of the NMOS transistor N55. The source terminal of the NMOS transistor N55 is connected to the power supply terminal of the power supply voltage VL, and the drain terminal is connected to the other power supply terminal of the sense amplifier 52. This NMOS transistor N55 is turned on when a signal having the level of logic H by the power supply voltage VH from the level conversion circuit 533 is supplied to the gate terminal, and is turned off by the signal of logic L.

[0118] The sense amplifier 52 supplies the power supply voltage VL when both the MOSFET P54 and the NMOS transistor N55 are turned on, and connects the word line WL and the bit line BL, / BL connected to the signal input terminal. It has a signal input terminal connected to, for example, bit lines BL, / BL of a cell array 512 having a plurality of memory cells MC arranged in a matrix at intersections.

[0119] The inverter 57 has an input terminal into which the signal S11 from the logic circuit 50 is input, and outputs a signal in which the logic of the signal S11 is inverted to the level conversion circuit 532. The level conversion circuit 532 receives the inverting signal from the inverter 57, outputs the level conversion signal S15, and supplies the level conversion signal S15 to the gate terminal of the NMOS transistor N58.

[0120] This NMOS transistor N58 has a source terminal and a drain terminal connected between the power supply terminals (510, 511) of the sense amplifier 52. When both the polymerase transistor P54 and the NMOS transistor N55 are in the off state, when the signal S15 having a high level of the amplitude of the power supply voltage VH is input to the gate terminal, the NMOS transistor N58 is turned on. As a result, the electric charge remaining on the power supply line of the sense amplifier 52 is discharged via the NMOS transistor N58, and the potential of the power supply line of the sense amplifier 52 is equalized, that is, equalized.

[0121] Further, outside the DRAM macro 10B, a logic circuit 59 is provided so as to supply a power supply voltage VL and supply a logic signal to the logic circuit 50.

Next, the configuration and operation of the level conversion circuit 531 used in the embodiment shown in FIG. 5 will be described with reference to FIG. The other level conversion circuits 532 and 533 are also configured in the same manner.

[0123] In FIG. 6, the full latch circuit included in the level conversion circuit 531 is composed of two NMOS transistors P61 and P62 and two NMOS transistors N61 and N62. The source of the polymerase transistors P61 and P62 is connected to the high voltage side power supply terminal of the power supply voltage VH, is connected to the drain terminal of the MIMO transistor N61 at node 68, and is connected in common with the gate of the MIMO transistor N62 and the MIMO transistor P62. The transistor.

[0124] At the node 69, the drain terminal of the MIMO transistor P62 is connected to the drain terminal of the NMOS transistor N62, and is also connected in common with the gate of the NMOS transistor N61 and the MIMO transistor P61. The sources of the NMOS transistors N61 and N62 are commonly connected to the ground potential via the NMOS transistors N65.

[0125] The level conversion circuit 531 further includes the full latch circuit, the input terminal IN50 of the logic signal input by the power supply voltage VL level signal S11 from the logic circuit 50, and the power supply voltage VL level from the power supply voltage detection circuit 51. It has an input terminal IN51 to which a detection signal is input.

[0126] The input terminal IN50 is connected to the gate terminal of the NMOS transistor N63, and is also connected to the gate terminal of the NMOS transistor N64 via the inverter 610 urged by the power supply voltage VL. The drain terminal of the NMOS transistor N63 is connected to the node 68, and the drain terminal of the NMOS transistor N64 is connected to the node 69.

[0127] The input terminal IN51 to which the detection signal from the power supply voltage detection circuit 51 is supplied is connected to the input terminal of the inverter 611 urged by the power supply voltage VL via the gate of the NMOS transistor N65. The output terminal of the inverter 611 is commonly connected to the gate of the NMOS transistors N66 and N67.

[0128] The drain terminal of the NMOS transistor N66 is connected to the node 69, and the source terminal is grounded. The node 69 is connected to the inverter 612 to which the power supply voltage VH is supplied and the input terminal is input to the output signal of the full latch circuit via the node 69. The output terminal of the inverter 612 is connected to the input terminal of the inverter 613 to which the power supply voltage VH is supplied. The output terminal of the inverter 613 is connected to the drain of the NMOS transistor N67, and the source terminal of the NMOS transistor N67 is grounded.

[0129] Hereinafter, an example of the circuit configuration of the sense amplifier 52 applied to the present embodiment shown in FIG. 5 will be described with reference to FIG. 7.

[0130] In FIG. 7, the sense amplifier 52 has one bit wire BLI commonly connected to the gate of the MOSFET P72 and the NMOS transistor N72 at the node 711 and to the drain of the MOSFET P71 and the NMOS transistor N71. Connected in common.

[0131] At node 712, the other bit wire / BLI is commonly connected to the gate of the MOSFET P71 and the NMOS transistor N71, and is commonly connected to the drain of the MOSFET P72 and the NMOS transistor N72.

Further, the sense amplifier drive lines 510 and 511 are connected to the source and drain terminals of the NMOS transistor N58, which is an equalizing element, respectively.

One end of this bit line BL is connected to the bit line BL via an NMOS transistor N78 whose gate is connected to one shared selection signal line MUXR, and the other end of the bit line BLI is shared with the other gate. It is connected to the bit line BLL via the NMOS transistor N75 connected to the selection signal line MUXL.

One end of the other bit line / BLI is connected to the bit line / BL via an NMOS transistor N79 whose gate is connected to one shared selection signal line MUXR, and the other end of the bit line BL2 has a gate. It is connected to the bit line / BLL via the NMOS transistor N76 connected to the other shared selection signal line MUXL.

[0135] Further, the bit line pairs BLI and / BLI are connected to the local data line pairs DQ1 and DQ2, respectively, via the NMOS transistors N73 and N74 whose gates are connected to the column selection line CSL.

[0136] Further, an NMOS transistor N77 having a gate connected to one equalized signal line EQLR is connected between the bit line pairs BL and / BL, and one bit line pair BLL and / BLL have a gate on the other side. The NMOS transistor N80 connected to the equalize signal line EQLL is connected.

[0137] Note that detailed description of the driver circuit for driving the signal lines EQLR, EQLL, MUXR, MUXL, and CSL will be omitted.

Next, the operation of the present embodiment will be described with reference to FIGS. 5 to 7.

First, a case where the sense amplifier circuit 52 is operated to amplify the read signal read from the memory cell MC and supplied from the bit line pair BLI and / BLI will be described.

[0140] In order to operate the sense amplifier circuit 52, it is necessary to supply the VL power supply voltage to the sense amplifier circuit 52 via the MOSFET transistor P54 and the NMOS transistor N55. Therefore, the logic circuit 50 outputs the signal S11 of the logic H having the amplitude of the power supply voltage VL level. The logic circuit 50 outputs a logic H signal S11 having an amplitude of the power supply voltage VL level by a signal from the logic circuit 59 formed outside the DRAM macro 10B, for example.

[0141] Further, when the two power supply voltages VL and VH are in the range of the specified value, the power supply voltage detection circuit 51 outputs a detection signal of the logic H having an amplitude of the power supply voltage VL level. This signal S11 and the detection signal are supplied to the level conversion circuits 531, 532, and 533.

As shown in FIG. 6, for example, the detection signal of the logic H input to the level conversion circuit 531 is input from the input terminal IN51 to the gate terminal of the NMOS transistor N65, and the NMOS transistor N65 is turned on. Further, the detection signal is input to the inverter 611 and inverted to the logic level L. The signal of this logic level L is input to the gate terminal of the NMOS transistors N66 and P67, and these NMOS transistors N66 and N67 are turned off.

On the other hand, from the logic circuit 50, a signal S11 having a logic H level of the power supply voltage VL level is supplied to the input terminal IN50. This signal S11 is input to the gate of the NMOS transistor N63 and the inverter 610. The NMOS transistor N63 is turned on by the signal of the logic H input to its gate. On the other hand, the logic H signal S11 input to the input terminal of the inverter 62 is inverted to the logic L signal / S11 and input to the gate of the NMOS transistor N64 to turn it off.

As a result, the node 68 connected to the drain of the NMOS transistor N63 is pulled down to the low level, and the MOSFET P62 having the potential of the node 68 as the gate input is turned on. At the same time, the NMOS transistor N62 whose gate input is the potential of the node 68 is turned off.

Further, when the NMOS transistor N64 is turned off, the potential of the node 69 is raised to the power supply voltage VH. Therefore, the MIMO transistor P61 whose gate input is the potential of the node 69 is turned off, and at the same time, the MIMO transistor N61 whose gate input is the potential of the node 69 is turned on. Therefore, the node 69 becomes the potential of the power supply voltage VH.

Here, since the NMOS transistor N66 connected to the node 69 is in the off state as described above, the signal of the level of the power supply voltage VH is transmitted through the inverters 612 and 613 to which the power supply voltage VH is supplied. Supplied to the output node. Since the NMOS transistor N67 connected to this output node is also in the off state, the output node is at the potential of the power supply voltage VH, and the level conversion circuit 531 outputs the signal S12 having the logical H level of the power supply voltage VH. To do.

[0147] The other level conversion circuits 532 and 533 also have the configuration shown in FIG. 6 like the level conversion circuit 531 and perform the same operation.

The level conversion circuit 531 shown in FIG. 5 outputs a signal S12 having a logical H level of the power supply voltage VH level to the inverter 56 connected to the output terminal. The inverter 56 inverts the logic of the signal S12 and outputs the signal S13 having the logic L level of the power supply voltage VH level. This signal S13 is input to the gate terminal of the MIMO transistor P54 to turn on the transistor P54.

On the other hand, since the level conversion circuit 533 outputs a signal S14 having a logic H level of the power supply voltage VH level to the gate terminal of the NMOS transistor N55, this transistor N55 is also turned on. Therefore, the power supply voltage VL is supplied to the sense amplifier circuit 52, and the sense amplifier circuit 52 is put into the operating state.

[0150] In the present embodiment, signals S13 and S14 having an amplitude of a power supply voltage VH level converted to a level are supplied to the gate terminals of the MOSFET transistor P54 and the NMOS transistor N55. By supplying the signals S13 and S14 having the amplitude of the power supply voltage VH level in this way, the transistors P54 and N55 are sufficiently turned on. As a result, the power supply voltage VL is sufficiently supplied to the sense amplifier circuit 52, and the sense amplifier circuit 52 can be operated without slowing down the operating speed.

Further, an inverter 57 is connected to the input side of the signal S11 of the level conversion circuit 532. This inverter 57 inverts the logic of the signal S11 from the logic circuit 50 and outputs it. Therefore, a signal having a logical L level of the power supply voltage VL level is input to the level conversion circuit 532. Since the signal / S11 of this logic L is supplied to the input terminal IN50 in FIG. 6, the NMOS transistor N63 on the input side of the full latch circuit is in the off state and the NMOS transistor N64 is in the on state, contrary to the case of the level conversion circuit 531 and 533. It becomes.

As a result, when the transistors P54 and N55 are turned on by the output signals S13 and S14 of the level conversion circuits 531 and 533, the transistor N58 is turned off by the output signal S15 from the level conversion circuit 532 and the sense amplifier is turned on. The circuit 52 is in the operating state. On the contrary, when the transistors P54 and N55 are turned off by the output signals S13 and S14 of the level conversion circuits 531 and 533, the transistor N58 is turned on by the output signal S15 from the level conversion circuit 532 and the sense amplifier circuit 52 is turned on. In the non-operating state, the transistor N58 equalizes the potential of the power supply circuit of the sense amplifier circuit 52.

[0153] Hereinafter, with reference to FIG. 6, a signal S11 having a logic L level of the power supply voltage VL level is input to the input terminal from the logic circuit 50 side of the level conversion circuit 531-533, and the power supply voltage detection circuit 51 The operation of the level conversion circuit when the signal S10 having the logical H level of the power supply voltage VL level is input to the input terminal on the side will be described.

[0154] First, as described above, the transistors N65 are turned on and the transistors N66 and N67 are turned off by the detection signal from the power supply voltage detection circuit 51.

On the other hand, a signal having a logical L level of the power supply voltage VL level from the logic circuit 50 is supplied to the gate of the transistor N63 and the inverter 610. The signal of the logic L supplied to the gate of the transistor N63 turns off the transistor N63.

On the other hand, the signal of the logic L supplied to the input terminal of the inverter 610 is inverted to the signal of the logic H and input to the gate of the transistor N64 to turn on the transistor N64. Then, the node 69 connected to the drain of the transistor N64 is pulled down to the low level, and the transistor P61 having the potential of the node 69 as the gate input is turned on. At the same time, the transistor N61 whose gate input is the potential of the node 69 is turned off.

[0157] Further, the potential of the node 68 is raised to a high level of the power supply voltage VH. Therefore, the transistor P62 having the potential of the node 68 as the gate input is turned off. At the same time, the transistor N62 whose gate input is the potential of the node 69 is turned on. Therefore, the node 69 has a low level potential of the power supply voltage VH amplitude.

Since the transistor N66 connected to the node 69 is in the off state, a signal having a logical L level of the power supply voltage VH level is supplied to the inverters 612 and 613 to which the power supply voltage VH is supplied. .. Since the transistor N67 connected to the output node is also in the off state, the level conversion circuits 531 and 533 output signals having a logical H level of the power supply voltage VH level, respectively. The signal S13 having the logical H level of the power supply voltage VH level output from the level conversion circuit 531 is inverted to the logical L level, and P54 is turned on. Further, the signal S14 having the logical H level of the power supply voltage VH level output from the level conversion circuit 533 turns N55 on.

On the other hand, since the level conversion circuit 532 outputs the signal S15 having the level of the logic L of the power supply voltage VH level, the transistor N58 is turned off. Therefore, when the transistors P54 and N55 are brought into the state by the output signals S13 and S14 of the level conversion circuits 531 and 533, the transistor N58 is turned off by the output signal S15 from the level conversion circuit 532 and the sense amplifier circuit 52 is in the operating state. It becomes. Therefore, when the sense amplifier circuit 52 is in the operating state, the power line potential equalization operation by the transistor N58 is not performed.

Next, the operation of the present embodiment in the case of equalizing the potential on the power supply terminal of the power supply voltage VL supplied to the sense amplifier circuit 52 will be described.

[0161] In order to equalize the potential on the power supply line, the logic circuit 50 outputs the signal S11 of the logic L having the amplitude of the power supply voltage VL level.

[0162] A signal S11 having a logical L level of the power supply voltage VL is input from the logic circuit 50 to the level conversion circuits 531 and 533, and a signal having a logical H level of the power supply voltage VL is input from the power supply voltage detection circuit 51. S10 inputs. As a result, as described above, the signals S13 and S14 having the logical L level of the power supply voltage VH level are output.

[0163] On the other hand. A signal / S11 having a logical H level of the power supply voltage VL whose logic is inverted by the inverter 57 is input to the level conversion circuit 532, and a signal having a logical H level of the power supply voltage VL is input from the power supply voltage detection circuit 51. Enter. As a result, as described above, the signal S15 having the logical H level of the power supply voltage VH level is output.

Therefore, when the transistors P54 and N55 are turned off by the output signals S13 and S14 of the level conversion circuits 531 and 533, the transistor N58 is turned on by the output signal S15 from the level conversion circuit 532 and the sense amplifier circuit. 52 is in the non-operating state, and the potential of the power supply circuit of the sense amplifier circuit 52 is equalized by the transistor N58.

[0165] Here, a case where the power supply voltage detection circuit 51 detects that one of the power supply voltages VH and VL is not within the specified voltage range will be described.

[0166] First, a case where the power supply voltage VH is unstable and becomes a voltage lower than VL will be described.

[0167] The power supply voltage detection circuit 51 that detects the fluctuation of the power supply voltage VH outputs a detection signal having a logical L level of the power supply voltage VL level. The detection signal of this logic L is input to the transistor N65 of the level conversion circuits 531, 532 and 533, and this transistor N65 is turned off. As a result, the power supply voltage VH is not supplied to the full latch circuit, and the full latch circuit cannot operate normally. However, as described above, it is possible to prevent a through current from flowing through the full latch circuit even though the supplied power supply voltage VH fluctuates, and wasteful power consumption can be reduced.

Further, the detection signal is inverted to the logic H by the inverter 611, and the transistors N66 and N67 are turned on. Therefore, the node 69 connected to the transistor N66 and the output node connected to the transistor N67 are pulled down to the ground potential. Therefore, the level conversion circuit 531-533 outputs a signal of the ground potential without being influenced by the output signal of the logic circuit 50. That is, the level conversion circuits 531, 532 and 533 all output low-level signals of the power supply voltage VH level.

[0169] The signal S12 having the logical L level output from the level conversion circuit 531 is input to the inverter 56. However, since the fluctuating power supply voltage VH is supplied to this inverter 56, the logic of the output is not fixed. However, since the logic of the input signal is fixed, no through current flows. Further, the logic-undefined signal S13 is supplied to the transistor P54, and the conduction state of the transistor P54 is also undefined.

However, the signal S14 having the logical L level output from the level conversion circuit 533 is input to the gate terminal of the transistor N55 and is completely turned off. Therefore, even if the conduction state of the transistor P54 is unknown, the power supply voltage VL is not supplied to the sense amplifier circuit 52, and the through current does not flow through the sense amplifier circuit 52.

[0171] Further, the signal S15 having the logical L level output from the level conversion circuit 532 turns off the transistor N58. Therefore, when the power supply voltage VH fluctuates, not only the through current does not flow in the sense amplifier circuit 52, but also the current does not flow through the transistor N58. Therefore, the penetrating current of the entire semiconductor integrated circuit is significantly reduced, so that wasteful power consumption can be reduced.

[0172] Next, a case where the power supply voltage VL is unstable and the power supply voltage VL is momentarily stopped or stopped will be described.

[0173] The power supply voltage detection circuit 51 that detects the fluctuation of the power supply voltage VL outputs a detection signal having a power supply voltage VL level. However, at this time, since the detection signal is generated from the power supply voltage VL in the fluctuating state, the logic is indefinite. This logic indefinite detection signal is supplied to the level conversion circuit 531-533 having the configuration shown in FIG. On the other hand, since the logic circuit 59, the logic circuit 50, and the inverter 57 are supplied with the power supply voltage VL in a fluctuating state, in this case, a signal with undefined logic is input to the input terminals of all the level conversion circuits 531-533. To do.

[0174] Since the logically indefinite input signal S11 from the logic circuit 50 is input to the gate of the transistor N63 and the gate of the transistor N64, the conduction state of these transistors N63 and N64 is indefinite. Therefore, the potentials of the nodes 68 and 69 are also indefinite.

However, the full latch circuit used in the level conversion circuit 531-533 of the present embodiment can converge the potential difference in an expanded manner if there is a small potential difference between the nodes 68 and 69. The nodes 68 and 69 can maintain potential states of opposite polarities.

The operation of this full latch circuit will be described. For example, when the transistors N64N63 are turned on at the same time, the output-side transistor N64 pulls down the node 69 to a low level, so that a low-level signal with an amplitude of the power supply voltage VH is output to the inverter 612.

[0177] When the transistors N64 and N63 are turned off at the same time, the potential difference between the nodes 68 and 69 converges in an expanded manner, and the node 69 outputs a signal having one of the amplitudes of the power supply voltage VH level. Output. Therefore, the level conversion circuit shown in FIG. 6 has a configuration in which a through current does not flow through the full latch circuit portion due to the expanded convergence of the potential difference between the node 68 and the node 69.

On the other hand, since the input signal from the power supply voltage detection circuit 51 is an unstable momentary power failure or stop signal of the power supply voltage VL, the logic of the signal is low level.

Therefore, the transistor N65 is turned off by the detection signal of the logic L input to the transistor N65. This ensures that the through current of the full latch circuit is prevented. Further, since the power supply voltage VL supplied to the inverter 611 is in a momentary power failure or stop state, the logic of the output signal is not inverted and is at a low level. Therefore, since the signal of the logic L is input to the gate of the transistors N66 and N67, both are turned off.

[0180] Therefore, the node 69 outputs a signal having one of the amplitudes of the power supply voltage VH level output by the full latch circuit to the inverter 612. Since the Invar 612 and the Inverter 613 are supplied with the specified voltage, they operate normally, so that the level conversion circuit 531 outputs the signal S12 whose logic is fixed.

[0181] The signal S12 is input to the inverter 56, and the inverter 56 outputs the signal S13 whose logic is inverted because the power supply voltage VH is supplied. Since the signal S14 output by the level conversion circuit 533 is a signal having the same polarity as the signal s12, the signals S13 and S14 are signals whose logic is inverted, and the transistors P54 and N55 with these signals as gate inputs are in a conductive state. Match. Therefore, the transistors P54 and N55 may be turned on at the same time.

However, since the supplied power supply voltage VL is in a momentary power failure or stop state, the transistor P54 is turned off, and in the end, not only the through current does not flow through the sense amplifier circuit 52 but also the current flows through the transistor N58. Nor. Therefore, the penetrating current of the entire semiconductor integrated circuit is significantly reduced, so that wasteful power consumption can be reduced.

[0183] As described above, according to this embodiment, even if the power supply voltage VL is in an unstable state, no through current flows through the level conversion circuit, the logic circuit element, and the sense amplifier circuit, and the power consumption can be reduced. At the same time, it is possible to provide a semiconductor integrated circuit that does not malfunction in logic.

[Effect of the Invention] As described in detail above, according to the present invention, even if one of the different power supply voltages fluctuates and a signal whose logic is unstable is formed inside, the penetration caused by this is caused. It is possible to provide a semiconductor integrated circuit capable of preventing a current, reducing power consumption, and preventing a malfunction of logic.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of a level conversion circuit used in the first embodiment shown in FIG.

FIG. 3 is a circuit diagram showing an example of the configuration of another level conversion circuit used in the first embodiment shown in FIG.

FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a configuration of a level conversion circuit used in the third embodiment shown in FIG.

FIG. 7 is a circuit diagram showing an example of a configuration of a sense amplifier circuit according to the third embodiment shown in FIG.

FIG. 8 is a block diagram showing the overall configuration of a conventional semiconductor integrated circuit and a circuit diagram showing an example of the configuration of a level conversion circuit used therein.

[Explanation of symbols] 11, 12, 15, 41, 42, 45, 50, 59 ... Logic circuits 13, 14, 43, 44,531, 532, 533 ... Level conversion circuits S11, S12, S13, S14, S15 ... Logic signal 40 ... Internal voltage generation circuit 10, 10A, 10B ... DRAM macro 51 ... Power supply voltage detection circuit 52 ... Sense amplifier circuit BL1, BL2 ... Bit line MC ... Memory cell