Semiconductor device and production method thereof

Technical Field The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a method for separating a semiconductor wafer into a semiconductor chip and a structure of the semiconductor chip obtained by the method. Background Technology Currently, a dicing method is mainly used to separate a compound semiconductor wafer into a semiconductor chip. Hereinafter, a method for separating the semiconductor wafer using the dicing method will be described. 28 to 30 are schematic cross-sectional views showing a method for separating semiconductor wafers using a dicing method in order of steps. 31 to 33 are schematic cross-sectional views taken along the GG line of FIGS. 28 to 30. First, with reference to FIGS. 28 and 31, a plurality of functional elements 3 are arranged and formed on the surface of the semiconductor layer 1 forming the semiconductor wafer 4c so as to be separated from each other by the dicing line region 2. After that, the back surface of the semiconductor layer 1 is polished by, for example, a polishing method, and the semiconductor wafer 4c is thinned to a thickness of 400 μm or less. On the back surface of the thinned semiconductor layer 1, a metal layer 5 is formed with a thickness of 1 μm or less as a solder-bonding layer when a semiconductor chip is die-bonded to a package. With reference to FIGS. 29 and 32, the metal layer 5 on the back surface of the semiconductor wafer 4c prepared in this way is attached to the expandable sheet 23. After that, the semiconductor wafer 4c is cut along the dicing line region 2 by the dicer. With reference to FIGS. 30 and 33, the semiconductor wafer 4c is divided into the respective semiconductor chips 10c by cutting the semiconductor wafer 4c. After that, by stretching the expanding sheet 23, the distance between the semiconductor chips 10c is widened, and the semiconductor chips 10c can be easily taken out (recovered). When dicing the semiconductor wafer 4c, the expanding sheet 23 also has a slight notch 23a. FIG. 34 is a perspective view schematically showing the configuration of the semiconductor chip 10c divided by this dicing. 35 and 36 are schematic cross-sectional views taken along the lines HH and II of FIG. 34. With reference to FIGS. 34 to 36, the semiconductor chip 1 divided by the above dicing In 0c, the functional element 3 is formed on the surface of the semiconductor layer 1, and a region 2a in which the element is not formed is distributed as a dicing line region surrounding the functional element 3. Further, a metal layer 5 is formed on the entire back surface of the semiconductor layer 1. Among the compound semiconductor devices mentioned above, high output FET (Field Effect) In a device such as Transistor) that requires reduction of thermal resistance, it is necessary to reduce the thickness of the semiconductor wafer 4c to 50 μm or less as shown in FIGS. 28 and 31. When the plate is thinned to 50 μm or less in this way, the semiconductor wafer 4c may crack during handling. Therefore, in order to reinforce the semiconductor wafer 4c, it is necessary to form the metal layer 5 on the back surface of the semiconductor wafer 4c with a film thickness of 1 μm or more. However, if dicing is performed with the metal layer 5 formed, the metal of the metal layer 5 adheres to the dicing blade, causing clogging of the dicing blade or severe wear of the dicing blade. Occurs. In order to solve this problem, a wet etching method has been conventionally used as a method for separating semiconductor wafers having a thickness of 50 μm or less. Hereinafter, a method for separating a semiconductor wafer using the wet etching method will be described. 37 to 39 are schematic plan views and schematic views showing the method of separating the semiconductor wafer by the wet etching method in the order of processes. 40 and 41 are schematic cross-sectional views taken along the line JJ of FIGS. 37 and 38, and FIG. 42 is a schematic view showing a state of the semiconductor chip corresponding to the process of FIG. 39. First, with reference to FIGS. 37 and 40, a plurality of functional elements 3 are arranged and formed on the surface of the semiconductor layer 1 forming the semiconductor wafer 4d so as to be separated from each other by the separation line region 2. The surface of the semiconductor wafer 4d on which the functional element 3 is formed is attached to a reinforcing plate 21 such as glass by an adhesive material 31. In this state, the back surface of the semiconductor layer 1 is polished, and the semiconductor wafer 4d is thinned to a thickness of 50 μm or less. The metal layer 5 is formed on the entire surface of the thinned semiconductor wafer 4d. The metal layer 5 is patterned by a normal photoengraving method or the like, and remains at the back surface position corresponding to the functional element 3. The semiconductor wafer 4d is wet-etched using the patterned metal layer 5 as a mask. With reference to FIG. 41, this wet etching forms a groove penetrating from the back surface to the front surface of the semiconductor layer 1. The semiconductor wafer 4d is separated into a plurality of semiconductor chips 10d. In this state, the semiconductor chip 10d and the reinforcing plate 21 are immersed in an organic solvent in order to melt the adhesive material 31. With reference to FIGS. 39 and 42, the adhesive material 31 is melted by immersion in the organic solvent 50, and the semiconductor chip 10d is peeled from the reinforcing plate 21. FIG. 43 is a perspective view schematically showing the configuration of the semiconductor chip 10d divided by the wet etching. In addition, FIGS. 44 and 45 are schematic cross-sectional views taken along the lines KK and LL of FIG. 43. With reference to FIGS. 43 to 45, in the semiconductor chip 10d divided by the above wet etching, the functional element 3 is formed on the surface of the semiconductor layer 1, and the element is used as a separation region so as to surround the functional element 3. Region 2b where was not formed is distributed. Further, a metal layer 5 is formed on the entire back surface of the semiconductor layer 1, and the end portion of the metal layer 5 projects from the back surface end portion of the semiconductor layer 1 toward the outer peripheral side. Further, the side surface of the semiconductor layer 1 has a shape narrowed from the front surface on which the functional element 3 is formed toward the back surface on which the metal layer 5 is formed. According to this method using wet etching, since the dicing method is not used, the metal layer 5 is not clogged with the blade of the dicer. However, in this method, the semiconductor chips 10d are scattered in the organic solvent 50 as shown in FIGS. 39 and 42. There is a problem that an excessive amount of time is required to collect the semiconductor chip 10d by handling with tweezers in a state where the semiconductor chips are scattered and not regularly arranged in this way. Further, when the scattered chips are collected, dried, and then transferred to another container in the atmosphere, the semiconductor chip 10d repeatedly collides with the other semiconductor chip 10d or the container. This causes many scratches on the surface of the semiconductor chip 10d and many adhesions such as semiconductor fragments, so that there is a problem that many of the semiconductor chips 10d have a poor appearance. Disclosure of the Invention The purpose of the present invention is to solve the above-mentioned problems, and the die It is an object of the present invention to provide a semiconductor device which prevents clogging and wear of a sir blade, facilitates recovery of a semiconductor chip by tweezers, and is less likely to cause a defective appearance of the semiconductor chip, and a method for manufacturing the same. A method for manufacturing a semiconductor device according to one aspect of the present invention includes the following steps. First, a plurality of element forming regions having first and second main surfaces facing each other and having functional elements, and a plurality of element forming regions surrounding the element forming regions on both the first and second main surfaces. A semiconductor wafer including a semiconductor layer having a separation region for separating the element forming regions from each other is prepared. Then, a metal layer is formed on the first main surface of the semiconductor layer in the separation region so as to surround the element formation region. Then, a reinforcing layer is adhered to the semiconductor wafer so as to cover the entire surface of the first main surface. Then, by selectively etching the separation region of the second main surface of the semiconductor layer, a hole reaching only the metal layer from the second main surface is formed so as to surround the periphery of the device forming region. .. Then, the reinforcing layer is removed from the semiconductor wafer. Then, the metal layer is irradiated with a laser, the metal layer is melted and cut, and the plurality of element forming regions are separated from each other to form a semiconductor chip. In the method for manufacturing a semiconductor device of the present invention, a semiconductor wafer is divided into semiconductor chips by using etching and laser melting. Therefore, the semiconductor wafer is not separated by dicing, and the dicing blade is prevented from being clogged or worn by the metal layer. Further, each of the semiconductor layers separated from the semiconductor wafer when the reinforcing layer is removed from the semiconductor wafer is connected by a metal layer. Therefore, the semiconductor layers are not scattered in the organic solvent. Finally, the metal layer is melt-cut by a laser to separate each semiconductor chip. Therefore, even when the semiconductor chips are separated, the semiconductor chips are not scattered apart. Therefore, it is possible to prevent the recovery time of each semiconductor chip from being lengthened by being scattered separately. In addition, each semiconductor chip is scattered apart and damages each other, or semiconductor fragments are chips. It is also possible to prevent the appearance from being deteriorated by adhering to the surface. In the above aspect, preferably, after removing the reinforcing layer from the semiconductor wafer, a stretchable sheet is attached to the second main surface of the semiconductor wafer. Then, the metal layer is irradiated with the laser from the first main surface side to separate the plurality of element forming regions from each other, and then the sheet is stretched to widen the interval between the plurality of semiconductor chips. As a result, the interval between the semiconductor chips can be widened, so that the recovery of each semiconductor chip becomes easier and the time for recovery can be further shortened. In the above aspect, preferably, the semiconductor wafer is prepared to have a groove formed in the separation region so as to surround the element formation region on the first main surface. This metal layer is formed in the groove of the first main surface. By forming the metal layer in the groove in this way, the metal layer can be arranged away from the functional element. Therefore, even if the scattered melt of the metal layer is generated when the metal layer is laser-melted, the scattered melt is prevented from being scattered on the functional element. Further, since the metal layer can be arranged away from the functional element, it is possible to prevent the wire from coming into contact with the fused metal layer at the time of wire bonding. In the above aspect, preferably, after the holes are formed, a second metal layer that covers the entire second main surface of the semiconductor wafer and is in contact with the metal layer is formed. The laser irradiation cuts the metal layer and the second metal layer by melting. By forming the second metal layer in this way, the effect of reinforcing the semiconductor wafer can be further improved, and the occurrence of cracks and the like can be further prevented. The semiconductor device of the present invention includes a semiconductor layer, a metal layer, and a laser melting portion. The semiconductor layer has an element forming region having a main surface and having a functional element. The metal layer is formed on the main surface so as to surround the element forming region. The inner peripheral side end portion of the metal layer is arranged at a distance from the element forming region, and the outer peripheral side end portion protrudes from the end portion of the main surface of the semiconductor layer to the outer peripheral side. The laser melting part is formed at the outer peripheral end. And has a round shape. In the semiconductor device of the present invention, poor appearance is unlikely to occur.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic plan view showing a second step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 3 is a schematic plan view showing a third step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic plan view showing a fourth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 5 is a schematic plan view showing a fifth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 6 is a schematic plan view showing a sixth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 7 is a schematic plan view showing a seventh step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 8 is a schematic cross-sectional view taken along the line AA of FIG. FIG. 9 is a schematic cross-sectional view taken along the line AA of FIG. FIG. 10 is a schematic cross-sectional view taken along the line AA of FIG. FIG. 11 is a schematic cross-sectional view taken along the line AA of FIG. FIG. 12 is a schematic cross-sectional view taken along the line AA of FIG. FIG. 13 is a schematic cross-sectional view taken along the line AA of FIG. FIG. 14 is a schematic cross-sectional view taken along the line AA of FIG. FIG. 15 is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 16 is a schematic cross-sectional view taken along the CC line of FIG. FIG. 17 is a schematic cross-sectional view taken along the DD line of FIG. FIG. 18 is a schematic cross-sectional view showing the first step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 19 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 20 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 21 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 22 is a schematic cross-sectional view showing a fifth step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 23 is a schematic cross-sectional view showing a sixth step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. Figure 24 is a schematic cross-sectional view showing a seventh step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 25 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 26 is a schematic cross-sectional view taken along the EE line of FIG. 25. FIG. 27 is a schematic cross-sectional view taken along the line FF of FIG. 25. FIG. 28 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 29 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 30 is a schematic plan view showing a third step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 31 is a schematic cross-sectional view taken along the line GG of FIG. 28. FIG. 32 is a schematic cross-sectional view taken along the line GG of FIG. 29. FIG. 33 is a schematic cross-sectional view taken along the line GG of FIG. FIG. 34 is a perspective view schematically showing the configuration of a semiconductor device manufactured by using a conventional dicing method. FIG. 35 is a schematic cross-sectional view taken along the HH line of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along line II of FIG. 34. FIG. 37 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 38 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 39 is a schematic view showing a third step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 40 is a schematic cross-sectional view taken along the line JJ of FIG. 37. FIG. 41 is a schematic cross-sectional view taken along the line JJ of FIG. 38. FIG. 42 is a schematic view showing the state of the semiconductor chips scattered separately in FIG. 39. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. .. FIG. 25 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 26 is a schematic cross-sectional view taken along the EE line of FIG. 25. FIG. 27 is a schematic cross-sectional view taken along the line FF of FIG. 25. FIG. 28 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 29 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 30 is a schematic plan view showing a third step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 31 is a schematic cross-sectional view taken along the line GG of FIG. 28. FIG. 32 is a schematic cross-sectional view taken along the line GG of FIG. 29. FIG. 33 is a schematic cross-sectional view taken along the line GG of FIG. FIG. 34 is a perspective view schematically showing the configuration of a semiconductor device manufactured by using a conventional dicing method. FIG. 35 is a schematic cross-sectional view taken along the HH line of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along line II of FIG. 34. FIG. 37 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 38 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 39 is a schematic view showing a third step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 40 is a schematic cross-sectional view taken along the line JJ of FIG. 37. FIG. 41 is a schematic cross-sectional view taken along the line JJ of FIG. 38. FIG. 42 is a schematic view showing the state of the semiconductor chips scattered separately in FIG. 39. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. .. FIG. 25 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 26 is a schematic cross-sectional view taken along the EE line of FIG. 25. FIG. 27 is a schematic cross-sectional view taken along the line FF of FIG. 25. FIG. 28 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 29 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 30 is a schematic plan view showing a third step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 31 is a schematic cross-sectional view taken along the line GG of FIG. 28. FIG. 32 is a schematic cross-sectional view taken along the line GG of FIG. 29. FIG. 33 is a schematic cross-sectional view taken along the line GG of FIG. FIG. 34 is a perspective view schematically showing the configuration of a semiconductor device manufactured by using a conventional dicing method. FIG. 35 is a schematic cross-sectional view taken along the HH line of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along line II of FIG. 34. FIG. 37 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 38 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 39 is a schematic view showing a third step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 40 is a schematic cross-sectional view taken along the line JJ of FIG. 37. FIG. 41 is a schematic cross-sectional view taken along the line JJ of FIG. 38. FIG. 42 is a schematic view showing the state of the semiconductor chips scattered separately in FIG. 39. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. Is. FIG. 28 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 29 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 30 is a schematic plan view showing a third step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 31 is a schematic cross-sectional view taken along the line GG of FIG. 28. FIG. 32 is a schematic cross-sectional view taken along the line GG of FIG. 29. FIG. 33 is a schematic cross-sectional view taken along the line GG of FIG. FIG. 34 is a perspective view schematically showing the configuration of a semiconductor device manufactured by using a conventional dicing method. FIG. 35 is a schematic cross-sectional view taken along the HH line of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along line II of FIG. 34. FIG. 37 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 38 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 39 is a schematic view showing a third step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 40 is a schematic cross-sectional view taken along the line JJ of FIG. 37. FIG. 41 is a schematic cross-sectional view taken along the line JJ of FIG. 38. FIG. 42 is a schematic view showing the state of the semiconductor chips scattered separately in FIG. 39. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. Is. FIG. 28 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 29 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 30 is a schematic plan view showing a third step of a method for manufacturing a semiconductor device using a conventional dicing method. FIG. 31 is a schematic cross-sectional view taken along the line GG of FIG. 28. FIG. 32 is a schematic cross-sectional view taken along the line GG of FIG. 29. FIG. 33 is a schematic cross-sectional view taken along the line GG of FIG. FIG. 34 is a perspective view schematically showing the configuration of a semiconductor device manufactured by using a conventional dicing method. FIG. 35 is a schematic cross-sectional view taken along the HH line of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along line II of FIG. 34. FIG. 37 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 38 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 39 is a schematic view showing a third step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 40 is a schematic cross-sectional view taken along the line JJ of FIG. 37. FIG. 41 is a schematic cross-sectional view taken along the line JJ of FIG. 38. FIG. 42 is a schematic view showing the state of the semiconductor chips scattered separately in FIG. 39. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. It is a schematic cross-sectional view along the line. FIG. 33 is a schematic cross-sectional view taken along the line GG of FIG. FIG. 34 is a perspective view schematically showing the configuration of a semiconductor device manufactured by using a conventional dicing method. FIG. 35 is a schematic cross-sectional view taken along the HH line of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along line II of FIG. 34. FIG. 37 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 38 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 39 is a schematic view showing a third step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 40 is a schematic cross-sectional view taken along the line JJ of FIG. 37. FIG. 41 is a schematic cross-sectional view taken along the line JJ of FIG. 38. FIG. 42 is a schematic view showing the state of the semiconductor chips scattered separately in FIG. 39. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. It is a schematic cross-sectional view along the line. FIG. 33 is a schematic cross-sectional view taken along the line GG of FIG. FIG. 34 is a perspective view schematically showing the configuration of a semiconductor device manufactured by using a conventional dicing method. FIG. 35 is a schematic cross-sectional view taken along the HH line of FIG. 34. FIG. 36 is a schematic cross-sectional view taken along line II of FIG. 34. FIG. 37 is a schematic plan view showing a first step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 38 is a schematic plan view showing a second step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 39 is a schematic view showing a third step of a method for manufacturing a semiconductor device using a conventional wet etching method. FIG. 40 is a schematic cross-sectional view taken along the line JJ of FIG. 37. FIG. 41 is a schematic cross-sectional view taken along the line JJ of FIG. 38. FIG. 42 is a schematic view showing the state of the semiconductor chips scattered separately in FIG. 39. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. It is a schematic diagram which shows the state of a chip. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. It is a schematic diagram which shows the state of a chip. FIG. 43 is a perspective view schematically showing the configuration of a semiconductor device manufactured by a conventional wet etching method. FIG. 44 is a schematic cross-sectional view taken along the line KK of FIG. 43. FIG. 45 is a schematic cross-sectional view taken along the line LL of FIG. 43. Best Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings.<u style="single">Embodiment 1</u>1 to 7 are schematic plan views showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention in the order of processes. 8 to 14 are partial schematic cross-sectional views of the portion along the AA line of FIGS. 1 to 7. The views seen from each arrow B direction of FIGS. 8 to 14 correspond to the plan views of FIGS. 1 to 7. First, with reference to FIGS. 1 and 8, a plurality of element forming regions having the functional elements 3 are formed on the surface of the semiconductor layer 1 forming the semiconductor wafer 4a. Each of the plurality of element forming regions is surrounded by a separation line region and separated from each other. A metal layer 5 is formed in this separation line region at a predetermined distance from the functional element 3. With reference to FIGS. 2 and 9, the reinforcing plate 21 is attached to the surface of the semiconductor wafer 4a on which the functional element 3 and the metal layer 5 are formed, with the adhesive material 31 interposed therebetween. The reinforcing plate 21 is made of, for example, glass. After that, the back surface of the semiconductor wafer 4a is ground and polished, and the semiconductor wafer 4a is thinned to a thickness of 50 μm or less. With reference to FIGS. 3 and 10, a resist pattern 33a is formed by a photoengraving method so as to cover a region other than the separation line region on the back surface of the semiconductor wafer 4a. The semiconductor wafer 4a is etched using the resist pattern 33a as a mask. As a result, holes 1b that penetrate the semiconductor layer 1 and reach the metal layer 5 on the surface are formed along the separation line region. After this, the resist pattern 33a is removed. The opening width L of the hole pattern of the resist pattern 33a₂Is the width L of the metal layer 5₁Is set to be smaller than. Even if the semiconductor wafer 4a is thinned and separated by the holes 1b in this way, the semiconductor layers 1 separated from each other can withstand the heat treatment (~ 100 ° C) in the subsequent process by being connected by the metal layer 5. And can also maintain alignment. With reference to FIGS. 4 and 11, the metal layer 7 is formed on the entire back surface of the semiconductor wafer 4a. After that, the resist pattern 33b is formed so as to cover other than the separation line region on the back surface of the semiconductor wafer 4a by the photoengraving method. In this state, electrolytic plating is performed while supplying power to the metal layer 7. As a result, the metal plating film 9 is formed on the surface of the metal layer 7 exposed from the resist pattern 33b. The metal plating film 9 has a function of connecting the semiconductor layers 1 separated from each other on the back surface of the semiconductor wafer 4a to reinforce the semiconductor wafer 4a. After this, the resist pattern 33b is removed. With reference to FIGS. 5 and 12, a resist pattern 33c is formed on the metal plating film 9 in the separation line region on the back surface of the semiconductor wafer 4a by a photoengraving method. In this state, by performing electrolytic plating while supplying power to the metal layer 7, the Au (gold) plating film 11 is formed on the element forming region on the back surface of the semiconductor wafer 4a. After this, the resist pattern 33c is removed. After that, the adhesive material 31 is melted by immersing it in an organic solvent, and the reinforcing plate 21 is peeled off from the semiconductor wafer 4a. The expanding sheet 23 is attached to the back surface of the semiconductor wafer 4a with reference to FIGS. 6 and 13. The expanding sheet 23 is a resin sheet made of a material commonly used in the semiconductor industry, such as acrylic and polyolefin, and has an adhesive on its surface. In this state, the laser beam is applied to the metal layer 5 in the separation line region from the surface side of the semiconductor wafer 4a. With reference to FIGS. 7 and 14, the irradiation of the laser beam causes the metal layers 5 and 7 and the metal plating film 9 to be blown and separated, and the semiconductor wafer 4a is separated into each semiconductor chip 10a. Of this laser beam By irradiation, the metal layers 5 and 7 and a part of the metal plating film 9 are melted and then solidified to form a metal foil 13 having a round shape at the end thereof. After that, by stretching the expanding sheet 23 in all directions, the distance between the semiconductor chips 10a is widened. This makes it easy to collect each semiconductor chip 10a with tweezers. As the metal layer 5 and the metal plating film 9, for example, Ni (nickel), Cr (chromium), or the like is used. Further, the metal layer 5 may be formed by an electroless plating method or a thin-film deposition lift method, or may be formed by a method combining a sputtering and a lift-off method, or a method combining an electroless plating method and an electrolytic plating method. May be good. Further, the metal plating film 9 may be formed by an electroless plating method instead of the electrolytic plating method. Further, the metal plating film 9 is formed so as to partially overlap with the Au plating film 11. The film thickness of the Au plating film 11 is 1 to 50 μm. The shape of the semiconductor chip thus formed will be described below. FIG. 15 is a plan view schematically showing the configuration of the semiconductor chip according to the first embodiment of the present invention. 16 and 17 are schematic cross-sectional views taken along the CC and DD lines of FIG. With reference to FIGS. 15 to 17, the metal layer 5 is formed at the surface end portion of the semiconductor layer 1 in which the functional element 3 is formed on the surface. The metal layer 5 is formed so as to surround the functional element 3 at a predetermined distance from the outer peripheral end portion of the semiconductor layer 1 and protrudes from the outer peripheral end portion to the outer peripheral side. Further, the metal layer 7 is formed so as to cover the entire back surface of the semiconductor layer 1. The metal layer 7 is in contact with the back surface of the metal layer 5. A metal plating film 9 is formed on the metal layer 7 at the back end of the semiconductor layer 1. At the ends of the metal layers 7 and 5 and the metal plating film 9, a metal foil 13 that has been once melted by a laser beam and then solidified is formed in a round shape. Film thickness T of this metal ton 13 By stretching the spanned sheet 23 in all directions, the distance between the semiconductor chips 10a is widened. This makes it easy to collect each semiconductor chip 10a with tweezers. As the metal layer 5 and the metal plating film 9, for example, Ni (nickel), Cr (chromium), or the like is used. Further, the metal layer 5 may be formed by an electroless plating method or a thin-film deposition lift method, or may be formed by a method combining a sputtering and a lift-off method, or a method combining an electroless plating method and an electrolytic plating method. May be good. Further, the metal plating film 9 may be formed by an electroless plating method instead of the electrolytic plating method. Further, the metal plating film 9 is formed so as to partially overlap with the Au plating film 11. The film thickness of the Au plating film 11 is 1 to 50 μm. The shape of the semiconductor chip thus formed will be described below. FIG. 15 is a plan view schematically showing the configuration of the semiconductor chip according to the first embodiment of the present invention. 16 and 17 are schematic cross-sectional views taken along the CC and DD lines of FIG. With reference to FIGS. 15 to 17, the metal layer 5 is formed at the surface end portion of the semiconductor layer 1 in which the functional element 3 is formed on the surface. The metal layer 5 is formed so as to surround the functional element 3 at a predetermined distance from the outer peripheral end portion of the semiconductor layer 1 and protrudes from the outer peripheral end portion to the outer peripheral side. Further, the metal layer 7 is formed so as to cover the entire back surface of the semiconductor layer 1. The metal layer 7 is in contact with the back surface of the metal layer 5. A metal plating film 9 is formed on the metal layer 7 at the back end of the semiconductor layer 1. At the ends of the metal layers 7 and 5 and the metal plating film 9, a metal foil 13 that has been once melted by a laser beam and then solidified is formed in a round shape. Film thickness T of this metal ton 13 By stretching the spanned sheet 23 in all directions, the distance between the semiconductor chips 10a is widened. This makes it easy to collect each semiconductor chip 10a with tweezers. As the metal layer 5 and the metal plating film 9, for example, Ni (nickel), Cr (chromium), or the like is used. Further, the metal layer 5 may be formed by an electroless plating method or a thin-film deposition lift method, or may be formed by a method combining a sputtering and a lift-off method, or a method combining an electroless plating method and an electrolytic plating method. May be good. Further, the metal plating film 9 may be formed by an electroless plating method instead of the electrolytic plating method. Further, the metal plating film 9 is formed so as to partially overlap with the Au plating film 11. The film thickness of the Au plating film 11 is 1 to 50 μm. The shape of the semiconductor chip thus formed will be described below. FIG. 15 is a plan view schematically showing the configuration of the semiconductor chip according to the first embodiment of the present invention. 16 and 17 are schematic cross-sectional views taken along the CC and DD lines of FIG. With reference to FIGS. 15 to 17, the metal layer 5 is formed at the surface end portion of the semiconductor layer 1 in which the functional element 3 is formed on the surface. The metal layer 5 is formed so as to surround the functional element 3 at a predetermined distance from the outer peripheral end portion of the semiconductor layer 1 and protrudes from the outer peripheral end portion to the outer peripheral side. Further, the metal layer 7 is formed so as to cover the entire back surface of the semiconductor layer 1. The metal layer 7 is in contact with the back surface of the metal layer 5. A metal plating film 9 is formed on the metal layer 7 at the back end of the semiconductor layer 1. At the ends of the metal layers 7 and 5 and the metal plating film 9, a metal foil 13 that has been once melted by a laser beam and then solidified is formed in a round shape. Film thickness T of this metal ton 13 It may be formed by a method or a vapor deposition lift method, or may be formed by a method combining sputtering and a lift-off method, or a method combining an electroless plating method and an electrolytic plating method. Further, the metal plating film 9 may be formed by an electroless plating method instead of the electrolytic plating method. Further, the metal plating film 9 is formed so as to partially overlap with the Au plating film 11. The film thickness of the Au plating film 11 is 1 to 50 μm. The shape of the semiconductor chip thus formed will be described below. FIG. 15 is a plan view schematically showing the configuration of the semiconductor chip according to the first embodiment of the present invention. 16 and 17 are schematic cross-sectional views taken along the CC and DD lines of FIG. With reference to FIGS. 15 to 17, the metal layer 5 is formed at the surface end portion of the semiconductor layer 1 in which the functional element 3 is formed on the surface. The metal layer 5 is formed so as to surround the functional element 3 at a predetermined distance from the outer peripheral end portion of the semiconductor layer 1 and protrudes from the outer peripheral end portion to the outer peripheral side. Further, the metal layer 7 is formed so as to cover the entire back surface of the semiconductor layer 1. The metal layer 7 is in contact with the back surface of the metal layer 5. A metal plating film 9 is formed on the metal layer 7 at the back end of the semiconductor layer 1. At the ends of the metal layers 7 and 5 and the metal plating film 9, a metal foil 13 that has been once melted by a laser beam and then solidified is formed in a round shape. Film thickness T of this metal ton 13 It may be formed by a method or a vapor deposition lift method, or may be formed by a method combining sputtering and a lift-off method, or a method combining an electroless plating method and an electrolytic plating method. Further, the metal plating film 9 may be formed by an electroless plating method instead of the electrolytic plating method. Further, the metal plating film 9 is formed so as to partially overlap with the Au plating film 11. The film thickness of the Au plating film 11 is 1 to 50 μm. The shape of the semiconductor chip thus formed will be described below. FIG. 15 is a plan view schematically showing the configuration of the semiconductor chip according to the first embodiment of the present invention. 16 and 17 are schematic cross-sectional views taken along the CC and DD lines of FIG. With reference to FIGS. 15 to 17, the metal layer 5 is formed at the surface end portion of the semiconductor layer 1 in which the functional element 3 is formed on the surface. The metal layer 5 is formed so as to surround the functional element 3 at a predetermined distance from the outer peripheral end portion of the semiconductor layer 1 and protrudes from the outer peripheral end portion to the outer peripheral side. Further, the metal layer 7 is formed so as to cover the entire back surface of the semiconductor layer 1. The metal layer 7 is in contact with the back surface of the metal layer 5. A metal plating film 9 is formed on the metal layer 7 at the back end of the semiconductor layer 1. At the ends of the metal layers 7 and 5 and the metal plating film 9, a metal foil 13 that has been once melted by a laser beam and then solidified is formed in a round shape. Film thickness T of this metal ton 13 It is a schematic cross-sectional view along with. With reference to FIGS. 15 to 17, the metal layer 5 is formed at the surface end portion of the semiconductor layer 1 in which the functional element 3 is formed on the surface. The metal layer 5 is formed so as to surround the functional element 3 at a predetermined distance from the outer peripheral end portion of the semiconductor layer 1 and protrudes from the outer peripheral end portion to the outer peripheral side. Further, the metal layer 7 is formed so as to cover the entire back surface of the semiconductor layer 1. The metal layer 7 is in contact with the back surface of the metal layer 5. A metal plating film 9 is formed on the metal layer 7 at the back end of the semiconductor layer 1. At the ends of the metal layers 7 and 5 and the metal plating film 9, a metal foil 13 that has been once melted by a laser beam and then solidified is formed in a round shape. Film thickness T of this metal ton 13 It is a schematic cross-sectional view along with. With reference to FIGS. 15 to 17, the metal layer 5 is formed at the surface end portion of the semiconductor layer 1 in which the functional element 3 is formed on the surface. The metal layer 5 is formed so as to surround the functional element 3 at a predetermined distance from the outer peripheral end portion of the semiconductor layer 1 and protrudes from the outer peripheral end portion to the outer peripheral side. Further, the metal layer 7 is formed so as to cover the entire back surface of the semiconductor layer 1. The metal layer 7 is in contact with the back surface of the metal layer 5. A metal plating film 9 is formed on the metal layer 7 at the back end of the semiconductor layer 1. At the ends of the metal layers 7 and 5 and the metal plating film 9, a metal foil 13 that has been once melted by a laser beam and then solidified is formed in a round shape. Film thickness T of this metal ton 13₃Is the sum of the film thicknesses of the metal layers 5 and 7 and the metal plating film 9 T₂It is less than 3 times. The Au plating film 11 is formed so as to cover the back surface of the semiconductor layer 1. The metal layer 5 should have a low reflectance with respect to the YAG (Yttrium Aluminum Garnet) laser, and is formed of at least a metal having a reflectance of 80% or less with respect to the YAG laser, such as Ni and Cr. If the metal layer 5 is an Au layer having a reflectance of more than 80% with respect to the YAG laser, the Au layer can be melted by increasing the energy of the laser beam. However, if the laser beam energy is increased, the lower expanding sheet 23 will be damaged by the laser beam when the Au layer is melted. Further, as shown in FIG. 11, the sum of the film thicknesses of the metal layers 5 and 7 and the metal plating film 9 T₁Is 0.5 μm or more and 50 μm or less. This film thickness T₁If is smaller than 0.5 μm, as shown in FIGS. 12 and 13, when the semiconductor wafer 4a having a thickness of 50 μm or less is peeled off from the reinforcing plate 21, it cannot be handled in the wafer shape. Also, the film thickness T₁If is larger than 50 μm, even if a material having a high laser beam energy absorption rate (low reflectance) is used for the metal layers 5, 7 and 9, the expanding sheet 23 will be damaged when the metal layer is blown. The film thickness of the metal layer 5 is 0.2 μm or more and 50 μm or less. 0.2 μm is the minimum film thickness required for each semiconductor device connecting material in order to maintain the alignment of each semiconductor device in the processing steps after etching from the back surface of the wafer shown in FIG. If the film thickness exceeds 50 μm, the laser beam damages the expanding sheet when the metal layer is cut by the laser beam as described above. That is, considering the case where the metal layer 7 and the metal plating film 9 are omitted, it is desirable that the film thickness of the metal layer 5 is 50 μm or less. The film thickness of the Au plating film 11 is preferably 10 μm or more and 50 μm or less, but it may be a thin-film film having a film thickness of 1000 Å or more. Further, if the thickness of the semiconductor layer 1 is 30 μm or more and 600 μm or less, it is suitable to use the method of the present embodiment. Further, as shown in FIG. 13, the distance T between the laminated metal layers 5, 7, and 9 and the expanding sheet 23 is T.₄Is the sum of the film thicknesses of the laminated metal layers 5, 7 and 9 T₂It may be one-fourth or more of (Fig. 16). Thus the interval T₄By setting, when the laminated metal layers 5, 7, and 9 are fused by the laser beam, the expanding sheet 23 is prevented from being directly damaged by heat from the fused metal that has absorbed the laser beam energy. .. In the method for manufacturing a semiconductor device of the present embodiment, the semiconductor wafer 4a is divided into semiconductor chips 10a by using the etching shown in FIG. 10 and the laser melting shown in FIG. Therefore, the semiconductor wafer is not separated by dicing as described in the conventional example. Therefore, the dicer blade is prevented from being clogged or worn by the metal layer. Further, when the reinforcing plate 21 is removed from the semiconductor wafer 4a in FIGS. 12 to 13, each of the semiconductor layers 1 separated from the semiconductor wafer 4a is connected by the metal layer 5. Therefore, the semiconductor chips 10a are not scattered in the organic solvent. Further, as shown in FIG. 14, the metal layer 5 and the like are finally blown by the laser beam and divided into each semiconductor chip. Therefore, even when the semiconductor chips 10a are divided by the laser beam, the semiconductor chips 10a are not scattered apart. Therefore, it is possible to prevent the recovery time of each semiconductor chip 10a from becoming long by being scattered separately. In addition, the semiconductor chips 10a are scattered apart from each other, and it is possible to prevent the appearance from being deteriorated due to damage to each other or semiconductor fragments adhering to the chips. Further, each of the semiconductor layers 1 separated from the semiconductor wafer 4a is connected by the metal layer 5. As a result, the semiconductor wafer 4a can be maintained in the wafer shape even after the semiconductor wafer 4a is peeled off from the reinforcing plate 21. Therefore, there is an advantage that the characteristics of the functional element 3 and the like can be tested by the automatic tester.<u style="single">Embodiment 2</u>18 to 24 are schematic cross-sectional views showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention in the order of processes. Each of the cross-sectional views shown in FIGS. 18 to 24 corresponds to a partial schematic cross-sectional view of a portion along the AA line of FIGS. 1 to 7 described in the first embodiment. First, referring to FIGS. 1 and 18, in the present embodiment, as compared with the first embodiment, a groove 1c is formed on the surface of the separation line region of the semiconductor layer 1 forming the semiconductor wafer 4b as preprocessing. Will be done. The groove 1c is formed along the separation line region by etching removal, and is formed at a depth of 5 μm or more so as not to penetrate the semiconductor layer 1. Then, the metal layer 5 is formed so as to cover the inner wall of the groove 1c provided on the separation line region. It is desirable that the groove 1c be formed in a tapered shape so that the inner diameter thereof becomes smaller as the position deeper from the surface of the semiconductor layer 1. After that, as shown in FIGS. 19 to 24, the semiconductor wafers 4b are formed into a plurality of semiconductor chips 10b by undergoing the same steps as in the first embodiment shown in FIGS. 2 to 7 and 9 to 14. Is separated into. The members having the same reference numerals as those in the first embodiment in FIGS. 19 to 24 are the same members as those described in the first embodiment. Next, the configuration of the semiconductor chip of the present embodiment formed in this way will be described. FIG. 25 is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. 26 and 27 are schematic cross-sectional views taken along the lines EE and FF of FIG. 25. With reference to FIGS. 25 to 27, the semiconductor chip 10b of the present embodiment has the inclined portion 1c in the outer peripheral region surrounding the region where the functional element 3 is formed on the surface of the semiconductor layer 1. The metal layer 5 is formed so as to cover the inclined portion 1c, and protrudes from the outer peripheral end portion of the semiconductor layer 1 toward the outer peripheral side. Since the other configurations are almost the same as those in the first embodiment described above, the same members are designated by the same reference numerals, and the description thereof will be omitted. In the present embodiment, as shown in FIG. 18, a groove 1c is formed in the separation line region of the semiconductor wafer 4b, and a metal layer 5 is formed so as to cover the groove 1c. Will be done. By forming the metal layer 5 in the groove 1c in this way, the metal layer 5 can be arranged away from the functional element 3 as compared with the first embodiment. Therefore, even if a splash or the like (scattered melt) of the metal layer 5 is generated when the metal layer 5 is laser-melted in the process shown in FIG. 24, the scattered melt may be scattered on the functional element 3. Be prevented. Further, in the assembly of the semiconductor device, it is possible to prevent the wire from coming into contact with the fused metal layer 5 during wire bonding. On the other hand, in the first embodiment, as shown in FIG. 8, the metal layer 5 is formed as it is without providing a groove on the surface of the semiconductor layer 1. Therefore, as shown in FIG. 13, the distance T between the metal layers 5, 7, and 9 and the expanding sheet 23 is T.₄Can be secured larger than that of the second embodiment. Therefore, it is possible to prevent the expanding sheet 23 from being damaged when the metal layers 5, 7, and 9 shown in FIG. 14 are laser-fractured. It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the scope of claims. Industrial Applicability The present invention may be advantageously applied to a method of dividing into thinned compound semiconductor wafers and semiconductor chips.