Non-volatile ferroelectric memory, and drive method thereof, and id card

The present invention relates to a transponder used in an RFID system, and in particular, is a non-volatile memory cell mounted on the transponder and having an array of memory cells using a ferroelectric film as an information storage capacitor. It relates to a ferroelectric memory, its driving method, and an ID card.

[0002] A RFID (Radio Frequency Identification) system is a non-contact tag system (identifier) using radio waves, and is a host side and a transponder composed of a personal computer, a controller, an antenna, and the like. It is composed of and. The transponder is equipped with a chip such as a non-volatile ferroelectric memory. Non-volatile ferroelectric memories using ferroelectric memory cells have been actively researched and developed in recent years as low power consumption semiconductor storage devices. This non-volatile ferroelectric memory is available in US Pat. No. 4,873,664 (Eaton, Jr.) and SS Eaton, Jr. et al. A Ferroelectric DRAM Cell for High Density NVRAMs, ISSCC Digest of Technical Papers, pp. 130-131, It is described in Feb. 1988 etc. Barium titanate (BaTiO) is used as the information storage capacitor for ferroelectric memory cells.₃), Lead zirconate titanate (Pb (Zr, Ti) O₃; PZT), lanthanum-doped lead zirconate titanate ((Pb, La) (Zr, Ti) O₃PLZT), Lithium niobate (LiNbO)₃), Lithium niobate (K)₃Li₂Nb₅O₁₅) Etc. are used. These ferroelectric films are polarized by applying a voltage. The relationship between voltage and polarization exhibits so-called hysteresis characteristics.

[0003] Regarding this relationship, when the inventor measured the characteristics of the ferroelectric film, it was found that the physical stress applied from the outside affects the hysteresis characteristics. That is, it was found that when a physical stress is applied to the ferroelectric film after the film formation, the hysteresis loop becomes smaller and the polarization retention characteristic deteriorates. Ferroelectric memory uses polarization to hold data. Therefore, it is clear that the physical stress applied from the outside leads to the deterioration of the data retention characteristics. Figure 45 (a) shows the layout of the memory cell array and peripheral circuits of the conventional non-volatile semiconductor storage device. A plurality of memory cell arrays are arranged in parallel, and a low decoder (RD) (word line selection circuit) 40 is shared by these. The plurality of word line WLs are selected by the low decoder circuit 40 according to the address signal input from the outside. The plate wire PL is connected in common to the memory cell array (connected to the counter electrode of the cell capacitor) in the same manner as the word wire WL, and is driven by the plate decoder (PD) (plate wire selection circuit) 38. The plate decoder 38 is formed by connecting a NAND circuit and an inverter circuit in series, and controls the plate electrodes by taking the logic of the word line signal and the plate line control signal. Word line signals and plate line signals for writing and reading are pulse signals, but as shown in FIG. 45 (b), the plate line signal that controls the plate line has a shorter pulse width than the word line signal. Since the plate line signal starts up and down in a short time in this way, the reading speed of the information in the memory cell is controlled by the pulse of the plate line signal. If this is avoided, it is necessary to increase the transistor of the inverter circuit of the plate wire selection circuit. However, if the transistor of the inverter circuit is made unnecessarily large, the pitch of the word line drive unit of the low decoder circuit and the pitch of the plate line selection circuit do not match, and the interval between the word line and the plate line is regulated to the wider side. The waste of area increases accordingly.

[0004] As described above, the non-volatile ferroelectric memory used in a conventional transponder has a CR (capacity / resistance) when decoding (pulse driving) a plate wire. Since it is large, there is a risk that the data written in the cell cannot be sufficiently read because the plate line operates with a delay, or the data cannot be sufficiently written in the cell. Further, the word wire is only connected to the gate of the transistor of the memory cell, whereas the plate wire is commonly connected to the counter electrode of the cell capacitor as described above, so that the additional capacitance is very large. As a result, it takes longer to drive the plate wire than when the word wire is driven. Since the plate line signal starts up and down in a short time, the reading speed of the information in the memory cell is controlled by the pulse of the plate line signal, so it is necessary to increase the signal speed of the plate line signal. Further, particularly when a non-volatile ferroelectric memory is mounted on a memory card or the like, if the thickness of the memory card is thin, physical stress is easily applied from the outside, and as a result, there is a problem that the data retention characteristics are deteriorated.

[0005] However, it is known that the shape of this hysteresis characteristic changes significantly depending on the temperature. That is, the hysteresis loop at a high temperature (for example, 80 ° C) becomes smaller than that at a low temperature (for example, 25 ° C at room temperature), and the polarization retention characteristic deteriorates. Ferroelectric memory uses polarization to hold data. Therefore, the presence of a heat source in the chip leads to deterioration of data retention characteristics. In particular, when a non-volatile ferroelectric memory is mounted on a non-power supply type memory card or the like, heat generated by a power supply circuit, a rectifier circuit, or the like may affect the data retention characteristics of the ferroelectric memory. FIG. 46 is a hysteresis curve of a ferroelectric material used for a memory cell (FRAM cell) using a ferroelectric film as a capacitor. When writing and reading operations, the state is changed along the edge of the curve in the order of a b c d. However, the current actually flows at b and d. The current required to reverse the polarization of the cell flows only at b and d. Therefore, even when the plate wire PL is driven as shown in FIG. 47 (a), almost no current flows in the first half of the rise of the plate wire PL, whereas the current flows in a pulse manner in the latter half (Fig. 47 (b)). .. When the current flows intensively in such an extremely short period of time, the maximum amount of current increases, and as a result, various malfunctions may occur due to fluctuations in the power supply potential and fluctuations in the reference potential caused by the fluctuations.

[0006] The present invention has been made in view of the above circumstances, and is a plate wire having a structure in which the risk of causing a malfunction when decoding (pulse driving) the plate wire is prevented and the driving speed thereof is improved. To provide a non-volatile ferroelectric memory mounted on a transponder. The present invention also provides a non-volatile ferroelectric memory capable of reducing the maximum amount of drive current flowing through the plate wire while improving the drive speed of the plate wire, and a method for driving the same.

[Means for Solving the Problems] In the non-volatile strong dielectric memory of the present invention, a capacitor for information storage using a strong dielectric for an interelectrode insulating film and a MOS transistor for charge transfer are connected in series. A memory cell array in which connected memory cells are arranged in a matrix, a plurality of word lines commonly connected to the gates of MOS transistors of the same memory cell, and one end of a capacitor of the same memory cell, respectively. A plurality of commonly connected plate wires, the word wire and the plate wire are arranged in parallel, and a plurality of plate wires are further divided with respect to the corresponding word wire, and the same memory is used for each. A plurality of bit lines commonly connected to one end of a MOS transistor of a cell, a word line selection circuit that selects a part of the plurality of word lines based on an address signal, and the plurality of word lines. And, for example, a Chip Enable signal ( It is characterized in that a plate wire selection circuit formed by a signal generated by an external terminal such as / CE) and a plurality of plate wire selection circuits exist for each word line. Further, the plurality of plate selection circuits corresponding to the word lines operate independently depending on the address signal, and all the plate selection circuits do not operate during normal operation. For each word line of a plurality of word lines, each has a plurality of plate line selection circuits (plate decoders), has divided plate lines, and partially decodes each of them, for example, a column address signal or the like. Since it is performed by the address signal of, the CR is no longer a large plate wire, and there is a sufficient operating margin to reduce the risk of malfunction.

[0008] Further, in the present invention, in a configuration in which a plate wire of a non-volatile ferroelectric memory using a ferroelectric film as a capacitor is divided into a plurality of plates in the row direction and the plate wires are driven, the driving timing of the divided plate wires It is characterized by reducing the current that flows temporarily by shifting. Further, the non-volatile ferroelectric memory of the present invention has a memory cell array in which ferroelectric memory cells using a ferroelectric film as an information storage capacitor are arranged in a matrix, and a gate of a transistor of a memory cell in the same row. A plate wire having a common connection of a word wire, a plate wire having a common connection of counter electrodes of capacitors of memory cells in the same row, and a row decoder for selecting and driving the word wire are provided, and the plate wire is aligned in the row direction. It is divided into n, and n plate wire selection circuits are connected to one end thereof, respectively, and the gate capacitance of the transistor of the memory cell is smaller than the capacitor capacitance of the memory cell.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the invention will be described with reference to the drawings. RFID systems are non-contact tag systems (identifiers) that use radio waves, and are also generally referred to as non-contact data carrier systems. The present invention relates to a transponder used in this system, a non-volatile ferroelectric memory mounted on the transponder, and a method for driving the transponder. FIG. 43 is a system configuration diagram of the entire RFID system using the transponder of the present invention. The RFID system consists of a host side consisting of a personal computer, a controller, an antenna, etc., and a data carrier called a transponder (Fig. 43 (a)). The transponder has a simple configuration with a built-in monolithic RFID chip in which FRAM and ASIC are integrated into a single chip on the card board and an antenna that also serves as power reception and data reception / transmission (Fig. 43 (b)). FIG. 43 (c) is a plan view of the monolithic RFID chip. The host side transmits commands and data on a carrier wave as needed, but the transponder side generates the required power from the carrier wave and uses it for writing, reading, and transmitting data to return information to the host side. .. The non-contact tag does not require a battery, and can be used for management such as people entering and exiting by reading the stored contents of FRAM non-contact using radio waves and rewriting the contents. For example, you can put a non-contact tag for a commuter pass in your clothes pocket and go to the ticket gate, or you can put a non-contact tag on your car and run without having to stop to pay at the tollhouse on the highway. It can be used for purposes such as monitoring and managing the entry and exit of parking lots without intervention. It can also be used to manage the behavior of migratory fish and livestock.

[0012] FIG. 44 shows the details of the internal circuit of the transponder. An LC circuit that detects an electromagnetic field input from the outside, a circuit that generates a signal from the electromagnetic field detected by the LC circuit (FSK demodulation circuit) 58, and a circuit that generates a power supply voltage from the electromagnetic field detected by the LC circuit (rectifying bridge). A plurality of memory cells including 59, a power-on circuit 60 that detects a rise in power supply voltage and outputs a power-on signal, a dielectric capacitor having a dielectric film between electrodes, and a MOS transistor for charge transfer. Arranged in a matrix, for example, MOS transistors of memory cells belonging to the same row are commonly connected by the same word line, and one electrode of the strong dielectric capacitor of the memory cell belonging to the same row is connected to the same capacitor plate wire. It is composed of an FRAM cell array 31 and the like, which are commonly connected to each other and one terminal of a MOS transistor of a memory cell belonging to the same row is commonly connected by the same bit line.

[0013] Next, a first embodiment will be described with reference to FIGS. 1 to 15. Figure 1 shows a cross-sectional view of the non-volatile ferroelectric memory mounted on the transponder. This ferroelectric memory is used mounted on a transponder as shown in FIG. 43 as a monolithic RFID chip. An element-separating insulating film 13 made of a silicon oxide film is formed on the surface of the P-type silicon substrate 10, and a MOS transistor is formed in a region partitioned by the element-separating insulating film 13. The MOS transistor is composed of source / drain regions 11 and 12 composed of N-type diffusion regions, a gate insulating film 21, gate electrodes 20 composed of polysilicon, and the like. The gate electrode 20 is referred to as a word line (WL). Silicon oxide (SiO) on this MOS transistor₂An interlayer insulating film 14 such as) is formed, and a contact hole 22 reaching the source region 12 is formed in the interlayer insulating film 14. A ferroelectric capacitor is formed on the interlayer insulating film 14. The ferroelectric capacitor is composed of a lower layer electrode 15, a ferroelectric film 16 composed of a PZT film and the like, and an upper layer electrode 17. The lower electrode 15 is referred to as a plate electrode (plate wire) (PL). This ferroelectric capacitor is covered with an interlayer insulating film 18 made of a silicon oxide film or the like, and the upper electrode 17 of the ferroelectric capacitor and the source region 12 are a contact hole of the interlayer insulating film 18 and a contact hole of the interlayer insulating film 14. It is electrically connected via a connecting wiring 19 such as aluminum via 22.

FIG. 2 shows the applied voltage / polarization characteristics of a ferroelectric thin film such as a PZT film. The ferroelectric thin film has a hysteresis characteristic as shown in FIG. Then, the data can be stored depending on whether the remanent polarization Pr in the state where no voltage is applied, that is, in the state of V = 0 (V) is "positive" or "negative". FIG. 3 shows a hysteresis characteristic that is not preferable for a ferroelectric memory cell of a non-volatile ferroelectric memory. That is, there are problems that the remanent polarization Pr is very small, and as a result, the read margin by the sense amplifier is lowered, and the data is easily lost due to external disturbance. The characteristics shown in FIG. 3 are hysteresis characteristics at a high temperature of 80 ° C. Subsequently, the writing operation of the memory cell using the ferroelectric thin film will be described with reference to FIGS. 4 and 5. A non-volatile ferroelectric memory using an FRAM cell constitutes one memory cell by two MOS transistors Q1 and Q2 and ferroelectric capacitors C1 and C2. Then, in the state of FIG. 4A, that is, the capacitor C1 has an upward polarization (hereinafter referred to as positive polarization) as shown by the upward arrow in the figure, and the capacitor C2 has the downward polarization as shown by the downward arrow in the figure. The state in which downward polarization (hereinafter referred to as negative polarization) appears is defined as "1", and the state shown in Fig. 4 (b), that is, the negative polarization in the capacitor C1 and the positive polarization in the capacitor C2. The appearing state is defined as "0".

(1 write operation) The steps for writing 1 to the memory cell are shown below. First, 5V is applied to the bit line BL, and 0V is applied to the bit line / BL (/ represents an inverted signal, hereinafter the same). Then, 7V is applied to the word line WL, and 0V is applied to the plate electrode PL. In this state, the capacitor C1 is in the state of a in FIG. 2, and the capacitor C2 is in the state of b in FIG. Next, set PL to 5V. As a result, the capacitor C1 is in the state b in FIG. 2, and the capacitor C2 is in the state c in FIG. Then, set PL to 0V. As a result, the capacitor C1 is in the state of a in FIG. 2, and the capacitor C2 is in the state of d in FIG. Figure 5 shows the change in the potential (VPL) of the plate electrode PL during writing. As described above, the state shown in FIG. 4A, that is, the positive polarization appears in the capacitor C1 and the negative polarization appears in the capacitor C2, and "1" writing is realized.

(0 write operation) The steps for writing 0 to the memory cell are shown below. First, 0V is applied to the bit line BL, and 5V is applied to the bit line / BL. Then, 7V is applied to the word line WL, and 0V is applied to the plate electrode PL. In this state, the capacitor C1 is in the state b in FIG. 2, and the capacitor C2 is in the state a in FIG. Next, set PL to 5V. As a result, the capacitor C1 is in the state of c in FIG. 2, and the capacitor C2 is in the state of b in FIG. Then, set PL to 0V. As a result, the capacitor C1 is in the state d in FIG. 2, and the capacitor C2 is in the state a in FIG. As described above, the state shown in FIG. 4B, that is, the negative polarization appears in the capacitor C1 and the positive polarization appears in the capacitor C2, and "0" writing is realized.

[0017] The non-volatile ferroelectric memory as described above is used for a non-powered ID device or the like because it consumes a small amount of power. A non-powered ID device receives radio waves from the outside, uses the DC voltage obtained by rectifying the radio waves as a power source, and receives and detects the information used as the radio wave carrier signal to input data to the outside. Output. The non-powered ID device is usually equipped with a radio wave transmission circuit. With the above configuration, the ID card can be configured without a power source, and information can be exchanged with the outside without any contact with the master unit. The above-mentioned non-powered ID cards are expected to be applied to driver's licenses, product tags, identification cards, commuter passes, ski lift tickets, and the like. Subsequently, FIGS. 6 and 7 show the arrangement of the memory cell array of the non-volatile ferroelectric memory and the peripheral circuits. The memory cell array 31 to 34 are arranged in parallel, and the word line selection circuit (low decoder RD) 40 is shared by these. When a plurality of memory cell arrays 31 to 34 are largely divided into two, a low decoder 40 is arranged in the center, and a plurality of word lines WL are wired to the low decoder 40. Then, the memory cell array separately arranged on the left and right is further divided and the plate line selection circuits (plate decoder PD) 35 and 36 are arranged respectively, and the plate line PL (PL1, PL2, respectively) are arranged from the plate decoders 35 and 36, respectively. PL3, PL4) are wired.

The word line WL is selected by the row decoder 40 according to an address signal input from the outside. The plate line PL is provided separately for each memory cell array, and is driven by the plate decoders 35 and 36 as shown in FIG. First, the sense amplifier circuits (S / A) 41 to 44 are provided for each memory cell array, and amplify the minute potential difference appearing in the bit line at the time of reading. A column gate circuit (not shown) selectively connects a data line and a bit line based on a column selection line. The column decoder (CD) 56 selects a column selection line (not shown) according to an address signal input from the outside. A data line sense amplifier circuit (not shown) amplifies the data on the data line. The circuit shown in FIG. 8 is the plate decoder of the present invention. The plate decoder is composed of a NAND circuit and an inverter circuit to which the output signal of the NAND circuit is input, and the inverter circuit supplies a power supply voltage (Vcc) as a plate voltage (VPL). As the input signal of the NAND circuit, the φ6 signal is / CE (Chip Enable signal) (if it is DRAM). It is a signal with a delay signal and a pulse from / RAS) (see Fig. 9). The Yα signal is an address related to the lateral direction in some address signals. In addition, WL indicates the corresponding word line for each. Here, for example, in the memory cell array shown in FIGS. 6 and 7, there are four divided plate line PLs for one word line WL. Therefore, one of the four plate wires is selected by this address signal (Yα). As a result, the capacity of the plate wire is at least 1/4 that of the conventional plate wire, so that the decoding of the plate wire becomes faster and malfunction can be prevented.

FIG. 11 is another embodiment of the plate decoder. For example, if there are two addresses i and j, the address buffer will generate complementary signals Aic // Aic and Ajc // Ajc (see Figure 10). If you make a precoder using this, it will be as shown in Fig. 12 (a). There are four types of input methods shown in Fig. 12 (b). By this method, four Yα signals (Yα0, Yα1, Yα2, Yα3) are generated. When these four Yαj signals are input to the plate decoder shown in FIG. 11, one of the four plate voltages (VPLs) can be pulse-driven. The input signals (WL, VPL, / CE (φ6)) of the plate decoders of FIGS. 8 and 11 have voltage waveforms as shown in the timing diagram of FIG. 13. A detailed circuit diagram is shown in FIG. 14. The row decoder is a circuit that selects word lines. A set of decoders is selected by the signals Xαj, Xαk, and Xαl that pre-decode the row address. One set of decoders Four word lines are connected to, and one of them is selected by the signals WDRVi to WDRVl.

[0020] Further, the details of the sense amplifier used for the memory cell array of FIGS. 6 and 7 are shown in FIG. FIG. 15 shows the details of the memory cell array 31, the sense amplifier circuit 41, and the column gate circuit 51. The memory cell array 31 includes memory cells 30 arranged in a matrix, and memory cells arranged in the same column have the same bit line pair (BLn; Memory cells connected to / BLn) (n = 1, 2, ...) and placed in the same row have the same word line WLn (n = 1, 2, ...), plate line PLn (n = 1, 2, ...) is connected. The sense amplifier circuit 41 is composed of a plurality of sense amplifiers 411, and a single sense amplifier is composed of two cross-connected P-type MOS transistors and two cross-connected N-type MOS transistors. .. This sense amplifier 411 is driven and controlled by the P-type sense amplifier drive line SAP and the N-type sense amplifier drive line / SAN. Further, an equalization circuit 412 composed of two N-type MOS transistors is connected for each bit pair, and is controlled by the equalization selection line EQ. The column gate circuit 51 is composed of column gates connected for each bit line, and each column gate is composed of two MOS transistors. These MOS transistors are selectively driven by the column selection line CSL.

Next, a second embodiment will be described with reference to FIGS. 16 to 18. FIG. 16 is a partial circuit diagram showing a detailed structure of a memory cell array and peripheral circuits of a non-volatile ferroelectric memory (FRAM) mounted on a transponder. Memory cells 31 to 34 are arranged in which memory cells (FRAM cells) 30 using a ferroelectric film as an information storage capacitor are arranged in a matrix. The word line WL commonly connects the polysilicon gates of those memory cells 30. The plate wires PL1 to PL4 formed by connecting the counter electrodes of the capacitors of the memory cells 30 in the same row in common are divided into n in the row direction (here, divided into four), and four plate wire selection circuits 35 to 38 are one end thereof. Are connected to each. These plate wire selection circuits are composed of a NAND circuit and an inverter circuit, and the inverter circuit supplies a power supply voltage Vcc to the plate wire as a plate voltage (VPL). A plurality of plate wire control lines PLC1 to PLC4 are arranged in the row direction along the plate wire selection circuit. Plate line control line drive circuits 62 to 65 that independently drive these plate line control lines are connected to the plate line control lines, respectively. The plate wire control line PLC is connected to one of the two inputs of the NAND circuit of the plate wire selection circuit, and the gate wire WL is connected to the other.

[0022] As shown in FIG. 16, a feature of this embodiment is that in a configuration in which the memory cell array is divided into a plurality of parts and the plate wires are divided and driven, the maximum current that temporarily flows by shifting the drive timing of the plate wires is increased. To reduce. As shown in the figure, for example, plate wire PLs (PL1 to PL4) that are independently driven and controlled are arranged in each of the four blocks, and a plate wire control line driving circuit 63 that controls the driving of these plate wire PLs 63. ~ 65 have delay line chains (D1, D2, D3) 66 ~ 68 at their inputs, respectively. As a result, as shown in FIG. 17 (a), the latter half of the rise of each plate wire PL (PL1 to PL4) is slightly shifted, so that the current flows in a dispersed manner. As a result, the maximum amount of current (| Isum) |) Will be significantly reduced as compared with the conventional case (Fig. 17 (b)). In this embodiment, the adjustment of the delay time of the delay line is important. If the delay time is long, the read / write cycle becomes long, and it becomes impossible to provide high-speed memory. As described above, in FRAM, the current flows only in a pulsed manner only in the latter half of the rising or falling of the plate wire. Therefore, the rise or fall times of the plate wires may overlap. Specifically, it is assumed that it takes 5 ns for each plate wire to rise. However, the actual current flows in the last 0.5ns. Therefore, in this case, 4.5 ns may be overlapped. Therefore, the delay time of the delay line is determined to be 0.5 ns or more. More generally, assuming that the rise time of the plate wire is t and the lamp rises to the lamp state, it is known that no current flows in about 90% of the time and a large amount of current flows in the remaining 10%. As a result, a delay time of 1/10 or more may be set. An example of the delay line is shown in FIG. The delay line is generally configured by connecting inverter circuits in series, but if the delay time is less than 1 ns, it is possible that only metal wiring is sufficient. 18 (a) and 18 (b) show an inverter circuit, and FIG. 18 (c) shows an example of metal wiring such as aluminum.

Next, a third embodiment will be described with reference to FIGS. 19 to 23. FIG. 19 is a partial circuit diagram showing a detailed structure of a memory cell array and peripheral circuits of a non-volatile ferroelectric memory mounted on a transponder. Memory cells 31, 32, ... In which memory cells (FRAM cells) 30 using a ferroelectric film as an information storage capacitor are arranged in a matrix (matrix) are arranged. The word line WL commonly connects the polysilicon gates of those memory cells 30. A metal wiring word wire Al-WL such as aluminum is formed on a semiconductor substrate on which the word wire WL is formed via an interlayer insulating film. This word line WL is connected to the metal wiring word line Al-WL by a shunt line SL at predetermined intervals. The plate wires PL (PL1, PL2, ...) Formed by connecting the counter electrodes of the capacitors of the memory cells 30 in the same row in common are divided into n in the row direction, and n plate wire selection circuits 35 and 36 are included in the plate wires PL (PL1, PL2, ...). Each is connected to one end. The plate wire selection circuits 35 and 36 are composed of a NAND circuit and an inverter circuit, and the inverter circuit supplies a power supply voltage to the plate wire. The plate wire selection circuits 35 and 36 are arranged in this shunted area and are arranged between the memory cell array. A plurality of plate wire control line PLCs (PLC1, PLC2 ...) Are arranged in a column direction along the plate wire selection circuit. Plate line control line drive circuits 61, 62, ... That independently drive these plate line control line PLCs are connected to the plate line control line PLC, respectively.

[0024] A plate wire control line is connected to one of the two inputs of the NAND circuit of the plate wire selection circuit, and a gate wire is connected to the other. The gate capacitance (C1) of the transistor of the memory cell is smaller than the capacitor capacitance (C2) of the memory cell (C1 <C2). FIG. 20 is a circuit diagram of plate wire selection circuits 35 and 36. The plate wire PL (PL1, PL2 ...) Is driven by the plate wire selection circuits 35 and 36. The plate wire selection circuits 35 and 36 are formed by connecting a NAND circuit and an inverter circuit in series, and control the plate electrodes by taking the logic of the word line signal WL and the plate line control signal PCL. FIG. 21 is a detailed circuit diagram of FIG. 20, and the inverter circuit is composed of an N-channel transistor N2 and a P-channel transistor P2. In this embodiment, the power supply voltage Vcc is 5V. FIG. 22 is a detailed circuit diagram of the low decoder (RD) 40 shown in FIG. As shown in FIG. 22, the width / length ratio ((W / L) 1) of the gate of the transistor in the low decoder 40 ) And the gate capacitance (C1) of the transistor of the memory cell 30 are the width / length ratio ((W / L) 2) of the gate of the transistor in the plate wire selection circuit PL and the capacitor capacitance (C1) of the memory cell. Since it is almost equal to the product of C2) ((W / L) 1 C1 ~ (W / L) 2 C2), the rise time and fall time of the signal can be made equal.

Further, as shown in FIG. 22, the low decoder has an inverter configuration in which the P-channel transistor P1 and the N-channel transistor N1 are directly connected to the final stage, and the plate wire selection circuits 35 and 36 are in the final stage. It has an inverter configured by connecting the P-channel transistor P2 and the N-channel transistor N2, and the width / length ratio ((W / L) n1) of the gate of the N-channel transistor in the row decoder and the transistor of the memory cell MS. The product of the gate capacitance (C1) is the gate width / length ratio ((W / L) n2) of the N-channel transistor N2 in the plate wire selection circuit and the capacitor capacitance (C2) of the memory cell MS. It is composed almost equal to the product ((W / L) n1 C1 ~ (W / L) n2 C2). The product of the gate width / length ratio ((W / L) p1) of the P-channel transistor P1 in the low decoder RD and the gate capacitance (C1) of the transistor of the memory cell MS is the plate wire selection circuits 35 and 36. It is configured to be approximately equal to the product of the gate width / length ratio ((W / L) p2) of the P-channel transistor P2 in the memory cell and the capacitor capacity (C2) of the memory cell ((W / L) p1 ·. C1 ~ (W / L) p2 C2).

Further, the width / length ratio ((W / L) n1) of the gate of the N-channel transistor N1 in the low decoder RD is the width / length ratio of the gate of the P-channel transistor P1 in the low decoder RD ((W / L) n1). It is configured to be smaller than (W / L) p1) ((W / L) n1 <W / L) p1. Furthermore, the width / length ratio ((W / L) n2) of the gate of the N-channel transistor N2 in the plate wire selection circuits 35 and 36 is the width / length of the gate of the P-channel transistor P2 in the plate wire selection circuits 35 and 36. It is configured to be smaller than the length ratio ((W / L) p2) ((W / L) n2 <(W / L) p2). As shown in FIG. 23, the metal wiring word wire Al-WL is shunt-connected to the word wire WL. The shunt line SL is arranged at regular intervals. In the present invention, the shunt wire SL and the plate wire selection circuits 35, 36, 37, 38 connected to one end of the plate wires PL1, PL2, ... Are connected to each predetermined shunt wire SL. In this embodiment, the shunt wires directly connected to the plate wire selection circuit are arranged every three. Therefore, the ratio (C1: C2) of the gate capacitance (C1) of the transistor of the memory cell to the capacitor capacitance (C2) of the memory cell is 1: 4, and the capacitor capacitance (C2) is about four times larger. ..

Next, a fourth embodiment will be described with reference to FIGS. 24 to 28. FIG. 24 shows an example in which a non-volatile ferroelectric memory (semiconductor element) 2 using a ferroelectric material is mounted on a card substrate 1 made of a plastic material. Here, the mounting position is very important. That is, since the card substrate has elasticity, "warp" occurs due to physical stress applied from the outside. Figure 25 shows the state. That is, it is assumed that the forces of Fa and Fb are applied along the long side of the card 1. The absolute values of Fa and Fb are equal and the directions are opposite. As a result, the forces of F1, F2, and F3 are applied to the card substrate. Figure 26 shows this in a partial area. The size of F2 in FIGS. 25 and 26 depends on the position shown in FIG. 24 (distance from the end of the card in the long side direction). That is, FIG. 27 shows the relationship between the distance d from the end of the card in the long side direction to the mounting position and the size of F2, where the length l in the long side direction of the card is 100. As shown in FIG. 27, the magnitude of F2 rises sharply from the point where the distance d exceeds 30 from both ends, and decreases again when the distance d exceeds 70. A metal plate can be interposed between the card substrate and the semiconductor element or chip (nonvolatile ferroelectric memory) to stabilize the semiconductor element or chip. FIG. 28 shows the relationship between the distance d and the remanent polarization Pr. In this way, the magnitude of the remanent polarization Pr decreases sharply from the point where d exceeds 30 from both ends, and rises again when d exceeds 70.

[0028] From the above, it is understood that the position where the non-volatile ferroelectric memory (semiconductor element) using the ferroelectric material of the card is mounted should be within 30% from the end of the elastic card. To. And if the card is rectangular, it is desirable that it is within 30 percent of the short side, not within 30 percent of the long side. This is because the card user tends to apply a force in the long side direction. When a transmitting / receiving antenna or the like is attached to this card and connected to this semiconductor element or chip, the transponder shown in FIG. 43 is formed.

[0029] Next, a fifth embodiment will be described with reference to FIGS. 29 to 31. As described above, when a force is applied to the card substrate, an external force such as F2 naturally acts on the memory cell formed in the semiconductor element mounted on the card substrate (see FIGS. 24 to 26). FIG. 29 is a schematic plan view of a memory cell of a non-volatile ferroelectric memory (semiconductor element or chip) mounted on a transponder. A plurality of memory cells are arranged and formed in a matrix in the form of a memory cell array in this semiconductor element. The figure shows a part of a memory cell array. As shown in FIG. 1, the memory cell includes a MOS transistor having a gate 20 and a capacitor having a ferroelectric film 16 made of PZT or the like. In this embodiment, one cell of the memory cell is composed of two transistors and two capacitors (2T / 2C), but the memory cell is not limited to this configuration and may be one transistor and one capacitor (1T / 1C). .. In this embodiment, the shape of the ferroelectric film of the capacitor is characteristic. In FIG. 29, the ferroelectric film F of the capacitor shown by the diagonal line has a square shape. When an external force is applied to the card substrate, the stress applied to the ferroelectric film F formed on the semiconductor element mounted on the card substrate is proportional to its length. Therefore, when the area of the ferroelectric film F is constant, the square shape is more resistant to stress than the rectangular shape. By the way, the magnitude of stress applied to the ferroelectric film affects its hysteresis characteristics. Therefore, if such a stress-resistant ferroelectric film is used, a memory card having high data retention characteristics can be obtained.

[0030] The card substrate 1 of the memory card shown in FIG. 24 is composed of a substantially rectangular plastic elastic body. The semiconductor element 2 formed on the semiconductor substrate of this embodiment is also substantially rectangular. Then, the semiconductor element 2 is mounted near the short side of the card substrate 1 so that the long side of the semiconductor element 2 is parallel to the short side of the card substrate 1. When the semiconductor element 2 is arranged in this way, a large amount of stress is not applied to the semiconductor element. The semiconductor element 2 may be mounted via a metal plate, or may be mounted directly. The former provides higher reliability, and the latter provides low cost and ultra-thin cards. In particular, the latter is possible only by using the configuration of this embodiment. FIG. 30 is a plan view showing another shape of the ferroelectric film of the capacitor. The stress-resistant ferroelectric film includes the above-mentioned square-shaped body, and there are a chamfered four corners of the square-shaped body (Fig. 30 (a)) and a circular body (Fig. 30 (b)). The chamfered body has a radius of curvature R attached to each corner of the square. The stress applied to the ferroelectric film changes depending on the magnitude of the radius of curvature R. FIG. 31 is a characteristic diagram showing the radius of curvature R irrelevance of the stress (F2) applied to the ferroelectric film. Assuming that the length of one side of the square is L, the stress is almost constant until R is about 0.1R, but the stress suddenly decreases around 0.2R to 0.3R and becomes 0.5R (that is, a circular body) and the stress becomes Become the minimum. By using a stress-resistant ferroelectric film having the above shape, it is possible to obtain a memory card having high data retention characteristics provided for the transponder shown in FIG. 43.

Next, a sixth embodiment will be described with reference to FIGS. 32 and 33. FIG. 32 is a plan view and a cross-sectional view of a memory card equipped with a non-volatile ferroelectric memory (semiconductor element or chip) including a ferroelectric memory cell mounted on a transponder. The card substrate 1 shown in FIG. 24 is composed of a substantially rectangular plastic elastic body having a long side A and a short side B. The semiconductor substrate 2 on which the semiconductor element of the present invention is formed is substantially rectangular with a long side a and a short side b. The semiconductor element 2 is mounted close to the short side B of the card substrate 1 so that the long side a of the semiconductor element 2 is parallel to the short side B. The semiconductor element 2 may be mounted via the metal plate 3 or may be mounted directly (the metal plate 3 is used in this embodiment). The former can provide higher reliability, and the latter can realize low-cost, ultra-thin cards. In particular, the latter is possible only by using the configuration of this embodiment. The magnitude of this external force F2 depends on the mounting direction of the semiconductor element 2. Further, this size depends on the length of the semiconductor element in the long side direction of the card substrate 1. The silicon substrate (chip) on which the semiconductor element 2 is formed has a substantially rectangular shape, and when the long side a is arranged parallel to the short side B of the card as shown in FIG. 32, the external force F2 is small and the external force is small. On the contrary, when it is arranged vertically as shown in FIG. 33, the external force F2 becomes large, and therefore this arrangement method is not advantageous. As described above, the magnitude of the external force F2 affects the hysteresis characteristics of the ferroelectric film. Therefore, in order to obtain a memory card having high data retention characteristics provided for a transponder or the like, it should be mounted as shown in FIG. 32 instead of being mounted as shown in FIG. 33.

Next, a seventh embodiment will be described with reference to FIGS. 34 to 38. Figure 34 (a) shows a non-volatile ferroelectric memory (semiconductor element) in which the circuits required for an RFID system are mounted on a single chip. FIG. 34 (b) is an example of a transponder in which this semiconductor element is mounted on a card substrate made of a plastic material used for this RFID system. As shown in FIG. 34 (b), a 1-chip type mixed non-volatile ferroelectric memory (semiconductor element) 60 is mounted on one end of a card substrate 69 made of a plastic material. A transmission / reception antenna 88 is stretched around the card board 69 in a loop. The semiconductor element 60 has a configuration as shown in FIG. 34 (a). That is, a row of input / output pads 601 is arranged at one end (preferably on the short side side) of the semiconductor element. A rectifier circuit 633 and a detection / transmission circuit 634 are arranged in the vicinity of the input / output pad 601. In the rectifier circuit 633, a DC 5V voltage is generated from the carrier wave of the input signal by a diode bridge circuit or the like. In the detection / transmission circuit 634, if the signal received by the antenna 88 is AM-modulated, for example, by the heterodyne method, and if it is FM-modulated, the information is received from the outside by, for example, the PLL method, and vice versa. Information is transmitted to the outside using the antenna 88. The non-volatile ferroelectric memory is arranged at the other end of the semiconductor element (particularly on the opposite side of the rectifier circuit 633). By arranging in this way, the heat generated in the rectifier circuit can be effectively dispersed. The configuration of the non-volatile memory is as follows. That is, it is composed of a non-volatile memory cell array 611, 612, a row decoding circuit 614, a plate decoding / driving circuit 613, 615, a sense amplifier array 616, 617, a column selection circuit 618, 619, and the like.

[0033] Various control circuits, arithmetic circuits, etc. 631 and 632 are arranged between the memory cell and the power supply system circuit (rectifier circuit 633, etc.). It is preferable that these arithmetic circuits have a standard cell structure for ASICs in order to shorten the design time and further to effectively dissipate heat. A power supply line is provided between the memory cell section (FRAM cell section) of the non-volatile ferroelectric memory and the power supply system circuit, and the DC voltage generated in the power supply system circuit is supplied to the non-volatile ferroelectric memory cell. To do. The power supply line consists of a VCC (high potential side) power supply line 84 and a VSS (low potential side) power supply line 85, and the potential difference between the two is usually 5V. The heat storage means 86 and 87, which are the features of the present application, are arranged in the middle of the power supply line. The heat storage means 86 and 87 are protrusions made of the same member (preferably aluminum) as the material provided on the power supply line, and are hereinafter referred to as lobes. FIG. 35 shows a characteristic diagram illustrating the effect of providing the lobe. The vertical axis of FIG. 35 shows the temperature, the horizontal axis shows the position (d) between the power supply system circuit such as the rectifier circuit on the semiconductor element and the FRAM section, and FIG. 35 shows the position (d) on the semiconductor element. It shows the state of temperature dispersion. As shown in the figure, if there is no lobe (curve B shown by the dotted line), heat is transferred from the power supply system circuit section, which tends to be relatively hot, to the FRAM cell section without any trouble, and the heat is transferred to the memory cell. The temperature will rise. This can lead to deterioration of the data retention characteristics as described above. The temperature distribution at this time is shown by the dotted curve B. The temperature distribution with the lobe is shown by the solid line curve A. The shape actually used is a rectangular shape with aluminum wiring VCC / VSS having a thickness of 1.1 μm and a width of 10 μm and a lobe shape of 150 × 900 μm, respectively. The sudden change in heat transfer due to the provision of the lobe is probably due to the fact that the power line played a major role in heat transfer.

[0034] Fig. 36 shows an example of deformation of the lobe. The same symbols as above are attached to the power line, robe, etc. Reference numeral 630 denotes an arithmetic circuit, a control circuit, and the like. In this way, by arranging the VCC line and the VSS line at a certain interval and spreading the lobe to the left and right, more effective heat insulation becomes possible. FIG. 37 shows an example in which a neck (neck) 70 is provided between the robes 86 and 87 and the power lines 84 and 85. Normally, the power supply circuit of a non-powered ID device does not operate for a long time (1 second or less), but when an exceptionally large amount of data processing is required, the operating time may be several seconds. In such a case, it is necessary to prevent the heat capacity of the lobe from being saturated immediately, and the configuration shown in FIG. 37 is preferable for a non-powered ID capable of operating for a long time. Power lines, lobes, etc. are marked with the same symbols as described above. FIG. 38 (a) shows an example in which the lobe is shared with a contact portion for supplying power to a transistor such as a control circuit. That is, the power line 84 is provided with a lobe 86, and the lobe is provided with a contact hole 72 for supplying the source power of the transistors (source 74, drain 75, gate 73) arranged under the lobe 86. There is. FIG. 38 (b) shows the equivalent circuit. With this configuration, the chip area can be reduced. The above examples have been described by taking a PZT ferroelectric film as an example, but the present invention is not limited to this, and as shown in FIG. 39, for example, BaTiO.₃It can also be applied to (BTO) membranes. Also, as a matter of course, PLZT film, LiNbO₃Membrane, K₃Li₂Nb₅O₁₅Membranes are also applicable.

Next, the ferroelectric thin film manufacturing process will be described with reference to FIGS. 40 to 42. For the production of the ferroelectric thin film, for example, a sol-gel method, a sputtering method, a MOCVD method, or the like is used. It is the sol-gel method and the sputtering method that can obtain more remarkable effects in combination with the present invention. The sol-gel method or the MOD method is a method obtained by applying a solution using an organometallic compound or the like as a source material on a substrate by dipping or spin coating, and thermally decomposing it. This can be formed even in the atmosphere, and it is easy to increase the area of the film (Fig. 40). The sputtering method is a method in which particles that are knocked out by colliding a gas (Ar gas, etc.) ionized during glow discharge with a target of a material that should be a thin film are deposited on a substrate, and has a high melting point that is difficult to make by the vacuum deposition method. It is possible to form a film such as a material. This film forming method includes direct current sputtering, high frequency (RF) sputtering, magnetron sputtering, ion beam sputtering, reactive sputtering, laser ablation and the like. A sintered body or powder is used as the target, and the mixture is sputtered in an argon and oxygen atmosphere. When a magnet is placed near the target, the sputter ions are constrained by the magnetic field and have a low gas pressure (~ 10).^-4Sputtering becomes possible with Torr), which increases the film growth rate several times.

[0036] The microstructure and characteristics of the ferroelectric film depend on the sputtering conditions (sputter voltage, gas composition and gas pressure, film formation rate, substrate material, substrate temperature, etc.) (Fig. 41). The basis of CVD is to introduce a gas compound of the elements to be made into a thin film into a high-temperature furnace and deposit it on the surface of the substrate to form a film, which forms a film in equilibrium on the surface of the substrate. Since it is a film, a more homogeneous crystal film may be obtained. In MOCVD, a ferroelectric film is formed from an organic metal such as acetylacetonate or alkoxide as a raw material (Fig. 42). The present invention is applicable not only to the case of forming a ferroelectric memory cell on a semiconductor substrate as described above, but also to the case of forming a ferroelectric memory cell on a semiconductor layer on an insulating substrate such as SOI. It is possible to do. Further, the present invention can be implemented by various modifications other than the above-described embodiment.

[Effect of the Invention] As described above, the non-volatile ferroelectric memory mounted on the transponder of the present invention has the above configuration, thereby reducing the CR (capacity / resistance) of the plate wire and causing malfunction. The risk of causing it can be prevented. Further, in the present invention, in a configuration in which a plate wire of a non-volatile ferroelectric memory using a ferroelectric film as a capacitor is divided into a plurality of plates in the row direction and each of them is driven, the drive timing of the divided plate wires is shifted. As a result, the maximum current that flows temporarily can be reduced. Further, in the present invention, since the plate wire drive circuit attached to the divided plate wire is arranged in the shunt region, the chip area can be reduced while reducing the resistance of the word wire.

BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] FIG. 1 is a cross-sectional view of a ferroelectric memory cell (FRAM cell) of the present invention.

FIG. 2 is a characteristic diagram showing the applied voltage / polarization characteristics of the ferroelectric thin film.

FIG. 3 is a hysteresis characteristic diagram in a state unfavorable as a FRAM cell.

FIG. 4 is a circuit diagram of an FRAM cell illustrating a writing operation.

FIG. 5 is a potential change diagram of the plate electrode PL during writing of the FRAM cell.

FIG. 6 is a block diagram showing an arrangement of the FRAM cell array of the present invention and peripheral circuits.

FIG. 7 is a block diagram showing an arrangement of the FRAM cell array of the present invention and peripheral circuits.

FIG. 8 is a circuit diagram of a plate decoder used in the present invention.

FIG. 9 is a circuit diagram of a circuit forming an input signal of the plate decoder of the present invention.

FIG. 10 is a circuit diagram of a circuit forming an input signal of the plate decoder of the present invention.

FIG. 11 is a circuit diagram of a plate decoder used in the present invention.

FIG. 12 is a diagram showing an input signal forming circuit and an input signal of the plate decoder of the present invention.

FIG. 13 is a timing diagram of an input signal of the plate decoder of the present invention.

FIG. 14 is a circuit diagram of a low decoder used in the present invention.

FIG. 15 is a circuit diagram showing an arrangement of the FRAM cell array of the present invention and peripheral circuits.

FIG. 16 is a partial circuit diagram showing a detailed structure of the FRAM cell array and peripheral circuits of the present invention.

FIG. 17 is an operation diagram of the plate wire of the present invention and the conventional plate wire.

FIG. 18 is a circuit diagram of a delay line chain of the present invention.

FIG. 19 is a partial circuit diagram showing a detailed structure of the memory cell array and peripheral circuits of the present invention.

FIG. 20 is a circuit diagram of a plate wire selection circuit of the present invention.

21 is a detailed circuit diagram of FIG.

FIG. 22 is a detailed circuit diagram of the low decoder shown in FIG.

FIG. 23 is a wiring circuit diagram showing an arrangement of word lines and plate lines of the present invention.

FIG. 24 is a plan view of a card substrate in which the semiconductor element of the present invention is made of a plastic material.

FIG. 25 is a cross-sectional view of a card substrate in which warp is generated due to physical stress applied from the outside.

26 is an enlarged cross-sectional view of a partial region of FIG. 25. FIG.

FIG. 27 is a characteristic diagram showing the relationship between the distance d from the end of the card in the long side direction to the mounting position and the size of F2.

FIG. 28 is a characteristic diagram showing the relationship between the distance d on the card substrate and the remanent polarization Pr in the hysteresis curve.

FIG. 29 is a partial plan view of a memory cell array formed in the semiconductor device of the present invention.

FIG. 30 is a plan view showing the shape of a ferroelectric film of a capacitor of the memory cell of the present invention.

FIG. 31 is a characteristic diagram showing the relationship between the magnitude of the radius of curvature of the corner portion of the ferroelectric film of the present invention and the stress applied to the ferroelectric film.

FIG. 32 is a plan view and a cross-sectional view of a card substrate on which the semiconductor element of the present invention is mounted.

FIG. 33 is a plan view and a cross-sectional view of a card substrate on which the semiconductor element of the present invention is mounted.

FIG. 34 is a plan view of a semiconductor element equipped with a circuit required for the RFID system of the present invention and a plan view of the semiconductor element mounted on a card substrate.

FIG. 35 is a characteristic diagram illustrating the effect of providing the lobe of the present invention.

FIG. 36 is a partial plan view of a semiconductor device showing the lobe arrangement of the present invention.

FIG. 37 is a partial plan view of a semiconductor device showing the lobe arrangement of the present invention.

FIG. 38 is a partial plan view and a circuit diagram of a semiconductor element showing the lobe arrangement of the present invention.

FIG. 39 is a characteristic diagram showing the characteristics of the ferroelectric film used in the present invention.

FIG. 40 is a diagram of a ferroelectric thin film manufacturing process of the present invention.

FIG. 41 is a diagram of a ferroelectric thin film manufacturing process of the present invention.

FIG. 42 is a diagram of a ferroelectric thin film manufacturing process of the present invention.

FIG. 43 is a system configuration diagram of an RFID system, a perspective view of a transponder, and a plan view of an RFID chip.

FIG. 44 is an internal circuit diagram of the transponder.

FIG. 45 is a block diagram showing an arrangement of a conventional FRAM cell and peripheral circuits.

FIG. 46 is a hysteresis characteristic diagram of a FRAM cell.

FIG. 47 is a voltage and current characteristic diagram for driving a plate wire of a ferroelectric memory.

[Explanation of codes] 1, 69 ... Card substrate, 2, 60 ... Semiconductor element, 3 ... Metal plate, 10 ... Silicon substrate, 11, 75 ... Drain region, 12, 74 ... Source region, 13 Element separation insulating film, 14, 18 Interlayer insulating film, 15 Lower layer electrode, 16 Strong dielectric film (PZT film), 17 Upper layer electrode , 19 ... Connection wiring, 20, 73 ... Gate electrode, 21 ... Gate insulating film, 22, 72 ... Contact hole, 30 ... Memory cell, 31, 32, 33, 34, 611 , 612 ... Memory cell array, 35, 36, 37, 38 ... Plate wire selection circuit, 40 ... Low decoder circuit, 41, 42, 43, 44 ... Sense amplifier circuit, 51, 52, 53 , 54 ... column gate circuit, 55 ... data line, 56 ... column decode circuit, 57 ... data line sense amplifier circuit, 58 ... FSK demodulation circuit, 59 ... Rectifier bridge, 60 ... Power-on circuit, 61, 62, 63, 64, 65 ... Plate line control line drive circuit, 66, 67, 68 ... Delay line chain, 70 ... Lobe constriction, 84 VCC power line, 85 VSS power line, 86, 87 Lobe (heat storage means), 88 Transmit and receive antenna, 411 Sense amplifier, 412 Equalize circuit, 601 Input / output pad, 613, 615 Plate decoding / drive circuit, 614 Line decoding circuit, 616, 617 Sense amplifier array, 618, 619 Column selection circuit, 630, 631, 632 ... arithmetic circuit, 633 ... rectifier circuit, 634 ... detection / transmission circuit.