Drain power supplies

【0001】

[Field of Invention]

The present invention generally relates to floating gate memory devices such as arrays of flash EEPROM (electrically erasable and programmable read-only memory) cells. More specifically, the present invention has been modified during programming to generate a tuned positive potential and deliver it through the bit lines of an array of flash EEPROM memory cells to the drain region of selected memory cells. Regarding the drain power supply.

【0002】

[Discussion on prior art]

Sameer S. Haddad et al., US Pat. No. 5,077,691, issued December 31, 1991, discloses a flash EEPROM array containing a positive drain voltage charge pump 201. The '691 patent is assigned to the same assignee as the invention and is incorporated by reference. During the sector programming mode of operation, the charge pump 201 in Figure 2B of the '691 patent produces a high level positive potential (ie + 6V), which is applied to the drain region through the bitline of the selected sector, while on the other hand. The drain area of the memory cell of the non-selected sector is in a floating state. In addition, the control gates of all transistors in the selected sector are raised to a relatively high positive voltage of about +12 volts, and their source region is drawn to a zero volt ground potential. Figure 5C of the '691 patent shows a schematic of a charge pump circuit with a single positive voltage charge pump stage 502 for producing +6 volts. The charge pump circuit of FIG. 5C is used for the charge pump block 201 shown in FIG. 2B of the '691 patent.

【0003】

US Pat. No. 5,126,808, issued June 30, 1992 by Antonio J. Montalvo et al., Flash EEPROM with a page-erasing architecture, which also includes a positive drain voltage charge pump. The array is disclosed. The '808 patent is also assigned to the same assignee as the invention and is incorporated by citation. In Figure 7F of the '808 patent, a charge pump circuit 576 consisting of a single positive voltage charge pump stage 570 to generate a high level positive potential of about +6 volts, similar to Figure 5C of the '691 patent. A schematic diagram of is shown.

【0004】

The present invention represents significant improvements made to the charge pump circuits set forth in the '691 and '808 patents described above, respectively. The drain power supply of the present invention is used during programming to generate a tuned positive potential and feed it through the bit lines of an array of flash EEPROM memory cells to the drain region of a selected memory cell. The drain power supply of the present invention is designed to provide approximately 6mA, but can be tuned between + 6.5V and + 6.9V over the military temperature and power supply range.

【0005】

The drain power supply is each driven by one of a plurality of staggered clock signals. It consists of multiple charge pump parts and includes a positive charge pump circuit for generating a moderately high level of positive voltage. The offset circuit is coupled to each of the plurality of charge pump portions to effectively offset the threshold voltage drop in the charge pump circuit. The drain power supply also gradually increases to reduce the high-level positive voltage in response to the adjusted positive potential and reference voltage at the output node, and gradually decreases to deliver the high-level positive voltage to the output node. Includes a tuning circuit to generate an increasing control voltage at the output node. The drain power supplies of the present invention have increased pump efficiency, reduced VCC and VSS noise, reduced ripple, and lower power dissipation than those previously available.

【0006】

[Summary of Invention]

Therefore, a general object of the present invention is to generate a tuned positive potential during programming and provide it through the bit lines of the array of flash EEPROM memory cells to the drain region of the selected memory cell, however. It is to provide an improved drain power supply that overcomes the shortcomings of the prior art power supply.

【0007】

An object of the present invention is to generate a tuned positive potential with increased efficiency, less ripple, reduced VCC and VSS noise, and lower power consumption than those previously available power supplies. It is to provide an improved drain power supply to provide.

【0008】

A further object of the present invention is a positive charge pump portion, each of which is driven by one of a plurality of staggered clock signals, to generate a reasonably high level of positive voltage. It is to provide an improved drain power source for generating and providing a tuned positive potential, including an offset circuit for effectively offsetting the threshold voltage drop in the circuit and the charge pump circuit.

【0009】

A further object of the present invention is to generate and provide a regulated positive potential, including a positive regulator circuit for generating a control voltage that is gradually increased or decreased to regulate a high level positive voltage. Is to provide an improved drain power supply for.

【0010】

According to these aims and objectives, the present invention is for generating a tuned positive potential during programming and feeding it through the bit lines of an array of flash EEPROM memory cells to the drain region of a selected memory cell. Regarding the provision of drain power supply. The drain power supply is a clock circuit for generating multiple staggered clock signals, and a moderately high level positive voltage in response to the external power potential VCC and multiple staggered clock signals. Includes charge pump circuit. The charge pump circuit consists of a plurality of charge pump parts. Each input of the plurality of charge pump parts is connected to receive each one of a plurality of staggered clock signals, and its output is connected to a pumped-up node.

【0011】

The offset circuit is coupled to each of the plurality of charge pump portions to effectively offset the threshold voltage drop in each of the plurality of charge pump portions. The positive regulator circuit is a control voltage that gradually increases to decrease the high level positive voltage and gradually decreases to increase the high level positive voltage in response to the adjusted positive potential and reference voltage at the output node. Is generated in the output node.

【0012】

These and other objectives and advantages of the present invention will become more apparent when reading the detailed description below, looking at the accompanying drawings with the same reference numbers indicating the corresponding parts throughout.

【0013】

[Detailed Description of Examples]

With reference to the drawings here, FIG. 1 shows that during the programming mode of operation, which is constructed by the principles of the present invention, a tuned positive potential is generated and it is passed through a bitline of the selected memory cell. A general overall simplified block diagram of the drain power supply 10 for feeding into the drain region is shown. The drain power supply 10 is formed as part of one integrated circuit chip (not shown) containing an array of many flash EEPROM memory cells arranged as an N × M matrix. Typically + 5.0V external or off-chip power potential VCC (also not shown) is given to the integrated circuit chip and to the input of the drain power supply 10.

【0014】

An array of flash EEPROM memory cells is formed on the board to define columns and rows, where the board has a common source line extending along at least one of the rows and multiple bit lines extending along each column. Including. Each of the memory cells contains an N-type source area, a control gate, a floating gate, and an N-type drain area and a channel area, each of which is connected to a common source line. In addition, each of the memory cells is primarily programmable by transferring hot electrons to its floating gate and is primarily erasable by tunneling electrons from its floating gate to its source area.

【0015】

The drain power supply 10 produces a tuned positive potential VPROG, which is fed to the data bitline DATABn via the data input buffer circuit 12 and the P-channel pull-up transistor 14. During programming, the data input buffer circuit 12 operates to provide a tuned positive potential VPROG to the drain region of the selected memory cell transistor through the bitline. The buffer circuit also allows zero volt to be applied to the bit line coupled to the drain region of the unselected memory cell. The drain power supply 10 includes a drain voltage generation and adjustment circuit 16 for generating a regulated positive potential. A more detailed block diagram of the drain voltage generation and regulation circuit 16 of FIG. 1 is shown in FIG.

【0016】

As seen in FIG. 2, the drain voltage generator and regulator circuit 16 comprises a staggered phase or clock generator 18, a drain charge pump circuit 20, and a voltage programming regulator circuit 22. The charge pump circuit 20 consists of eight small pump parts 20a, 20b to 20g, and 20h, which are connected in parallel to produce a reasonably high level positive voltage DPUMP at the pumped up node 24. The charge pump circuit 20 is formed by eight small single-stage pump portions rather than a multi-stage pump. Pump parts 20a to 20h of 8 are driven by the staggered clock signals generated by the clock generator 18 to reduce noise on the VCC and VSS power lines. In addition, only two pump parts can be switched at any given time, one being switched on and the other off, further reducing noise. Since staggered clock signals are used, less perturbation is caused by the damping of charge to the node 24 by each pump portion, thereby reducing ripples.

【0017】

To increase pump efficiency, each of the pump parts has a threshold drop V at pass transistor T1._tpFirst offset circuit 26 to effectively offset, and threshold drop V in pass transistor T2_tpNote that it includes a second offset circuit 28 to effectively offset. In FIG. 3, exemplary waveforms Pn, Qn, and Rn are shown, which drive the input node, the gate of pass transistor T1, and the gate of pass transistor T2, respectively, in the pump portion. The voltage programming regulator circuit 22 is a series regulator and includes a differential comparator 30 for generating a tuned positive potential VPROG at the output node 32.

【0018】

FIG. 4 shows a more detailed schematic of blocks 18, 20 and 22 of FIG. The staggered clock generator 18 includes a driver portion 18a and a delay portion 18b. The driver part includes the NAND logic gate G1 and the inverter gate G2. The logic gate G1 receives the 20MHz clock signal OSC, the program mode signal PGM, and the enable polling signal ENPOLL on its input. The output of logic gate G1 on line 34 is given to the input of inverter gate G2. The output of the inverter gate G2 gives the first clock phase signal P0.

【0019】

The delay portion 18b consists of inverter gates G3 to G6 and delay elements G7 to G9. The input of the inverter gate G3 is connected to the output of the inverter gate G2 to receive the first clock phase signal P0 on the line 36 and generate the second clock phase signal P1 on the output (line 38). The input of the delay element G7 is connected to the output of the inverter gate G3, and its output (line 40) defining the third clock phase signal P2 is connected to the input of the inverter gate G4. The input of the delay element G8 is connected to the output of the inverter gate G4 (line 42) that defines the fourth clock phase signal P3, and the output (line 44) that defines the fifth clock phase signal P4 is of the inverter gate G5. Connected to the input. The input of the delay element G9 is connected to the output of the inverter gate G5 (line 46) that defines the sixth clock phase signal P5, and the output (line 48) that defines the seventh clock phase signal P6 is of the inverter gate G6. Connected to the input. The output of the inverter gate G6 (line 50) provides the eighth clock phase signal P7.

【0020】

The waveforms of the staggered clock phase signals P0 to P7 are shown in FIGS. 5A to 5H. Note that the delay element G7 delays and inverts the clock phase signal P1 to generate the delayed clock phase signal P2. Similarly, the delay element G8 delays and inverts the delayed clock phase signal P3 to generate the delayed clock phase signal P4. Finally, the delay element G9 delays and inverts the delayed clock phase signal P5 to generate the delayed clock phase signal P6.

【0021】

The input of pump portion 20a is connected to line 36 to receive the first clock phase signal P0, and the input of pump portion 20b is connected to line 38 to receive the second clock phase signal P1. Similarly, the inputs of pump portions 20c to 20h are connected to lines 40, 42, 44, 46, 48 and 50, respectively, to receive the corresponding third to eighth clock phase signals P2 to P7. The output of pump portions 20a to 20h on each line 52-66 is connected to the pumped up node 24 to provide a reasonably high level of positive voltage DPUMP.

【0022】

The voltage programming regulator circuit 22 has its inputs as clock signal OSC on line 68, control signal APDB on line 70, test signal VTB on line 72, enable polling signal ENPOLL on line 74, and program mode signal on line 76. It receives a PGM, a high level positive voltage DPUMP on node 77 or line 78, and a reference potential VREF on line 80. The regulator circuit 22 produces a tuned positive (drain) potential VPROG at the output node 32. Transistor N301 is used to discharge the positive potential VPROG after programming.

【0023】

Looking back and looking at Figure 2, the signal INITIALIZE is given prior to the programming mode, allowing a reference voltage VREF of about +2.0 volts to charge and raise the capacitor Cn. In addition, the capacitor Cp is initially charged to ground potential (zero volt). During programming mode, the differential comparator 30 is used to compare the voltage VCDV at node 82 with the reference voltage VREF at node 84. If the voltage VCDV is greater than the voltage VREF, the output voltage VOUT of the comparator will gradually increase to make the P-channel pull-up transistor 86 less conductive, thereby reducing the voltage DPUMP from the output node 32. On the other hand, if the voltage VCDV is less than the reference voltage VREF, the output voltage VOUT is gradually reduced to make the transistor 86 less conductive, thereby pulling up or increasing the output node to a high positive voltage DPUMP.

【0024】

Referring here to FIG. 6, of the high level positive voltage DPUMP (curve A) at the pumped up node 24 and the tuned positive voltage VPROG (curve B) at the output node 32 in FIGS. 2 and 4. The output waveform is shown. The differential comparator 30 compares the voltage VCDV (curve C) at node 82 with the reference voltage VREF. Depending on the comparison, the output voltage VOUT (curve D) is generated at the output of the comparator. The voltage VOUT is the control voltage at node 118 (Fig. 10), which is used to change the gate voltage of pass transistor P903 (86 in Fig. 2). In this aspect, the tuned positive voltage VPROG will be generated by changes in the control voltage.

【0025】

Since each of the pump parts 20a-20h of 8 in FIGS. 2 and 4 is identical in its structure and operation, it is sufficient to elaborate on only one of the pump parts. Therefore, a detailed schematic schematic of pump portion 20a is shown in FIG. The pump portion 20a includes a pump clock driver 88 consisting of inverter gates G10 to G17, a NOR logic gate G18, and a NAND logic gate G19. The clock driver 88 receives the clock phase signal P0 on line 89 from the driver portion 18a and responds to generate the high positive voltage DPUMP on line 52 and the internal clock phases PHI1, PHI2 and PHI3. The pump portion 20a further includes pass transistors T1, T2, a pump capacitor C701, a first offset circuit 26, a second offset circuit 28, a reverse charge prevention transistor T3, and a booster diode connection transistor T4.

【0026】

The first offset circuit 26 is formed by the initialization transistor T5 and the coupling capacitor C702, and the threshold drop V applied to the pass transistor T1._tpTo offset. The second offset circuit 28 is formed by the initialization transistor T6 and the coupling capacitor C703, and the threshold voltage drop V applied to the pass transistor T2._tpTo offset. The internal clock phases PHI2, PHI1 and PHI3 are connected to one side of the capacitors C702, C701 and C703, respectively. The other side of the coupling capacitor C702 is connected at node 90 to the gate of pass transistor T1. The other side of the pump capacitor C701 is connected to the node PMP and the other side of the coupling capacitor C703 is connected to the gate of the pass transistor T2.

【0027】

The operation of pump portion 20a shown in FIG. 8 is shown here with respect to the waveform of FIG. Initially, it is assumed that node 90 is precharged to about +4 volts at time t1 by the initialization transistor T5. Therefore, when node B goes high, the potential at node 90 is also raised at time t2. This will also cause the node PMP to be precharged to the power potential VCC without the loss of threshold drop on the pass transistor T1. Therefore, if the internal clock phase PHI1 goes high and prevents reverse charge, the pass transistor T1 will be turned off before time t3. It is noted that the reverse charge prevention transistor T3 is also used to precharge the node PMP gate and discharge it to the power potential VCC between cycles to prevent reverse charge. The initialization transistor T6 is also used to precharge the node PMP gate.

【0028】

When the internal clock phase PHI1 goes high at time t3, the node PMP is raised to about +8 volts. Then, when the internal clock phase PHI3 goes high at time t4, the node PMP gate is also raised to turn on the pass transistor T2, which causes the voltage at node PMP to be increased to node 24 (DPUMP) without loss of threshold drop. ). The booster diode connection transistor T4 helps to provide additional precharge to the node PMP gate. This further precharge is required as node 24 (DPUMP) may be heavily loaded and therefore may not precharge the node PMP gate to a reasonable level. Precharging at time t3 allows the voltage on the node PMP gate to be kicked up higher at time t4.

【0029】

Since the pump portion 20b is driven by the second clock phase signal P1, which is the inverted version of the signal P0, the pump portion 20b is turned off while the pump portion 20a is turned on. Similarly, the other pump parts 20d, 20f and 20h are turned off while the corresponding pump parts 20c, 20e, and 20g are turned on. By delaying the clock signal for each of the continuous pump parts, there is one pump part that constantly carries the current to the pumped up node 24 and reduces the ripple effect.

【0030】

Since each of the delay elements G7 to G9 is identical in their structure and operation, it is sufficient to elaborate on only one of the delay elements. Therefore, a detailed schematic circuit diagram of the delay element G7 is shown in FIG. The delay element G7 includes an RC delay circuit 92 and a Schmitt trigger circuit 94. The RC delay circuit consists of an inverter 96, a resistor 98, and a capacitor 100. The input of the inverter 96 defines the input of the delay element G7. The junction of resistor 98 and capacitor 100 gives a delayed and inverted signal from the input signal on line 102. The Schmitt trigger circuit includes P-channel transistors P801, P802 and P803, N-channel transistors N801, N802 and N803, an inverter 104, and source degeneracy resistors 106, 108. The input of the Schmitt trigger circuit defined by the gates of transistors P801 and N801 receives a delayed inverted signal. The output of the Schmitt trigger circuit is defined by the output of the inverter 104.

【0031】

The trip point at node L1 is determined by the ratio of transistor N803 to the series combination of transistor N802 and resistor 108. The trip point at node U1 is determined by the ratio of transistor P803 to the series combination of transistor P802 and resistor 106. Resistors 106 and 108 have a smaller positive temperature coefficient compared to the temperature coefficients of the transistors P802 and N802, so the resistors are useful for Schmitt trigger circuits and to provide temperature compensated VCC.

【0032】

The voltage programming regulator circuit 22 in FIG. 4 consists of a test level circuit portion 22a and a programming regulator portion 22b. The test level circuit portion 22a includes a clock driver portion 110 and a charge pump portion 112 driven by the driver portion. During test mode, the node PRE gate will be pumped up to approximately +8 volts by the high frequency clock signal OSC. As a result, the pull-up transistor N901 is turned on and pulls node 24 (DPUMP) to the power potential VCC. If the enable signal ENPR is high (ie, during programming mode), the node PRE gate will be drawn to ground potential via transistor N902.

【0033】

The programming adjustment part 22b is used to provide the adjusted (drain) positive potential VPROG at the output node 32 during programming. The adjustment portion 22b consists of a reference voltage VREF, a precharge circuit 901, a differential comparator 902, a series pass P-channel transistor P903, and a capacitor C901. The reference voltage is given on line 80 and is about +2 volts. The precharge circuit 901 includes precharge transistors N903, N904, N-well type capacitors Cp, MOS capacitors Cn, and sense transistors P904. Prior to entering programming mode, the signals ENPRB and ENPRBP are initially set high, precharging node VRG to approximately +2 volts and precharging node 114 to ground potential. Therefore, the signals ENPRB and ENPRBP are set low to separate the reference voltage. As can be seen, the capacitor Cn is connected between the node VRG and the node 114, and the capacitor Cp is connected between the node 114 and the ground potential. Since the sense transistor P904 is turned on during programming, the voltage VPROG is split by the capacitive divider formed by the capacitors Cn and Cp to give a smaller voltage VCDV at node 114. The reference voltage is further applied to line 116.

【0034】

In operation, the differential comparator 902 also compares the voltage (VCDV) at node 114, which is proportional to the tuned positive potential VPROG, with the reference voltage VREF on line 116, and at node 118 the control gate voltage on its output. To generate. This gate voltage is connected to the gate of the series pass transistor P903. If the voltage at node 114 (VCDV) is higher than the reference voltage VREF on line 116, the gate voltage will gradually increase to make transistor P903 less conductive, thereby outputting less high positive voltage DPUMP. Give to node 32 (VPROG). On the other hand, if the voltage at node 114 is less than the reference voltage on line 116, the gate voltage will gradually decrease to allow transistor P904 to conduct more, thereby delivering a higher voltage DPUMP to output node 32. give away. In this embodiment, the differential comparator provides a positive potential VPROG tuned at the output node 32.

【0035】

Note that the differential comparator 902 includes two N-channel transistors N905 and N906 whose gates are connected to the supply potential VCC for thermal switching protection. Capacitor C901 is connected between node 118 and node 32 (VPROG) to provide compensation. In addition, the capacitor C902 is connected between the pumped up node 24 (VPUMP) and the ground potential to reduce any ripple at the output of the charge pump circuit 20.

【0036】

Here, referring to FIG. 11, a circuit diagram of the data input buffer circuit 12 of FIG. 1 is shown. The data buffer circuit allows the data bit line coupled to the drain region of the selected memory cell transistor to be given a regulated positive potential VPROG during programming. The data buffer circuit also allows the data bit line coupled to the drain region of the non-selected memory cell transistor to be given zero volt. The buffer circuit includes an inverter gate G20, G21, a capacitor C101, a D latch circuit 120, an AND logic gate G22, a NOR logic gate G23, two N-channel path transistors 122 and 124, and a level shift circuit 126. The data input signal INn is given to line 128 and is delayed by inverters G20, G21 and capacitor C101 with respect to the data terminal DIN of the D latch circuit 120. If the clock signal DLB on terminal CKB is high level, the data signal on terminal DIN is passed through output terminal QB. If the clock signal DLB goes low, the data is latched on the output terminal QB. The level shift circuit 126 consists of P-channel transistors 130, 132 and N-channel transistors 134.

【0037】

During programming mode, the signal PGM goes high to enable the output terminal QB. Since the data signal INn is low level (QB = 1) for the selected memory cell, the output of the NOR gate G23 is low. Therefore, this row is passed through transistors 122, 124 and given to the gate of the pull-up transistor 14, thereby turning it on. As a result, the adjusted positive potential VPROG on the output node 32 is passed to the data bit line DATABn. On the other hand, the data signal INn is at a high level (QB = 0) for unselected memory cells. Therefore, the output of the NOR gate G23 is high. This high is again passed through transistors 122, 124 and given to the gate of transistor 14, thereby turning it off. As a result, zero volt is given to the data bitline.

【0038】

Note that the gate of the pass transistor 122 is connected to the adjusted positive voltage VPROG and the gate of the pass transistor 124 is connected to the power potential VCC to form a latch-up protection circuit. If the voltage VPROG either drops below the supply voltage VCC or increases above the supply potential VCC, then the two transistors 122, 124 are forward biased for the junction on either side of the pass transistor. To prevent. The discharge transistor 136 is used to discharge the data bit line DATABn during the program reset mode. FIG. 12 shows a circuit diagram of the D-latch circuit 120 of FIG. The D-latch circuit includes N-channel pass transistors 138 and inverter gates G24, G25, and G26. One of the conduction path electrodes of the pass transistor 138 is connected to the input terminal DIN to receive the delayed data signal, and the other one of the conduction path electrodes is connected to the node 140. The gate of transistor 138 is connected to terminal CKB to receive the clock signal DLB. The input of inverter G24 is connected to node 140 and its output is connected to node 142 and the input of inverter G25. The output of inverter G25 is also connected to node 140. Node 142 is also connected to the input of inverter G26 and the output terminal QB that defines the output of the D-latch circuit. The output of the inverter G26 is connected to another output terminal Q.

【0039】

From the above detailed description, the present invention is an improvement for generating a tuned positive potential during programming and feeding it through the bit lines of an array of flash EEPROM memory cells to the drain region of a selected memory cell. It can be seen that it provides a drained power supply. The drain power supply consists of multiple charge pump sections, each driven by one of a plurality of staggered clock signals, and includes a charge pump circuit for producing a reasonably high level of positive voltage. The offset circuit is coupled to each of the plurality of charge pump portions to effectively offset the threshold voltage drop in the charge pump circuit. Further, a regulator circuit is given to generate a control voltage that gradually increases to decrease and gradually decrease the high level positive voltage on the output node to increase the high level positive voltage to the output node.

【0040】

Although what is currently considered as a preferred embodiment of the invention has been illustrated and described, it will be understood by those skilled in the art that various modifications and modifications can be made and the equivalent deviates from the true scope of the invention. It may be used in place of the element without exception. In addition, many modifications may be made to adapt a particular situation or substance to the teachings of the present invention without departing from the main scope. Therefore, it is intended that the present invention is not limited to the specific examples disclosed as the best aspects considered in the practice of the invention, but the present invention is all examples within the scope of the above-mentioned claims. Is intended to include.

[Simple explanation of drawings]

FIG. 1 is a general overall block diagram of a drain power source constructed according to the principles of the present invention.

2 is a block diagram of the drain voltage generation and adjustment circuit of FIG. 1. FIG.

FIG. 3 is a diagram showing exemplary waveforms, Pn, Qn, and Rn.

FIG. 4 is a more detailed schematic view of the drain voltage generation and adjustment circuit of FIG.

5 is a timing diagram for the staggered phases of the clock signals generated by the clock generator circuit of FIG.

FIG. 6 is a timing diagram showing various signal states of FIGS. 2 and 4, which are useful for understanding the operation of the present invention.

7 is a timing diagram showing various signal states at a certain internal node of the charge pump portion of FIG. 8. FIG.

FIG. 8 is a detailed schematic circuit diagram of one of the charge pump portions of FIG.

9 is a schematic view of one of the delay elements of FIG. 4. FIG.

10 is a schematic diagram of the voltage programming regulator circuit of FIG.

11 is a more detailed schematic diagram of the data input buffer circuit of FIG. 1. FIG.

12 is a schematic view of the D-latch circuit of FIG. 11. FIG.

[Explanation of symbols]

VCC Power potential 18 Clock generator 20 Charge pump circuit 22 Voltage programming regulator circuit 26 First offset circuit 28 Second offset circuit