Apparatus and method for recording and reproducing digital data

【0001】

[Industrial application field]

The present invention relates to a digital data recording / playback apparatus and method for recording / reproducing MPEG2 transport packets on magnetic tape.

【0002】

[Conventional technology]

Development of a digital VTR that compresses a digital video signal by DCT (Discrete Cosine Transform) and variable length coding and records it on a magnetic tape by a rotating head is underway. In such a digital VTR, a mode for recording a video signal of a current television system such as the NTSC system (hereinafter referred to as SD mode) and a mode for recording an HDTV signal (hereinafter referred to as HD mode) can be set. .. In SD mode, video signals are recorded at a rate of 25 Mbps. In HD mode, the video signal is recorded at a rate of 50 Mbps. It is being considered to record MPEG2 transport packets using such a digital VTR.

【0003】

That is, MPEG2 is provided with a multi-program compatible function that enables transmission of a plurality of programs. This is time division multiplexing of individual coded streams in relatively short units called transport packets.

【0004】

Transport packets have a fixed length of 188 bytes. The header part of the transport packet contains the content identification information of the packet data, whereby the packet required for the target program reproduction is selected and decoded.

【0005】

FIG. 22 shows the configuration of the transport packet. As shown in FIG. 22A, a header is provided at the beginning of the transport packet, followed by a payload (information). As shown in Figure 22B, the header contains an 8-byte sink, a transport error indicator that indicates the presence or absence of an error in the packet, a payload unit start indicator that indicates the start of the payload unit, and a transformer that indicates the importance of the packet. Packet identification (PID), which indicates the port priority and the attributes of the individual slime of the packet, transport scramble control, which indicates the presence or absence of payload scramble and type, and adaptation field control, which indicates the presence or absence of an adaptation field. It consists of a patrol counter to detect if it has been partially rejected, and an adaptation field that can contain additional information about individual streams and stuffing bytes.

【0006】

The adaptation fields are, as shown in Figure 22C, the adaptation field length, which indicates the length of the adaptation field, the discontinuity indicator, which indicates that the system clock is reset to new content, and the random access, which indicates the entry point for random access. It contains an indicator, a priority stream elemental indicator that the important part is in this payload, and an optional field.

【0007】

Optional fields include PCR, OPCR, splice countdown, transport private data length and transport private data, adaptive field extension length, and optional fields, as shown in FIG. 22D. PCR is a time stamp for setting and calibrating a time reference value in MPEG system decoding. The system clock (27 MHz) is reproduced by the PLL from this PCR, and the time axis information of these packets is retained in order to use it as a reference for the timing of the subsequent decoding process.

【0008】

When recording such an MPEG2 transport packet on a digital VTR, as shown in FIG. 23, a desired program (for example, a program) is selected from the time-division-multiplexed programs A, B, and C. A) is selected. At this time, if the data rate of the multi-program is, for example, 30 Mbps and the actual rate of the selected program is 10 Mbps, the rate conversion buffer performs rate conversion from 30 Mbps to 10 Mbps.

【0009】

That is, as shown in FIG. 24, the transport packet of the selected program is supplied from the input terminal 101 to the rate conversion buffer 102. The rate conversion buffer 102 reduces the rate by a factor of three. This will reduce the rate from 30Mbps to 10Mbps. This rate-converted transport packet is output from the output terminal 103 and recorded by the digital VTR.

【0010】

Since the SD mode recording rate of the digital VTR is 25 Mbps, the transport packet can be recorded as it is on the digital VTR by performing rate conversion in this way.

【0011】

[Problems to be Solved by the Invention]

However, when the transport packet is rate-converted, the input time information changes. That is, the PCR value provided as a time stamp in the header of the transport packet does not indicate the correct time information. Therefore, if the transport packet is rate-converted and recorded by the digital VTR, it will be played back.<u style="single">At the time of recording</u>There arises a problem that playback cannot be performed on the same time axis as.

【0014】

Therefore, an object of the present invention is to provide a digital data recording / reproduction apparatus and method that can maintain a correct time axis during reproduction even when a transport packet is rate-converted and recorded.

【0016】

[Means for solving problems]

This invention<u style="single">It arrives intermittently on the time axis</u>In a digital data recording device that records data packets on tape, based on the reference clock<u style="single">By generating time information and latching the time information by sinking incoming data packets</u>In the time generation means that generates the arrival time of the data packet and the data packet<u style="single">To</u>It is a digital data recording device provided with a means for adding an arrival time.

【0017】

This invention<u style="single">By generating time information based on the reference clock and latching the time information by sinking data packets that arrive intermittently on the time axis, the arrival time of the data packet is generated and the arrival time is added.</u>In a digital data reproduction device that reproduces a data packet recorded on a tape, based on the arrival time added to the data packet.<u style="single">Reproduce the time axis state at the time of recording</u>It is a digital data reproduction device characterized by the above.

【0020】

[Action]

When a program is selected from a transport packet, rate-converted and recorded, packet arrival time information is added to each packet based on the reference clock in order to retain the time axis information of each packet. At the time of reproduction, the same time axis state as at the time of input is reproduced based on this time information.

【0021】

For packets with time information, the relationship between the number of sink blocks and the number of packets is set to an integer ratio.

【0022】

In the recording / playback of the digital VTR, since the rotation of the drum is synchronized with the reference clock, the time information is retained in the recording / playback.

【0024】

[Example]

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a recording system of a digital VTR to which the present invention is applied. In FIG. 1, 1 is an input terminal for a video signal of a current television system such as the NTSC system. When recording a television signal from the outside, a component video signal is supplied to the input terminal 1. The component video signal from the input terminal 1 is supplied to the A / D converter 2, and the component video signal is converted into a digital signal by the A / D converter 2.

【0025】

3 is a DCT compression circuit. The DCT compression circuit 3 compresses the input video signal by DCT transform and variable length coding. That is, the component video signal from the A / D converter 2 is blocked, shuffled, and subjected to DCT conversion. The DCT-converted data is buffered in a predetermined buffer unit. The code of this predetermined buffer unit is estimated, a quantization table is determined so that the total code amount is equal to or less than a predetermined value, and the quantization is performed by this optimum quantization table. Then, it is variable-length coded and framed.

【0026】

Reference numeral 4 denotes a switch circuit that can be switched between recording an MPEG2 transport packet and recording a video signal from the input terminal 1. An MPEG2 transport packet is supplied to the terminal 4A of the switch circuit 4 via the rate conversion and format conversion unit 9.

【0027】

The rate conversion and format conversion unit 9 extracts a necessary program from the MPEG2 transport packet and converts this rate from, for example, 30 MBps to 10 Mbps. Further, as will be described later, the data of the trick play area is arranged so that a good screen can be obtained at the time of variable speed reproduction. The output of the DCT compression circuit 3 is supplied to the terminal 4B of the switch circuit 4. When recording an MPEG2 transport packet, the switch circuit 4 is set on the terminal 4A side. When recording the video signal from the input terminal 1, the switch circuit 4 is set on the terminal 4B side.

【0028】

The output of the switch circuit 4 is supplied to the framed circuit 5. The framing circuit 5 expands the recorded data into a predetermined frame and performs error correction coding processing.

【0029】

The output of the framing circuit 5 is supplied to the channel coder 6 and modulated. The output of the channel coder 6 is supplied to the rotary head 8 via the recording amplifier 7. The rotating head 8 records a video signal compressed on magnetic tape or an MPEG2 transport packet.

【0030】

In such a recording system, when recording an MPEG2 transport packet, the switch circuit 4 is switched to the terminal 4A side. Therefore, the MPEG2 transport packet input via the rate conversion and format conversion unit 9 is framed by the framing circuit 5, modulated by the channel coder 6, and recorded on the magnetic tape by the rotating head 8.

【0031】

When recording the video signal from the input terminal 1, the switch circuit 4 is switched to the terminal 4B side. Therefore, the video signal from the input terminal 1 is compressed by the DCT circuit 3, framed by the framing circuit 5, modulated by the channel coder 6, and recorded on the magnetic tape by the rotating head 8.

【0032】

In this way, when recording an MPEG2 transport packet, the rate conversion and format conversion unit 9 selects, for example, one program in a multi-program, and the data rate of the selected program is, for example, 30 Mbps to 10 Mbps. Is converted to. Here, since the time axis information changes, it is not possible to return to the same state as at the time of recording at the time of reproduction as it is.

【0033】

Therefore, in one embodiment of the present invention, time information (packet arrival time) based on the reference clock is added to each packet before the stream of the transport packet is input to the rate conversion buffer. At the time of reproduction, if the packet is sent out at the same clock as at the time of input and the packet is sent at the timing of this time information, the same time state as at the time of input can be maintained.

【0034】

That is, as shown in FIG. 2A, an 8-byte sink is added to the header at the beginning of the transport packet. When recording an MPEG2 transport packet, one byte of this sink is removed and three bytes of time information are added here, as shown in Figure 2B.

【0035】

That is, FIG. 3 shows a configuration for adding 3 bytes of time information before recording the transport packet after rate conversion. In FIG. 3, the transport packet before rate conversion is supplied to the input terminal 31. This transport packet is supplied to the sink detection circuit 32. The sink detection circuit 32 detects the sink at the beginning of the transport packet. The detection output of the sink is supplied to the latch 33. The output of the sink detection circuit 32 is supplied to the sink removal circuit 37. The sink removal circuit 37 removes 1 byte of the sink when the sink is detected. The output of the sink removal circuit 37 is supplied to the time stamp circuit 38.

【0036】

The reference clock generation circuit 34 generates a reference clock of, for example, 27 MHz. This reference clock is supplied to the PLL 35 and also to the counter 36. Based on the output of PLL35, the drum is rotated, for example, at 150Hz.

【0037】

The reference clock is counted by the counter 36. Time information can be obtained from the output of this counter 36. This time information is supplied from the counter 36 to the latch 33. The output of the time stamp circuit 38 is output from the output terminal 39.

【0038】

When the sink detection circuit 32 detects the sink of the transport packet, the time information at this time is latched by the latch 33. Then, the sink detection circuit 37 removes the 1-byte sink, and the time stamp circuit 38 adds the 3-byte time information to the packet.

【0039】

Further, as described above, the output of the reference clock generation circuit 34 is supplied to the PLL 35, the drum is rotated by the output of the PLL 35, and the rotation of the drum is synchronized with the reference clock during recording / playback. As a result, the time information is retained in the recording / playback.

【0040】

The transport packet is 188 bytes, which is 190 bytes when the 1-byte sink is removed and 3 bytes of time information are added. In this 190-byte packet, 2 packets are packed in 5 sink blocks as shown in FIG.

【0041】

That is, in the digital VTR, one sink block is 90 bytes, and the sink and ID are added to the first 5 bytes. Then, when 1 byte of parity is added, the payload of 1 sink block becomes 77 bytes. Further, this 1-byte extra header (see FIG. 5) is added to each sink block. In the extra header, the serial number etc. in 5 sink blocks are recorded. The remaining 76 bytes are allocated for packet recording. Therefore, in a 5-sync block, 5 × 76 = 380 bytes, and a 190-byte packet with time information added can be packed exactly into 2 × 190 = 380 bytes for 2 packets.

【0042】

Further, in one embodiment of the present invention, in order to improve the image quality at the time of shifting reproduction, the playable area at the time of shifting reproduction is set as a trick play area, and a packet including an I picture is recorded in this trick play area. .. In MPEG2, an in-screen coded I picture, a forward predictive coded P picture, and a bidirectional predictive coded B picture are sent, and only the I picture data can be used during variable speed reproduction. If the trick play area is provided, the I-picture data obtained from this trick play area can be used at the time of shifting reproduction, and the image quality at the time of shifting reproduction can be improved.

【0043】

That is, the recording rate of the digital VTR is 25 Mbps in SD mode. On the other hand, when transport packets are recorded at a rate of 10 Mbps, there is a margin in the recording rate. Therefore, the playable area at the time of variable speed reproduction is set as the trick play area, and packets including the I picture can be duplicated and recorded in this trick play area.

【0044】

For example, FIG. 6 shows the locus of the head during variable speed reproduction. As shown in FIG. 6, when the head traces, the part indicated by TP becomes the reproducible area. This playable area TP is used as a trick play area for recording packets for speed change playback. In the helical scan and azimuth recording VTR, the data reproduced from the TP is bursted, as shown in FIG. If the track-shaped position of this reproducible area is fixed by ATF or the like and a packet containing an I picture is recorded in this reproducible area, the data of the I picture is surely reproduced.

【0045】

In one embodiment of the present invention, two types of trick play areas TP1 and TP2 are provided. One trick play area TP1 is for high speed speed change reproduction, and the other trick play area TP2 is for low speed speed change reproduction. The trick play areas TP1 and TP2 are provided on tracks having different azimuth angles.

【0046】

That is, in a digital VTR, as shown in FIG. 8, one track is divided into an ITI sector used for dubbing and the like, an audio sector, a video sector, and a subcode sector used for search and the like. Then, it is traced by heads having different azimuth angles. As for the head configuration, two 180-degree opposed heads and a double magic head can be used. Then, the pilot signal is superimposed to perform ATF tracking.

【0047】

As shown in FIG. 9, the trick play area TP1 for high-speed speed change reproduction is provided in, for example, a track having a pilot signal f0, which can be reproduced at 18 times speed. Then, the data is repeatedly recorded 18 times in the trick play area TP1. The low-speed trick play area TP2 is provided in an area that can be played back at 4x speed on tracks other than the pilot signal f0. In the trick play area TP2, the same data is repeated twice and the data is recorded.

【0048】

In this way, the trick play areas TP1 and TP2 are arranged on different Ajimas tracks. In this way, in each of the trick play areas TP1 and TP2, by using only one azimuth track, variable speed reproduction can be performed without being restricted by the head configuration such as two 180-degree opposed heads or a double azimuth head. It will be possible.

【0049】

Further, in the digital VTR, since the tracking information is obtained on the track of the pilot signal of f0 when the phase is locked, the track of the pilot signal other than f0 is easily affected by the head mounting error and the like. Therefore, the trick play area TP2 for low-speed shift reproduction is arranged on the track of the pilot signal other than f0, and the trick play area TP1 for high-speed shift reproduction is arranged on the track of the pilot signal of f0. This is because the 4x speed has a larger margin for tracking deviation between the 5 sink block at 18x speed and the 25 sink block at 4x speed.

【0050】

The same data is repeatedly recorded 18 times in the trick play area TP1 for high-speed shift reproduction, and the same data is repeatedly recorded twice in the trick play area TP2 for low-speed shift reproduction. .. Therefore, the tape speeds that can be achieved are as shown in FIG.

【0051】

In other words, if the tape speed during variable speed playback is set to (N + 0.5) double speed, such as 1.5x speed, 2.5x speed, and 3.5x speed, as shown in Fig. 11 and Fig. 12, two scans of the same azimuth track All parts are reproducible. That is, FIG. 11 shows a case where the maximum speed change reproduction speed is set to 7 times speed and the speed change reproduction is performed at 3.5 times speed. In this case, as shown in Figure 12A, the first scan replays both ends of the Azimus A track, the second scan replays the middle part of the Azimus A track, and these two times. The scan plays the entire part of one track. If the same trick play data is repeatedly recorded on the corner track of Azimus A, all the data on one track of Ajimas A track can be reproduced by these two scans. Therefore, if the trick play data is repeatedly recorded on the same track of Ajimas, the playback of the trick play data is guaranteed at (N + 0.5) times speed such as 1.5 times speed, 2.5 times speed, and 3.5 times speed. , Shift reproduction at these speeds is possible.

【0052】

In the above example, the same data was recorded over 18 tracks, but it is also conceivable to provide a mode for recording the same data over the trick play area of 36 tracks as an option. If you record over 36 tracks, you can shift playback with speed lock up to 17.5x speed. Which mode was recorded can be recorded in the video AUX data, for example.

【0053】

FIG. 13 shows the arrangement of sink blocks on each track. The number of sync blocks per track is 135 sync blocks. As shown in FIG. 13A, track T0 is provided with a normal play area and trick play area TP1, track T1 is provided with a normal play area and trick play area TP2, and track T2 is provided with normal play. An area and a trick play area TP1 are provided, and track T3 has only a normal play area and no trick play areas TP1 and TP2.

【0054】

If a trick play area TP1 or TP2 is provided, this trick play area TP1 or TP2 is set to 25 sink blocks. Then, the normal play area is set to 101 sink blocks, and an error correction code ECC3 for 9 sink blocks can be prepared. As shown in Fig. 4 above, 2 packets are packed in 5 sink blocks, so if the number of sink blocks in the trick play areas TP1 and TP2 is an integral multiple of the 5 sink blocks, the matching will be good. Become.

【0055】

Tracks T0 and T2 have five trick play areas TP1 per track, as shown in Figure 13B, where sync block numbers 40-44, 62-66, 84-88, 106-110, 128. ~ 132 data is recorded. A trick play area TP2 is generated on track T1, and data of sink block numbers 38 to 32 are recorded in this area.

【0056】

The trick play area TP1 for high-speed variable speed reproduction is arranged so that the head can read both the subcode sector and the ITI sector. This makes it possible to access the subcode even during variable speed playback at 18x speed. Also, at 18x speed, the burst length is short, and a tracking error signal sufficient for ATF control cannot be obtained. Therefore, ATF control can be performed here by scanning the ITI sector. In the ITI sector, a pilot signal with a higher S / N ratio can be obtained than in other data areas. At 4x speed, the burst is long, so ATF control can be performed even in the data area. Therefore, the trick play area TP2 for low speed is arranged at a position where only the subcode can be read.

【0057】

As described above, FIG. 14 shows an example of a configuration for recording data for speed change reproduction in the trick play areas TP1 and TP2. In FIG. 14, an MPEG2 transport packet is supplied to the input terminal 51. This transport packet is supplied to the rate conversion buffer 52 and also to the TS / PES decoder 53. If the data rate of the input transport packet is, for example, 30 Mbps, the rate conversion buffer 52 converts this data rate to, for example, 10 Mbps. In a multi-program, when a plurality of programs are time-division-multiplexed and sent, a desired program is selected from these programs, and the selected program is supplied to the rate conversion buffer 52.

【0058】

The TS / PES decoder 53 extracts the payload part and extracts only the video stream from the payload part. The output of the TS / PES decoder 53 is supplied to the start code analysis circuit 54. In the start code analysis circuit 54, it is determined from the information in the header of the transport packet whether or not the packet is necessary for variable speed reproduction. That is, from the information such as the transport priority in the header of the transport packet, it is determined whether or not the packet contains the I picture and has a high importance, and the packet including the I picture is regarded as a packet necessary for variable speed reproduction. The output of the start code analysis circuit 54 is supplied to the TP processing circuit 55. The output of the TP processing circuit 55 is supplied to the TS / PES packetizing circuits 56A and 56B. The TS / PES packetization circuit 56A forms a packet to be recorded in the trick play area TP1 for high-speed speed change reproduction. The TS / PES packetization circuit 56B forms a packet to be recorded in the trick play area TP2 for low-speed speed change reproduction. The output of the TS / PES packetizing circuits 56A and 56B is supplied to the TP1 buffer 57A and the TP2 buffer 57B.

【0059】

The outputs of the rate conversion buffer 52, the TP1 buffer 57A, and the TP2 buffer 57B are supplied to the multiplexer 58 via the sink block formatters 59A, 59B, and 59C, respectively. The multiplexer 58 multiplexes the outputs of the rate conversion buffer 52, the TP1 buffer 57A, and the TP2 buffer 57B. The output of buffer 52 for rate conversion is recorded in the above-mentioned normal play area, the output of TP1 buffer 57A is recorded in trick play area TP1, and the output of TP2 buffer 57B is recorded in trick play area TP2. ..

【0060】

As described above, FIG. 15 shows another example of the configuration for recording data for speed change reproduction in the trick play areas TP1 and TP2. In the example shown in FIG. 14, the trick play area TP1 for high-speed shift reproduction and the trick play area TP2 for low-speed shift reproduction are combined with the TS / PES packetization circuits 56A and 56B, the TP1 buffer 57A and the TP2 buffer 57B. Each is processed separately, but in this example, the trick play area TP1 for high-speed speed change reproduction and the trick play area TP2 for low-speed speed change reproduction are combined into one circuit, TS / PES packetization circuit 56. , TP1 / TP2 buffer 57 is processing. In such a configuration, the processing of the trick play area TP2 for low-speed playback finishes recording the I-picture data faster, and then the recording of the trick play area TP1 for high-speed variable speed playback ends. Until, dummy data is recorded. Further, in order to facilitate this process, the number of sync blocks of the trick play areas TP1 and TP2 in one track is the same (25 sync blocks).

【0061】

By the way, in the above example, the data for shifting reproduction is recorded in the trick play area without deleting the high frequency coefficient. In this way, if the extracted I-picture is used as it is as the variable speed reproduction data without removing the high frequency coefficient, the update rate of the reproduced image decreases due to the large amount of data, and a large capacity is used to store the data. Memory is required. That is, FIG. 16 shows the relationship between the number of coefficients and the amount of data. In FIG. 16, the horizontal axis represents the number of coefficients and the vertical axis represents the amount of data. From FIG. 16, for example, if the memory size is deleted so that the coefficient becomes 6, 500 kbits is sufficient, but if the memory size is 64 without deleting the coefficient, 1 M bit is required. ..

【0062】

At the time of reproduction, only the data of the variable speed reproduction area is taken out from the reproduction data and sent to a decoder. However, in the case of variable speed reproduction in the reverse direction, the data of the I picture is reproduced in the reverse direction, so if it is sent to the decoder as it is, it cannot be decoded normally. Therefore, the data for one picture is stored in the buffer memory, and by reading from the packet at the beginning of the picture, the data is transmitted in the same form as in the forward direction. The buffer memory here also needs to have a size of one picture (shifted playback data).

【0063】

Therefore, it is conceivable to delete the high frequency coefficient and record it. That is, as shown in FIG. 17, the packet from the input terminal 61 is supplied to the buffer 62 and also to the TS / PES decoder 63. The output of the TS / PES decoder 63 is supplied to the start code analysis circuit 64. An I picture is extracted from the start code analysis circuit 64. The output of the start code analysis circuit 64 is supplied to the coefficient reduction circuit 65. The coefficient reduction circuit 65 deletes the high frequency coefficient of the I picture. The shift reproduction data created in this way is stored in the buffer memory 66. The data in the buffer memory 66 is sent to the TS / PES packetizing circuit 67 and packetized again.

【0064】

The data for normal reproduction and the data for variable speed reproduction from the TS / PES packetizing circuit 67 stored in the buffer 62 are sent to the sync block formatters 68A and 68B, respectively, with headers, and sent to the multiplexer 69. ..

【0065】

VLD (variable length decoding) processing is required in the coefficient reduction circuit 65 that deletes the high frequency coefficient of each block from the I picture in order to create the variable speed reproduction data. However, in MPEG2, the layers below the slice layer are not byte-aligned, so this variable-length decoding block becomes considerably large. Therefore, as shown in FIG. 16, when recording with the high frequency coefficient reduced, an increase in the circuit scale becomes a problem by providing the variable length decoding processing circuit 65.

【0066】

Therefore, all I pictures are used as variable speed playback data, but instead of recording all one picture, a part (for example, the upper third of the screen) is recorded, and the next time it is recorded, it is continuous on the screen. Multiple screens, such as recording the next third<u style="single">Several times</u>It is conceivable to record separately. As a result, the required memory size can be reduced.

【0067】

As an example, consider the case of recording one third of the screen at a time. FIG. 18 shows this situation. In FIG. 18, from the first GOP I picture, the data corresponding to the upper third of the screen is taken out and stored in the memory. Then, data for shifting reproduction is formed from the data of the upper third of this screen, and this is recorded in the trick play area. Next, the data corresponding to the middle third of the screen is taken out and stored in the memory, and the data for shifting playback is formed from the data of the upper third of this screen, which is a trick. Recorded in the play area. Then, the data corresponding to the lower third of the screen is taken out and stored in the memory, and the data for shifting reproduction is formed from the data of the upper third of this screen, and this is the trick play area. Recorded in. Similarly, the data of the upper third, the middle third, and the lower third of the screen are sequentially stored in the memory and recorded in the trick play area. In this way, the required memory can be as large as one-third of the screen.

【0068】

The area on the screen can be found by counting the slice vertical position in the slice header. Here, the last slice number is memorized, and one-third equivalent amount is taken from the next slice. After that, by repeating this, it becomes possible to record one-third of the screen as shift reproduction data.

【0069】

Further, although the screen is divided into three areas here, how many areas the screen is divided into can be appropriately changed in consideration of the capacity of the buffer memory and the like. Also, when the screen is divided, for the part that is not divisible, insert a stuffing byte to match. In this case, the header may indicate that the data is dummy data, or the header may be set as valid data and used as dummy data.

【0070】

FIG. 19 shows a configuration in the case where the screen is divided into one-third and stored in the memory, and the shift reproduction data is recorded in the trick play area.

【0071】

In FIG. 19, the packet from the input terminal 71 is supplied to the buffer 72 and also to the TS / PES decoder 73. The output of the TS / PES decoder 73 is supplied to the start code analysis circuit 74. An I picture is extracted from the start code analysis circuit 74. The output of the start code analysis circuit 74 is supplied to the screen division unit 75.

【0072】

As shown in FIG. 20, the screen dividing unit 75 counts the slice vertical positions in the slice header, calculates the number of vertical slices (block 81), and extracts up to a predetermined slice number (block 82). Is. The last slice number is memorized (block 83), and in the next area, extraction is performed from this next slice number.

【0073】

The area data extracted by the screen dividing unit 75 is stored in the buffer memory 76. The data in the buffer memory is sent to the TS / PES packetizing circuit 77 and packetized again. The data for normal reproduction and the data for variable speed reproduction from the TS / PES packetizing circuit 77 stored in the buffer 72 are sent to the sink block formatters 78A and 78B, respectively, with headers, and sent to the multiplexer 79. ..

【0074】

By combining the method of storing one-third of the screen in the memory and the method of reducing the high frequency coefficient in this way, it is possible to further reduce the memory capacity. Of course.

【0075】

FIG. 21 shows the configuration of the regeneration system. In FIG. 21, the recording signal of the magnetic tape is reproduced by the rotary head 60 and supplied to the channel coder 62 via the reproduction amplifier 61. The channel coder 62 demodulates the reproduction signal corresponding to the recording system channel coder 6.

【0076】

The output of the channel coder 62 is supplied to the TBC (Time Base Corrector) 63. TBC63 is for removing the time axis fluctuation component of the reproduction signal. The TBC63 is given a clock based on the reproduction signal and a clock based on the reference signal.

【0077】

The output of the TBC63 is supplied to the deframed circuit 64. The deframed circuit 64 corresponds to the framed circuit 5 of the recording system, and performs error correction processing and the like.

【0078】

65 is a switch circuit. The switch circuit 65 is switched between the case of reproducing the MPEG2 transport packet and the case of reproducing the component video signal. The output of the deframed circuit 64 is supplied to the switch circuit 65. When the reproduction signal is an MPEG2 transport packet, the switch circuit 65 is switched to the terminal 65A side. When the reproduced signal is a component signal, the switch circuit 65 is switched to the terminal 65B side.

【0079】

66 is a DCT extension circuit. The DCT circuit 66 corresponds to the DCT compression circuit 3 of the recording system. That is, the DCT circuit 66 restores the compressed video signal by decoding the variable length code and performing the inverse DCT transform. The output of terminal 65B of the switch circuit 65 is supplied to the DCT circuit 66. The output of the DCT extension circuit 66 is taken out from the output terminal 67.

【0080】

68 is a packet processing circuit. The output of the switch circuit 65 is supplied to the packet processing circuit 68. The packet processing circuit 68 includes a buffer for rate conversion, and converts a transport packet reproduced at a rate of, for example, 10 Mbps into the original rate. At the same time, the 3-byte time axis information attached to the beginning of the packet is detected, and the time axis is set based on this time information. At the time of reproduction, the rotation of the drum is synchronized with the reference clock similar to that at the time of recording. Therefore, the time axis state at the time of recording can be completely reproduced.

【0081】

Further, at the time of variable speed reproduction, it is determined whether or not the reproduced packet contains the I picture, and only the packet containing the I picture is transmitted. The output of the packet processing circuit 68 is output from the output terminal 70.

【0082】

71 is a controller. The controller 71 performs switching control between normal reproduction and variable speed reproduction. A mode setting signal is supplied to the controller 71 from the input unit 72. The servo circuit 73 and the packet processing circuit 69 are set according to this mode setting signal. When shifting playback is performed based on the data of the transport packet, phase control and speed control are performed by the servo circuit 73 using ATF tracking control. As a result, the trick play areas TP1 and TP2 are regenerated.

【0083】

In the above example, for example, one program is selected and recorded from a 30 Mbps multi-program, but if the total rate of the multi-program is 25 Mbps, all the multi-programs are directly recorded in the digital VTR. be able to. The shift reproduction process at this time is as follows.

【0084】

Select Program A, extract the I picture data from it, and record it in the trick play area. When the recording is finished, select program B and record the frame data from there. Next, select program C and record it. In the above manner, processing is performed as Program A-Program B-Program C ... Program A-Program B-Program C.

【0085】

At the time of reproduction, for example, when viewing the variable speed reproduction image of the program A, only the data of the program A is reproduced, and dummy data is sent while the data of another program is being picked up.

【0086】

The present invention can also be used when shifting and reproducing a scrambled bit stream. In other words, 1 bit is prepared in the header part of the transport packet at the time of encoding to indicate whether or not an I picture is included. At the time of recording, the packet including the I picture is recorded as it is by looking at this header. In this case, since the data other than the header part is scrambled, it is not possible to remove the high frequency coefficient. At the time of playback, if the data in the trick play area is sent back as it is, it will be descrambled by the decoder and the variable speed playback image can be viewed.

【0087】

[Effect of the invention]

According to the present invention, when a program is selected from a transport packet, rate conversion is performed, and the time axis information of each packet is retained, the arrival time information of the packet based on the reference clock is added to each packet. Will be done. As a result, the same time axis state as at the time of input is reproduced at the time of reproduction. In the recording / playback of the digital VTR, since the rotation of the drum is synchronized with the reference clock, the time information is retained in the recording / playback.

[Simple explanation of drawings]

FIG. 1 is a block diagram showing a configuration of a recording system of a digital VTR to which the present invention is applied.

FIG. 2 is a schematic diagram used for explaining time information.

FIG. 3 is a block diagram of an example of a circuit for adding time information.

FIG. 4 is a schematic diagram showing a data arrangement of a packet to which time information is added.

FIG. 5 is a schematic diagram used for explaining an extra header.

FIG. 6 is a schematic diagram used for explaining a trick play area.

FIG. 7 is a waveform diagram used for explaining a trick play area.

FIG. 8 is a schematic diagram showing a track configuration of a digital VTR to which the present invention is applied.

FIG. 9 is a schematic diagram used for explaining a trick play area.

FIG. 10 is a schematic diagram used for explaining variable speed reproduction.

FIG. 11 is a schematic diagram used for explaining variable speed reproduction.

FIG. 12 is a schematic diagram used for explaining speed change reproduction.

FIG. 13 is a schematic diagram used for explaining variable speed reproduction.

FIG. 14 is a block diagram of an example of a circuit for setting a trick play area.

FIG. 15 is a block diagram of another example of a circuit for setting a trick play area.

FIG. 16 is a graph showing the relationship between a coefficient and a bit amount.

FIG. 17 is a block diagram of yet another example of a circuit for setting a trick play area.

FIG. 18 is a schematic diagram used for explaining screen division. ..

FIG. 19 is a block diagram of yet another example of a circuit for setting a trick play area.

FIG. 20 is a block diagram used for explaining screen division.

FIG. 21 is a block diagram showing a configuration of a reproduction system of a digital VTR to which the present invention is applied.

FIG. 22 is a schematic diagram used for explaining a transport packet.

FIG. 23 is a schematic diagram used for explaining the recording of a conventional transport packet.

FIG. 24 is a block diagram used for explaining the recording of a conventional transport packet.

[Explanation of symbols]

32 Sink detection circuit 34 Reference signal generation circuit 38 Time stamp circuit 52 Rate conversion buffer 56A, 56B TS / PES packetization circuit