Semiconductor device and its manufacture

【0001】

[Technical field to which the invention belongs]

The invention disclosed herein relates to a semiconductor device having a semiconductor thin film formed on a substrate having an insulating surface as an active layer. In particular, the present invention relates to a thin film transistor having an active layer formed of a crystalline silicon film.

【0002】

[Conventional technology]

In recent years, attention has been focused on a technique for forming a thin film transistor (TFT) using a semiconductor thin film (thickness of several hundred to several thousand Å) formed on a substrate having an insulating surface. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and their development is urgently needed, especially as switching elements for image display devices.

【0003】

For example, in a liquid crystal display device, a pixel matrix circuit that individually controls pixel regions arranged in a matrix, a drive circuit that controls the pixel matrix circuit, and a logic circuit (processor circuit or memory circuit) that processes an external data signal. Attempts have been made to apply TFT to all types of electric circuits such as).

【0004】

At present, TFTs using an amorphous silicon film (amorphous silicon film) as an active layer have been put into practical use, but for electric circuits such as drive circuits and logic circuits that require higher speed operation performance. , TFT using a crystalline silicon film (polysilicon film) is required.

【0005】

As a method for forming a crystalline silicon film on a substrate, the techniques described in JP-A-6-232059 and JP-A-6-244103 by the applicant are known. The technique described in this publication is crystalline silicon with excellent crystallinity by heat treatment at 500 to 600 ° C for about 4 hours by using a metal element (especially nickel) that promotes crystallization of silicon. It makes it possible to form a film.

【0006】

Further, the technique described in JP-A-7-321339 applies the above technique to carry out crystal growth substantially parallel to the substrate, and the inventors particularly set the formed crystallization region as a lateral growth region (or). Lateral growth area).

【0007】

However, even if a drive circuit is configured using such a TFT, the required performance is still not completely satisfied. In particular, it is currently impossible to configure a high-speed logic circuit that requires extremely high-performance electrical characteristics that realize high-speed operation and high withstand voltage characteristics at the same time with a conventional TFT.

【0008】

[Problems to be Solved by the Invention]

As described above, in order to improve the performance of electro-optical devices and the like, it is necessary to realize a TFT having performance comparable to that of a MOSFET formed by using a single crystal silicon wafer.

【0009】

Therefore, it is an object of the invention disclosed in the present specification to provide an extremely high-performance thin film semiconductor device and a method for manufacturing the same, which is a breakthrough for realizing further high performance of the electro-optical device.

【0010】

[Means for solving problems]

The reason why the above-mentioned high-performance TFT could not be obtained by the conventional method is that carriers (electrons or holes) are trapped at the grain boundaries, and the electric field effect is one of the parameters indicating the TFT characteristics. It is probable that the improvement in mobility was hindered.

【0011】

For example, there are many unpaired bonds (dangling bonds) and defect (capture) levels of silicon atoms at the grain boundaries. Therefore, when the carriers moving inside each crystal approach or come into contact with the grain boundaries, they are easily trapped by unpaired bonds, defect levels, etc., and the grain boundaries are "malignant crystals" that hinder the movement of carriers. It is probable that it behaved as a "grain boundary".

【0012】

In order to realize the semiconductor device of the present invention, a technique for structurally changing such a "malignant grain boundary" and transforming it into a "benign crystal grain boundary" for a carrier is indispensable. That is, it can be said that it is important to form at least a grain boundary having a small probability of capturing a carrier and a small possibility of hindering the movement of the carrier.

【0013】

Therefore, the constitution of the invention disclosed in the present specification includes a step of forming an amorphous silicon film on a substrate having an insulating surface and the non-crystal when producing a semiconductor device having an active layer made of a semiconductor thin film. A step of selectively forming a mask insulating film on a quality silicon film, a step of selectively holding a metal element that promotes crystallization on the amorphous silicon film, and a first heat treatment to prevent the non-formation. A step of transforming at least a part of the crystalline silicon film into a crystalline silicon film, a step of removing the mask insulating film, a step of forming an active layer composed of only the crystalline silicon film by patterning, and the above-mentioned step. By performing a step of forming a gate insulating film on the active layer and a second heat treatment in an atmosphere containing a halogen element, the metal element in the active layer is gettered and removed, and the active layer and the gate are removed. At least a step of forming a thermal oxide film at the interface with the insulating film and a step of improving the film quality of the gate insulating film including the thermal oxide film and the state of the interface by a third heat treatment in a nitrogen atmosphere. The active layer is characterized in that it is a crystal structure in which crystal grain boundaries are substantially aligned in one direction and a plurality of needle-shaped or columnar crystals substantially parallel to the substrate are assembled.

【0014】

When the crystalline silicon film is formed by the production method according to the above configuration, a thin film having an appearance as shown in FIG. 9 can be obtained. FIG. 9 is a magnified micrograph of the present invention when the present invention is carried out using the technique described in JP-A-7-321339 as a means for crystallizing an amorphous silicon film, and the length may be several tens to one hundred and several tens of μm. A lateral growth region 901 is formed.

【0015】

It should be noted that this transverse growth region 901 grows substantially perpendicular to the region (indicated by 902) to which a metal element that promotes crystallization of needle-shaped or columnar crystals is added, and substantially parallel to each other. , The feature is that the crystal directions are aligned. Further, what is shown by 903 is a macroscopic grain boundary formed by collision of needle-shaped or columnar crystals extending from the facing addition regions 902 (distinguishable from the crystal grain boundary between needle-shaped or columnar crystals). ).

【0016】

Further, FIG. 10 is a TEM photograph in which the inside of the crystal grain is further enlarged to a fine region, focusing on the inside of the lateral growth region shown in FIG.

【0017】

That is, the crystalline silicon film of the present invention macroscopically appears to be composed of a large lateral growth region 901 as shown in FIG. 9, but in fact, when the lateral growth region 901 is microscopically observed, it is shown in FIG. The crystal structure is formed by assembling a plurality of needle-shaped or columnar crystals 1001.

【0018】

Further, in FIG. 10, 1002 indicates a crystal grain boundary indicating a boundary between needle-shaped or columnar crystals, and the needle-shaped or columnar crystal 1001 crystallizes in a direction substantially parallel to each other from the extending direction of the crystal grain boundary 1002. It can be confirmed that it has grown. Unless otherwise specified, the grain boundaries in the present specification refer to the boundaries between needle-shaped or columnar crystals.

【0019】

Further, in the semiconductor device of the present invention, metal elements (mainly nickel) that promote crystallization are removed by gettering by heat treatment in an atmosphere containing halogen elements, and 5 × 10¹⁷atoms / cm³ Nickel remaining at the above concentration is 1 × 10¹⁶~ 5×10¹⁷atoms / cm³ It is reduced to (preferably less than or equal to the spin density in the active layer).

【0020】

Of course, it is considered that other metal elements (Cu, Al, etc.) mixed (not intentionally added) due to contamination or the like are also gettered and removed.

【0021】

At this time, the unpaired bond of the silicon atom is expected to combine with oxygen during the heat treatment to form an oxide (silicon oxide). As a result, it is considered that silicon oxide is formed in the region that was the "malignant grain boundary", and the silicon oxide substantially functions as the crystal grain boundary.

【0022】

It is presumed that the grain boundaries 1002 formed in this way are in a state where the interface between silicon oxide and crystalline silicon is in a state of excellent consistency with almost no lattice defects. This is due to the synergistic effect of the process of forming silicon oxide by thermal oxidation and the process of promoting the recombination of silicon atoms with each other or between silicon atoms and oxygen atoms by the catalytic action of nickel. This is because silicon atoms are consumed.

【0023】

That is, the grain boundaries shown by 1002 in FIG. 10 are "benign crystals" that have almost no defects that capture carriers and function only as an energetic barrier for carriers that move inside needle-shaped or columnar crystals. It is thought to behave as a "grain boundary".

【0024】

Further, since the thermal oxidation reaction proceeds preferentially at such grain boundaries, the thermal oxide film is formed thicker than other regions. Therefore, it is presumed that the apparently small gate voltage applied near the grain boundaries can be an energy barrier.

【0025】

In addition, since this heat treatment is performed at a relatively high temperature exceeding 700 ° C (typically 800 to 1100 ° C), crystal defects such as dislocations and stacking defects existing inside needle-shaped or columnar crystals are almost present. It will disappear. Furthermore, the unpaired bonds of the remaining silicon atoms are terminated by hydrogen and halogen elements contained in the membrane.

【0026】

Therefore, the present inventors define the region inside the plurality of needle-shaped or columnar crystals as "a region that can be regarded as a substantially single crystal by the carrier" in the state shown in FIG. 10 obtained as described above. ..

【0027】

"It can be regarded as a single crystal for carriers" means that there are no barriers that hinder the movement of carriers when they move, that there are no crystal defects or grain boundaries, and that there is an energetically barrier potential. In other words, there is no barrier.

【0028】

The present invention uses a crystalline silicon film having the above configuration to form an active layer of a semiconductor device represented by a TFT, and realizes a high-performance semiconductor device sufficient to form a drive circuit and a logic circuit. It is a thing.

【0029】

The configuration of the present invention as described above will be described in detail with reference to the examples described below.

【0030】

[Example]

[Example 1] In this example, an example in which a crystalline silicon film formed according to the production method of the present invention is used as an active layer of a thin film transistor (TFT) is shown. Figure 1 shows an example of the TFT manufacturing process.

【0031】

The means for crystallizing the amorphous silicon film used in this example is the technique described in JP-A-7-321339. Therefore, in this embodiment, only the outline thereof will be described, and the above-mentioned publication may be referred to for details.

【0032】

First, a substrate 101 having an insulating surface is prepared. In this embodiment, a silicon oxide film 102 is formed on a quartz substrate as a base film to a thickness of 2000 Å. As a method for forming the silicon oxide film 102, a reduced pressure thermal CVD method, a plasma CVD method, a sputtering method, or the like may be used.

【0033】

It should be noted that, when the amorphous silicon film is crystallized later, it has been found by the studies of the present inventors that the crystallinity of the crystalline silicon film obtained is better when the underlying film is denser. Also, 5 × 10 in the membrane¹⁷~ 2×10¹⁹atoms / cm³ It is preferable that oxygen is contained. Oxygen contained in the membrane plays an important role in the gettering process of metal elements that promotes subsequent crystallization.

【0034】

Next, the amorphous silicon film 103 is deposited to a thickness of 200 to 1000 Å (350 Å in this example) by the reduced pressure thermal CVD method. Silane gas (SiH) is used as the film forming gas.₄, Si₂H₆ , Si₃H₈ Etc.) may be used. The amorphous silicon film formed by the vacuum thermal CVD method has a small natural nucleation rate during subsequent crystallization. This is desirable for increasing the lateral growth width because the rate at which individual crystals interfere with each other (collide with each other and stop growing) is reduced.

【0035】

Of course, as a method for forming the amorphous silicon film 103, a plasma CVD method, a sputtering method, or the like can also be used.

【0036】

Next, a silicon oxide film 104 having a thickness of 500 to 1200 Å is formed by a plasma CVD method or a sputtering method, and only the region into which a metal element that promotes crystallization is introduced is selectively etched and removed. That is, the silicon oxide film 104 functions as a mask insulating film for selectively introducing nickel into the amorphous silicon film 103.

【0037】

The region 105 exposed by the silicon oxide film 104 is formed in a slit shape having a longitudinal direction in the direction perpendicular to the paper surface. (Fig. 1 (A)) [0038]

Next, UV light is irradiated in an oxygen atmosphere to form an ultrathin oxide film (not shown) on the surface of the amorphous silicon film 103 exposed by the region 105. This oxide film is for improving the wettability of the solution in the solution coating step when a metal element that promotes crystallization is introduced later.

【0039】

As the metal element that promotes crystallization, one or more kinds of elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used. In the example, Ni (nickel) will be described as an example.

【0040】

Next, a nickel nitrate solution (or nickel acetate solution) containing nickel is dropped at a predetermined concentration (100 ppm in terms of weight in this example) to form a thin water film 106 containing nickel by a spin coating method. .. The concentration of nickel added to the amorphous silicon film can be easily controlled by adjusting the concentration of the nickel salt solution in the solution coating step. (Fig. 1 (B)) [0041]

Next, hydrogen is discharged at 450 ° C for about 1 hour in an inert atmosphere, and then heat-treated at a temperature of 500 to 700 ° C, typically 550 to 600 ° C, for 4 to 8 hours (No. 1). The heat treatment of 1) is added to crystallize the amorphous silicon film 103. In this way, the crystalline silicon film 107 is obtained. (Fig. 1 (C)) [0042]

At this time, the crystal growth proceeds in the direction in which the needle-shaped or columnar crystals are substantially parallel to the substrate. In the case of this embodiment, since the region indicated by 105 has a slit shape having a longitudinal direction from the front side to the back side of the drawing, the crystal growth proceeds substantially in one direction as shown by the arrow 108. To do. At this time, crystal growth can be carried out over several hundred μm or more.

【0043】

In addition, what is indicated by 109 is a nickel-added region, which contains nickel at a higher concentration than the transverse growth region 107. The crystallinity of the addition region 109 is not very good because the crystal nuclei are excessively dense and crystal growth occurs. Therefore, the active layer to be formed later is composed of a region excluding the addition region 109.

【0044】

Next, when the heat treatment for crystallization is completed, the silicon oxide film 104 serving as the mask insulating film for selectively adding nickel is removed. This step is easily carried out with buffered hydrofluoric acid or the like.

【0045】

The crystalline silicon film 107 may be laser annealed with an excimer laser before and / or after the heat treatment in an atmosphere containing a halogen element. However, although the crystallinity of the crystalline silicon film can be improved by laser irradiation, care must be taken because irregularities are likely to be formed on the surface of the silicon film.

【0046】

Next, the obtained crystalline silicon film 107 is patterned to form an active layer 110 that later functions as an active layer of a TFT. The arrangement of the active layer is important in the present invention. This will be described later.

【0047】

After the active layer 110 is formed, a gate insulating film 111 made of a silicon oxide film is formed on the active layer 110 to a thickness of 200 to 1500 Å (300 Å in this example). As a method for forming the gate insulating film 111, a vapor phase method such as a plasma CVD method, a thermal CVD method, or a sputtering method may be used.

【0048】

Further, a silicon nitride film or a silicon nitride film may be used instead of the silicon oxide film, or an insulating film thereof may be laminated and used.

【0049】

Next, heat treatment (second heat treatment) is performed in an atmosphere containing a halogen element. This heat treatment is primarily aimed at removing the metal elements (particularly nickel) in the active layer 110 by utilizing the gettering effect of the metal elements by the halogen elements. (Fig. 1 (D)) [0050]

It is important that the heat treatment for this gettering be performed at a temperature above 700 ° C to obtain its effect. At a temperature lower than that, the gate insulating film 111 may become a blocking layer and a sufficient gettering effect may not be obtained.

【0051】

Therefore, the temperature range of this heat treatment is more than 700 ° C, preferably 800 to 1000 ° C (typically 950 ° C), and the treatment time is 0.1 to 6 hours, typically 0.5 to. 1 hour.

【0052】

In this embodiment, oxygen (O)₂ ) Perform heat treatment at 950 ° C for 30 minutes in an atmosphere containing hydrogen chloride (HCl) at a concentration of 0.5 to 10% by volume with respect to the atmosphere. If the HCl concentration is equal to or higher than the above concentration, the surface of the crystalline silicon film will have irregularities similar to the film thickness, which is not preferable.

【0053】

Further, in this example, an example in which an HCl gas is used as a compound containing a halogen element is shown, but HF and NF are used as other gases.₃ , HBr, Cl₂ , ClF₃ , BCl₃ , F₂ , Br₂ One or more kinds selected from the halogen-containing compounds such as, etc. can be used. In general, halogen hydrides or organic substances (carbohydrates) can also be used.

【0054】

In this step, nickel segregated at the grain boundaries of needle-like or columnar crystals is gottered by the action of halogen elements (chlorine in this case), becomes volatile nickel chloride, and is removed into the atmosphere. Conceivable.

【0055】

Therefore, the nickel in the active layer 110 does not affect the device characteristics (1 × 10).¹⁶~ 5×10¹⁷atoms / cm³ , Preferably below the spin density in the active layer) has been confirmed by SIMS analysis. The lower limit of 1 × 10¹⁶atoms / cm³ Is the lower limit of SIMS detection. In addition, the impurity concentration in the present specification is defined by the minimum value of the measured value obtained by SIMS analysis.

【0056】

According to the findings of the present inventors, nickel used for promoting crystallization tends to segregate a large amount at the grain boundaries of needle-shaped or columnar crystals, and substantially almost the inside of needle-shaped or columnar crystals. It is considered not to be included.

【0057】

However, since the current SIMS analysis picks up information on both the inside of the crystal and the grain boundary, the nickel concentration in the present specification is strictly the average of the nickel concentrations contained in the inside of the crystal and the grain boundary. It means the average concentration of crystals.

【0058】

In addition, when the gettering process is performed, the halogen element used for the gettering process is 1 × 10 in the crystalline silicon film.¹⁵~ 1×10²⁰atoms / cm³ Remains at the concentration of. At that time, it tends to be distributed in a high concentration between the crystalline silicon film and the thermal oxide film.

【0059】

It is considered that nickel was extruded to the grain boundaries of needle-shaped or columnar crystals during crystallization and segregated, and was present as nickel silicide. Then, during gettering, it becomes nickel chloride and is separated, and the unpaired bond of silicon whose bond with nickel is broken is present in many grain boundaries.

【0060】

However, since the above step is performed at a relatively high temperature in an oxidizing atmosphere, the formed unpaired bond easily combines with oxygen to form an oxide (SiO)._X(Silicon oxide represented by) is considered to be formed. That is, the present inventors consider that the crystalline silicon film becomes a crystal structure in which silicon oxide functions as a crystal grain boundary by the above series of heating steps.

【0061】

In addition, the remaining unpaired bonds are terminated by hydrogen or halogen elements contained in the active layer 110 or compensated by the recombination between silicons, and crystal defects such as dislocations and stacking defects are rebonded by silicon atoms. It is considered that the crystallinity inside the needle-shaped or columnar crystal is also remarkably improved because it almost disappears due to the rearrangement or rearrangement.

【0062】

Therefore, nickel is sufficiently removed from the active layer 110 by heat treatment in a halogen atmosphere to the extent that the device characteristics are not hindered, and the needle-shaped or columnar crystals constituting the active layer 110 are significantly improved in crystallinity. , It is composed of a crystal structure having a region that can be regarded as a single crystal by the carrier.

【0063】

Further, by the above heat treatment, a thermal oxidation reaction proceeds at the interface between the active layer 110 and the gate insulating film 111, and a silicon film of about 100 Å is oxidized to form a thermal oxide film of 200 Å. That is, the total film thickness of the gate insulating film 111 is 500 Å, which is the sum of the film thickness formed by the CVD method and the film thickness formed by thermal oxidation.

【0064】

Furthermore, by performing the heat treatment in the halogen atmosphere and then the heat treatment at 950 ° C for about 1 hour in the nitrogen atmosphere, the film quality of the gate insulating film 111 is improved and an extremely good semiconductor / insulating film interface is realized. Will be done.

【0065】

Further, the active layer 110 is formed by a dry etching method, and the plasma damage remaining at the edge of the active layer at that time may cause a leakage current of the TFT. In the case of this embodiment, since the edge of the active layer 110 is thermally oxidized, it also removes plasma damage.

【0066】

After the formation of the gate insulating film (thermal oxide film) 111 is completed as described above, an aluminum film (not shown) for forming the gate electrode is then formed to a thickness of 2500 Å by a sputtering method. .. The aluminum film contains 0.2% by weight of scandium to prevent hillocks and whiskers.

【0067】

In this embodiment, a material containing aluminium as a main component is used as a material for forming the gate electrode (including the gate wiring), but tungsten, tantalum, molybdenum and the like can also be used. Further, a crystalline silicon film imparted with conductivity may be used as a gate electrode.

【0068】

Next, as shown in FIG. 1 (D), the aluminum film is patterned to form the island-shaped aluminum film pattern 112 which is the prototype of the gate electrode. The resist mask (not shown) used at this time is left as it is. (Fig. 2 (A)) [0069]

Then, anodizing is performed using the pattern 112 of the aluminum film as an anode. This technique uses a known anodizing technique (for example, Japanese Patent Application Laid-Open No. 7-135318). First, by this anodizing step, a porous anodized film 113 is formed on the side surface of the pattern 112. In this embodiment, the film thickness of the anodized film 113 is 0.7 μm.

【0070】

After forming the porous anodic oxide film 113 shown in FIG. 2 (B), a resist mask (not shown) is removed. Then, by performing anodizing again, a dense anodized film 114 is formed. The film thickness of the dense anodized film 114 is 900 Å.

【0071】

Further, the gate electrode 115 is defined through the above steps. The dense anodized film 114 functions to protect the surface of the gate electrode 115 and suppress the generation of hillocks and whiskers in a later step.

【0072】

Next, after forming the dense anodic oxide film 114, impurity ions for forming the source / drain region are injected in this state. If an N-channel type TFT is to be produced, P (phosphorus) ions may be injected, and if a P-channel type TFT is to be produced, B (boron) ions may be injected.

【0073】

In this step, a source region 116 and a drain region 117 to which impurities are added at a high concentration are formed.

【0074】

Next, the porous anodic oxide film 113 is selectively removed using a mixed acid in which acetic acid, phosphoric acid, and nitric acid are mixed, and then P ion implantation is performed again. This ion implantation is performed with a lower dose than when forming the source / drain region above. (Fig. 2 (C)) [0075]

Then, low-concentration impurity regions 118 and 119 having a lower impurity concentration than the source region 116 and the drain region 117 are formed. The region indicated by 120 directly below the gate electrode 115 becomes a channel forming region in a self-aligned manner.

【0076】

The low-concentration impurity region 119 arranged between the channel formation region 120 and the drain region 117 is particularly called an LDD (light-doped drain region) region, and is formed between the channel formation region 120 and the drain region 117. It has the effect of relaxing the high electric field.

【0077】

In addition, the channel formation region 120 (strictly speaking, inside the needle-shaped or columnar crystal) is composed of a true or substantially true region. A true or substantially true region is one in which the activation energy is approximately 1/2 (the Fermi level is located in the center of the forbidden band) and the impurity concentration is lower than the spin density. Or, it means that it is an undoped region to which impurities such as P and B are not intentionally added.

【0078】

Further, after the above-mentioned impurity ion implantation step, the region where the ion implantation has been performed is annealed by irradiating with laser light, infrared light, or ultraviolet light. This treatment activates the added ions and recovers the damage inflicted on the active layer during ion implantation.

【0079】

It is also effective to carry out the hydrogenation treatment in the temperature range of 300 to 350 ° C for 0.5 to 1 hour. In this step, the unpaired bond generated by hydrogen desorption from the active layer is hydrogen-terminated again. When this step is performed, 1 × 10 is contained in the active layer.²¹atoms / cm³ Below, preferably 1 × 10¹⁵~ 1×10²¹atoms / cm³ Hydrogen is added at the concentration of.

【0080】

When the state shown in FIG. 2C is obtained in this way, the interlayer insulating film 121 is then formed. The interlayer insulating film 121 is composed of a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, an organic resin film, or a laminated film of these films. (Fig. 2 (D)) [0081]

Further, when polyimide, which is an organic resin film, is used, since the relative permittivity is small, the parasitic capacitance between the upper and lower wirings can be reduced. Further, since it can be formed by the spin coating method, the film thickness can be easily increased and the throughput can be improved.

【0082】

Next, the interlayer insulating film 121 contact hole is formed to form the source electrode 122 and the drain electrode 123. Further, by performing heat treatment in a hydrogen atmosphere at 350 ° C., the entire device is hydrogenated, and the TFT shown in FIG. 2 (D) is completed.

【0083】

The TFT shown in FIG. 2 (D) has the simplest structure for explanation, but it is easy to obtain a desired TFT structure as appropriate by making some changes or additions to the manufacturing process procedure of this embodiment. is there.

【0084】

Here, the reason why the arrangement is important when forming the active layer 110 as described above will be described. The explanation will be given using Fig. 3.

【0085】

When this embodiment is carried out, the needle-shaped or columnar crystals grow substantially parallel to each other, so that the crystal grain boundaries are aligned in one direction. Further, by selectively adding a metal element that promotes crystallization, it is possible to freely control the direction in which needle-shaped or columnar crystals grow. This has a very important meaning.

【0086】

Here, an example in which an active layer is formed on a substrate having an insulating surface is shown in FIG. FIG. 3 shows active layers arranged in a matrix on the substrate 301 when the active matrix type liquid crystal display device is manufactured.

【0087】

The region indicated by the broken line of 302 is the location where the region for selectively introducing nickel existed. Further, 303 is a place where a macroscopic grain boundary formed by the lateral growth regions colliding with each other existed. Since these cannot be confirmed after the active layer is formed, they are shown by dotted lines.

【0088】

When crystallization is performed by the means shown in this example, the needle-shaped or columnar crystals grow in a direction substantially perpendicular to the nickel-added region 302 (the direction indicated by the arrow in the figure).

【0089】

Therefore, by arranging the island-shaped semiconductor 304 as shown in FIG. 3, the channel direction and the grain boundary of the needle-shaped or columnar crystal can be aligned in a direction that substantially coincides with each other. Moreover, by designing the nickel addition region 302 so as to reach from one end of the substrate 301 to the other, it is possible to realize the above-described configuration on the entire surface of the substrate.

【0090】

With such a configuration, the channel direction and the direction in which the needle-shaped or columnar crystals are lined up coincide with each other. That is, when functioning as the active layer of the TFT, it means that there are extremely few energy barriers that hinder the movement of carriers in the channel formation region, and further improvement in operating speed can be expected.

【0091】

In other words, the above means that the directionality of the needle-shaped or columnar crystal can be controlled so as to have a specific angle with respect to the channel direction. Figure 3 corresponds to the case where a specific angle is 0 °.

【0092】

That is, from a different point of view from FIG. 3, it is conceivable that the active layer 304 is rotated by 90 °. In that case, although the carrier mobility is reduced, low off-current characteristics and high withstand voltage characteristics can be expected.

【0093】

Here, FIG. 4 shows the electrical characteristics of the semiconductor device shown in FIG. 2 (D) produced by the present inventors according to the present embodiment. FIG. 4 (A) shows the electrical characteristics (Id-Vg characteristics) of the N-channel TFT, and FIG. 4 (B) shows the electrical characteristics of the P-channel TFT. The graph showing the Id-Vg characteristics displays the measurement results for 5 points together.

【0094】

The VG on the horizontal axis is the gate voltage value, and the ID on the vertical axis is the current value flowing between the source and drain. The Id-Vg characteristics (Id-Vg curve) shown by 401 and 403 show the characteristics when the drain voltage VD = 1V, and the Id-Vg characteristics shown by 402 and 404 are when the drain voltage VD = 5V. It shows the characteristics. Further, 405 and 406 indicate the leakage current when the drain voltage VD = 1V.

【0095】

The drain current (Ioff) in the off region (-1V or less in Fig. 4 (A) and -1V or more in Fig. 4 (B)) and the leakage current (IG) in the on and off regions are mostly 1 × 10.^-13 Since it is below A (measurement limit), it is confused with noise in FIGS. 4 (A) and 4 (B).

【0096】

Here, Tables 1 and 2 show typical characteristic parameters of the TFT according to the present invention obtained from the electrical characteristics shown in FIGS. 4 (A) and 4 (B). Table 1 shows the results of the electrical characteristics of the N-channel TFT (arbitrary 20-point measurement), and Table 2 shows the results of the electrical characteristics of the P-channel TFT (arbitrary 20-point measurement).

【0097】

[table 1] 【0098】

[Table 2] 【0099】

Of particular note in Tables 1 and 2 are that the subthreshold characteristic (S value, S-value) is small enough to fit between 60 and 100 mV / dec, and the mobility (μFE, mobility) is 150 to 300 cm.²It is extremely large, such as / Vs. In this specification, the mobility means the electric field effect mobility.

【0100】

These measurement data are values that cannot be achieved by conventional TFTs, and prove that the TFT according to the present invention is an extremely high-performance TFT comparable to a MOSFET manufactured on a single crystal.

【0101】

At the same time, it has been confirmed by an accelerated deterioration test by repeated measurement that the TFT according to the present invention is extremely resistant to deterioration. From experience, it has been found that a TFT operating at high speed has a drawback of being easily deteriorated, but the TFT according to the present invention has no deterioration and has extremely high withstand voltage characteristics.

【0102】

In addition, Tables 1 and 2 also show the mean value and standard deviation (σ value) for reference. The standard deviation is used as a measure of the variance from the mean. Generally, assuming that the measurement result (population) follows a normal distribution (Gaussian distribution), 68.3% of the total within ± 1σ, 95.4% within ± 2σ, and 99.7 within ± 3σ centered on the mean value. It is known that% is entered.

【0103】

In order to more accurately evaluate the variance of the TFT characteristics of this example, the present inventors measured 540 TFTs and obtained the mean value and aiming deviation from the results. As a result, the average S values were 80.5 mV / dec (n-ch) and 80.6 mV / dec (p-ch), and the standard deviations were 5.8 (n-ch) and 11.5 (p-ch). .. The average mobility (max) is 194.0 cm.²/ Vs (n-ch), 131.8cm²It was / Vs (p-ch) and the standard deviations were 38.5 (n-ch) and 10.2 (p-ch).

【0104】

That is, in the N-channel TFT using the present invention, the following TFT characteristics can be obtained. (1) The σ value of the S value is within 10 mV / dec, preferably within 5 mV / dec. (2) The S value is within 80 ± 30 mV / dec, preferably within 80 ± 15 mV / dec. (3) The σ value of μFE is 40 cm²Within / Vs, preferably 35 cm²It fits within / Vs.

【0105】

Further, in the P-channel type TFT using the present invention, the following TFT characteristics can be obtained. (1) The σ value of the S value is within 15 mV / dec, preferably within 10 mV / dec. (2) The S value is within 80 ± 45 mV / dec, preferably within 80 ± 30 mV / dec. (3) The σ value of μFE is 15 cm²Within / Vs, preferably 10 cm²It fits within / Vs.

【0106】

As described above, the TFT according to the present invention realizes extremely excellent electrical characteristics, and operates at high speed in complicated SRAM circuits and DRAM circuits in which only MOSFETs manufactured on a single crystal have been used so far. It is possible to configure a logic circuit that requires.

【0107】

Further, although only the manufacturing process example of the single-gate structure TFT is described in this embodiment, it can be applied to the double-gate structure TFT and the multi-gate structure TFT having more gate electrodes. ..

【0108】

Further, the present invention can be realized by increasing the crystallinity of the active layer, and can be carried out regardless of the TFT structure as long as the heat resistance allows.

【0109】

[Findings Regarding the Crystal Structure Obtained by the Present Invention] It has already been described that the crystalline silicon film obtained by the present invention is a crystal structure composed of an aggregate of needle-shaped or columnar crystals as shown in FIG. Here, a comparison is made between the crystal structure according to the present invention and the crystal structure formed by another method.

【0110】

The photograph shown in FIG. 11 is a TEM photograph of the sample which has completed the crystallization of the amorphous silicon film in the procedure of Example 1. That is, it shows the crystal structure of a crystalline silicon film containing a halogen element and not subjected to heat treatment.

【0111】

As can be confirmed in FIG. 11, a large number of dislocation defects (inside the circle indicated by 1101) exist inside the needle-shaped or columnar crystal immediately after crystallization. However, in the TEM photograph shown in FIG. 10, such dislocation defects are not confirmed inside the crystal, and it can be seen that the crystal structure is clean.

【0112】

This is evidence that the heat treatment in an atmosphere containing a halogen element contributes greatly to the improvement of crystallinity in the present invention.

【0113】

Further, the crystal structure shown in FIG. 12 is an example in which the crystallization conditions of the amorphous silicon film are different from those of the present invention. Specifically, the amorphous silicon film is crystallized by heat treatment at 600 ° C for 48 hours in a nitrogen atmosphere, and is subjected to thermal oxidation treatment at a temperature of about 900 to 1100 ° C.

【0114】

As shown in FIG. 12, the crystalline silicon film formed as described above has large individual crystal grains and is in a state of being divided by irregularly distributed grain boundaries.

【0115】

In FIG. 12, the crystal grains 1201 are surrounded by irregular grain boundaries 1202. Therefore, when the crystal structure shown in FIG. 12 is actually used as the active layer of the TFT, the energy barrier generated by the irregular grain boundaries 1202 hinders the movement of carriers.

【0116】

On the other hand, in the crystal structure as shown in FIG. 10, as shown in FIG. 10, the crystal grain boundaries 1002 are arranged with a certain degree of regularity. Therefore, it is considered that there is no energy barrier that hinders the movement of carriers inside the needle-shaped or columnar crystals.

【0117】

As a result of the present inventors observing the arrangement state of the needle-shaped or columnar crystals in a wide field of view of about 10,000 to 50,000 times, it was confirmed that the needle-shaped or columnar crystals may progress in a zigzag manner. There is. This is a phenomenon caused by the crystal growth going in an energetically stable direction, and it is presumed that a kind of grain boundary is formed at the place where the crystal direction is changed.

【0118】

However, we speculate that the grain boundaries that may occur inside needle-like or columnar crystals are like energetically inactive twin grain boundaries. That is, it is considered that the grain boundaries are different in crystal direction but are continuously bonded with good consistency and do not act as an energy barrier to hinder the movement of carriers (substantially not regarded as grain boundaries). There is.

【0119】

As described above, the crystalline silicon film crystallized by a general process has a crystal structure as shown in FIG. 12, and irregular grain boundaries are distributed so as to block the movement of carriers, so that the mobility is high. Is difficult to achieve.

【0120】

However, the crystalline silicon film according to the present invention has a crystal structure as shown in FIG. 10, the grain boundaries are substantially aligned in one direction, and the inside of the needle-shaped or columnar crystal becomes a substantial energy barrier. It is considered that there is no grain boundary. That is, since the carrier can move inside the crystal without being hindered at all, extremely high mobility can be achieved.

【0121】

In particular, the remarkable point of the needle-shaped or columnar crystal obtained by the present invention is that it continuously grows at a distance of several tens to several hundreds of μm while avoiding distortion caused by unevenness, stress, etc. It is a point that is considered to be done.

【0122】

If our guesses are correct, the crystalline silicon film according to the present invention grows without forming grain boundaries that can serve as carrier traps inside the crystal, and is a completely new crystal structure composed of a special aggregate of crystals. It can be said that it is a body.

【0123】

[Example 2] This embodiment is an example of forming a CMOS circuit with the TFT shown in the first embodiment. The CMOS circuit is configured by complementarily combining an N-channel type TFT and a P-channel type TFT having a structure as shown in Example 1.

【0124】

An embodiment of the process of manufacturing the CMOS circuit in this embodiment will be described with reference to FIGS. 5 and 6. The crystalline silicon film formed by the present invention has a wide range of applications, and the method for forming a CMOS circuit is not limited to this embodiment.

【0125】

First, a silicon oxide film 502 is formed on the quartz substrate 501 according to the manufacturing procedure shown in Example 1, and a crystalline silicon film (not shown) is obtained on the film. Then, by patterning it, an active layer 503 of an N-channel TFT and an active layer 504 of a P-channel TFT are formed.

【0126】

After the active layers 503 and 504 are formed, a gate insulating film 505 is formed, and further heat treatment is performed in an atmosphere containing a halogen element. In this embodiment, the processing conditions are the same as those in Example 1. In this way, the active layers 503 and 504 become the crystal structure of the present invention, and the gate insulating film 505 having a good film quality and interface is formed.

【0127】

Next, an aluminum film (not shown) that later constitutes the prototype of the gate electrode is formed and patterned to form aluminum film patterns 506 and 507 (the resist mask used for patterning remains even after pattern formation). deep).

【0128】

In this way, the state shown in FIG. 5 (A) is obtained. After the aluminum film patterns 506 and 507 are formed, the porous anodic oxide films 508 and 509 are then formed on the side surfaces of the aluminum film patterns 506 and 507 under the same conditions as in Example 1. In this example, the film thickness of the porous anodic oxide films 508 and 509 is 0.5 μm.

【0129】

Further, dense and strong anodic oxide films 510 and 511 are formed under the same conditions as in Example 1. However, in this embodiment, the ultimate voltage is adjusted so that this film thickness is 700 Å. Further, the gate electrodes 512 and 513 are defined by this step. In this way, the state shown in Fig. 5 (B) can be obtained.

【0130】

When the state shown in FIG. 5 (B) is obtained, the gate insulating film 505 is etched by a dry etching method. In this etching step, the gate electrodes 512 and 513 and the porous anodic oxide films 508 and 509 serve as masks, and the gate insulating film remains only immediately below the masks. When the porous anodic oxide films 508 and 509 are removed after etching, the state shown in Fig. 5 (C) is obtained.

【0131】

Next, a resist mask 514 is formed so as to cover the P-channel type TFT, and P (phosphorus) ion is doped as an impurity that imparts N-type. This doping has an acceleration voltage of 50 KeV and a dose of 0.1 to 5 × 10.¹³atoms / cm² , Preferably 0.5 ~ 2 × 10¹³atoms / cm² atoms / cm² Do it at.

【0132】

Since this doping step has a relatively high acceleration voltage, P ions pass through the exposed gate insulating film and are driven into the active layer 503. As a result, P ions are added to the regions indicated by 515 and 516. (Fig. 5 (C)) [0133]

Next, P ions are injected again as shown in FIG. 5 (D). For this injection of P ions, the acceleration voltage is set as low as 5KeV, and the dose amount is 0.1 to 1 × 10.¹⁵atoms / cm² , Preferably 2 ~ 5 × 10¹⁴atoms / cm² And. As a result of this step, regions 517 and 518 in which P ions are added at a high concentration are formed.

【0134】

When the process shown in FIG. 5 (D) is completed, the active layer of the N-channel TFT is completed. That is, the source region 517, the drain region 518, the low-concentration impurity region (or LDD region) 519, 520, and the channel formation region 521 of the N-channel TFT are defined.

【0135】

Next, as shown in FIG. 6 (A), a resist mask 522 covering the left N-channel TFT is formed. Then, in the state shown in FIG. 6 (A), B (boron) ion is injected as an impurity that imparts P type. Doping of this B ion is also performed in two steps as in the case of P ion.

【0136】

The first doping of B ions has an acceleration voltage of 30 KeV and a dose amount of 0.1 to 5 × 10.¹⁴atoms / cm² , Preferably 0.5 ~ 2 × 10¹⁴atoms / cm² To the extent. By this step, B ions are added to the regions indicated by 523 and 524. (Fig. 6 (A)) [0137]

The second B ion doping has an acceleration voltage of 5 KeV and a dose of 0.1 to 1 x 10.¹⁵atoms / cm² , Preferably 2 ~ 5 × 10¹⁴atoms / cm² To the extent. By this step, regions 525 and 526 to which B ions are added at a high concentration are formed. (Fig. 6 (B)) [0138]

Through the above steps, the source region 525, drain region 526, low-concentration impurity region (or LDD region) 527, 528, and channel formation region 529 of the P-channel TFT are defined.

【0139】

Next, after the step shown in FIG. 6B is completed, the resist mask 522 is removed, and the entire surface of the substrate is irradiated with laser light or strong light such as infrared light or ultraviolet light. The impurity ions added by this step are activated and the damage in the region where the impurity ions are injected is recovered.

【0140】

Next, the interlayer insulating film 530 is formed to a thickness of 4000 Å. The interlayer insulating film 530 may be any of a silicon oxide film, a silicon nitride film, a silicon nitride film, and an organic resin film, and may have a multilayer structure. As a method for forming these insulating films, a plasma CVD method, a thermal CVD method, or a spin coating method may be used.

【0141】

Next, a contact hole is formed to form a source electrode 531 of an N-channel TFT and a source electrode 532 of a P-channel TFT. Further, a CMOS circuit is realized by configuring the drain electrode 533 to be shared by the N-channel type TFT and the P-channel type TFT. (Fig. 6 (C)) [0142]

Through the above process, a CMOS circuit having the structure shown in FIG. 6 (C) can be manufactured. A CMOS circuit is an inverter circuit having the simplest configuration, and a closed circuit formed by connecting an odd number of CMOS inverter circuits in series is called a ring oscillator and is used when evaluating the operating speed of a semiconductor device.

【0143】

Here, the top photograph shown in FIG. 7A is a ring oscillator circuit configured by combining CMOS circuits manufactured according to this embodiment. The present inventors actually prototyped an active matrix type liquid crystal display device using the present invention, and confirmed the operating performance of the drive circuit with a ring oscillator.

【0144】

The gate electrode width of the CMOS circuit constituting the ring oscillator shown in FIG. 7 (A) is as narrow as about 0.6 μm, and the channel formation region is usually miniaturized to the extent that a short channel effect occurs.

【0145】

In addition, FIG. 7B shows a photograph of the shift register circuit for reference. The shift register circuit shown in FIG. 7B is one of the important circuits constituting the prototype peripheral drive circuit, and is a logic circuit that specifies the address of the pixel area. In particular, the shift register circuit for horizontal scanning (for the source side) is required to be driven at a very high frequency of about several MHz to several tens of MHz during actual operation.

【0146】

The oscillation frequency of the ring oscillator circuit was measured with a ring oscillator connected to 9, 19, and 51 sets (stages) of CMOS circuits. As a result, it was found that the ring oscillator with a power supply voltage of 3 to 5 V and a 9-stage ring oscillator had an oscillation frequency of 300 MHz or more, and some of which exceeded 500 MHz, and the operating speed was extremely high.

【0147】

These values mean that the operating speed is close to 20 times that of the ring oscillator manufactured in the conventional manufacturing process. Moreover, even if the power supply voltage is shaken in the range of 1 to 5V, the oscillation frequency of several tens to several hundreds of MHz is always realized.

【0148】

As described above, the CMOS circuit using the present invention can be operated at high speed without any problem even in a situation where added value is unavoidably added in the circuit design, and has the performance to meet the demands of all logic circuits. ..

【0149】

Further, it is according to the present invention that the channel length is extremely fine as 0.6 μm, but it also has a high withstand voltage characteristic that can withstand extremely high speed operation as shown in this embodiment. This means that the TFT is almost unaffected by the short-channel effect and has extremely high reliability.

【0150】

[Inference derived from the configuration of the present invention] As shown in Example 1 and Example 2, the TFT manufactured according to the present invention realizes extremely high performance (high-speed operation characteristics, high withstand voltage characteristics). In addition, it can be said that the characteristic of having such high-speed operation characteristics and being resistant to deterioration is an empirically peculiar phenomenon. Therefore, the present inventors have considered why the TFT according to the present invention is so excellent in deterioration resistance, and inferred one theory from it, which will be described below.

【0151】

The present inventors emphasized the influence of the grain boundaries of needle-shaped or columnar crystals as the reason for the high withstand voltage of the TFT according to the present invention. That is, the present inventors have a high grain boundary (expected to be an oxide region) locally existing in the channel formation region, which is applied between the source region and the drain region, particularly between the channel formation region and the drain region. It was speculated that the electric field was effectively relaxed.

【0152】

Specifically, the intergranular boundary suppresses the electric field formed by the depletion layer charge spreading from the drain region, and even when the drain voltage is high (the drain side depletion layer charge is increased), the diffusion on the source side is achieved. I thought that it was functioning so as not to change the electric potential.

【0153】

Summarizing the above, when the crystalline silicon film according to the present invention is used for the active layer, the channel forming region can be considered to satisfy the following constitution. (1) There is a substantially true region (inside the needle-like or columnar crystal) where the carrier moves (for the carrier). (2) There is an energy barrier that suppresses the movement of carriers or relaxes the electric field applied in the channel direction (the direction connecting the source and drain).

【0154】

Therefore, by satisfying the above two configurations, in other words, a configuration having a channel forming region substantially intrinsic to the carrier and a locally formed energy barrier, the excellent characteristics as shown by the present invention can be obtained. It is considered that TFT can be manufactured.

【0155】

The above configuration is derived from the experimental data of the present inventors, albeit with some speculation. Therefore, the present inventors have predicted that the same effect can be obtained by artificially creating this configuration.

【0156】

As a result, the present inventors have proposed an effective configuration for suppressing the short-channel effect. Here, the outline is described below. The considerations described below are currently limited to speculation.

【0157】

The short-channel effect is a general term for a decrease in threshold voltage, deterioration of withstand voltage due to punch-through phenomenon, and deterioration of subthreshold characteristics. The punch-through phenomenon, which is a particular problem, is a phenomenon in which the depletion layer on the drain side spreads to the source region, the diffusion potential on the source side decreases, and a through current flows between the source and drain.

【0158】

Therefore, the present inventors pay attention to the effect of the grain boundaries of the present invention, and in the short channel TFT having a channel length of about 0.01 to 2 μm, an impurity region is artificially and locally provided with respect to the channel formation region. Therefore, it was speculated that the effect of suppressing the spread of the depletion layer on the drain side could be obtained.

【0159】

It is considered that such a configuration can be achieved by forming the active layer as shown in FIG. In FIG. 8A, 801 is a source region, 802 is a drain region, 803 is a channel formation region, and an impurity region 804 is artificially formed in the channel formation region 803. Further, in the channel forming region 803, the region 805 other than the impurity region 804 is a substantially genuine region and is a region in which carriers move.

【0160】

Here, it is important that the structure shown in FIG. 8 (A) is a structure imitating the crystal structure of the present invention shown in FIG. That is, the grain boundary shown by 1001 in FIG. 10 corresponds to the impurity region 804 in FIG. 8 (A), and the acicular or columnar crystal in FIG. 10 corresponds to the region 805 in which the carrier in FIG. 8 (A) moves. It is.

【0161】

Therefore, the impurity region 804 arranged in the channel formation region 803 locally forms a region having a large built-in potential (which can be said to be an energy barrier) in the channel formation region, and the energy barrier effectively expands the drain side depletion layer. It can be inferred that it is suppressed.

【0162】

Further, FIG. 8 (B) shows a cross-sectional view obtained by cutting FIG. 8 (A) at A-A'. Reference numeral 806 is a substrate having an insulating surface. Further, a cross-sectional view obtained by cutting FIG. 8 (A) at B-B'is shown in FIG. 8 (C).

【0163】

In FIG. 8C, wpi and n represent the width of the impurity region 804, and wpa and m represent the width of the region where carriers move. Here, n and m mean that wpi and n are the widths of the nth impurity region and wpa and m are the regions in which the mth carrier moves in the channel formation region 803.

【0164】

Therefore, for the actual field effect mobility of the TFT according to the present invention, the effective channel width Wpa (sum of wpa, m added from 1 to m) must be substituted into the theoretical formula shown in the following equation.

【0165】

μFE = 1 / Cox (ΔId / ΔVg) 1 / Vd L / W where Cox is the gate oxide film capacity, ΔId and ΔVg are the changes in drain current Id and gate voltage Vg, respectively, and Vd is drain voltage, L, W is the channel length and channel width, respectively.

【0166】

However, since it is practically impossible to measure the effective channel width Wpa, the field effect mobility in the present specification is obtained by substituting the design value W of the channel width. That is, it is considered that a value smaller than the actual mobility is obtained.

【0167】

In addition, it is expected that providing the impurity region in the arrangement shown in FIG. 8 (A) has a great significance for improving the mobility. The reason will be explained below.

【0168】

Mobility (μFE) is determined by the scattering of carriers in a semiconductor film (here, a silicon film is taken as an example), and the scattering in a silicon film is roughly divided into lattice scattering and impurity scattering. The overall mobility μ formed by the influence of these is expressed by the following equation.

【0169】

[Number 1] 【0170】

The equation shown by the equation 1 shows that the overall mobility μ is the mobility μ when it is affected by lattice scattering._l(_lMeans lattice) mobility μ when affected by the reciprocal of and impurity scattering_i(_iMeans impurity) means that it is inversely proportional to the sum of the reciprocals of. In addition, lattice scattering and impurity scattering are each expressed by the following equations.

【0171】

[Number 2] 【0172】

[Number 3] 【0173】

According to these equations, when impurities are uniformly added to the entire channel formation region, the mobility cannot be increased due to the influence of impurity scattering. However, in the case of the configuration shown in FIG. 12, since the impurity region is locally formed, the impurity is not added to the region where the carrier moves, which is substantially true to the carrier.

【0174】

That is, theoretically, the concentration N of the impurities ionized in Equation 3_iMobility μ_iWill approach infinity infinitely. That is, 1 / μ in Equation 1_iSince it means that impurities are reduced to the extent that the term of can be ignored, the overall mobility μ is infinitely mobility μ._lIt is presumed that it will approach.

【0175】

Further, it is important that the impurity region 804 is arranged so as to be substantially parallel to the channel direction in FIG. 8 (A). Such an arrangement corresponds to the case where the extending direction of the grain boundary of the needle-shaped or columnar crystal shown in FIG. 10 and the channel direction coincide with each other.

【0176】

With such an arrangement, the impurity region 804 is expected to behave as a "benign grain boundary", so it is presumed that it acts like a rail and defines the moving direction for the carriers without capturing the carriers. Ru. This is a very important configuration for reducing the influence of scattering due to collisions between carriers.

【0177】

In addition, it is expected that the above-mentioned configuration can suppress a decrease in the threshold voltage, which is one of the short-channel effects. This is a conjecture based on the inference that the narrow-channel effect that occurs when the channel width becomes extremely narrow can be artificially caused between impurity regions.

【0178】

Further, as described above, it is considered possible to suppress the punch-through phenomenon by suppressing the spread of the depletion layer on the drain side, but by suppressing the punch-through phenomenon, the withstand voltage is improved and the subthreshold characteristic (S value). Can also be expected to improve.

【0179】

The improvement of the subthreshold property can be explained as follows from the inference that the volume occupied by the drain-side depletion layer can be reduced by using this configuration.

【0180】

If the spread of the depletion layer is effectively suppressed when the configuration shown in FIG. 8 (A) is adopted, it should be possible to significantly reduce the volume occupied by the depletion layer on the drain side. Therefore, it is considered that the depletion layer capacity can be reduced because the total depletion layer charge can be reduced. Here, the formula for deriving the S value is expressed by the following approximate formula.

【0181】

[Number 4] 【0182】

In Eq. 4, k is the Boltzmann constant, T is the absolute temperature, q is the charge amount, Cd is the depletion layer capacity, Cit is the equivalent capacity of the interface state, and Cox is the gate oxide film capacity. Therefore, in this configuration, by making the depletion layer capacitance Cd and the equivalent capacitance Cit of the interface state as close as possible to 0, an ideal state where Cd = Cit = 0, that is, a semiconductor device with an S value of 60 mV / decade is realized. There is a possibility that it can be done.

【0183】

However, the formula shown in Equation 4 is an approximate formula for deriving the S value, and TFT may obtain a measured value of 60 mV / decade or less without following this approximate formula.

【0184】

By the way, in the present configuration inferred from the present invention, nitrogen or carbon may be used in addition to oxygen as the impurity region corresponding to the grain boundary of the present invention. This is because the purpose of this configuration is to artificially place an energy barrier with respect to the channel formation region.

【0185】

Therefore, from the viewpoint of forming an energy barrier, it can be said that the impurity region having a conductive type opposite to that of the conductive type of the inversion layer is also effective. That is, it can be said that the impurity region may be formed by using B ions in the case of an N-channel type semiconductor device and P ions in the case of a P-channel type semiconductor device.

【0186】

Further, when the impurity region is composed of P or B ions, it is also possible to directly control the threshold value by the concentration of the impurity ions to be added.

【0187】

As described above, the present configuration is a technique derived by the inventors of the present inventors based on the constitution of the invention disclosed in the present specification and the experimental facts. It is presumed that by implementing this configuration, the short-channel effect, which is a problem in semiconductor devices in the deep submicron region where the channel length is extremely short, can be effectively suppressed.

【0188】

[Example 3] In this example, a process example different from the manufacturing process shown in Example 1 is shown. Specifically, before forming the active layer, the crystalline silicon film is heat-treated in an atmosphere containing a halogen element to remove nickel by gettering.

【0189】

By combining the steps shown in this example with Example 1, the nickel concentration in the active layer can be further effectively reduced.

【0190】

In addition, since the film thickness of the crystalline silicon film is reduced by heat treatment exceeding 700 ° C, it also has the effect of thinning the active layer. When the film thickness becomes thin, effects such as improvement of mobility and reduction of off-current can be expected.

【0191】

[Example 4] In this example, a process example different from the manufacturing process shown in Example 1 is shown. Specifically, in Example 1, the step of forming the gate insulating film 111 is omitted, and immediately after the active layer is formed, heat treatment is performed in an atmosphere containing a halogen element.

【0192】

The film quality can be improved by annealing the thermal oxide film formed at this time in a nitrogen atmosphere in the same manner as in Example 1. In this case, it is possible to form the gate insulating film only with such a thermal oxide film. The film thickness of the thermal oxide film can be formed in the range of 100 to 1500 Å (typically 500 to 1000 Å) by adjusting the heat treatment conditions.

【0193】

If the gate insulating film is formed only of the thermal oxide film, a semiconductor device capable of high-speed operation can be manufactured, and the process of forming the gate insulating film can be simplified. However, it is often difficult to form a uniform film thickness.

【0194】

It is also possible to deposit an insulating film on the thermal oxide film formed in the above step by the vapor phase method and use the laminated film as a gate insulating film. In that case, the gate pressure resistance is improved, but it is important to keep the interface between the thermal oxide film and the film by the vapor phase method clean.

【0195】

Further, the above step can be regarded as a step of removing a metal element (particularly nickel), the thermal oxide film formed in the above step can be removed, and the thermal oxide film can be formed again to form a gate insulating film. Further, after removing the thermal oxide film, a gate insulating film can be formed on the active layer by the vapor phase method. In this case, it is possible to reduce the concentration of extra impurities present at the interface between the active layer and the gate insulating film, but care must be taken in the cleanliness of the surface of the active layer.

【0196】

[Example 5] In this example, an example in which a TFT produced by applying the present invention is applied to DRAM (Dynamic Rondom Access Memory) and SRAM (Static Rondom Access Memory) will be described. FIG. 13 will be used for the explanation.

【0197】

DRAM is a type of memory that stores stored information as electric charge in a capacitor. The informational charge transfer to and from the capacitor is controlled by a TFT connected in series with the capacitor. Figure 13 (A) shows the TFT and capacitor circuits that make up one DRAM memory cell.

【0198】

When a gate signal is given by the word line 1301, the TFT indicated by 1303 becomes conductive. In this state, the capacitor 1304 is charged with an electric charge from the bit wire 1302 side to read the information, or the electric charge is taken out from the charged capacitor to read the information. That is, by writing and reading the electric charge accumulated in this capacitor by TFT, it has a function as a storage element.

【0199】

The feature of DRAM is that the number of elements that make up one memory is very small with only TFTs and capacitors, so it is suitable for building large-scale memories with high integration density. In addition, the price is kept low, so it is currently used in the largest amount.

【0200】

In addition, since the storage capacity can be set small as a feature when a DRAM cell is formed using a TFT, it is possible to operate at a low voltage.

【0201】

Next, FIG. 13 (B) shows a SRAM circuit using a high resistance as a passive load element. It is also possible to adopt a SRAM structure in which the same function as the passive load element is replaced by a TFT.

【0202】

SRAM is a memory that uses a bistable circuit such as a flip-flop as a storage element, and stores a binary information value (0 or 1) corresponding to the ON-OFF or OFF-ON bistable state of the bistable circuit. Is what you do. It is advantageous in that the memory is retained as long as the power is supplied.

【0203】

1305 is a word line and 1306 is a bit line. 1307 is a load element composed of high resistance, and SRAM is composed of two sets of driver transistors as shown by 1308 and two sets of access transistors as shown by 1309.

【0204】

The features of SRAM with the above configuration are that it can operate at high speed, has high reliability, and is easy to incorporate into the system.

【0205】

[Example 6] In the present embodiment, the semiconductor device of the first embodiment and the CMOS circuit of the second embodiment are used to configure an active matrix type electro-optic device in which a pixel matrix circuit and a logic circuit are integrated on the same substrate. An example is shown. The electro-optical device includes a liquid crystal display device, an EL display device, an EC display device, and the like.

【0206】

The logic circuit refers to an integrated circuit for driving an electro-optic device such as a peripheral drive circuit or a control circuit. In the active matrix type electro-optic device, an external IC was generally used as the logic circuit due to the limitation of operating performance and the problem of the degree of integration. However, by using the TFT of the present invention, all of them are integrated on the same substrate. It becomes possible to change.

【0207】

Further, the control circuit includes all electric circuits necessary for driving an electro-optical device such as a processor circuit, a memory circuit, a clock generation circuit, and an A / D (D / A) converter circuit. Of course, the memory circuit includes the SRAM circuit and the DRAM circuit shown in Examples 5 and 6.

【0208】

By utilizing the invention disclosed in the present specification for such a configuration, it is possible to configure a logic circuit with a TFT having performance comparable to that of a MOSFET formed on a single crystal.

【0209】

[Example 7] In this example, an example of producing a TFT having a structure different from that of Example 1 is shown. FIG. 14 is used for the explanation.

【0210】

First, the state shown in FIG. 2B is obtained through the same steps as in Example 1. When the state shown in FIG. 2 (B) is obtained, the resist mask (not shown) used for patterning the aluminum film is removed, and then anodizing treatment is performed in tartaric acid to obtain a dense anodized film having a thickness of 1000 Å. .. This state is shown in FIG. 14 (A).

【0211】

In FIG. 14 (A), 101 is a quartz substrate, 102 is an undercoat film, 110 is an active layer, and 111 is a thermal oxide film that later functions as a gate insulating film. Further, 1401 is a gate electrode made of a material containing aluminum as a main component, and 1402 is a dense anodized film obtained by anodizing the gate electrode 1401.

【0212】

Next, in this state, impurity ions that impart one conductivity to the active layer 110 are injected. Then, the impurity regions 1403 and 1404 are formed by this ion implantation step.

【0213】

After the injection of impurity ions is completed, a silicon nitride film 1405 is formed to a thickness of 0.5 to 1 μm. The film forming method may be any of a reduced pressure thermal CVD method, a plasma CVD method, and a sputtering method. Further, a silicon oxide film may be used in addition to the silicon nitride film.

【0214】

In this way, the state shown in FIG. 14 (B) is obtained. Once the state shown in FIG. 14 (B) is obtained, the silicon nitride film 1405 is then etched by the etchback method, leaving only on the side wall of the gate electrode 1401. The silicon nitride film left in this way functions as a sidewall 1406.

【0215】

At this time, the thermal oxide film 111 remains in the state shown in FIG. 14 (C) after the region other than the region where the gate electrode is used as a mask is removed.

【0216】

Impurity ions are injected again in the state shown in FIG. 14 (C). At this time, the dose amount is set higher than the dose amount of the ion implantation described above. During this ion implantation, the regions 1407 and 1408 immediately below the sidewall 1406 are not ion-implanted, so that the concentration of impurity ions does not change. However, higher concentrations of impurity ions will be injected into the exposed areas 1409 and 1410.

【0217】

As described above, after the second ion implantation, low-concentration impurity regions (LDD regions) 1407 and 1408 having lower impurity concentrations than the source region 1409, drain region 1410 and source / drain region are formed. Immediately below the gate electrode 1401 is an undoped region, which is a channel formation region 1411.

【0218】

When the state shown in FIG. 14 (C) is obtained through the above steps, a titanium film (not shown) having a thickness of 300 Å is formed, and the titanium film and the silicon (crystalline silicon) film are reacted. Then, after removing the titanium film, titanium silicides 1412 and 1413 are formed on the surfaces of the source region 1409 and the drain region 1410 by performing a heat treatment such as lamp annealing. (Fig. 14 (D)) [0219]

In the above step, a tantalum film, a tungsten film, a molybdenum film, or the like can be used instead of the titanium film.

【0220】

Next, a silicon oxide film is formed as an interlayer insulating film 1414 to a thickness of 5000 Å to form a source electrode 1415 and a drain electrode 1416. In this way, the TFT having the structure shown in FIG. 14 (D) is completed.

【0221】

In the TFT having the structure shown in this embodiment, good ohmic contact can be realized because the source / drain electrodes are connected to the source / drain region via titanium silicides 1412 and 1413.

【0222】

[Example 8] In this example, an example of producing a TFT having a structure different from that of Example 1 or Example 7 is shown. FIG. 15 is used for the explanation.

【0223】

First, the state shown in FIG. 2 (B) is obtained through the same steps as in Example 1. However, in this embodiment, a crystalline silicon film imparted with conductivity is used as the material for the gate electrode. This state is shown in FIG. 15 (A).

【0224】

In FIG. 15 (A), 101 is a quartz substrate, 102 is an undercoat film, 110 is an active layer, and 111 is a thermal oxide film that later functions as a gate insulating film. Further, 1501 is a gate electrode made of a crystalline silicon film (polysilicon film).

【0225】

Next, in this state, impurity ions that impart one conductivity to the active layer 110 are injected. Then, the impurity regions 1502 and 1503 are formed by this ion implantation step. (Fig. 15 (B)) [0226]

After the injection of the impurity ions is completed, the sidewall 1504 is formed by using the etchback method in the same manner as in Example 7.

【0227】

Then, after the sidewall 1504 is formed, the impurity ions are injected again. Through the above two ion implantations, a source region 1507, a drain region 1508, a low-concentration impurity region (LDD region) 1505, 1506, and a channel formation region 1509 are formed.

【0228】

When the state shown in FIG. 15 (C) is obtained through the above steps, a tungsten film (not shown) having a thickness of 500 Å is formed, and the tungsten film and the silicon film are reacted. Then, after removing the tungsten film, a heat treatment such as lamp annealing is performed to form tungsten silicides 1510 to 1512 on the surfaces of the gate electrode 1501, the source region 1507, and the drain region 1508. (Fig. 15 (D)) [0229]

Next, a silicon nitride film is formed as an interlayer insulating film 1513 to a thickness of 4000 Å to form a source electrode 1514 and a drain electrode 1515. In this way, the TFT having the structure shown in FIG. 15 (D) is completed.

【0230】

In the TFT having the structure shown in this embodiment, good ohmic contact can be realized because the gate electrode and the source / drain electrode are connected to the take-out electrode via tungsten silicides 1510 to 1512.

【0231】

[Example 9] In the present embodiment, an example of an electro-optical device (display device) incorporating a semiconductor device using the present invention is shown. The electro-optical device may be used as a direct-view type or a projection type as needed. Further, since the electro-optical device is also considered to be a device that functions using a semiconductor, the electro-optic device in the present specification is included in the category of the semiconductor device.

【0232】

Further, examples of application products of semiconductor devices using the present invention include TV cameras, head-mounted displays, car navigation systems, projections (front type and rear type), video cameras, personal computers and the like. A simple example of these applications is shown with reference to FIG.

【0233】

FIG. 16A shows a TV camera, which is composed of a main body 2001, a camera unit 2002, a display device 2003, and an operation switch 2004. The display device 2003 is used as a viewfinder.

【0234】

FIG. 16B shows a head-mounted display, which is composed of a main body 2101, a display device 2102, and a band portion 2103. Two relatively small size display devices 2102 are used.

【0235】

FIG. 16C shows a car navigation system, which is composed of a main body 2201, a display device 2202, an operation switch 2203, and an antenna 2204. Although the display device 2202 is used as a monitor, it can be said that the allowable range of resolution is relatively wide because the main purpose is to display a map.

【0236】

FIG. 16D shows a mobile information terminal device (a mobile phone in this embodiment), which is composed of a main body 2301, a voice output unit 2302, a voice input unit 2303, a display device 2304, an operation button 2305, and an antenna 2306. It is expected that the display device 2303 will be required to display moving images as a videophone in the future.

【0237】

FIG. 16E shows a video camera, which is composed of a main body 2401, a display device 2402, an eyepiece 2403, an operation switch 2404, and a tape holder 2405. Since the captured image displayed on the display device 2402 can be viewed in real time through the eyepiece 2403, the user can shoot while viewing the image.

【0238】

Figure 16 (D) shows the front projection, which consists of a main body 2501, a light source 2502, a reflective display device 2503, an optical system (including a beam splitter and a polarizer, etc.) 2504, and a screen 2505. Since the screen 2505 is a large screen used for presentations such as conferences and conference presentations, the display device 2503 is required to have a high resolution.

【0239】

In addition to the electro-optical device shown in this embodiment, it can be applied to portable information terminal devices such as rear projections, mobile computers, and handy terminals. As described above, the scope of application of the present invention is extremely wide, and it can be applied to display media in all fields.

【0240】

Further, the TFT of the present invention is not limited to the electro-optical device, and can be incorporated into an integrated circuit in the form of, for example, SRAM or DRAM, and used as a drive circuit of an applied product as shown in this embodiment.

【0241】

[Effect of the invention]

According to the invention disclosed in the present specification, it is possible to realize a TFT having high performance comparable to that of a MOSFET manufactured on single crystal silicon. In addition, the ring oscillator composed of the TFT of the present invention can operate 20 times faster than the ring oscillator composed of the conventional TFT.

【0242】

Furthermore, despite having such high characteristics, it has extremely high withstand voltage characteristics even in a fine region with a channel length of 1 μm or less, confirming that the short-channel effect is effectively suppressed. it can.

【0243】

By applying the integrated circuit configured by using the above-mentioned TFT to the electro-optic device, it is possible to further improve the performance of the electro-optic device. In addition, applied products to which an electro-optical device is applied can also have high performance and high added value.

[Simple explanation of drawings]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 2 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 3 is a diagram showing an arrangement configuration of an active layer.

FIG. 4 is a diagram showing characteristics of a semiconductor device.

FIG. 5 is a diagram showing a semiconductor device field fabrication process.

FIG. 6 is a diagram showing a manufacturing process of a semiconductor device. FIG. 7 is a photograph showing a configuration of an electric circuit.

FIG. 8 is a diagram showing the structure of an active layer.

FIG. 9 is a photograph showing the surface of a crystalline silicon film.

FIG. 10 is a photograph showing a crystal structure.

FIG. 11 is a photograph showing a crystal structure.

FIG. 12 is a photograph showing a crystal structure.

FIG. 13 is a diagram showing a configuration of a DRAM and SRAM. FIG. 14 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 15 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 16 is a diagram showing an application example of a semiconductor device.

[Explanation of symbols]

103 Amorphous silicon film 104 Silicon oxide film (mask insulating film) 105 Area where amorphous silicon film is exposed 106 Water film containing nickel 107 Crystalline silicon film 108 Arrow indicating the direction of crystallization 109 Nickel-added area 110 Active Layer 111 Thermal oxide film