High temperature electrode-barriers for ferroelectric and other capacitor structures

【0001】

[Technical field to which the invention belongs]

The present invention relates to the field of capacitors and memory devices, and more particularly to multilayer electrode structures applicable to such devices.

【0002】

[Conventional technology]

Ferroelectric capacitors have received considerable attention as a potential source of non-volatile memory. Expected benefits include, for example, flash<u style="single">EEPROM</u>There are higher read / write speeds and cycle capacities, as well as lower voltage conditions. Researchers have long developed 5 μm ferroelectric memory cell technology and even smaller memory cells. Onishi et al. "A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure", IEDM Digest of Technical Papers, p. 843 (1996); K. Shoji et al., "A 7.03 μm"²Vcc / 2-plate Nonvolatile DRAM Cell With a Pt / PZT / Pt / TiN CapacitorPatterned by One-Mask Dry Etching VLSI Tech. Symp. Digest of Technical Papers, p.28 (1996). (The contents of all references referred to herein are incorporated herein by reference.) Conventionally, these memory cells have used a Pt / TiN / Ti polysilicon plug structure as the capacitor bottom electrode. It was. The notable drawbacks of this structure were the oxidation of the TiN surface and the subsequent exfoliation of Pt from the TiN. This occurs during ferroelectric film formation at high temperatures as a result of oxygen passing through the Pt layer to the TiN surface. Temperatures above about 600 ° C to 700 ° C (this temperature is the "high temperature" used herein) are lead zirconate titanate (PZT) or SrBi.₂Ta₂O₉Since it is necessary to obtain a highly reliable ferroelectric film such as (SBT), the development of a highly stable electrode structure is an important key to achieving an advanced ferroelectric memory.

【0003】

[Problems to be Solved by the Invention]

Platinum (Pt) has been the material of choice for thin film electrodes due to its excellent electrical conductivity, thermal and chemical stability and good adhesion to the ferroelectric layer. However, Pt reacts with Si at fairly low temperatures (less than about 400 ° C) to form a silicide layer. Therefore, to prevent silicide formation and subsequent Si diffusion into the ferroelectric layer, SiO between the Pt electrode and the Si substrate.₂It is necessary to provide a barrier layer. SiO₂In addition to layers, Pt layer and SiO₂Further Ti layers have been used to improve the adhesion between the layers. However, even if the Ti intermediate layer is provided, the formation of hilok-like substances is usually observed on the surface of the Pt film. This is due to the disproportionate thermal expansion between Pt and Si during high temperature treatment. These hillocks can be quite large (between about 50 nm and 100 nm) and can be extremely detrimental to the properties of the ferroelectric film. Furthermore, it is well known that PZT capacitors with Pt electrodes exhibit a significant continuous reduction in switch charge with increasing switch cycle (ie, polarization fatigue). This fatigue is due to the domain accumulating due to the accumulation of space charge, especially at the PZT / Pt interface. Conductive oxide electrodes (ie, RuO) instead of Pt electrodes₂, La_1-XSr_XO₃(LSCO), YBa₂, Cu₃O_7-X(YBCO) etc.) can be used to reduce this problem to some extent. This improvement is due to the reduced accumulation of charge defects at the PZT / oxide interface and a better work function with PZT. However, the oxide electrode / PZT capacitor shows a much higher leakage current than the Pt / PZT capacitor.

【0004】

Multilayer conductive oxide / metal electrodes have been studied to simultaneously improve the fatigue and leakage current properties of PZT thin films. LSCO / Pt, RuO₂/ Pt and IrO₂Previous studies have shown that / Ir is somewhat promising in reducing fatigue and leakage current characteristics. However, the leakage current value at Pt is still high and must be improved. Polarization was sometimes worse.

【0005】

Electrode systems for memory applications must have the desired electrical and ferroelectric properties. In addition, the electrodes must be able to integrate within the design of the memory cell structure. Especially in large scale integration, the electrodes of the capacitors need to be in direct electrical contact with the source / drain of the transistors in a 1-transistor-1 capacitor single memory cell. Such electrode conditions should be: remain electrically conductive after exposure to an oxidizing atmosphere at high temperatures; under the oxygen / moving components of the ferroelectric film. Prevent diffusion to the substrate, thereby preserving the electrical properties of the transistor; Preventing Si from diffusing to the electrode surface during processing; Does not interact (react) with.

【0006】

The Pt electrode and the conductive oxide / metal electrode do not meet at least one of the above conditions and therefore cannot be effectively used in such a configuration. Pt / TiN / Ti / polysilicon plugs for NVRAM cell structures, and RuO for DRAM applications₂With / TiN, ferroelectric systems using PZT and SBT, as well as high dielectric materials (eg BST) have been studied. However, during high temperature (eg, above about 500 ° C.) treatment, the TiN layer is easily oxidized, resulting in increased electrode resistance and Pt layer exfoliation due to changes in the stress state of the Pt / TiN layer.

【0007】

Electrode systems that meet the above (and other) criteria are not considered known in the art.

【0008】

The present invention solves these conventional problems, and an object of the present invention is to provide a device provided with such an electrode system, thereby showing significant progress in the technical field.

【0014】

The present invention is also a capacitor having a lower electrode, an upper electrode, and a dielectric sandwiched between the lower electrode and the upper electrode formed on the substrate, wherein the lower electrode is Pt-Rh-. O_XFirst layer consisting of, second layer consisting of Pt-Rh, and Pt-Rh-O_XA third layer comprising the third layer provides a capacitor adjacent to the dielectric, whereby the above object is achieved.

【0015】

In a preferred embodiment of the present invention, the dielectric is a ferroelectric substance.

【0016】

In a more preferred embodiment of the present invention, the upper electrode is Pt-Rh-O._XFirst layer consisting of, second layer consisting of Pt-Rh, and Pt-Rh-O_XA third layer comprising the first layer is adjacent to the dielectric.

【0017】

In a more preferred embodiment of the present invention, the first layer of the lower electrode has a thickness of about 15 nm, the second layer of the lower electrode has a thickness of about 50 nm, and the first layer of the lower electrode has a thickness of about 50 nm. Three layers have a thickness of about 30 nm.

【0018】

In a more preferred embodiment of the present invention, the lower electrode<u style="single">The second layer is</u>It consists of Pt-13% Rh.

【0019】

In a more preferred embodiment of the invention, the first layer of the lower electrode has an atomic composition ratio of Pt: Rh: O = 66: 14: 20, and the second layer has Pt: Rh = about 87:13. The third layer has an atomic composition ratio of Pt: Rh: O = about 50:20:30. In a more preferred embodiment of the invention, the substrate comprises at least one of silicon, germanium, GaAs or other semiconductors.

【0020】

In a more preferred embodiment of the invention, the substrate is n⁺Si (100), n⁺Polysilicon / SiO₂/ Si and SiO₂Selected from the group consisting of / Si.

【0021】

The present invention further describes (a) Pt-Rh-O on a substrate._XA step of forming a first layer composed of (b) a step of forming a second layer composed of Pt-Rh on the first layer, and (c) a step of forming Pt-Rh-O on the second layer._XA step of forming a third layer composed of the first layer, the second layer and the third layer forming a lower electrode, and (d) a step of forming a dielectric on the third layer. (e) Provided is a method for manufacturing a capacitor having a high temperature electrode barrier, which includes a step of forming an upper electrode on the lower electrode, whereby the above object is achieved.

【0022】

In a preferred embodiment of the present invention, the steps (a), (b) and (c) are performed by RF sputtering.

【0023】

In a more preferred embodiment of the invention, the first layer is Ar + O.₂Sputtered in an atmosphere, the second layer is sputtered in an Ar atmosphere, and the third layer is Ar + O.₂Sputtered in the atmosphere.

【0024】

In a more preferred embodiment of the invention, the Ar atmosphere has a gas pressure of about 5 mTorr and the Ar + O₂The atmosphere has a gas pressure of about 7 m Torr.

【0025】

In a more preferred embodiment of the invention,<u style="single">Said</u><u style="single">Ar</u><u style="single">+</u><u style="single">O</u>_{<u style="single">2</u>}<u style="single">In the atmosphere</u>Ar: O₂The ratio is kept constant at about 20: 4 sccm.

【0026】

In a more preferred embodiment of the invention, the first layer is formed in about 3 minutes, the second layer is formed in about 17 minutes, and the third layer is formed in about 6 minutes. ..

【0027】

In a more preferred embodiment of the invention, the RF power density is about 16 watts per square inch.

【0028】

In a more preferred embodiment of the invention, the substrate temperature is about 450 ° C. during the forming step.

【0029】

A more preferred embodiment of the present invention further includes the step of annealing the capacitor.

【0030】

In a more preferred embodiment of the present invention, the annealing step is performed at about 650 ° C. for about 30 minutes.

【0031】

In a more preferred embodiment of the invention, the annealing step is performed at a temperature above at least 500 ° C.

【0032】

In a more preferred embodiment of the invention, the first layer is n⁺Si (100), n⁺Polysilicon / SiO₂/ Si and SiO₂Formed on a substrate selected from the group consisting of / Si.

【0035】

The present invention also comprises a lower electrode, an upper electrode, and a capacitor having a dielectric sandwiched between the lower electrode and the upper electrode, wherein the lower electrode is Pt-Rh-O._XFirst layer consisting of, second layer consisting of Pt-Rh, and Pt-Rh-O_XIt comprises a third layer consisting of the third layer, which is adjacent to the dielectric.<u style="single">FeRAM</u>And the dielectric is SrBi₂(Ta_1-XNb_X)₂O₉, And selected from the group consisting of solid solutions, PZT, and ferroelectrics,<u style="single">FeRAM</u>Is provided, thereby achieving the above objectives.

【0036】

The present invention further comprises a lower electrode, an upper electrode formed on a substrate, and a capacitor having a dielectric sandwiched between the lower electrode and the upper electrode.<u style="single">Pt-Rh-O</u>_{<u style="single">X</u>}<u style="single">First layer consisting of</u><u style="single">Pt-Rh</u><u style="single">Second layer consisting of, and</u><u style="single">Pt-Rh-O</u>_{<u style="single">X</u>}<u style="single">It comprises a third layer consisting of the third layer, which is adjacent to the dielectric.</u>DRAM, the dielectric is Sr_1-XBa_XTiO₃, BaBi₂Ta₂O₉, And a DRAM selected from the group consisting of high dielectrics, thereby achieving the above objectives.

【0037】

The operation will be described below.

【0038】

The present invention is an optimal capacitor for ferroelectric memories and DRAMs, as well as other applications. This capacitor is formed on a substrate such as silicon and, in some applications, can be placed in electrical contact with the source / drain of a transistor to form a memory cell for large-scale device integration.

【0039】

In one embodiment, the lower electrode structure consists of three layers, which together form an electrode and a diffusion barrier between the substrate and the ferroelectric (or other capacitor dielectric). The lower layer (closest to the substrate) is Pt-Rh-O_XIt is a metal oxide formed from. The intermediate layer is formed from the metal Pt-Rh. The upper layer (closest to the ferroelectric) is Pt-Rh-O_XFormed from.

【0040】

The ferroelectric layer is formed on this lower electrode structure.

【0041】

Upper electrodes are formed on the ferroelectric material to complete the capacitor. The upper electrode is preferably formed in exactly the same manner as the lower electrode. That is, Pt-Rh-O_XThe layer is formed directly on the ferroelectric. The Pt-Rh layer is its Pt-Rh-O_XFormed on the layer. Pt-Rh-O_XA layer is formed on the Pt-Rh layer to complete the capacitor structure.

【0042】

Other embodiments as shown below are included within the scope of the present invention.

【0043】

The capacitor of the present invention is preferably formed by RF sputtering, as shown below. However, the capacitors of the present invention can be formed by any other forming technique, including, for example, any chemical vapor deposition method or sol-gel method or physical vapor deposition process.

【0044】

The capacitor of the present invention has excellent ferroelectric properties and fatigue properties. In addition, the electrodes according to the invention act as an excellent barrier between the ferroelectric and the substrate even at high processing temperatures (eg 700 ° C).

【0045】

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention relates mainly to a device structure useful as a capacitor of a ferroelectric memory, and more particularly to a type of device structure in which a capacitor electrode is in direct electrical contact with the source / drain of a transistor via a polysilicon plug. Conventional devices have used separate electrodes and diffusion barrier layers that require the formation of four or five different layers.

【0046】

For example, the prior art device of FIG. 9 has a separate electrode and diffusion layer. Silicide (TiSi)₂Or TaSi₂) Layer 10 is formed on the polysilicon plug 8. TiO₂A (or Ta) layer 20 is formed on the silicide layer 10. TiN layer 30 is formed on layer 20. The Pt layer 40 is formed on the layer 30. RuO₂(Or LSCO or IrO₂) Layer 50 is formed on layer 40. Layers 20-50 form the lower electrode structure, on which a ferroelectric material such as PZT60 is formed. PZT as used herein includes undoped variants and any doped variants, including doping Pb, Zi and Ti. The devices can be located within the substrate and integrated into one device. Pt layer 40 and RuO₂Layer 50 is a metal and conductive oxide that improves the lowering properties of PZT ferroelectric capacitors. TiSi₂Layer 10, Ti layer 20 and TiN layer 30 form a diffusion barrier. The entire device is relatively complex and requires the formation of four or five different layers. However, such a design is necessary due to the constraints of diffusivity, oxidation resistance and adhesion. Even with this complexity, the device has problems with adhesion to processing temperatures above about 500 ° C and oxidation of the TiN layer 30.

【0047】

The lower electrode device of the present invention is shown in FIG. The electrode has a three-layer structure Pt-Rh-O_X/ Pt-Rh / Pt-Rh-O_XIs the basis. Pt-Rh-O_XA lower metal oxide layer consisting of 90 is formed on the substrate 80. An intermediate metal layer consisting of Pt-Rh100 is formed on layer 90. Pt-Rh-O_XAn upper metal oxide layer 110 composed of is formed on the intermediate layer 100. A ferroelectric layer 120 such as PZT is formed on the metal layer 110. Layers 90, 100 and 110 together form the bottom electrode of the capacitor device.

【0048】

The device was formed by an in situ sputtering process. The lower oxide layer 90 contains argon (Ar) and oxygen (O).₂) Sputtered in the atmosphere. The metal layer 100 is sputtered in pure Ar. Upper layer 110 is Ar and O₂Sputtered in the atmosphere. An RF sputtering system manufactured by Cooke Vacuum Products was used for sputtering.

【0049】

A Pt-10% Rh alloy target sized 2 inches in diameter and 0.125 inches thick was used. Electrode substrate temperature 450 ° C, RF power 50W (approx. 16W / in)²Power density). 5m Torr, Ar and O for pure Ar sputtering₂A gas pressure of 7 mTorr was used for the sputtering inside. Ar: O₂Ar and O while maintaining a constant ratio of 20: 4 sccm₂Sputtering was performed. The formation time was 3 minutes for the lower layer 90, 17 minutes for the intermediate layer 100, and 6 minutes for the upper layer 110. Lower electrode structure single crystal n⁺It was formed on the substrate 80 of Si (100). Yet another embodiment is n + polysilicon / SiO.₂/ Si, and SiO₂It is configured using the / Si substrate 80.

【0050】

Substrate 80 was cleaned and degreased to remove any surface contamination. Natural oxides on single crystal Si and poly Si substrates were removed and the surface was H-protected by using HF acid treatment. The substrate was then immediately transferred to a sputtering chamber for lower electrode formation to minimize natural oxide formation. Following the formation of the lower electrode, the composition PbZr_0.53Ti_0.47O₃MOD-induced PZT membrane was formed from metal-organic precursors. For preparation details, see G. Yi and M. Sayer, Ceram Bull., 70, 1173 (1991). The thickness of the PZT film was about 3000 Å as measured by spectroscopic elliptical polarization. The perovskite phase in the PZT membrane was then crystallized by annealing in a quartz tube furnace at 650 ° C for 30 minutes under an oxygen stream. Next, as shown in FIG. 2, an upper electrode was formed (the upper electrode is Pt-Rh / Pt-Rh-O)._X/ Pt-Rh layer). For more information, Pt-Rh-O_XThe layer 130 is formed on the ferroelectric layer 120. The metal Pt-Rh layer 140 is formed on the layer 130. Finally, the upper Pt-Rh-O_XLayer 150 is formed on layer 140. The top electrode contains layers 130-150. The upper electrode was formed under the same deposition conditions as the lower electrode, but other conditions may be used. The structure was then annealed at 600 ° C for 30 minutes. The thickness of the upper electrode is approximately 3.0 x 10^-4It was cm.

【0051】

The composition and thickness of the electrode film were measured using Rutherford Backscattering Spectroscopy (RBS). The phase formation and phase orientation of the PZT film were investigated using X-ray diffraction (XRD). The morphology of the membrane was examined using an atomic force microscope (AFM). The ferroelectric properties (hysteresis and fatigue) of the capacitor structure were measured using an RT66A ferroelectric tester manufactured by Radian Technologies of Albuquerque, NM. Direct current (dc) leakage current was measured using a Kiethley 617 programmable electric meter. This electrometer was programmed to measure the leak current in a stable state as a function of the applied voltage.

【0052】

SiO₂RBS studies on electrode films that have just been formed on the / Si substrate show that the surface by reactive sputtering (ie, the upper layer of the upper electrode) and the oxide layer as the electrode / substrate interface (ie, the lower layer of the lower electrode). The formation was confirmed. The composition of each layer at the electrodes was measured by adapting the theoretical spectrum using a simulation program until it was approximately in agreement with the experimental spectrum. The results of the RBS simulation confirm that there are three different layers in the formed film. SiO₂The lower layer adjacent to the layer is an oxide layer with an atomic composition ratio of Pt: Rh: O = 66: 14: 20. The intermediate layer is a metal layer having an atomic composition ratio of Pt: Rh = 87:13. The upper oxide layer is an oxide layer having an atomic composition ratio of Pt: Rh: O = 50:20:30. When the thickness of these layers corresponding to the above formation times was measured, the lower layer was 15 nm, the middle layer was 50 nm, and the upper layer was 30 nm.

【0053】

The intermediate metal layer formed in a pure Ar atmosphere had a 13% increase in Rh compared to the target and a 10% increase in Rh compared to Pt. This is probably due to the preferential sputtering of Rh. Based on the results of the compositional analysis, it has not been determined whether the membrane is a completely mixed oxide or a mixture of metal and oxide components. Both Rh and Pt are conductive oxides (RhO)_XOr PtO₂) Is formed. However, Rh has a high affinity for oxygen and is more likely to be oxidized than Pt. Therefore, preferential separation of Rh can occur in the oxide layer as compared to the metal layer, as observed in our case. The resistivity of the multilayer electrode barrier film measured using four point probes was in the range of 18 μOhm-cm to 24 μOhm-cm. This indicates that the multilayer electrode had a resistivity comparable to that of the metal film.

【0054】

Figure 3 shows O₂After annealing at 700 ° C for 60 minutes under air flow, n⁺The RBS spectra of the multilayer electrode film and the Pt film on the Si substrate are shown. This result clearly shows that there is no significant interdiffusion between Pt-Rh and Si compared to the case of Pt / Si (both ends of Pt and Si are significantly shifted). This is Pt-Rh-O_XIt is shown that the layer acts as an effective diffusion / reaction barrier up to a treatment temperature of at least 700 ° C. X-ray analysis of the freshly formed electrode membranes shows the formation of crystalline Pt-Rh electrode structures under their formation conditions. The XRD data for the multilayer electrode film formed on the Si substrate showed no new peaks compared to the Pt / Rh silicide and the corresponding Pt after annealing at 650 ° C. This means Pt-Rh-O_XIt shows the barrier effect of the layer. Morphological examination of the electrodes with AFM showed that the electrodes had fine and very fine particle structures with an average particle size of about 400 Å. Furthermore, after annealing at 650 ° C, no hillock formation was observed for these electrodes, and the average surface roughness (Ra) measured from AFM data was only 0.68 nm. Figure 4 shows O formed on the lower electrode / Si (100) structure and at 650 ° C for 30 minutes.₂The XRD pattern of the PZT film annealed in the atmosphere is shown. As observed from the XRD pattern, the membrane appears to crystallize preferentially to the ferroelectric perovskite phase. The absence of a peak in the pyrochlore phase means that the remaining pyrochlore phase is within the detectable limits of the XRD technique. This film does not appear to have a favorable orientation. The PZT film has an average particle size of about 800 Å as observed from the AFM micrograph.

【0055】

It is important to note the extreme smoothness (Ra = 0.62 nm) of the PZT film, which has an average roughness Ra value of only 1.31 nm, due to the smooth and fine particle structure of the lower electrode. In comparison, the films formed on the Pt electrodes tend to be fairly coarse and also have a large particle size (eg 1000 Å). This is due to the large particle size and hillock formation of the lower Pt electrode. See JO Olowolfe et al., J. App. Phy., 73, 1764 (1993). Therefore, the multilayer electrode according to the present invention has a significant advantage when used for a thinner film of PZT as compared with a Pt electrode.

【0056】

(A) in Fig. 5 and (B) in Fig. 5 are O at 650 ° C for 30 minutes.₂Annealed in n⁺The typical hysteresis curve and fatigue characteristics of the upper electrode / PZT / lower electrode structure of the present invention formed directly on the Si (100) substrate are shown. Hysteresis curves for these test structures are fully saturated and approximately 16 μC / cm.²The residual polarization (Pr) value of is shown. The coercive field value (Ec) is also low, in the range of 30 kV / cm to 40 kV / cm. n⁺Poly Si / SIO₂/ Si and SiO₂The Pr and Ec values for the capacitors formed on the / Si structure were within the same range. The Pr value of the PZT film formed on the multilayer electrode is lower than that of the film formed on the Pt electrode, probably due to the smaller particle size of PZT.

【0057】

A fatigue test was performed using a square wave generated from the outside with an amplitude of ± 5 V and a frequency of 500 kHz. In FIG. 5 (B), the switched and unswitched charges are plotted as a log (cycle) function applied to the capacitor. The result of the fatigue test is 10¹¹Indicates that there is no significant fatigue (less than 5% polarization) until the cycle.

【0058】

Figure 6 shows n⁺Applied voltage and polarity (upper electrode) for test structure on Si (100) substrate⁺Or lower electrode⁺The dependence of the dc leak current on any of) is shown. The leakage current increased very slightly up to the applied electric field of 100 kV / cm, followed by a linear increase up to the applied field of 500 kV / cm (log J vs. E).^1/2Dependence). This physical property indicates either Paul-Frenkel or Schottky barrier control mechanism. However, the different values of leakage current with respect to the polarity change during measurement mean that the Schottky barrier is the dominant leak current mechanism. The leakage current at the applied electric field of 100kV / cm (3V) is 2 × 10.^-8A / cm²It has a low value of, and can be comparable to PZT on the Pt electrode.

【0059】

In summary, Pt-Rh-O_X/ Pt-Rh / Pt-Rh-O_XFerroelectric test capacitors with multilayer electrode barriers have been formed on several substrates with excellent ferroelectric and fatigue properties. The multilayer electrode structure acts as an excellent barrier between the ferroelectric film and the Si substrate up to a high processing temperature of 700 ° C, and greatly improves the deterioration of the characteristics of these capacitors. The barrier properties of the multilayer electrode structure allow the use of integrated ferroelectric (eg, PZT, SBT) capacitors and high dielectric constant normal dielectric capacitors in large integrated memory cell structures. Now, although the devices have been constructed with excellent results, it should be understood that the present invention covers a wider range than these particular compositions. A typical capacitor device is schematically shown in FIG. The capacitor is formed on the substrate 200. The substrate 200 can be made of any material suitable for capacitor formation, with particularly suitable substrates being silicon, germanium, GaAs and other semiconductors. A metal oxide layer 210 is formed on the substrate 200. The metal oxide layer 210 can be any metal oxide, but in one embodiment most preferably it is a transition metal oxide. More specifically, the following metals are preferred: any transition metal, Pd, Pt, Ir, Rh and Ru. Silver (Ag) is also a suitable metal. As used throughout this specification, the term "metal" includes any alloy or other composition comprising a multilayer metal and does not merely refer to a single elemental compound. The term "alloy" can be used occasionally for further clarity, but does not change its meaning. The metal layer 220 is formed on the metal oxide layer 210. The metal of layer 220 is of the same type as the metal in the oxide form of layer 210 and therefore, as mentioned above, the same metal is preferred. The dielectric layer 230 is formed on the metal layer 220. The dielectric layer 230 is preferably a ferroelectric (eg, PZT and SBT) or other high dielectric material (eg, BST). Layers 210 and 220 come together to form the lower electrode.

【0060】

The upper electrode 240 is formed on the dielectric 230. The upper electrode 240 preferably has the same metal oxide and metal layer structure as the lower electrode. Therefore, the metal layer 242 is formed on the dielectric 230. A metal oxide layer 244 is formed on it (see FIG. 8). However, different top electrodes can also be used.

【0061】

An intermediate metal oxide layer (not shown) can be used to prevent fatigue, which is especially useful when the dielectric 230 is PZT. Therefore, a metal oxide layer is formed between the metal layer 220 and the dielectric 230. In this case, another metal oxide layer is preferably formed directly on top of the dielectric 230, which forms additional elements of the top electrode.

【0062】

The above capacitor structure<u style="single">FeRAM</u>(Non-volatile memory) and<u style="single">DRAM</u>Especially useful for.<u style="single">FeRAM</u>The following compounds are suitable dielectrics for: PbZr_1-XTi_XO₃(Including doped and undoped variants); SrBi₂Ta_1-XNb_XO₉, And solid solutions; other ferroelectrics.

【0063】<u style="single">DRAM</u>The following compounds are suitable dielectrics for: Sr_1-XBa_XTiO₃BaBi₂Ta₂O₉Other high dielectric constant materials.

【0064】

[Effect of the invention]

According to the present invention, it remains electrically conductive even after being exposed to an oxidizing atmosphere at high temperatures, preventing the ferroelectric film from diffusing into the substrate under the oxygen / moving components of the transistor. A ferroelectric capacitor can be provided that can retain electrical properties, prevent Si from diffusing into the electrode surface during treatment, and do not interact (react) between the ferroelectric and the substrate during treatment at high temperatures.

[Simple explanation of drawings]

FIG. 1 is a schematic view of a lower electrode and a ferroelectric capacitor on a substrate according to an embodiment of the present invention.

FIG. 2 is a schematic view of an upper electrode, a lower electrode, and a ferroelectric capacitor on a substrate according to an embodiment of the present invention.

FIG. 3 is a graph of RBS spectra for an electrode film and a Pt film according to the present invention on a substrate.

FIG. 4 is an XRD pattern of a ferroelectric (PZT) film formed on a high temperature electrode barrier and a substrate according to the present invention after annealing.

FIG. 5 (A) is a hysteresis curve of the capacitor according to the present invention, and FIG. 5 (B) is a fatigue plot of the capacitor according to the present invention.

FIG. 6 is a plot of dc leak current vs. applied voltage for both polarities of the capacitor according to the present invention.

FIG. 7 is a schematic diagram of a general capacitor structure according to the present invention.

FIG. 8 is a schematic view of an upper electrode according to one aspect of the present invention. FIG. 9 is a schematic view of a lower electrode and a ferroelectric capacitor on a substrate according to a conventional design.

[Explanation of symbols]

8 Polysilicon plug 10 silicide layer 20 TiO₂Layer 30 TiN Layer 40 Pt Layer 50 RuO₂Layers 60, 120 Ferroelectric materials 90, 110, 130, 150 Pt-Rh-O_XLayer 100, 140 Pt-Rh