JP3549788B2

Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system

Abstract

This record has no abstract on file.

Term

Term ended

Expired 5 November 2019, 6.9 years ago.

19 claims: 4 independent, 15 dependent

1
pluralFor input code sequenceCorrect in parallelAdd a bit stringpluralOutput code sequenceIn parallelIn a multi-stage coding method in which a plurality of coding processing steps for output are provided and the input information series is sequentially subjected to the coding processing steps multiple times to generate a multi-stage coding series. CommunicatingTwo to followthe aboveAt least one of the coding processesWhile selecting the replacement state that differs in timeMultiple output code sequences output from the coding process in the previous stageIn parallel between the output code sequencesSwapIs performed to perform interleaving, and a plurality of interleaved output code sequences are output in parallel.Provide a replacement processCharacterized byMulti-stage coding method. 複数の入力符号系列に並列に訂正ビット列を付加して複数の出力符号系列を並列に出力する符号化処理工程を複数備え、入力情報系列に対して順次この複数回の符号化処理工程を実施して多段符号化系列を生成する多段符号化方法において、連続する2つの上記符号化処理工程の間のうちの少なくとも1個所に、時間的に異なる入れ替え状態を選択しながら前段の符号化処理工程から出力される複数の出力符号系列に対して該出力符号系列間で並列に入れ替えを行うことによりインタリーブを行い、インタリーブされた複数の出力符号系列を並列に出力する入れ替え処理工程を設けることを特徴とする多段符号化方法。
4
pluralInput code sequenceToeachcorrectionBased on bit stringIn parallelDecrypt and do thispluralAs an output code sequenceIn parallelIn a multi-stage decoding method in which a plurality of output decoding processing steps are provided and the multi-stage coding sequence is sequentially subjected to the plurality of decoding processing steps to generate an output information sequence. CommunicatingTwo to followthe aboveAt least one location during the decryption processWhile selecting the replacement state that differs in timeMultiple output code sequences output from the decoding process in the previous stageIn parallel between the output code sequencesReverse replacementBy doingDeinterleaveAnd output multiple deinterleaved output code sequences in parallelProvide a reverse replacement processCharacterized byMulti-stage decoding method. 複数の入力符号系列をそれぞれの訂正ビット列に基づいて並列に復号し、これを複数の出力符号系列として並列に出力する復号処理工程を複数備え、多段符号化系列に対して順次この複数回の復号処理工程を実施して出力情報系列を生成する多段復号方法において、連続する2つの上記復号処理工程の間のうちの少なくとも1個所に、時間的に異なる入れ替え状態を選択しながら前段の復号処理工程から出力される複数の出力符号系列に対して該出力符号系列間で並列に逆入れ替えを行うことによりデインタリーブを行い、デインターリーブされた複数の出力符号系列を並列に出力する逆入れ替え処理工程を設けることを特徴とする多段復号方法。
7
For multiple input code sequencesCorrect in parallelAdd a bit string to create multiple output code sequencesIn a multi-stage coding apparatus having a plurality of coding processing means for outputting in parallel and sequentially performing correction bit string addition processing by the plurality of coding processing means on an input information series to generate a multi-stage coding series.The output code is used for a plurality of output code sequences output from the coding processing means in the previous stage while selecting temporally different replacement states at at least one of the two consecutive coding processing means. It is characterized in that interleaving is performed by exchanging in parallel between the series, and an exchange processing means for outputting a plurality of interleaved output code sequences in parallel is provided.Multi-stage coding device. 複数の入力符号系列に並列に訂正ビット列を付加して複数の出力符号系列を並列に出力する符号化処理手段を複数備え、入力情報系列に対して順次この複数の符号化処理手段による訂正ビット列付加処理を実施して多段符号化系列を生成する多段符号化装置において、連続する2つの上記符号化処理手段の間のうちの少なくとも1個所に、時間的に異なる入れ替え状態を選択しながら前段の符号化処理手段から出力される複数の出力符号系列に対して該出力符号系列間で並列に入れ替えを行うことによりインタリーブを行い、インタリーブされた複数の出力符号系列を並列に出力する入れ替え処理手段を設けることを特徴とする多段符号化装置。
12
Multiple input code sequencesToeachcorrectionBased on bit stringA plurality of decoding processing means for decoding in parallel and outputting this as a plurality of output code sequences in parallel are provided, and the multi-stage coded sequence is sequentially subjected to the decoding process by the plurality of decoding processing means to generate an output information sequence. In a multi-stage decoding deviceBetween the output code sequences for a plurality of output code sequences output from the decoding processing means in the previous stage while selecting temporally different replacement states at at least one of the two consecutive decoding processing means. It is characterized in that deinterleaving is performed by performing deinterleaving in parallel in parallel, and a deinterleaving processing means for outputting a plurality of deinterleaved output code sequences in parallel is provided.Multi-stage decoding device. 複数の入力符号系列をそれぞれの訂正ビット列に基づいて並列に復号し、これを複数の出力符号系列として並列に出力する復号処理手段を複数備え、多段符号化系列に対して順次この複数の復号処理手段による復号処理を実施して出力情報系列を生成する多段復号装置において、連続する2つの上記復号処理手段の間のうちの少なくとも1個所に、時間的に異なる入れ替え状態を選択しながら前段の復号処理手段から出力される複数の出力符号系列に対して該出力符号系列間で並列に逆入れ替えを行うことによりデインタリーブを行い、デインタリーブされた複数の出力符号系列を並列に出力する逆入れ替え処理手段を設けることを特徴とする多段復号装置。

Independent claims4

209 paragraphs in 1 section, as filed

【0001】

[Technical field to which the invention belongs]

The present invention relates to an information sequence generated in a transmission medium such as the optical cable or a storage medium such as the hard disk device in various information transmission systems using an optical cable or the like or various information processing systems equipped with a hard disk device or the like. It relates to a multi-stage coding method, a multi-stage decoding method, a multi-stage coding device, a multi-stage decoding device, and an information transmission system using these for detecting / correcting (inspecting) an error, and in particular, a product coding process (product decoding process). Information transmission delay, etc., which becomes a problem when error detection / correction capability is improved by performing multiple coding processes (decoding process) represented by articulated coding process (joint decoding process). It is related to the improvement to effectively suppress the above and enable higher speed information transmission.

【0002】

[Conventional technology]

Conventionally, a technique for performing this kind of coding process multiple times is disclosed in "Code Theory" (written by Hideki Imai, Institute of Electronics, Information and Communication Engineers, published in 1990) and Japanese Patent Application Laid-Open No. 10-190486. FIG. 6 is a block diagram showing a configuration of a conventional information transmission system that sequentially transmits an information sequence while performing coding processing and decoding processing a plurality of times. In the figure, 29 is a concatenated coding device, 30 is a concatenated decoding device, and 3 is a transmission medium connected between them.

【0003】

In the concatenated coding device 29, 31 is an information sequence input circuit into which an input information sequence is input, 32 is a Reed-Solomon external coding circuit that encodes an input information sequence, and 33 is an interleave that sequentially stores a plurality of external coding sequences. Memory, 34 is an address generation circuit that controls writing and reading to this interleaved memory 33, 35 is a Reed-Solomon internal coding circuit that further encodes the read code sequence, and 36 is an output connection of the internal coding series. This is a concatenated coded sequence output circuit that outputs to the transmission medium 3 as a coded sequence.

【0004】

In the concatenated decoding device 30, 37 is a reed-Solomon decoding circuit that decodes an input concatenated coding sequence, 38 is a reed-Solomon decoding circuit that decodes an input concatenated coding sequence, and 39 sequentially stores a plurality of internal decoding sequences. 40 is an address generation circuit that controls writing and reading to this deinterleaved memory 39, 41 is a Reed-Solomon external decoding circuit that further decodes the read decoding sequence, and 42 outputs an external decoding sequence. It is an information series output circuit that outputs as an information series.

【0005】

Next, the operation will be described. When an input information sequence is input to the information sequence input circuit 31, the Reed-Solomon external coding circuit 32 encodes the input information sequence and sequentially stores the input information sequence in the interleave memory 33. Then, when a predetermined number of externally coded sequences are written, the address generation circuit 34 outputs all the data in an order different from the writing order. The Reed-Solomon internal coding circuit 35 further encodes the read data, and the concatenated coding series output circuit 36 outputs the internal coding series to the transmission medium 3 as an output concatenated coding series.

【0006】

When the input concatenated coding sequence is input from the transmission medium 3 to the concatenated coding sequence input circuit 37, the decoding circuit 38 in the Reed-Solomon decodes the input concatenated coding sequence and sequentially stores the decoding in the deinterleaved memory 39. Then, when a predetermined number of decoding sequences are written, the address generation circuit 40 outputs all the data in an order different from the writing order. The Reed-Solomon external decoding circuit 41 further decodes this read data, and the information sequence output circuit 42 outputs this external decoding sequence as an output information sequence.

【0007】

Then, in such a conventional information transmission system, an information sequence is sequentially input to the concatenated coding device 29, converted into a concatenated code sequence, and then transmitted to the concatenated decoding device 30 via the transmission medium 3, and further. By decoding with this concatenated decoding device 30, the above information series can be transmitted while detecting / correcting the error.

【0008】

[Problems to be Solved by the Invention]

Since the conventional information transmission system is configured as described above, for example, when the concatenated coding device 29 is described as an example, the external coding sequence output from the Reed-Solomon external coding circuit 32 is sequentially stored in the interleaved memory 33. Then, when a predetermined number is stored, it is read out in order from a direction different from this storage order, so that the coding directions in the two coding circuits 32 and 35 are different, which in turn causes a high error due to several coding processes. Since the detection / correction capability is exerted, an interleaved memory 33 having a capacity capable of storing the predetermined number of output code sequences is always required, and the accumulation in the interleaved memory 33 is always completed. Since the next read cannot be performed until after that, there is a problem that the delay time during that period becomes very long.

【0009】

FIG. 7 is a format diagram for explaining the writing and reading operations of the conventional information transmission system to the interleaved memory 33. In the figure, the outer-coded series is stored in order from the left column to the right, and when the last outer-coded series is stored in the right end, the reading is performed in order from the upper row. When such an interleaved memory 33 is used, the read process cannot be performed until the externally coded sequence is stored from the left end to the right end, and the read of the bottom line is not completed. Since writing cannot be performed, a delay time will occur accordingly. Further, FIG. 8 is a format diagram when one externally coded sequence extends over a plurality of lines of the interleaved memory 33.

【0010】

In particular, as the number of coding circuits 32 and 35 increases, the total storage capacity of the memory 33 and the total delay time increase in a substantially proportional relationship, and information cannot be transmitted at a speed exceeding the delay time. , There was naturally a limit to improving the transmission speed of information while ensuring the reliability of the transmitted information.

【0011】

The concatenated decoding device 30 also has the same problem.

【0012】

The present invention has been made to solve the above-mentioned problems, and while performing coding processing (decoding processing) in which the coding directions are different from each other a plurality of times, the delay time in the conventional information transmission system is longer than that in the above-mentioned conventional information transmission system. The multi-stage processing can be performed with a short delay time, and information can be transmitted at a higher speed than the conventional information transmission system while ensuring the same reliability of transmission information as the conventional information transmission system. It is an object of the present invention to obtain a multi-stage coding method, a multi-stage decoding method, a multi-stage coding device, a multi-stage decoding device, and an information transmission system using these.

【0013】

[Means for solving problems]

The multi-stage coding method according to the present invention ispluralFor input code sequenceCorrect in parallelAdd a bit stringpluralOutput code sequenceIn parallelIn a multi-stage coding method in which a plurality of coding processing steps for output are provided, and the coding processing steps are sequentially performed a plurality of times for an input information series to generate a multi-stage coding series., CommunicatingTwo to followthe aboveAt least one of the coding processesWhile selecting the replacement state that differs in timeMultiple output code sequences output from the coding process in the previous stageIn parallel between the output code sequencesSwapIs performed to perform interleaving, and a plurality of interleaved output code sequences are output in parallel.A replacement process is provided.

【0014】

In the multi-stage coding method according to the present invention, all the coding processing steps are performed in parallel for the same number of input code sequences.correctionBit string addition processing is performed, all replacement processing steps are provided between two consecutive coding processing steps, and all the replacement processing steps are the number of parallel input code sequences input to the above coding processing steps. The exchange processing is performed between the same number of output code sequences as.

【0015】

In the multi-stage coding method according to the present invention, the replacement processing step counts up to the value obtained by dividing the number of bits or symbols of the input output code series by the unit of the replacement processing, and each count value has a different replacement state. It will be.

【0016】

The multi-stage decoding method according to the present inventionpluralInput code sequenceToeachcorrectionBased on bit stringIn parallelDecrypt and do thispluralAs an output code sequenceIn parallelIn a multi-stage decoding method in which a plurality of output decoding processing steps are provided and the multi-stage coding sequence is sequentially subjected to the plurality of decoding processing steps to generate an output information sequence., CommunicatingTwo to followthe aboveAt least one location during the decryption processWhile selecting the replacement state that differs in timeMultiple output code sequences output from the decoding process in the previous stageIn parallel between the output code sequencesReverse replacementBy doingDeinterleaveAnd output multiple deinterleaved output code sequences in parallelA reverse replacement process is provided.

【0017】

In the multi-stage decoding method according to the present invention, all the decoding processing steps perform decoding processing in parallel for the same number of input code sequences, and a reverse replacement processing step is provided between two consecutive decoding processing steps. In all of the reverse replacement processing steps, reverse replacement processing is performed between the number of parallel input code sequences input to the decoding processing step and the same number of output code sequences.

【0018】

In the multi-stage decoding method according to the present invention, the reverse replacement processing step counts up to the value obtained by dividing the number of bits or symbols of the input output code series by the unit of the reverse replacement processing, and the reverse replacement is different for each count value. It is a state.

【0019】

The multi-stage coding device according to the present invention has a plurality of input code sequences.Correct in parallelAdd a bit string to create multiple output code sequencesIn a multi-stage coding apparatus which is provided with a plurality of coding processing means for outputting in parallel and sequentially performs correction bit string addition processing by the plurality of coding processing means to generate a multi-stage coding series, the input information series is continuous. Between the output code sequences for a plurality of output code sequences output from the coding processing means in the previous stage while selecting temporally different replacement states at at least one of the two coding processing means. Interleave is performed by exchanging in parallel with, and an exchange processing means for outputting a plurality of interleaved output code sequences in parallel is provided.It is a thing.

【0020】

In the multi-stage coding apparatus according to the present invention, the number of input code sequences input to all the coding processing means and the number of input code sequences input to all the replacement processing means are the same.

【0021】

In the multi-stage coding apparatus according to the present invention, the replacement processing means is provided with a replacement counter that counts the number of bits or symbols of the input code sequence up to the value divided by the unit of the replacement process, and the same number as the number of the input code series. It is provided with a replacement selector in which all input code sequences are input and one input code sequence is selected according to the count value of the replacement counter and output as an output code sequence.

【0022】

The multi-stage coding device according to the present invention, EnterThe replacement selector selects the same input code sequence for the same number of switching times as the number of input code sequences.

【0023】

In the multi-stage coding apparatus according to the present invention, all coding processing means are based on the Reed-Solomon coding method.correctionIt adds a bit string.

【0024】

The multi-stage decoding device according to the present invention has a plurality of input code sequences.ToeachcorrectionBased on bit stringA plurality of decoding processing means for decoding in parallel and outputting this as a plurality of output code sequences in parallel are provided, and the multi-stage coded series is sequentially subjected to the decoding processing by the plurality of decoding processing means to generate an output information sequence. For a plurality of output code sequences output from the previous-stage decoding processing means while selecting temporally different replacement states at at least one of the two consecutive decoding processing means. Deinterleaving is performed by performing reverse swapping in parallel between the output code sequences, and a reverse swapping processing means for outputting a plurality of deinterleaved output code sequences in parallel is provided.It is a thing.

【0025】

In the multi-stage decoding apparatus according to the present invention, the number of input code sequences input to all decoding processing means and the number of input code sequences input to all reverse replacement processing means are the same.

【0026】

In the multi-stage decoding device according to the present invention, the reverse replacement processing means counts up to the value obtained by dividing the number of bits or symbols of the input code sequence by the unit of the replacement process, and the number of reverse replacement counters is the same as the number of input code sequences. It is provided with a reverse replacement selector in which all input code sequences are input and one input code sequence is selected according to the count value of the reverse replacement counter and output as an output code sequence.

【0027】

The multi-stage decoding device according to the present invention, ConverseThe replacement selector selects the same input code sequence for the same number of switching times as the number of input code sequences.

【0028】

In the multi-stage decoding apparatus according to the present invention, all decoding processing means perform decoding processing based on the Reed-Solomon coding method.

【0029】

In the multi-stage decoding apparatus according to the present invention, at least one re-decoding processing means that performs the same decoding processing as any of the decoding processing means is arranged at a position other than immediately after the decoding processing means, and the decoding processing means is described above. A re-replacement processing means arranged between the and the re-decoding processing means, which generates a code sequence in a coding state similar to the input code sequence input to the decoding processing means and outputs the code sequence to the re-decoding processing means. Provided and further used in the above decoding processing meanscorrectionThe bit string is transmitted to the re-decoding processing means.

【0030】

The multi-stage decoding device according to the present invention uses all decoding processing means.correctionSum of the number of error bits or the number of error symbolsCalculationIt is provided with an error number estimation circuit.

【0031】

The information transmission system according to the present invention includes the above-mentioned multi-stage coding device, the above-mentioned multi-stage decoding device, and a transmission medium for transmitting the multi-stage coding series of the above-mentioned multi-stage coding device to the above-mentioned multi-stage decoding device. ..

【0032】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described. Embodiment 1. FIG. 1 is a block diagram showing a configuration of an information transmission system according to a first embodiment of the present invention. In the figure, 1 is a concatenated coding device (multi-stage coding device) in which an input information series consisting of a plurality of information symbols is sequentially input, and an output concatenated coding series is generated and output based on this input information series. Is a concatenated decoding device (multi-stage decoding device) in which input concatenated coding sequences are sequentially input and an output information sequence is generated and output based on this input concatenated coding sequence, and 3 is a concatenated coding device 1 and a concatenated decoding device. It is a transmission medium such as an optical fiber that is connected to 2 and transmits the output concatenated coding sequence output by the concatenated coding device 1 to the concatenated decoding device 2 and outputs it as an input concatenated coding sequence.

【0033】

In the concatenated coding device 1, 4 is an information sequence input circuit that parallelizes L (L is an integer) of input information sequences and outputs L parallel input information sequences in synchronization at the same time, and 5 is an L that operates in the same manner. Equipped with Reed-Solomon coding circuits, each of these L Reed-Solomon coding circuits simultaneously performs coding processing for each parallel input information sequence and outputs L external coding sequences of the same code length. Coding circuit (coding processing means, coding processing process), 6 has L input units and L output units, and each time a new symbol of the external coding series is input, each input unit An interleave circuit (replacement process) that performs interleaving by switching by switching the connection with each output unit and outputs the L interleaved coded sequences obtained by interleaving the above L external coded sequences for each new symbol input. Means, replacement processing step), 7 is equipped with L Reed-Solomon coding circuits that perform the same operation, and these L Reed-Solomon coding circuits simultaneously perform coding processing for each interleaved coding series and have the same code. An internal coding circuit (coding processing means, coding processing step) that outputs L internal coding series of length, 8 transmits this L internal coding series as L output concatenated coding series. It is a concatenated coded series output circuit that sequentially outputs to the medium 3.

【0034】

In the concatenated decoding device 2, 9 is a concatenated coding sequence input circuit that parallelizes L (L is an integer) of input concatenated coding sequences and outputs L parallel input concatenated coding sequences in synchronization at the same time. Equipped with L Reed-Solomon decoding circuits that perform the same operation, each of these L Reed-Solomon decoding circuits simultaneously performs decoding processing of each parallel input concatenated coding series, and L internal decoding series of the same code length are obtained. The internal decoding circuit (decoding processing means, decoding processing process) that outputs, 11 has L input units and L output units, and each time a new symbol of the internal decoding series is input, each input unit and each A deinterleaved circuit that outputs the L deinterleaved decoding series by switching the connection with the output unit to perform deinterleaving by switching and deinterleaving the above L deinterleaved sequences each time a new symbol is input. (Reverse replacement processing means, reverse replacement processing step), 12 is provided with L Reed-Solomon decoding circuits that perform the same operation, and these L Reed-Solomon decoding circuits simultaneously perform decoding processing of each deinterleaved decoding series and are the same. An external decoding circuit (decoding processing means, decoding processing step) that outputs L external decoding sequences of code length, and 13 is an information sequence output circuit that sequentially outputs these L external decoding sequences as L information sequences. Reference numeral 14 denotes an error number estimation circuit that calculates the sum of all the error bits corrected in the entire Reed-Solomon decoding circuit, estimates this value as the error number, and outputs it.

【0035】

FIG. 2 is a block diagram showing an internal configuration of the interleave circuit 6 according to the first embodiment of the present invention. In the figure, 15 counts up to the same number as the value obtained by dividing the number of symbols in the externally coded series by the number of parallel input symbols, and each time a new symbol in the externally coded series is input, select switching is provided with the count value information at that time. L external coded sequences are input to each of the counters (replacement counters) and 16 that output signals, and one external code that is fixedly assigned to that value according to the count value information of the select switching signal. There are L selectors (replacement selectors) that select a conversion series and output it as an interleaved coding series. The deinterleaved circuit 11 has the same internal configuration.

【0036】

Next, the operation will be described. When an input information sequence is input to the concatenated coding device 1, the information sequence input circuit 4 parallelizes the input information sequence by L, synchronizes the L parallel input information sequence at the same time, and outputs one symbol at a time. In the external coding circuit 5, L Reed-Solomon coding circuits simultaneously perform coding processing for each parallel input information series each time the symbol is input, and finally at the end of each parallel input information series. Outputs L external coded sequences with external error correction bit strings added. When a new symbol is input to the interleaving circuit 6, the counter 15 outputs a new count value, and each of the selectors 16, ..., 16 selects a predetermined external coding sequence accordingly. Output as an interleaved coded sequence. The L selectors 16, ..., 16 are set to select different externally coded sequences at the input timing of each symbol. The internal coding circuit 7 performs further coding processing of each interleaved coding series at the same time each time a symbol is input by the L Reed-Solomon coding circuits, and finally at the end of each of the above interleaved coding series. Outputs L internal coded sequences with internal error correction bit strings added. Then, the articulated coded sequence output circuit 8 sequentially outputs the L internal coded sequences to the transmission medium 3 as L output articulated coded sequences.

【0037】

When an input concatenated coding sequence is input from the transmission medium 3, the concatenated coding sequence input circuit 9 of the concatenated decoding device 2 parallelizes this input concatenated coding sequence by L and L parallel input concatenated coding sequences. Are synchronized at the same time and output one symbol at a time. In the internal decoding circuit 10, each time the above symbols are input, the L Reed-Solomon decoding circuits simultaneously perform decoding processing of each parallel input concatenated coding series, and finally the bit error is corrected by the internal error correction bit string. Outputs L decoding sequences at a time. The decoding sequence is the same as the interleaved coding sequence, assuming that there are no errors in the transmission medium 3 or the like. When a new symbol is input to the deinterleave circuit 11, the counter 15 outputs a new count value, and each of the selectors 16, ..., 16 selects a predetermined internal decoding sequence accordingly. Output as a deinterleaved decoding series. The L selectors 16, ..., 16 are set to select different internal decoding series at the input timing of each symbol. This deinterleaved decoding sequence is the same sequence as the above-mentioned externally coded sequence, assuming that there are no errors in the transmission medium 3 or the like. The external decoding circuit 12 performs further decoding processing of each deinterleaved decoding series at the same time each time the L Reed-Solomon decoding circuits input a symbol, and finally the external error correction bit string corrects the bit error. Outputs L decoding sequences at a time. This external decoding sequence is the same sequence as the parallel input information sequence, assuming that there are no errors in the transmission path 3 or the like. Then, the information sequence output circuit 13 sequentially outputs the L external decoding sequences as the L output information sequences.

【0038】

Further, the error number estimation circuit 14 calculates the sum total of all the error bits corrected in the entire Reed-Solomon decoding circuit, estimates this value as the error number, and outputs it. The number of errors is an index indicating the transmission state of the transmission medium 3, and can be used to optimize, for example, the amplification factor of the receiving amplifier.

【0039】

FIG. 3A is a format diagram for explaining in detail the concatenated coding process in the information transmission system according to the first embodiment of the present invention. In the figure, # 1, ..., #L are the numbers of the parallel input information series processed at the same time, 223 symbols from the left end are the symbol strings of the parallel input information series, 224 to 239 are the external error correction bit strings, and 240 to 255. Up to the symbol means an internal error correction bit string. That is, the outer coded sequence has a Reed-Solomon code having a code length of 239 bytes and information of 223 bytes, and the inner coded series has a code length of 255 bytes and information of 239 bytes. Then, each parallel input information sequence is input as it is to each Reed-Solomon coding circuit of the external coding circuit 5, and an external coding sequence to which an external error correction bit string is added is output. One of the externally coded sequences corresponds to the arrow 17 in the figure. Further, when this outer coded sequence is interleaved so as to periodically select it in order, the symbol of each outer coded sequence is sequentially switched and input to each Reed-Solomon coding circuit of the inner coding circuit 7. The internal coded sequence to which the internal error correction bit string is added is output. One of the coded sequences corresponds to the arrow 18 in the figure. As is clear from the figure, the coding direction of the outer coding series and the coding direction of the inner coding series are different.

【0040】

FIG. 3B is a format diagram when the same contents as in FIG. 3A are viewed in the output concatenated coding series output to the transmission medium 3. Then, for example, if it is considered that each line in the figure is output to the transmission medium 3 in order, as shown in the figure, all the symbols of each internal coded sequence are output in succession. , Each external coded sequence, that is, each symbol of each information sequence and each external error correction bit string is output to the transmission medium 3 in a discrete state, whereby an error is detected for a single bit error or burst error. / It turns out that correction is possible. In addition, block code processing is performed for each L symbol.

【0041】

The counters of each Reed-Solomon coding circuit and each Reed-Solomon decoding circuit count up to the same value as the code length of the series input to each. Further, the selector operates so as to select the same input unit for each of the parallel number L.

【0042】

As described above, according to the first embodiment, the external coding circuit 5 that simultaneously adds an error correction bit string to the L parallel input information sequences and outputs the L external coding sequences, and the L external coding circuits 5 Interleave circuit 6 that performs interleaving by swapping the outer coded sequence and outputs the same number of interleaved code sequences, and L interleaved code sequences with internal error correction bit strings added at the same time to create L internal coded sequences. Equipped with an internal coding circuit 7 to output, error correction code addition processing by the external coding circuit 5 and the internal coding circuit 7 is performed on the parallel input information series, and replacement processing is performed by the interleaving circuit 6 in the meantime. Since the output concatenated coding sequence is generated, the processing capacity of the outer coding circuit 5 and the inner coding circuit 7 is multiplied by L, and the L outer coding sequences output from the outer coding circuit 5 are replaced. Is input to the internal coding circuit 7 by interleaving by.

【0043】

Therefore, not only the processing capacity in each of the coding circuits 5 and 7 is increased by L times, but also L pieces are directly transferred from the outer coding circuit 5 to the inner coding circuit 7 without accumulating L outer coding sequences. Since the externally coded sequence can be transmitted and the delay time there can be significantly reduced, it is significantly compared to the conventional one in which the externally coded sequence is sequentially stored in the interleaved memory and then read. The information transmission speed will be improved, and the total delay time will be significantly reduced. In addition, no memory is required for interleaving processing.

【0044】

Therefore, while ensuring the reliability of the transmitted information as before by executing the coding process twice while performing the interleaved process in the middle, the delay time and the memory used are significantly higher than those of the conventional one. It is possible to reduce the capacity, and by extension, it is possible to transmit information at a transmission speed that cannot be realized in the past while ensuring the reliability of the transmitted information.

【0045】

According to the first embodiment, the number of code sequences processed simultaneously by the outer coding circuit 5, the inner coding circuit 7, and the interleaving circuit 6 is unified to L, so that, for example, some codes are processed at the same time. There is no total information transmission speed bottleneck that occurs when the number of parallel series is reduced, and the throughput of the entire two-stage coding process can be improved by at least L times. There is an effect that it is possible to realize a very high coding processing speed several times higher than the conventional one.

【0046】

According to the first embodiment, the interleaving circuit 6 inputs a counter 15 that counts up to the number of bits or symbols of the externally coded sequence, and all the externally coded sequences are input and responds to the count value of the counter 15. Since it is equipped with L selectors 16, ..., 16 that select one outer coding series and output it as an interleaved code series, the inner coding circuit 7 blocks the code length of the outer coding series as a unit. There is an effect that the coding process can be performed.

【0047】

According to the first embodiment, since the L selectors 16, ..., 16 select the same outer coding series for each L symbol, the inner coding circuit 7 periodically uses the maximum count value as a unit. There is an effect that various block interleaving processes can be performed.

【0048】

According to the first embodiment, since both the outer coding circuit 5 and the inner coding circuit 7 add an error correction code based on the Reed-Solomon coding method, the symbols (bytes) are added under this Reed-Solomon coding method. ) Each coding process can be performed, and parallel processing can be performed efficiently with a simpler configuration than when a check bit string is added based on other BCH (Bose-Chaudhuri-Hocquenghem) coding methods. There is an effect that can be done.

【0049】

According to the first embodiment, the internal decoding circuit 10 that simultaneously performs decoding processing on L parallel input concatenated code sequences based on each error correction bit string and outputs L internal decoding sequences, and The deinterleaved circuit 11 that performs deinterleaving by reverse replacement and outputs L deinterleaved decoding sequences and the L deinterleaved decoding sequences are simultaneously subjected to decoding processing based on their respective error correction bit strings. An external decoding circuit 12 that outputs an number of external decoding sequences is provided, and the multiple decoding processing steps are sequentially performed on the input concatenated coding series, and the reverse replacement processing by the deinterleaved circuit 11 is performed between them. Since the external decoding series is generated, the processing capacity of the internal decoding circuit 10 and the external decoding circuit 12 is multiplied by L, and the L internal decoding series output from the internal decoding circuit 10 are deinterleaved by reverse replacement. It is input to the decoding circuit 12.

【0050】

Therefore, not only the processing capacity of the internal decoding circuit 10 and the external decoding circuit 12 is multiplied by L, but also the L internal decoding sequences are directly transmitted from the internal decoding circuit 10 to the external decoding circuit 12 without accumulating them. Since the delay time can be significantly reduced, the information transmission speed is significantly improved compared to the conventional one in which the internal decoding series is sequentially stored in the deinterleaved memory and then read out, resulting in a total. The delay time will be significantly reduced. In addition, no memory is required for deinterleaved processing.

【0051】

Therefore, while ensuring the reliability of the transmitted information as before by executing the decryption process twice while performing the deinterleaved process in the middle, the delay time and the memory used are significantly higher than those of the conventional one. It is possible to reduce the capacity, and by extension, it is possible to transmit information at a transmission speed that cannot be realized in the past while ensuring the reliability of the transmitted information.

【0052】

According to the first embodiment, since the code sequences processed in parallel by the inner decoding circuit 10, the deinterputing circuit 11, and the outer decoding circuit 12 are unified into L, for example, the number of parallels is partially increased. Since there is no bottleneck in the total information transmission speed that occurs when the information is reduced, the throughput of the entire multi-stage decoding process can be improved by at least the number of parallel processes, which is several times higher than before. There is an effect that a high decoding processing speed can be realized.

【0053】

According to the first embodiment, the deinterleaved circuit 11 inputs a counter 15 that counts up to the number of bits or symbols of the internal decoding series, and all the internal decoding series are input and according to the count value of the counter 15. Since it is equipped with L selectors 16, ..., 16 that select one internal decoding series and output it as a deinterleaved decoding series, for example, the external decoding circuit 12 blocks the internal decoding series in units of the maximum count value. There is an effect that the processing can be carried out.

【0054】

According to the first embodiment, since the L selectors 16, ..., 16 select the same internal decoding series for each L bit or symbol, the external decoding circuit 12 is periodic with the above L as a unit. There is an effect that block deinterleave processing can be performed.

【0055】

According to the first embodiment, since both the inner decoding circuit 10 and the outer decoding circuit 12 perform the decoding process based on the Reed-Solomon coding method, the byte-by-byte decoding process is performed under this Reed-Solomon coding method. This can be performed, and there is an effect that parallel processing can be efficiently performed with a simpler configuration than other BCH (Bose-Chaudhuri-Hocquenghem) code decoding methods.

【0056】

According to the first embodiment, the above-described concatenated coding device 1, the above-mentioned concatenated decoding device 2, and a transmission medium 3 connected between them are provided, and a plurality of the above-mentioned concatenated coding devices 1 are provided. Since the coding circuits 5 and 7 and the interleaving circuit 6 and the plurality of decoding circuits 10 and 12 and the deinterleaved circuit 11 of the articulated decoding device 2 are arranged so as to be line-symmetrical with the transmission medium 3 as the axis of symmetry. While ensuring the reliability of transmitted information as in the past, it is possible to significantly reduce the delay time and memory capacity used compared to the conventional one, and by extension, it has been realized in the past while ensuring the reliability of the transmitted information. There is an effect that information can be transmitted at a transmission speed that cannot be achieved.

【0057】

Embodiment 2. FIG. 4 is a block diagram showing a configuration of an information transmission system according to Embodiment 2 of the present invention. In the figure, 19 is provided between the information series input circuit 4 and the external coding circuit 5, has L input units and L output units, and a new symbol of the parallel input information series is input. Interleaving is performed by switching by switching the connection between each input unit and each output unit each time, and the L interleaved information series obtained by interleaving the above L parallel input information series for each new symbol input are output. It is an interleaved circuit (replacement processing means, replacement processing process), and these L interleaved information sequences are input to the external coding circuit 5. Further, 20 is provided between the external decoding circuit 12 and the information series output circuit 13, and includes L input units and L output units, and each time a new symbol of the external decoding series is input. By switching the connection between the input unit and each output unit, deinterleaving is performed by switching, and the L deinterleaved decoding information series obtained by deinterleaving the above L external decoding series for each input of a new symbol are output. This is a deinterleaved circuit (reverse replacement processing means, reverse replacement processing step), and the L deinterleaved decoding information sequences are input to the information sequence output circuit 13. The internal configurations of the interleaving circuit 19 and the deinterleaving circuit 20 are the same as those in FIG. The configuration other than this is the same as that of the first embodiment, and the description thereof will be omitted.

【0058】

Next, the operation will be described. When L parallel input information sequences from the information sequence input circuit 4 are simultaneously output one symbol at a time, the counter 15 of the interleave circuit 19 outputs a new count value, and each selector 16, ..., 16 Selects a predetermined parallel input information sequence according to this and outputs it to the external coding circuit 5 as an interleaved information sequence. The L selectors 16, ..., 16 are set to select different externally coded sequences at each timing.

【0059】

When L external decoding sequences are output from the external decoding circuit 12, the counter outputs a new count value each time a new symbol is input in the deinterleaved circuit 20, and each selector 16, ..., 16 selects a predetermined external decoding sequence accordingly and outputs it to the information sequence output circuit 13 as a deinterleaved decoding information sequence. The L selectors 16, ..., 16 are set to select different external decoding sequences at each timing. This deinterleaved decoding information sequence is the same sequence as the parallel input information sequence, assuming that there are no errors in the transmission medium 3 or the like. The operations other than this are the same as those in the first embodiment, and the description thereof will be omitted.

【0060】

With such a configuration, not only the coding direction of the outer coding series and the coding direction of the inner coding series are different, but also the coding direction of the outer coding series and the information series with respect to the information series. The coding direction of the inner coding series can be set to any direction, and the coding direction of the outer coding series and the coding direction of the inner coding series can be made orthogonal to each other. It is possible to carry out the same error correction as in the case of using.

【0061】

Embodiment 3. FIG. 5 is a block diagram showing a configuration of an information transmission system according to Embodiment 3 of the present invention. In the figure, reference numeral 21 denotes an internal decoding circuit (decoding process) that performs the same decoding process as the internal decoding circuit 10 of the first embodiment using the internal error correction code, outputs an internal decoding series, and outputs an internal error correction bit string. Means, decoding processing step), 22 performs the same deinterleaving process as the deinterleaving circuit 11 of the first embodiment on the internal decoding sequence to output the deinterleaved decoding sequence, and the above internal error correction bit string is passed through. The deinterleaved circuit (replacement processing means, replacement processing step) to be caused 23 performs the same decoding process as the external decoding circuit 12 of the first embodiment using the external error correction bit string for the deinterleaved decoding series. An external decoding circuit (decoding processing means, decoding processing step) that outputs a decoding sequence and outputs the above internal error correction bit string and external error correction bit string, 24 is a concatenated coding device for the external decoding series and the external error correction bit string. A re-interleaved circuit (re-replacement processing means) that performs the same interleaving processing as the interleaving circuit 6 of the above, outputs a regenerated interleaved coding sequence, and passes through an internal error correction bit string, and 25 is an internal replay interleaving coding sequence. A re-internal decoding circuit (re-decoding processing means) that performs the same decoding process as the internal decoding circuit 21 using an error correction bit string and outputs a reproduction internal decoding sequence, and 26 is the above-mentioned deinterleave with respect to the reproduction internal decoding series. A re-deinterleaved circuit (re-replacement processing means) that performs the same deinterleave processing as circuit 22 and outputs a replay deinterleaved decoding sequence, and 27 uses an external error correction bit string for the replay deinterleaved decoding sequence. A re-external decoding circuit (re-decoding processing means) that performs the same decoding process as the decoding circuit 23 and outputs the non-reproduced decoding sequence to the information series output circuit 13, and 28 is all the error bits corrected in the entire read solomon decoding circuit. It is an error number estimation circuit that calculates the total number of numbers, estimates this value as the number of errors, and outputs it. The configuration other than this is the same as that of the first embodiment, and the description thereof will be omitted.

【0062】

Next, the operation will be described. When a parallel input concatenated coding sequence is input from the concatenated coding sequence input circuit 9, the internal decoding circuit 21 performs decoding processing using the internal error correction bit string and outputs the internal decoding sequence and the internal error correction bit string. .. The deinterleaved circuit 22 deinterleaves the internal decoding sequence and passes through the internal error correction bit string, and the external decoding circuit 23 decodes the internal decoding sequence using the external error correction bit string and corrects the internal error together with the external decoding sequence. Outputs a bit string and an external error correction bit string. Then, if no error occurs in the transmission medium 3 or the like, this external decoding sequence is the same as the input information sequence.

【0063】

The reinterleaved circuit 24 interleaves the external decoding sequence and the external error correction bit string again to output a reproduction interleaved coding sequence and passes through the internal error correction bit string, and the reinternal decoding circuit 25 uses the internal error correction bit string. The reproduction interleaved coding sequence is decoded and output, the re-deinterleaved circuit 26 deinterleaves the reproduction in-reproduction decoding sequence, and the re-external decoding circuit 27 decodes the reproduction deinterleaved decoding sequence and outputs the reproduction outside decoding sequence. Then, these series of decoding sequences are the same as the above-mentioned respective decoding sequences as long as there is no error in the transmission medium 3 or the like. Further, although some bit errors are corrected as a result of the first internal decoding process and external decoding process, the result of the external decoding process is not appropriate as a result of the internal decoding process. In some cases, the internal decoding process is performed again, so even such an error can be corrected and more appropriately decoded.

【0064】

With such a configuration, the internal error correction bit string used in the internal decoding circuit 21 is transmitted to the re-internal decoding circuit 25 and used for the second error correction. Similarly, the external error correction bit string used in the external decoding circuit 23 is transmitted to the re-external decoding circuit 27 and used for the second error correction. Therefore, even if a bit error occurs in the input concatenated coding sequence and the error cannot be completely removed at one time, a more probable information sequence can be obtained by repeating the external decoding and the internal decoding again. be able to.

【0065】

In this embodiment, the internal error correction bit string is passed through in the reinterleaving circuit 24 or the like, but interleaving may be performed here. That is, in any case, it is sufficient that the error correction bit string is correctly reproduced when used in the reinternal decoding circuit 25 and the reexternal decoding circuit 27. In particular, if the deinterleaved circuit 22 and the reinterleaved circuit 24 are in a relationship of performing completely opposite replacement processing, the respective error correction bit strings are re-decoded by the respective re-decoding circuits 25, without performing special processing such as the above-mentioned through processing. Can be entered appropriately in 27.

【0066】

As described above, according to the third embodiment, the re-interleaved circuit 24, the re-internal decoding circuit 25, the re-deinterleaved circuit 26, and the re-external decoding circuit 27 are provided after the external decoding circuit 23, and the internal decoding circuit is provided. Since the error correction bit string is transmitted from 21 to the re-internal decoding circuit 25 and from the external decoding circuit 23 to the re-external decoding circuit 27, when the result of the external decoding process is an inappropriate decoding sequence as a result of the internal decoding process. Or, if an inappropriate decoding sequence is obtained as a result of the external decoding process as a result of the reinternal decoding process, this can be corrected by the reinternal decoding circuit 25 and the external decoding circuit 27, so that more appropriate decoding can be performed. It can be a series. That is, there is an effect that the data reliability of the received information series can be further improved.

【0067】

According to the third embodiment, the total number of error bits corrected by the internal decoding circuit 21, the external decoding circuit 23, the re-internal decoding circuit 25, and the re-external decoding circuit 27 is the total number of error bits generated on the transmission medium 3. Since the error number estimation circuit 28 to be estimated is provided, error correction in the reinner decoding circuit 25 and the re-outer decoding circuit 27 can be considered in particular, and the number of bit errors included in the received concatenated coding series can be more accurately determined. Has the effect of being able to detect / correct.

【0068】

In the above embodiment, an example in which two Reed-Solomon codes are combined has been described, but the same applies to other codes such as a BCH code, a block code, and a convolutional code having a limited code length. The effect can be obtained. In addition, the combination and the number of stages are arbitrary.

【0069】

Further, in the above-described embodiment, an example in which decoding is repeated twice in the concatenated decoding device 2 has been shown, but the number of repetitions of this decoding process is arbitrary. In particular, in the present invention, the delay time in the deinterleaved circuit 11 and the like can be remarkably reduced, so that even if such a repeating technique is used, the processing can be performed with a delay time comparable to that of the conventional one. Both high-speed processing and high reliability can be achieved at a level that could not be obtained.

【0070】

Further, although the error number estimation circuit exemplifies the one that calculates the total number of error bits, it may also calculate the total number of error symbols.

【0071】

[Effect of the invention]

As described above, according to the present invention.pluralFor input code sequenceCorrect in parallelAdd a bit stringpluralOutput code sequenceIn parallelIn a multi-stage coding method in which a plurality of coding processing steps for output are provided, and the coding processing steps are sequentially performed a plurality of times for an input information series to generate a multi-stage coding series., CommunicatingTwo to followthe aboveAt least one of the coding processesWhile selecting the replacement state that differs in timeMultiple output code sequences output from the coding process in the previous stageIn parallel between the output code sequencesSwapIs performed to perform interleaving, and a plurality of interleaved output code sequences are output in parallel.Since the replacement processing step is provided, the processing capacity in each coding processing step is more than doubled, and at least one of the two consecutive coding processing steps is output from the coding processing step. The output code sequence of is input to the subsequent coding process by interleaving by replacement.

【0072】

Therefore, not only the processing capacity in each coding processing step is more than doubled, but also the coding processing in the first stage to the subsequent coding processing directly without accumulating a plurality of output code sequences at at least one place. Since multiple output code sequences can be transmitted to the process and the delay time there can be significantly reduced, the output code sequences are sequentially stored in the interleaved memory and then read out, which is significantly compared to the conventional one. The information transmission speed will be improved, and the total delay time will be significantly reduced. Similarly, the total memory storage capacity will be significantly reduced.

【0073】

Therefore, while ensuring the reliability of the transmitted information as in the past by executing the coding process multiple times while performing interleave processing in the middle, the delay time and the memory used are significantly higher than those of the conventional one. It is possible to reduce the capacity, and by extension, it is possible to transmit information at a transmission speed that cannot be realized in the past while ensuring the reliability of the transmitted information.

【0074】

According to the present invention, all coding processing steps are performed in parallel for the same number of input code sequences.correctionBit string addition processing is performed, all replacement processing steps are provided between two consecutive coding processing steps, and all the replacement processing steps are the number of parallel input code sequences input to the above coding processing steps. Since the exchange processing is performed between the same number of output code sequences as the above, the bottleneck of the total information transmission speed that occurs when the number of parallels is reduced in some parts does not occur, so that the coding processing is performed in multiple stages. The throughput of the entire process can be improved by at least the number of parallel processes, and there is an effect that a very high coding processing speed several times higher than that of the conventional one can be realized.

【0075】

According to the present invention, the replacement processing step counts up to the value obtained by dividing the number of bits or symbols of the input output code series by the unit of the replacement processing, and each count value is in a different replacement state. Assuming that the unit of the above replacement processing is n symbols (n is an integer), the subsequent coding processing step performs the block coding processing in units of the number of bits or symbols n times the maximum count value of the input output code series. There is an effect that can be carried out.

【0076】

According to the present inventionpluralInput code sequenceToeachcorrectionBased on bit stringIn parallelDecrypt and do thispluralAs an output code sequenceIn parallelIn a multi-stage decoding method in which a plurality of output decoding processing steps are provided and the multi-stage coding sequence is sequentially subjected to the plurality of decoding processing steps to generate an output information sequence., CommunicatingTwo to followthe aboveAt least one location during the decryption processWhile selecting the replacement state that differs in timeMultiple output code sequences output from the decoding process in the previous stageIn parallel between the output code sequencesReverse replacementBy doingDeinterleaveAnd output multiple deinterleaved output code sequences in parallelSince the reverse replacement processing step is provided, the processing capacity in each decoding processing step is more than doubled, and at least one of the two consecutive decoding processing steps is a plurality of outputs output from the decoding processing step. The code sequence is input to the subsequent decoding process by deinterleaving by reverse replacement.

【0077】

Therefore, not only the processing capacity in each decoding processing step is doubled or more, but also a plurality of decoding processing steps in the previous stage are directly transferred to the decoding processing step in the subsequent stage without accumulating a plurality of output code sequences at at least one location. Since the output code sequence can be transmitted and the delay time there can be significantly reduced, the information is significantly reduced compared to the conventional one in which the output code sequence is sequentially stored in the deinterleaved memory and then read. The transmission speed will be improved and the total delay time will be significantly reduced. Similarly, the total memory storage capacity will be significantly reduced.

【0078】

Therefore, while ensuring the reliability of the transmitted information as in the past by executing the decryption process multiple times while performing the deinterleaved process in the middle, the delay time and the memory used are significantly higher than those of the conventional one. It is possible to reduce the capacity, and by extension, it is possible to transmit information at a transmission speed that cannot be realized in the past while ensuring the reliability of the transmitted information.

【0079】

According to the present invention, in all the decoding processing steps, decoding processing is performed in parallel for the same number of input code sequences, and a reverse replacement processing step is provided between two consecutive decoding processing steps, and the reverse is made. In all the replacement processing steps, the reverse replacement processing is performed between the parallel number of the input code series input to the decoding processing step and the same number of output code series. Therefore, for example, when the number of parallels is reduced in some parts. Since there is no bottleneck in the total information transmission speed that occurs in the above, the throughput of the entire multi-stage decoding processing process can be improved by at least the above parallel number, and the decoding processing speed is extremely high, which is several times faster than the conventional one. There is an effect that can be realized.

【0080】

According to the present invention, the reverse replacement processing step counts up to the value obtained by dividing the number of bits or symbols of the input output code sequence by the unit of the reverse replacement processing, and each count value is in a different reverse replacement state. Therefore, for example, assuming that the unit of the reverse replacement process is n symbols (n is an integer), the subsequent decoding process performs block decoding in units of bits or symbols n times the maximum count value of the input output code sequence. There is an effect that the processing can be carried out.

【0081】

According to the present invention, a plurality of input code sequencesCorrect in parallelAdd a bit string to create multiple output code sequencesIn a multi-stage coding apparatus which is provided with a plurality of coding processing means for outputting in parallel and sequentially performs correction bit string addition processing by the plurality of coding processing means to generate a multi-stage coding series, the input information series is continuous. Between the output code sequences for a plurality of output code sequences output from the coding processing means in the previous stage while selecting temporally different replacement states at at least one of the two coding processing means. Interleave is performed by exchanging in parallel with, and an exchange processing means for outputting a plurality of interleaved output code sequences in parallel is provided.Therefore, the processing capacity of each coding processing means is more than doubled, and at least one of the two consecutive coding processing means has a plurality of output code sequences output from the coding processing means. It is input to the coding processing means in the subsequent stage by interleaving by replacement.

【0082】

Therefore, not only the processing capacity of each coding processing means is more than doubled, but also the coding processing of the first stage to the subsequent coding processing directly without accumulating a plurality of output code sequences at at least one place. Since a plurality of output code sequences can be transmitted to the means and the delay time there can be significantly reduced, the output code sequences are sequentially stored in the interleaved memory and then read out. The information transmission speed will be improved, and the total delay time will be significantly reduced. Similarly, the total memory storage capacity will be significantly reduced.

【0083】

【0084】

According to the present invention, the number of input code sequences input to all the coding processing means and the number of input code sequences input to all the replacement processing means are the same, so that, for example, some of them are processed at the same time. Since there is no bottleneck in the total information transmission rate that occurs when the number of parallel input code sequences is reduced, the throughput of the entire multi-stage coding process should be improved by at least the number of parallels. This has the effect of achieving a very high coding processing speed that is several times faster than before.

【0085】

According to the present invention, the replacement processing means is provided with a replacement counter that counts up to the value obtained by dividing the number of bits or symbols of the input code sequence by the unit of the replacement process, and the same number as the number of the input code series. Since the input code sequence is input and a replacement selector that selects one input code sequence according to the count value of the replacement counter and outputs it as an output code sequence is provided, for example, the unit of the above replacement process is n symbols (n). Is an integer), there is an effect that the subsequent coding processing means can perform the block coding processing in units of the number of bits or the number of symbols n times the maximum count value of the input output code series.

【0086】

According to the present invention, EnterSince the replacement selector selects the same input code sequence for each switching count that is the same as the number of input code sequences, the subsequent coding processing means cycles in units of n times the number of bits or symbols of the maximum count value. There is an effect that a typical block interleaving process can be performed.

【0087】

According to the present invention, all coding processing means are based on the Reed-Solomon coding method.correctionSince a bit string is added, it is possible to perform byte-by-byte coding processing under this Reed-Solomon coding method, and a check bit string is added based on other BCH (Bose-Chaudhuri-Hocquenghem) coding methods and the like. There is an effect that parallel processing can be performed efficiently with a simpler configuration than in the case of performing.

【0088】

According to the present invention, a plurality of input code sequences.ToeachcorrectionBased on bit stringA plurality of decoding processing means for decoding in parallel and outputting this as a plurality of output code sequences in parallel are provided, and the multi-stage coded series is sequentially subjected to the decoding processing by the plurality of decoding processing means to generate an output information sequence. For a plurality of output code sequences output from the previous-stage decoding processing means while selecting temporally different replacement states at at least one of the two consecutive decoding processing means. Deinterleaving is performed by performing reverse swapping in parallel between the output code sequences, and a reverse swapping processing means for outputting a plurality of deinterleaved output code sequences in parallel is provided.Therefore, the processing capacity in each decoding processing step is more than doubled, and at least one of the two consecutive decoding processing means, the plurality of output code sequences output from the decoding processing means are reversely replaced. It is input to the decoding processing means in the subsequent stage in the deinterleave.

【0089】

Therefore, not only the processing capacity of each decoding processing means is doubled or more, but also a plurality of decoding processing means in the previous stage are directly transferred to the decoding processing means in the subsequent stage without accumulating a plurality of output code sequences at at least one place. Since the output code sequence can be transmitted and the delay time there can be significantly reduced, the information is significantly reduced compared to the conventional one in which the output code sequence is sequentially stored in the deinterleaved memory and then read out. The transmission speed will be improved and the total delay time will be significantly reduced. Similarly, the total memory storage capacity will be significantly reduced.

【0090】

【0091】

According to the present invention, the number of input code sequences input to all decoding processing means and the number of input code sequences input to all reverse replacement processing means are the same, so that, for example, a parallel number in some parts. Since the bottleneck of the total information transmission speed that occurs when is reduced, the throughput of the entire multi-stage decoding process can be improved by at least the above parallel number, which is several times higher than the conventional one. There is an effect that a high-speed decoding processing speed can be realized.

【0092】

According to the present invention, the reverse replacement processing means is provided with a reverse replacement counter that counts up to the value obtained by dividing the number of bits or symbols of the input code series by the unit of the replacement processing, and the same number as the number of the input code series. Since all the input code sequences are input and a reverse exchange selector that selects one input code sequence according to the count value of the reverse exchange counter and outputs it as an output code sequence is provided, for example, the unit of the reverse exchange process is described above. If n symbols (n is an integer), the effect is that the subsequent decoding processing means can perform block decoding processing in units of the number of bits or symbols that are n times the maximum count value of the input output code sequence. is there.

【0093】

According to the present invention, ConverseSince the replacement selector selects the same input code sequence for each switching count, which is the same as the number of input code sequences, the subsequent decoding processing means is periodic in units of n times the number of bits or symbols of the maximum count value. There is an effect that block deinterleave processing can be performed.

【0094】

According to the present invention, since all the decoding processing means perform the decoding process based on the Reed-Solomon coding method, it is possible to carry out the decoding process for each byte under this Reed-Solomon coding method. Compared to other BCH (Bose-Chaudhuri-Hocquenghem) code decoding methods, there is an effect that parallel processing can be performed efficiently with a simple configuration.

【0095】

According to the present invention, at least one re-decoding processing means that performs the same decoding processing as any of the decoding processing means is arranged at a position other than immediately after the decoding processing means, and the above-mentioned decoding processing means and re-decoding are performed. A re-replacement processing means is provided which is arranged between the processing means and generates a code sequence in the same coding state as the input code sequence input to the decoding processing means and outputs the code sequence to the re-decoding processing means. , Used in the above decoding processing meanscorrectionSince the bit string is transmitted to the re-decoding processing means, for example, an error correction of a portion corresponding to the result information series of another decoding processing means arranged between the decoding processing means and the re-decoding processing means is performed. In such a case, and if the decoding sequence is inappropriate for error correction of the decoding processing means, the re-decoding processing means can make it an appropriate decoding sequence. Therefore, there is an effect that the error checking ability can be improved as compared with the case where only a series of decoding processes corresponding to the coding process is performed, and by extension, the data reliability of the received information sequence can be further improved.

【0096】

According to the present invention, all decoding processing meanscorrectionSum of the number of error bits or the number of error symbolsCalculationSince it is equipped with an error number estimation circuit, it is possible to take into consideration errors especially in the re-decoding means, and it is possible to detect / correct (inspect) the number of bit errors included in the received multi-stage coding series with higher accuracy. There is an effect that can be done. [0097]

According to the present invention, the above-mentioned multi-stage coding device, the above-mentioned multi-stage decoding device, and a transmission medium for transmitting the multi-stage coding series of the above-mentioned multi-stage coding device to the above-mentioned multi-stage decoding device are provided. While ensuring the same reliability as before, the delay time and memory capacity used can be significantly reduced compared to conventional ones, and by extension, transmission that cannot be achieved in the past while ensuring the reliability of transmitted information. It has the effect of being able to transmit information at high speed.

[Simple explanation of drawings]

FIG. 1 is a block diagram showing a configuration of an information transmission system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of an interleaved circuit according to a first embodiment of the present invention.

FIG. 3 is a format diagram for explaining in detail the concatenated coding process in the information transmission system according to the first embodiment of the present invention ((a) is an input information sequence reference, and (b) is an output concatenated coding sequence. Criteria).

FIG. 4 is a block diagram showing a configuration of an information transmission system according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an information transmission system according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional information transmission system.

FIG. 7 is a format diagram for explaining a write / read operation for an interleaved memory of a conventional information transmission system.

FIG. 8 is a format diagram for explaining a write / read operation for an interleaved memory of a conventional information transmission system. However, it is a format diagram when one externally coded sequence extends over a plurality of lines of interleaved memory.

[Explanation of symbols]

1 Concatenated coding device (multi-stage coding device), 2 concatenated decoding device (multi-stage decoding device), 3 transmission medium, 4 information series input circuit, 5 external coding circuit (coding processing means, coding processing process), 6 interleaving Circuit (replacement processing means, replacement processing process), 7 internal coding circuit (coding processing means, coding processing process), 8 concatenated coding series output circuit, 9 concatenated coding series input circuit, 10 internal decoding circuit (decoding) Processing means, decoding processing process), 11 Deinterleaved circuit (reverse replacement processing means, reverse replacement processing process), 12 External decoding circuit (decoding processing means, decoding processing process), 13 Information series output circuit, 14 Error number estimation circuit, 15 counter (replacement counter), 16 selector (replacement selector), 19 interleaved circuit (replacement processing means, replacement processing process), 20 deinterleaved circuit (reverse replacement processing means, reverse replacement processing process), 21 internal decoding circuit (decoding processing) Means, decoding processing process), 22 deinterleaved circuit (replacement processing means, replacement processing process), 23 external decoding circuit (decoding processing means, decoding processing process), 24 reinterleaved circuit (replacement processing means), 25 Re-internal decoding circuit (re-decoding processing means), 26 red-deinterleaved circuit (re-replacement processing means), 27 re-external decoding circuit (re-decoding processing means), 28 error number estimation circuit.

Citations
Document	Relation	Office	Cited during
US7992069B2	Cited by	United States of America	Applicant

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Document	Office	Kind	Date
31583299	Japan	A	1999-11-05
JP19990315832	–	–	–

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Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system

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