Multi-level memory

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a multi-value memory, and more particularly to a semiconductor storage device that performs multi-value storage such as a multi-value flash memory, a multi-value EEPROM, and a multi-value EPROM.

【0002】

[Conventional technology]

As one of the memory cells of EEPROM, one having a MOSFET structure in which a charge storage layer (floating gate) and a control gate are laminated and formed on a semiconductor substrate is known. Normally, data "0" or "1" is stored and 1 bit of data is stored in one cell depending on the amount of electric charge stored in the floating gate. On the other hand, in order to realize a higher density EEPROM, a multi-value storage method in which multiple bits of data are stored in one cell is also known. For example, in the quaternary storage method, in order to store data "0", "1", "2", and "3" in one cell, four charge amounts corresponding to the data are stored in the floating gate.

【0003】

An example of the data storage state will be described using the 4-value method as an example. The state in which the amount of charge of the floating gate is 0 is defined as the neutral state, and the state in which positive charges are stored from the neutral state is defined as the erased state. Also, make the erased state correspond to the data "0". For example, a high voltage (~ 20V) is applied to the substrate, the control gate is set to 0V, and erasure is performed. The state in which negative charges are stored from the neutral state is defined as the state of data "1". The state of data "2" is also a state in which negative charges are stored compared to the neutral state, but the amount of negative charges is larger than the amount of negative charges in the state of data "1". In the state of data "3", the amount of negative charge is further increased. For example, during the writing operation, the board, source, and drain are set to 0V, the control gate is set to a high voltage (~ 20V), negative charges are stored in the floating gate, and data 1, 2, and 3 are written. Also, during the writing operation, the board is set to 0V, the source and drain are set to 10V, the control gate is set to a high voltage (~ 20V), the charge in the floating gate is retained, and the data "0" is stored in the memory cell. As a result, four write states (0, 1, 2, 3) having different threshold levels in the memory cell transistor are realized in the memory cell.

【0004】

As one of the multi-value storage EEPROMs, a device that collectively writes data for a plurality of bytes to a memory cell as multi-value level data is known (for example, JP-A-7-93979). The purpose of writing all at once is to shorten the writing time, and a plurality of data storage circuits for storing control data for writing multi-valued data to individual memory cells are provided. Further, in order to control the write state with high accuracy, for example, the write state of the memory cell is detected after the write operation (write verify), and if there is an insufficiently written memory cell, writing is promoted only to that memory cell. The control data of the data storage circuit is converted so that the write voltage is applied. Using the converted control data, the write operation is performed again, and the write operation and the write verify operation are continued until all the selected memory cells are sufficiently written.

【0005】

[Problems to be Solved by the Invention]

However, in the conventional multi-value storage EEPROM as described above, in addition to the time required to actually accumulate the charge in the floating gate, the write verify operation is performed, so that the total time required for writing becomes redundant. There was a problem. In particular, it detects whether or not the memory cell has reached the "1" write state, then detects whether or not the memory cell has reached the "2" write state, and so on. When it is detected separately whether or not the cells have been reached, the writing time becomes significantly long if all the writing states are detected each time. However, there is a difference in the time it takes for the memory cells to reach their respective write states, that is, they are written in the order of "1", "2", and "3", so the memory cell that is easiest to write is in the "1" state. By the time it reaches, the memory cell has not yet reached the "2" or "3" state, and it is completely useless to detect whether or not it has reached the "2" or "3" state. Is. That is, in such a write verification operation, unnecessary verify read is executed at the initial stage of writing, which causes a long writing time.

【0006】

In addition, one data storage circuit has a plurality of sense circuits in order to perform write verification and convert control data. When detecting a specific writing state at the same time by a plurality of sense circuits, a certain sense circuit may detect that the writing is sufficient, and another sense circuit may detect that the writing is insufficient. This is because there is a difference in sense sensitivity due to variations in the performance of the transistors constituting the sense circuit. Therefore, there is a problem that the control data may not be converted normally.

【0007】

As described above, the multi-value storage method is an effective means for increasing the density, but since there is a difference in the time it takes for the memory cells to reach their respective write states, it is written when unnecessary verify read is executed. There is a problem that the time becomes redundant, and as a result, the writing time becomes long due to the write verification. Further, when the writing state of one memory cell is detected by a plurality of sense circuits at the same time, the result may differ due to the variation in sense sensitivity, and there is a problem that the reliability is impaired.

【0008】

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a multi-valued memory capable of shortening the write verification time. Further, another object of the present invention is to provide a highly reliable multi-valued memory that can obtain stable write verification results.

【0009】

[Means for solving problems]

In the first invention of the present application, the following configuration is adopted in order to solve the above problems. That is, the multi-valued memory in the present invention has at least an erase state, a first write state, and a second write state, and is electrically writable. A write voltage is applied to the memory cell to write a predetermined value. A write operation for performing the above, a first write confirmation operation for confirming whether or not the memory cell has reached the first write state after the write operation, or a second write confirmation operation for the memory cell after the write operation. It is a multi-valued memory provided with a write circuit that writes data while repeating a second write confirmation operation for confirming whether or not a write state has been reached, and the write circuit is the first period at the beginning of data writing. Repeats the write operation and the first write confirmation operation by omitting the second write confirmation operation, and during the second period after the first period, the write operation and the first write are performed. It is characterized in that the confirmation operation and the second write confirmation operation are repeated.

【0010】

Further, as a desirable embodiment of the present invention, the following can be mentioned. (1) The write circuit repeats the write operation and the second write confirmation operation in the third period after the second period, omitting the first write confirmation operation. (2) When the write circuit confirms that the memory cell has reached the predetermined first write state or the second write state, the write circuit changes the write voltage applied to the memory cell.

【0011】

Further, the multi-valued memory in the present invention has at least an erase state, a first write state, and a second write state, and applies a write voltage to a plurality of electrically writable memory cells and the plurality of memory cells. A first write operation for performing a predetermined write operation and a first confirmation of whether or not the memory cell to be in the first write state among the plurality of memory cells has reached the first write state after the write operation. A write confirmation operation or a second write confirmation operation for confirming whether or not a memory cell that should be in the second write state among the plurality of memory cells has reached the second write state after the write operation. A multi-valued memory including a write circuit that writes data while repeating the above, and the write circuit omits the second write confirmation operation during the first period at the beginning of data writing, and performs the write operation and the above. The first write confirmation operation is repeated, and the second period after the first period repeats the write operation, the first write confirmation operation, and the second write confirmation operation.

【0012】

Further, as a desirable embodiment of the present invention, the following can be mentioned. (1) The write circuit repeats the write operation and the second write confirmation operation in the third period after the second period, omitting the first write confirmation operation. (2) When the write circuit confirms that the memory cell to be in the first write state has reached the first write state, the write voltage is applied to the memory cell to be in the first write state. When it is confirmed that the memory cell to be in the second write state has reached the second write state, the write voltage applied to the memory cell to be in the second write state is changed. (3) The first period is predetermined. (4) When the write circuit confirms that all the memory cells to be in the first write state have reached the first write state, the first write confirmation operation is omitted and the write operation is performed. The second write confirmation operation is repeated. (5) The writing circuit collectively detects whether or not all the memory cells to be in the first writing state have reached the first writing state. (6) The writing circuit collectively detects whether or not all the memory cells to be in the second writing state have reached the second writing state. (7) The write voltage applied to the memory cell to be in the first write state is equal to the write voltage applied to the memory cell to be in the second write state. (8) The writing circuit ends the writing operation after confirming that all of the written memory cells have reached a predetermined writing state. (9) The writing circuit collectively detects that all of the written memory cells have reached a predetermined writing state.

【0013】

The multi-valued memory according to the first invention of the present application performs write verification by paying attention only to a write state that requires write verification performed after writing. Since there is a difference in the time it takes for the memory cells to reach their respective write states, only the necessary verify reads are executed in consideration of this. As a result, redundant write verification time can be omitted, and a multi-valued memory that can be written at high speed can be realized.

【0014】

Further, in the second invention of the present application, the following configuration is adopted in order to solve the above problems. That is, the multi-valued memory in the present invention includes a memory cell array composed of a plurality of non-volatile memory cells, each capable of storing n-value (n 3) data, and a selected memory cell in the memory cell array. A data storage circuit for storing control data that determines a write control voltage applied during a write operation is provided, and the data storage circuit is a memory cell selected based on the control data stored in the data storage circuit. The data storage circuit, which applies the write control voltage to the data and stores the first control data, detects whether or not the write state of the selected memory cell has reached the first state, and reaches the state. If so, the control data is changed to the second control data, and the data storage circuit storing the second control data determines whether or not the write state of the selected memory cell has reached the second state. It is characterized in that the control data is changed to the third control data when the data is detected.

【0015】

Further, as a desirable embodiment of the present invention, the following can be mentioned. (1) The first state has a first threshold level, and the second state has a second threshold level lower than the first threshold level. (2) The data storage circuit is composed of a first sub-data circuit and a second sub-data circuit, and stores first logic level sub-data in the first sub-data circuit and is a second sub-data circuit. Stores the first logic level sub-data, stores the first control data, stores the first logic level sub-data in the first sub-data circuit, and stores the first logic-level sub-data in the second sub-data circuit. The second logic level sub-data is stored in the first sub-data circuit, the second control data is stored in the first sub-data circuit, the second logic level sub-data is stored in the first sub-data circuit, and the second sub-data circuit stores the sub data. The second logic level sub-data is stored, and the third control data is stored. (3) The data storage circuit detects whether or not the write state of the selected memory cell has reached the first state in one of the first and second sub data circuits, and the selected memory. Whether or not the writing state of the cell has reached the second state is detected by the other of the first and second sub-data circuits. (4) Further, it is collectively detected whether or not all the sub-data stored in the first and second sub-data circuits constituting all the data storage circuits are at the second logic level. Equipped with a circuit. (5) The memory cell can store four values, and the first and second sub data circuits each include one flip-flop circuit. (6) The memory cell can store three values, and the first and second sub data circuits each include one flip-flop circuit.

【0016】

The multi-valued memory according to the second invention of the present application performs a sense operation with only one sub data circuit to detect a certain write state at the time of write verification performed after writing. As a result, the write verification result is stable, and a highly reliable multi-valued memory can be realized.

【0017】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a multi-valued memory of the present invention, specifically, a multi-valued storage type NAND flash memory.

【0018】

The memory cell array 1 is formed by arranging a plurality of memory cells in which data can be electrically rewritten in a matrix. The memory cell array 1 includes a plurality of bit lines to which each memory cell is connected row by row and a plurality of word lines to which each memory cell is connected column by column, and bit lines are provided to the memory cell array 1 with respect to the memory cell array 1. A bit line control circuit 2 and a word line control circuit 6 for control are provided.

【0019】

The bit line control circuit 2 reads the data of the memory cell in the memory cell array 1 via the bit line, detects the state of the memory cell in the memory cell array 1 via the bit line, and stores the memory via the bit line. A write control voltage is applied to the memory cells in the cell array 1 to write to the memory cells. The bit line control circuit 2 includes a plurality of data storage circuits, and the data of the memory cell read from the data storage circuit selected by the column decoder 3 is transmitted from the data input / output terminal 5 via the data input / output buffer 4. It is output to the outside. Further, the write data input to the data input / output terminal 5 from the outside is input as initial control data to the data storage circuit selected by the column decoder 3 via the data input / output buffer 4. A data detection circuit 9 is provided to detect the contents stored in a plurality of data storage circuits included in the bit line control circuit 2.

【0020】

The word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage required for reading, writing, or erasing. The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4, the word line control circuit 6, and the data detection circuit 9 are controlled by the control signal and control voltage generation circuit 7. The control signal and the control voltage generation circuit 7 are controlled by a control signal input to the control signal input terminal 8 from the outside. It also responds to the contents of the plurality of data storage circuits included in the bit line control circuit 2 detected by the data detection circuit 9.

【0021】

FIG. 2 shows a configuration example of the memory cell array 1 and the bit line control circuit 2 shown in FIG. 1 in the first embodiment of the present invention. One end of a NAND cell unit in which four memory cells M are connected in series is connected to the bit line BL via the selection transistor S, and the other end is connected to the common source line SRC via the selection transistor S. The control gate electrode of the memory cell M is connected to the word line WL, and the two selection transistors S are connected to the selection gates SG1 and SG2, respectively. A memory cell M sharing one word line WL forms a unit called a page, and four pages form one block. Although two blocks are shown here, any integer, such as 1024 blocks, may be used. Further, although 4224 bit lines BL0 to BL4223 are shown as the bit line BL, any integer, for example, 2112 lines may be used.

【0022】

The bit line control circuit 2 includes a plurality of data storage circuits 10. Here, one data storage circuit 10 is provided for two bit lines BL, but one may be provided for any integer line, for example, one line, four lines, six lines, or nine lines. The signal CSL is an output signal of the column decoder 3, and for example, the data of the memory cell stored in the data storage circuit 10 connected to the bit lines BL0 and BL1 is output to the data input / output buffer 4 by CSL0 and CSL1. Further, for example, control data is initially transferred from the data input / output buffer 4 to the data storage circuit 10 connected to the bit lines BL2 and BL3 by CSL2 and CSL3. At the time of reading, the data storage circuit 10 reads the data of the memory cell connected to either bit line. Further, at the time of writing, a writing control voltage is applied to the memory cell connected to either bit line according to the stored control data. Further, when the write state is detected, the write state of the memory cell connected to either bit line is detected.

【0023】

FIG. 3 is a cross-sectional view of the memory cell M and the selection transistor S shown in FIG. An n-type diffusion layer 12 is formed on the surface of the p-type semiconductor substrate 11. In the memory cell M, a floating gate 14 is formed on the semiconductor substrate 11 via the insulating film 13, and a control gate 16 serving as a word line WL is formed on the floating gate 14 via the insulating film 15. In the selection transistor S, a selection gate 18 serving as a selection gate SG is formed on the semiconductor substrate 11 via an insulating film 17.

【0024】

FIG. 4 is a cross-sectional view showing the structure of the NAND cell unit shown in FIG. 2 together with the two selection transistors at both ends thereof. Four memory cells M are connected in series, and one end is connected to the common source line SRC via the selection transistor S. The other end is connected to the bit line BL via the selection transistor S. Assuming that the selected word line is WL2, for example, 20V is applied to the selected word line WL2 at the time of writing. 10V is applied to the non-selected word lines WL1, WL3 and WL4. Further, the selection gate SG1 is given a power supply voltage VCC. The selection gate SG2 is 0V.

【0025】

For example, in the case of 4-value storage, when writing data "1", "2", "3", the bit line BL is set to 0V. As a result, in the selected memory cell, electrons are injected into the floating gate and the threshold value becomes positive. When writing data 0, set the bit line BL to the power supply voltage VCC. In this case, no electrons are injected into the floating gate. The voltage of the bit line BL when writing the data 1, 2, 3 does not have to be 0V. For example, the voltage of the bit line BL when writing the data 1 may be set to 0.8V, and the voltage of the bit line BL when writing the data 2 and 3 may be set to 0V. This is because the amount of electrons injected into the floating gate of the memory cell M to store the data 1 may be less than the electrons injected to store the data 2 and 3. Further, the voltage of the bit line BL when writing the data 1, 2, and 3 may be different from each other. For example, it may be 0.8V, 0.4V, and 0V, respectively.

【0026】

When erasing, set the board voltage Vsub to 20V. Also, select gates SG1 and SG2, common source line SRC, and bit line BL are set to 20V. When the word lines WL1 to WL4 of the block to be erased are set to 0V, electrons are emitted from the floating gate and the threshold value becomes negative (data 0 state). When the word lines WL1 to WL4 of the block to be not erased are set to 20V, electrons are not emitted from the floating gate.

【0027】

For example, in the case of 4-value storage, the threshold value of the memory cell corresponding to data "0" is 0V or less, the threshold value of the memory cell corresponding to data "1" is 0.4V to 0.8V, and the threshold value corresponds to data "2". The threshold value of the memory cell to be used is 1.2V to 1.6V, and the threshold value of the memory cell corresponding to the data "3" is 2.0V to 2.4V. When reading, set the selected word line WL2 to Vread. The non-selected word lines WL1, WL3 and WL4 are set to the power supply voltage VCC (for example, 3.3V). Select gates SG1 and SG2 are also set to VCC. The common source line SRC is 0V.

【0028】

(1) When Vread is set to 0V, if the selected memory cell stores data "1", "2", or "3", the voltage of the bit line charged to VCC and put into a floating state remains VCC. is there. If the selected memory cell stores data 0, the voltage of the bit line charged to VCC and suspended will drop to 0V.

【0029】

(2) When Vread is set to 1V, if the selected memory cell stores data "2" or "3", the voltage of the bit line charged to VCC and put into a floating state remains VCC. If the selected memory cell stores data 0 or 1, the voltage of the bit line charged to VCC and suspended will drop to 0V.

【0030】

(3) When Vread is set to 1.8V, if the selected memory cell stores data "3", the voltage of the bit line charged to VCC and put into a floating state remains VCC. If the selected memory cell stores data 0, 1, or 2, the voltage of the bit line charged to VCC and suspended will drop to 0V.

【0031】

As described in (1) to (3) above, the data stored in the memory cell M is determined by detecting the voltage of the bit line when the voltage Vread is changed.

【0032】

FIG. 5 is for explaining a more specific configuration example of the memory cell array 1 and the data storage circuit 10 shown in FIG. 2, and extracts some circuit configurations by focusing on the bit lines BLi and BLi + 1. Is shown. Here, a configuration example of a quadrature storage flash memory is shown.

【0033】

That is, in the data storage circuit 10, first and second sub data circuits 20 and 21 including a flip-flop circuit are provided, respectively. Specifically, the p-channel MOS transistors Qp1 and Qp2, and the n-channel MOS transistors Qn1, Qn2, Qn4, Qn5, and Qn8 constitute the first sub-data circuit 20. Further, the p-channel MOS transistors Qp4 and Qp5, and the n-channel MOS transistors Qn12, Qn13, Qn15, Qn16, and Qn19 form a second sub-data circuit 21. The first and second sub-data circuits 20 and 21 store the first and second sub-data at the time of writing, respectively, and store the first and second read sub-data at the time of reading, respectively. The p-channel MOS transistors Qp3 and Qp6 are for resetting the first and second sub-data circuits 20 and 21, respectively. When reset, the node Nai in the first sub data circuit 20 becomes "H" level. In this state, the first sub-data circuit 20 stores the first read sub-data of "1" or the first sub-data of "1". When reset, the node Nai + 1 in the second sub data circuit 21 becomes H level. In this state, the second sub-data circuit 21 stores the second read sub-data of "1" or the second sub-data of "1". When the node Nai in the first sub data circuit 20 is at the L level, the first sub data circuit 20 stores the first read sub data of 0 or the first sub data of 0. It is in a state of being. When the node Nai + 1 in the second sub data circuit 21 is at the L level, the second sub data circuit 21 is the second read sub data of 0 or the second sub data of 0. Is in a state of remembering.

【0034】

The n-channel MOS transistors Qn6 and Qn17 are for electrically connecting the first and second sub-data circuits 20 and 21 to the data input / output lines IOL and IOU, respectively. Each gate electrode is given outputs CSLi and CSLi + 1 from the column decoder 3, respectively. For example, when CSLi becomes H, the first sub data circuit 20 of the data storage circuit 10 provided on the bit line BLi and BLi + 1 and the data input / output line IOL are electrically connected. The data input / output lines IOL and IOU are connected to the data input / output buffer 4, and sub data can be set in the first sub data circuit 20. Alternatively, the read subdata of the first subdata circuit 20 can be output to the data input / output buffer 4. The n-channel MOS transistors Qn3 and Qn14 are for presetting "0" sub-data in the first and second sub-data circuits 20 and 21, respectively. Once preset, the node Nai in the first sub-data circuit 20 will be at the L level. Further, when preset, the node Nai + 1 in the second sub data circuit 21 becomes the L level.

【0035】

The n-channel MOS transistors Qn7 and Qn8 control the voltage of the bit line BLi or BLi + 1 according to the first sub-data stored in the first sub-data circuit 20. Further, the n-channel MOS transistors Qn18 and Qn19 control the voltage of the bit line BLi or BLi + 1 according to the second sub-data stored in the second sub-data circuit 21.

【0036】

The n-channel MOS transistors Qn7 and Qn9 set the voltage of the bit line BLi or BLi + 1 to 0V when the first subdata of 1 is stored in the first subdata circuit 20. Further, the n-channel MOS transistors Qn18 and Qn20 set the voltage of the bit line BLi or BLi + 1 to 0V when the second subdata of 1 is stored in the second subdata circuit 21.

【0037】

The n-channel MOS transistors Qn10 and Qn21 control the electrical connection between the first and second sub-data circuits 20, 21 and the bit line BLi or BLi + 1. If the signal BLC1 is H and BLC2 is L, the first and second sub-data circuits 20, 21 and the bit line BLi are electrically connected. If the signal BLC1 is L and BLC2 is H, the first and second sub-data circuits 20, 21 and the bit line BLi + 1 are electrically connected.

【0038】

The n-channel MOS transistors Qn11 and Qn22 control the electrical connection between the bit line BLi and the voltage VBL1 and the electrical connection between the bit line BLi + 1 and the voltage VBL2. If the signal PRE1 is H, the bit line BLi and the voltage VBL1 are electrically connected. If the signal PRE2 is H, the bit line BLi + 1 and the voltage VBL2 are electrically connected.

【0039】

Signals RST, SEN1, SEN2, RD1, RD2, PRO1, PRO2, PRST, BLC1, BLC2, PRE1, PRE2, voltage VRP, VBL1, VBL2 are control signals and output signals of control voltage generation circuit 7, shown in FIG. It is common to all of the data storage circuits 10. The data input / output lines IOL and IOU are connected to the data input / output buffer 4 and are common to all the data storage circuits 10 shown in FIG. The voltage VCC is the power supply voltage, for example, 3.3V.

【0040】

The first and second sub-data circuits 20 and 21 store "0" or "1" sub-data, while they are stored as sense circuits in response to the "H" level of the bit line signal "1". It is configured to change the sub-data of "" to the sub-data of "0" and retain the sub-data of "0". Further, the first and second sub-data circuits 20 and 21 store the read sub-data of "0" or "1", and are stored in response to the "H" level of the bit line signal, respectively. It is configured to change the read subdata of "1" to the read subdata of "0" and retain the read subdata of "0".

【0041】

That is, when the signal SEN1 or SEN2 shown in FIG. 5 becomes H and the H level of the bit line BL is transferred to the gate electrode of the n-channel MOS transistor Qn5 or Qn16 at this time, the n-channel MOS transistor Qn5 or Qn16 conducts and node Nai or Nai + 1 is brought to the L level. As a result, the sub-data or read sub-data of "1" is changed to the sub-data or read sub-data of "0". The "0" subdata or read subdata is not changed because the node Nai or Nai + 1 is originally at the "L" level. Further, depending on the "L" level of the bit line BL, the sub data or the read sub data is not changed because the n-channel MOS transistor Qn5 or Qn16 is non-conducting. The first and second sub-data circuits 20 and 21 can be similarly realized by using various circuits having the above-mentioned functions, regardless of the configuration example shown in FIG.

【0042】

FIG. 6 shows a specific configuration example of the data detection circuit 9 shown in FIG. It is a circuit composed of inverters I1, NAND logic circuits G1, G2, and G3, and detects whether or not there is control data of "1" in the data storage circuit 10. If even one of the data storage circuits 10 stores the control data of "1", the signal FR1 becomes "H". It is a circuit composed of inverters I2 and NAND logic circuits G4, G5, and G6, and detects whether or not there is "2" control data in the data storage circuit 10. If even one of the data storage circuits 10 stores the control data of "2", the signal FR2 becomes "H". It is a circuit composed of NAND logic circuits G7, G8, and G9, and detects whether or not there is control data of "3" in the data storage circuit 10. If even one of the data storage circuits 10 stores the control data of "3", the signal FR3 becomes "H". When the signal DT is H, the control data of the data storage circuit 10 is detected via the data input / output lines IOL and IOU. When the signal DRSTB becomes L, the signals FR1, FR2 and FR3 are reset to L. The signals DT and DRSTB are the control signal and the output signal of the control voltage generation circuit 7. The signals FR1, FR2, and FR3 are fed back to the control signal and the control voltage generation circuit 7.

【0043】

FIG. 7 shows the operation of reading the quaternary data stored in the memory cell. Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. If the memory level is limited to 3 levels, ternary memory can be easily performed. The voltages VBL1 and VBL2 are 0V during reading.

【0044】

First, the signal BLC1 becomes H and the bit line BLi is selected (t1). The first and second sub-data circuits 20 and 21 are set with the first and second read sub-data of 1 by the signal RST (t1 to t2), respectively (t1 to t2). The voltage VRP becomes the power supply voltage VCC (t1).

【0045】

The signal PRE1 becomes L and the bit line BLi and the voltage VBL1 are separated (t3). The signal PRO2 becomes H (t3), and the bit line BLi is charged to the H level by the second sub-data circuit 21 (t3 to t4). Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 1.8V (t4). Here, Table 1 shows the relationship between the data stored in the memory cell M and the threshold value.

【0046】

[table 1]

<img file="JPP3409986B2_D0001.tif" />【0047】

When the selected word line WL2 reaches 1.8V, the bit line BLi remains H only when the memory cell stores 3 data ((1) in Fig. 7). In other cases, the bit line BLi is L ((2) in Fig. 7). Then, the signals SEN1 and SEN2 are set to H, and the voltage of the modulated bit line BLi is sensed and read out (t5 to t6). Only when the memory cell stores "3" data, the first and second read sub data of the first and second sub data circuits 20 and 21 are both "0". Otherwise, the first and second read subdata remains "1".

【0048】

The signal PRE1 becomes H (t6 to t7), and the bit line BLi is reset to 0V. After that, the signal PRO2 becomes H (t7 to t8), and the bit line BLi is charged to the H level by the voltage VRP only when the second read subdata is 1 (t7 to t8). .. The bit line BLi remains at the L level when the second read subdata stored in the second subdata circuit 21 is 0 ((5) in FIG. 7). Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 1.0V (t8).

【0049】

When the selected word line WL2 becomes 1.0V, the bit line BLi remains H only when the memory cell stores 2 data ((3) in Fig. 7). When the memory cell stores 1 or 0 data, the bit line BLi becomes L ((4) in Fig. 7). Then, the signal SEN2 is set to H and the voltage of the modulated bit line BLi is sensed and read out (t9 to t10). Only when the memory cell stores "2" data, the second read sub data changes from "1" to "0". If the memory cell stores "1" or "0" data, the second read subdata remains "1". If the memory cell stores "3" data, the second read subdata is already "0".

【0050】

The signal PRE1 becomes H (t10 to t11), and the bit line BLi is reset to 0V. After that, the signal PRO2 becomes H (t11 to t12), and the bit line BLi is charged to the H level by the voltage VRP only when the second read subdata is 1 (t11 to t12). .. The bit line BLi remains at the L level when the second read subdata stored in the second subdata circuit 21 is 0 ((8) in FIG. 7). Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 0V (t12).

【0051】

When the selected word line WL2 becomes 0V, the bit line BLi remains H only when the memory cell stores 1 data ((6) in Fig. 7). When the memory cell stores 0 data, the bit line BLi becomes L ((7) in Fig. 7). Then, the signal SEN1 is set to H and the voltage of the modulated bit line BLi is sensed and read out (t13 to t14). Only when the memory cell stores "1" data, the first read sub data changes from "1" to "0". If the memory cell stores "0" data, the first read subdata remains "1". If the memory cell stores "3" data, the first read subdata is already "0". When the memory cell stores "2" data, the first read subdata remains "1" because the voltage of the bit line BLi is "L" regardless of the memory cell.

【0052】

When the signals CSLi and CSLi + 1 become H, the first read subdata is output to the data input / output line IOL and output from the data input / output terminal 5 to the outside via the data output buffer 4. Further, the second read sub data is output to the data input / output line IOU and is output to the outside from the data input / output terminal 5 via the data output buffer 4. The first and second read sub-data of an arbitrary column address can be output according to the signal CSL selected by the column decoder 3.

【0053】

During the read operation, the non-selected bit line BLi + 1 is fixed by the voltage VBL2. Here it is 0V. Table 2 shows the relationship between the quaternary data of the memory cell and the first and second read sub-data.

【0054】

[Table 2]

<img file="JPP3409986B2_D0002.tif" />【0055】

FIG. 8 shows the initial setting and writing operation of the control data to the data storage circuit 10. Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. If the memory level is limited to 3 levels, ternary memory can be easily performed.

【0056】

The initial setting of the control data in the data storage circuit 10 provided in the bit line BLi is performed as follows. The initial sub data of the first sub data circuit 20 is transferred to the data input / output line IOL, the signal CSLi becomes H, and the initial sub data is stored in the first sub data circuit 20. At the same time, the initial sub data of the second sub data circuit 21 is transferred to the data input / output line IOU, the signal CSLi + 1 becomes H, and the initial sub data is stored in the second sub data circuit 21. .. At this time, the relationship between the initial control data and the initial sub data is shown in Table 3 below.

【0057】

[Table 3]

<img file="JPP3409986B2_D0003.tif" />【0058】

Here, it is desirable to set the signal PRST to H and preset the control data of all the data storage circuits 10 to 0 before setting all the initial control data. As will be described later, the state of the memory cell M cannot be changed by the control data 0. Therefore, if the initial control data is set from the outside only in the desired data storage circuit 10 among the 2112 data storage circuits 10. Good. Of course, initial control data may be set externally in all 2112 data storage circuits 10.

【0059】

In the write operation, first, the signal BLC1 becomes H and the bit line BLi is selected (t1). The signal DRSTB becomes L and the data detection circuit 9 is reset (t1 to t2). The voltage VBL1 becomes VCC, the selection bit line BLi is charged to VCC via the n-channel MOS transistor Qn11, then the signal PRE1 becomes L, and the selection bit line BLi is floated (t2 ~). t3). Further, the voltage VBL2 becomes VCC, and the non-selective bit line BLi + 1 is charged to VCC via the n-channel MOS transistor Qn22 (t2 to t3). Also, the selection gate SG1 and the word lines WL1 ~ 4 are set to VCC (t2 ~ t3).

【0060】

If the signals PRO1 and PRO2 are H and either one of the first or second subdata is 1, the selected bit line BLi is set to 0V by the n-channel MOS transistor Qn9 or Qn20 ( t3). As a result, the bit line BLi becomes VCC when the control data is 0 and 0V when the control data is 1, 2 or 3. The selected word line WL2 is set to 20V and the non-selected word line is set to 10V, and electron injection into the floating gate of the memory cell starts according to the control data (t3). When the bit line BL is 0V, electron injection occurs when the potential difference between the memory cell channel and the word line is 20V. When the bit line BL is VCC, electron injection does not substantially occur because the potential difference between the channel of the memory cell and the word line is small.

【0061】

While the selected word line WL2 is set to 20V (t3 to t7), the control data stored in the data storage circuit 10 is detected. The column decoder 3 selects CSL0 and CSL1 to CSL4222 and CSL4223 in order, and the control data is transmitted to the data detection circuit 9 via the data input / output lines IOL and IOU. As an example, the case where CSLi and CSLi + 1 are selected is shown in FIG. When CSLi and CSLi + 1 become H (t4 to t5), control data is output to the data input / output lines IOL and IOU, and when the signal DT becomes H, the control data is detected by the data detection circuit 9. (T5 ~ t6). If even one of the data storage circuits 10 stores data "1", the signal FR1 becomes "H". If even one of the data storage circuits 10 stores data "2", the signal FR2 becomes "H". If even one of the data storage circuits 10 stores data "3", the signal FR3 becomes "H".

【0062】

After the word lines WL1 ~ 4 are dropped to VCC (t7 ~ t8), the voltage VBL2 becomes 0V, the signal PRE1 becomes H, and the bit lines BLi and BLi + 1 are reset to 0V (t8 ~ t9). .. The voltage VBL1 is 0V. Word lines WL1 ~ 4 are also reset to 0V (t8 ~ t9).

【0063】

FIG. 9 shows a write verification operation for detecting the write state of the memory cell after the write operation performed at the times t1 to t9 shown in FIG. Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. The voltages VBL1 and VBL2 are 0V. If the memory level is limited to 3 levels, ternary memory can be easily performed.

【0064】

First, the signal PRE1 becomes "L", the bit line BLi and the voltage VBL1 are separated, and the bit line BLi becomes a floating state of 0V (t1). At the same time, the signal BLC1 becomes H and the bit line BLi is selected (t1).

【0065】

When the voltage VRP becomes the power supply voltage VCC (t2) and the signal PRO2 becomes H (t3), the bit line BLi corresponding to the data storage circuit 10 that stores the control data of 3 and 2. Is charged to the H level by the n-channel MOS transistor Qn20 (t3 ~ t4). The bit line BLi corresponding to the data storage circuit 10 storing the control data of 1 and 0 remains at the L level. Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 2V (t4). When the selected word line WL2 reaches 2.0V, the bit line BLi will be changed if the memory cell corresponding to the data storage circuit 10 that stores the control data of "3" has reached the state of storing the "3" data. It remains H ((1) in Figure 9). If the memory cell corresponding to the data storage circuit 10 storing the control data of 3 has not reached the state of storing the 3 data, the bit line BLi becomes L ((in FIG. 9). 2)). Since the memory cell corresponding to the data storage circuit 10 that stores the control data of 2 does not reach the state of storing the 3 data, the bit line BLi becomes L ((2) in FIG. 9). )). The bit line BLi corresponding to the data storage circuit 10 that stores the control data of 1 and 0 remains L ((3) in Fig. 9). Subsequently, the signals SEN1 and SEN2 are changed to L. The voltage of the bit line BLi modulated to H is sensed and read out (t5 to t6). The memory cell corresponding to the data storage circuit 10 that stores the control data of 3 stores the 3 data. Only when the state is reached, the first and second sub data of the first and second sub data circuits 20 and 21 are both set to "0", and the control data is changed to "0". Otherwise, the first and second sub-data are retained. Times t2 to t6 are verify reads of data 3.

【0066】

The bit line BLi corresponding to the data storage circuit 10 that stores the control data of 2 and 0 when the signals PRO1 and RD1 become H (t7) is determined by the first sub data circuit 20. , "H" level is charged (t7 ~ t8). The bit line BLi corresponding to the data storage circuit 10 that stores the control data of 3 and 1 is set to the L level by the first sub data circuit 20 (t7 to t8). Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 1.2V (t8). The selected word line WL2 is 1. At 2V, the bit line BLi remains "H" if the memory cell corresponding to the data storage circuit 10 that stores the control data of "2" has reached the state of storing the "2" data. There is ((4) in Fig. 9). If the memory cell corresponding to the data storage circuit 10 that stores the control data of 2 has not reached the state of storing the 2 data, the bit line BLi becomes L ((in FIG. 9). Five)). If the memory cell corresponding to the data storage circuit 10 that stores the control data of "0" has reached the state of storing the "2" or "3" data, the bit line BLi remains "H". There is ((4) in Fig. 9). If the memory cell corresponding to the data storage circuit 10 that stores the control data of 0 has not reached the state of storing the 2 data, the bit line BLi becomes L ((in FIG. 9). Five)). The bit line BLi corresponding to the data storage circuit 10 that stores the control data of 3 and 1 remains L ((6) in FIG. 9). Then, the signal SEN2 is set to H and the voltage of the modulated bit line BLi is sensed and read out (t9 to t10). The second sub of the second sub data circuit 21 only when the memory cell corresponding to the data storage circuit 10 storing the control data of 2 has reached the state of storing the 2 data. The data becomes "0" and the control data is changed to "0". Otherwise, the second subdata is retained. The time t7 to t10 is the verify read of data "2".

【0067】

The bit line BLi corresponding to the data storage circuit 10 that stores the control data of 1 and 0 when the signals PRO2 and RD2 become H (t11) is determined by the second sub data circuit 21. , "H" level is charged (t11 ~ t12). The bit line BLi corresponding to the data storage circuit 10 that stores the control data of 3 and 2 is set to the L level by the second sub data circuit 21 (t11 to t12). Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 0.4V (t12). The selected word line WL2 is 0. At 4V, the bit line BLi remains "H" if the memory cell corresponding to the data storage circuit 10 that stores the control data of "1" has reached the state of storing the "1" data. There is ((7) in Fig. 9). If the memory cell corresponding to the data storage circuit 10 that stores the control data of 1 has not reached the state of storing the 1 data, the bit line BLi becomes L ((of FIG. 9). 8)). If the memory cell corresponding to the data storage circuit 10 that stores the control data of 0 has reached the state of storing the 1, 2, or 3 data, the bit line BLi is H. ((7) in Fig. 9). If the memory cell corresponding to the data storage circuit 10 that stores the control data of 0 has not reached the state of storing the 1 data, the bit line BLi becomes L ((of FIG. 9). 8)). The bit line BLi corresponding to the data storage circuit 10 that stores the control data of 3 and 2 remains L ((9) in FIG. 9). Then, the signal SEN1 is set to H and the voltage of the modulated bit line BLi is sensed and read out (t13 to t14). The first sub of the first sub data circuit 20 only when the memory cell corresponding to the data storage circuit 10 storing the control data of 1 has reached the state of storing the 1 data. The data becomes "0" and the control data is changed to "0". Otherwise, the first subdata is retained. The time t11 to t14 is the verify read of data "1".

【0068】

At time t15, the signal PRE1 is set to H and BLC1 is set to L, and the write verification is completed. In the write verify operation, the control data stored in the data storage circuit 10 is changed from the write state of the memory cell as shown in Table 4.

【0069】

[Table 4]

<img file="JPP3409986B2_D0004.tif" />【0070】

Therefore, by repeating the write operation shown in t1 to t9 in FIG. 8 and the write verify operation shown in FIG. 9 until all the control data becomes 0, the data writing (program) to the memory cell M can be performed. Will be done. However, in reality, the verify read of the data "3", the verify read of the data "2", and the verify read of the data "1" are selectively executed as follows. (1) To execute the verify read of the data "3", the verify read of the data "2", and the verify read of the data "1", the write verify operation is performed as shown in FIG. (2) To execute only the verify read of the data 3 and the verify read of the data 2, the times t11 to t14 are omitted from the timing chart shown in FIG. (3) In order to execute only the verify reading of the data 3 and the verify reading of the data 1, the times t7 to t10 are omitted from the timing chart shown in FIG. (4) To execute only the verify reading of the data 3, omit the times t7 to t14 from the timing chart shown in FIG. (5) To execute only the verify read of the data 2 and the verify read of the data 1, the times t2 to t6 are omitted from the timing chart shown in FIG. (6) To execute only the verify reading of the data 2, the times t2 to 6 and t11 to t14 are omitted from the timing chart shown in FIG. (7) data "1" verify read of the run only out only, omitted from the timing chart shown in FIG. 9, the time t2 ~ t10.

【0071】

FIG. 10 shows the detailed flow of the program for the multi-valued memory in the first embodiment of the present invention. The flow of this program is controlled by the control signal and control voltage generation circuit 7 shown in FIG.

【0072】

The program starts with the program start command input to the control signal input terminal 8. The counter circuit that counts the variable IWT provided in the control signal and control voltage generation circuit 7 is reset and the IWT is set to 0 (S1). The 4224 bits of initial control data input to the data input / output terminal 5 are loaded into the data storage circuit 10 (S2).

【0073】

After loading the data, a write operation is performed, at which time the variable IWT is incremented by 1 (S3). It is checked whether the output FR3 of the data detection circuit 9 is H (S4). If the output FR3 of the data detection circuit 9 is H and the data 3 remains in the data storage circuit 10, it is checked whether the variable IWT is equal to or higher than the predetermined W3 (S5). If the variable IWT is W3 or higher, the verify read of data 3 is performed (S6). If FR3 is L or the variable IWT is smaller than W3, the verify read of data 3 is omitted.

【0074】

Subsequently, it is checked whether or not the output FR2 of the data detection circuit 9 is H (S7). If the output FR2 of the data detection circuit 9 is H and the data 2 remains in the data storage circuit 10, it is checked whether the variable IWT is equal to or higher than the predetermined W2 (S8). If the variable IWT is W2 or higher, the verify read of data 2 is performed (S9). If FR2 is L or the variable IWT is smaller than W2, the verify read of data 2 is omitted.

【0075】

Subsequently, it is checked whether or not the output FR1 of the data detection circuit 9 is H (S10). If the output FR1 of the data detection circuit 9 is H and the data 1 remains in the data storage circuit 10, it is checked whether the variable IWT is equal to or higher than the predetermined W1 (S11). If the variable IWT is W1 or higher, the verify read of data 1 is performed (S12). If FR1 is L or the variable IWT is smaller than W1, the verify read of data 1 is omitted.

【0076】

Subsequently, if all of the outputs FR3, FR2, and FR1 of the data detection circuit 9 are L, the program ends (S13, S14, S15). If any one of the outputs FR3, FR2, and FR1 of the data detection circuit 9 has "H", the write operation (S3) is returned again. Every time the variable IWT increases by one, the writing voltage applied to the selected word line (the voltage of the selected word line between the times t3 and t7 shown in Fig. 8) is increased by 0.4V to 1. , "2", "3" The threshold value of the memory cell M to be written increases by about 0.4V. The predetermined W1, W2, and W3 are determined as follows.

【0077】

FIG. 11 shows an example of the write characteristics of the memory cell M. The horizontal axis is the write operation count IWT. The vertical axis shows the threshold values of the memory cell (white circle) that is the easiest to write and the memory cell (black circle) that is the most difficult to write after the number of write operations IWT. The most writable memory cell threshold reaches 0.1V after the first write operation. At this time, the threshold value of the memory cell that is the most difficult to write is -1.5V. As the number of write operations increases by 1, the voltage at the time of writing the selected word line increases by 0.4 V, so the threshold value of the memory cell also increases by approximately 0.4 V.

【0078】

After the first write operation, the threshold of any memory cell does not reach 0.4V, so it is not necessary to verify and read data "3", data "2", and data "1". From the second time onward, the threshold value of the memory cell that is the easiest to write exceeds 0.4V, so it is necessary to verify and read the data "1". Therefore, W1 is predetermined to be 2. From the 4th time onward, the threshold value of the memory cell that is the easiest to write exceeds 1.2V, so it is necessary to verify and read the data "2". Therefore, W2 is predetermined to be 4. From the 6th time onward, the threshold value of the memory cell that is the easiest to write exceeds 2.0V, so it is necessary to verify and read the data "3". Therefore, W3 is predetermined to be 6.

【0079】

After the sixth write operation, even the most difficult memory cell threshold exceeds 0.4V. Therefore, at least after IWT = 7, the output FR1 of the data detection circuit becomes L, and it is no longer necessary to verify and read the data 1. After the 8th write operation, even the most difficult memory cell threshold exceeds 1.2V. Therefore, at least after IWT = 9, the output FR2 of the data detection circuit becomes L, and it is no longer necessary to verify and read the data 2. After the 10th write operation, even the most difficult memory cell threshold exceeds 2.0V. Therefore, at least after IWT = 11, the output FR3 of the data detection circuit becomes L. When FR1, FR2, and FR3 all become "L" in this way, the program ends as shown in FIG.

【0080】

FIG. 12 shows a modified example of the data detection circuit 9 shown in FIG. N-channel MOS transistors Qn23, Qn24, Qn25, Qn26, Qn27, Qn28, Qn29, and Qn30 are provided adjacent to or close to each of the data storage circuits 10 shown in FIG. The node Nai + 1 of the second sub data circuit 21 shown in FIG. 5 is connected to the gate electrode of Qn23. The node Nai of the first sub data circuit 20 shown in FIG. 5 is connected to the gate electrode of Qn24. The node Nbi + 1 of the second sub data circuit 21 shown in FIG. 5 is connected to the gate electrode of Qn25. The node Nai of the first sub data circuit 20 shown in FIG. 5 is connected to the gate electrode of Qn26. The node Nai + 1 of the second sub data circuit 21 shown in FIG. 5 is connected to the gate electrode of Qn27. The node Nbi of the first sub data circuit 20 shown in FIG. 5 is connected to the gate electrode of Qn28. The node Nai + 1 of the second sub data circuit 21 shown in FIG. 5 is connected to the gate electrode of Qn29. The node Nai of the first sub data circuit 20 shown in FIG. 5 is connected to the gate electrode of Qn30.

【0081】

If the DECB input to the inverter I3 is L and the output PTs of the inverters I4 and I5 are H, the control data of all the data storage circuits 10 is 0. If the DEC1B input to the inverter I6 is L and the output FR1 of the inverter I7 is H, the control data of at least one data storage circuit 10 is 1. If the DEC2B input to the inverter I8 is "L" and the output FR2 of the inverter I9 is "H", the control data of at least one data storage circuit 10 is "2". If the DEC3B input to the inverter I10 is L and the output FR3 of the inverter I11 is H, the control data of at least one data storage circuit 10 is 3. The signals DECB, DEC1B, DEC2B, and DEC3B are control signals and signals from the control voltage generation circuit 7. The signals PT, FR1, FR2, and FR3 are fed back to the control signal and the control voltage generation circuit 7. The data detection circuit 9 shown in FIG. 12 enables batch data detection at high speed. Therefore, as shown in FIG. 8, the signal DEC3B can be set to L and the signal FR3 can be examined immediately before the verify reading of the data 3 (time t1 to t2 shown in FIG. 9), not during the writing operation. Just do it. Similarly, immediately before the verification reading of the data 2 (time t6 to t7 shown in FIG. 9), the signal DEC2B may be set to L and the signal FR2 may be examined. Immediately before the verification reading of the data 1 (time t10 to t11 shown in FIG. 9), the signal DEC1B may be set to L and the signal FR1 may be examined. Further, if the signal DECB is set to L and the signal PT is examined after the write verification operation shown in FIG. 9, steps S13, S14, and S15 in FIG. 10 can be performed in one step. Therefore, a useless one-time writing operation is not required, and programming can be performed at higher speed.

【0082】

FIG. 13 shows the flow of the program when the data detection circuit 9 shown in FIG. 12 is used. Steps S4, S7, and S10 are executed by examining the signals FR3, FR2, and FR1 with the signals DEC3B, DEC2B, and DEC1B as L, respectively. Step S13 is executed by examining the signal PT with the signal DECB as L. Other than that, the flow is the same as that shown in FIG.

【0083】

Next, FIG. 14 is a circuit diagram for explaining a specific configuration example of the memory cell array 1 and the bit line control circuit 2 shown in FIG. 1 in the second embodiment of the present invention. Here, an example of a 4-value storage EEPROM is shown as a multi-value memory.

【0084】

In the multi-valued memory of the second embodiment of the present invention, the first sub-data circuit 20 in the data storage circuit 10 is a clock synchronous inverter CI1 and CI2, and n-channel MOS transistors Qn33, Qn34, Qn35. It is composed. The second sub-data circuit 21 is composed of clock synchronous inverters CI3 and CI4, and n-channel MOS transistors Qn40, Qn41, and Qn42. The first and second sub-data circuits 20 and 21 store the first and second sub-data at the time of writing, respectively, and store the first and second read sub-data at the time of reading, respectively. When the node Nai in the first sub data circuit 20 is at the H level, the first sub data circuit 20 stores the first read sub data of 1 or the first sub data of 1. It is in a state of being. Further, when the node Nai + 1 in the second sub data circuit 21 is at the H level, the second read sub data in which the second sub data circuit 21 is 1 or the second read sub data of 1. It is a state in which sub data is stored. When the node Nai in the first sub data circuit 20 is at the L level, the first sub data circuit 20 stores the first read sub data of 0 or the first sub data of 0. It is in a state of being. When the node Nai + 1 in the second sub data circuit 21 is at the L level, the second sub data circuit 21 is the second read sub data of 0 or the second sub data of 0. Is in a state of remembering.

【0085】

The n-channel MOS transistors Qn32 and Qn39 are for electrically connecting the first and second sub-data circuits 20 and 21 to the data input / output lines IOL and IOU, respectively. Each gate electrode is given outputs CSLi and CSLi + 1 from the column decoder 3, respectively. For example, when CSLi becomes H, the first sub data circuit 20 of the data storage circuit 10 provided on the bit line BLi and BLi + 1 and the data input / output line IOL are electrically connected. The data input / output lines IOL and IOU are connected to the data input / output buffer 4, and sub data can be set in the first sub data circuit 20. Alternatively, the read subdata of the first subdata circuit 20 can be output to the data input / output buffer 4.

【0086】

The n-channel MOS transistors Qn36 and Qn43 control the electrical connection between the first and second sub-data circuits 20, 21 and the bit line BLi or BLi + 1. If the signal BLC1 is H and BLC2 is L, the first and second sub-data circuits 20, 21 and the bit line BLi are electrically connected. If the signal BLC1 is L and BLC2 is H, the first and second sub-data circuits 20, 21 and the bit line BLi + 1 are electrically connected.

【0087】

The n-channel MOS transistors Qn37 and Qn44 control the electrical connection between the bit line BLi and the voltage VBL1 and the electrical connection between the bit line BLi + 1 and the voltage VBL2. If the signal PRE1 is H, the bit line BLi and the voltage VBL1 are electrically connected. If the signal PRE2 is H, the bit line BLi + 1 and the voltage VBL2 are electrically connected.

【0088】

The n-channel MOS transistors Qn31 and Qn38 are for setting the sub-data of "0" in the first and second sub-data circuits 20 and 21 when the signal PRST becomes "H".

【0089】

A signal indicating the data or write state of the memory cell M is transferred via the bit line BLi or BLi + 1. In the first sub-data circuit 20, the clock-synchronized inverter CI1 and in the second sub-data circuit 21, the clock-synchronized inverter CI3 also functions as a sense amplifier that senses the logic level of the bit line BL signal. In this example, the clock synchronous inverter senses the absolute value of the voltage of the bit line BL as the logic level, but a differential type (differential) sense amplifier or the like may be used. The difference between is detected as a logical level.

【0090】

The specific configuration of the clock synchronous inverter CI shown in FIG. 14 is shown in FIGS. 15 (a) and 15 (b). FIG. 15 (a) is a symbol diagram, and FIG. 15 (b) is a detailed circuit diagram thereof. The input terminal of the inverter circuit composed of the n-channel MOS transistor Qn45 and the p-channel MOS transistor Qp8 is IN and the output terminal OUT. An n-channel MOS transistor Qn46 and a p-channel MOS transistor Qp7 are provided to activate or deactivate this inverter circuit by the signal CLOCK and its inverting signal CLOCKB. The signal CLOCK is activated with "H" and CLOCKB is activated with "L", and the signal CLOCK is deactivated with "L" and CLOCKB is deactivated with "H".

【0091】

Signals SEN1, LAT1, SEN2, LAT2, PRO1, PRO2, BLC1, BLC2, PRE1, PRE2, VRFY1, VRFY2, PRST, voltage VBL1, VBL2, VREG, VFF are control signals and output signals of control voltage generation circuit 7. It is common to all of the data storage circuits 10 shown in FIG. The voltage VCC is the power supply voltage, for example, 3.3V.

【0092】

The first and second sub-data circuits 20 and 21 store "0" or "1" sub-data, and the "1" subs stored in response to the "H" level of the bit line signal, respectively. It is configured to change the data to "0" subdata and retain the "0" subdata. That is, before the signal PRO1 or PRO2 becomes H and the voltage level of the bit line BL is sensed by the clock synchronous inverter CI1 or CI3, the bit line BL of the bit line BL depends on the first or second sub-data. The voltage level is regulated by n-channel MOS transistors Qn34, 35 or Qn41, 42. Only when the first or second sub data is 0, the voltage level of the bit line BL is set to H. When the signal PRO1 or PRO2 becomes H and the H level of the bit line is transferred to the input terminal of the clock synchronous inverter CI1 or CI3, the node Nai or Nai + 1 becomes L level. Will be done. Further, the clock synchronous inverter CI2 or CI4 stores the sub data of 0.

【0093】

Therefore, the originally stored "0" sub-data is not changed. On the other hand, when the originally stored sub-data is "1", when the bit line BL level is "H", it is changed to the sub-data of "0" and stored, and the bit line BL level is "L". Holds sub-data of time "1". The first and second sub-data circuits 20 and 21 can be similarly realized by using various circuits having the above-mentioned functions, regardless of the configuration example shown in FIG.

【0094】

16 and 17 show the operation of reading the quaternary data stored in the memory cell. Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. If the memory level is limited to 3 levels, ternary memory can be easily performed. Here, the voltage VBL2 is 0V, the BLC2 is "L", the PRE2 is "H", the PRST is "L", and the bit line BLi + 1 remains 0V, so the display in FIG. 16 is omitted.

【0095】

First, the voltage VBL1 becomes 1.3V and the bit line BLi is charged to H (t1). In addition, the signal BLC1 becomes H and the bit line BLi is selected (t1). The voltage VFF is fixed at 2V to stabilize the sense sensitivity of the clock synchronous inverters CI1 and CI3 that operate as a sense amplifier. Subsequently, the signal PRE1 becomes L and the bit line BLi and the voltage VBL1 are separated. Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 1.8V (t2). Here, Table 5 shows the relationship between the data stored in the memory cell M and the threshold value.

【0096】

[Table 5]

<img file="JPP3409986B2_D0005.tif" />【0097】

When the selected word line WL2 reaches 1.8V, the bit line BLi remains H only when the memory cell stores 3 data. In other cases, the bit line BLi is L. After the selection gates SG1, SG2 and word lines WL1 to WL4 are reset to 0V (t3), the signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t4). When the signal PRO2 becomes H (t5) and the signal SEN2 becomes H (t6), the clock synchronous inverter CI3 is activated and the voltage of the bit line BLi is sensed. When the signal LAT2 becomes H (t7), the clock synchronous inverter CI4 is activated and the logic level of the sensed bit line BLi signal is latched. The signal PRO2 becomes L (t8), and the operation of detecting whether the threshold value of the memory cell M is 1.8V or more ends. Only when the memory cell stores "3" data, the second read sub data of the second sub data circuit 21 becomes "0". Otherwise, the second read subdata is 1.

【0098】

Then, the operation of detecting whether the threshold value of the memory cell M is 0.0V or more is started. When the voltage VBL1 becomes 1.3V (t8) and the signal PRE1 becomes H, the bit line BLi is charged to H (t9). Subsequently, the signal PRE1 becomes L and the bit line BLi and the voltage VBL1 are separated. Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 0.0V (t10). At the same time, the signal VRFY2 is set to 1.3V and the n-channel MOS transistor Qn41 becomes conductive. As a result, the potential of the bit line BLi becomes L by the n-channel MOS transistors Qn41 and Qn42 only when the second read subdata is 0 (t10 to t11).

【0099】

When the selected word line WL2 becomes 0.0V, the bit line BLi remains H only when the memory cell stores 1 or 2 data. In other cases, the bit line BLi is L. After the selection gates SG1, SG2 and word lines WL1 to WL4 are reset to 0V (t11), the signals SEN1 and LAT1 become L and the clock synchronous inverters CI1 and CI2 are deactivated (t12). When the signal PRO1 becomes H (t13) and the signal SEN1 becomes H (t14), the clock synchronous inverter CI1 is activated and the voltage of the bit line BLi is sensed. When the signal LAT1 becomes H (t15), the clock synchronous inverter CI2 is activated and the logic level of the sensed bit line BLi signal is latched. The signal PRO1 becomes L (t16), and the operation of detecting whether the threshold value of the memory cell M is 0.0V or more ends. Only when the memory cell stores "1" or "2" data, the first read sub data of the first sub data circuit 20 becomes "0". Otherwise, the first read subdata is 1.

【0100】

Then, the operation of detecting whether the threshold value of the memory cell M is 1.0 V or more is started. When the voltage VBL1 becomes 1.3V (t16) and the signal PRE1 becomes H, the bit line BLi is charged to H (t17). Subsequently, the signal PRE1 becomes L and the bit line BLi and the voltage VBL1 are separated. Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 1.0V (t18).

【0101】

When the selected word line WL2 reaches 1.0V, the bit line BLi remains H only if the memory cell stores 3 or 2 data. In other cases, the bit line BLi is L. After the selection gates SG1, SG2 and word lines WL1 to WL4 are reset to 0V (t19), the signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t20). When the signal PRO2 becomes H (t21) and the signal SEN2 becomes H (t22), the clock synchronous inverter CI3 is activated and the voltage of the bit line BLi is sensed. When the signal LAT2 becomes H (t23), the clock synchronous inverter CI4 is activated and the logic level of the sensed bit line BLi signal is latched. The signal PRO2 becomes L (t24), and the operation of detecting whether the threshold value of the memory cell M is 1.0 V or more ends. Only when the memory cell stores 3 or 2 data, the second read sub data of the second sub data circuit 21 becomes 0. Otherwise, the second read subdata is 1.

【0102】

The signal BLC1 is L, the signal PRE1 is H, the voltage VFF is VCC, and the operation of storing the data of the memory cell M in the data storage circuit 10 as read data ends.

【0103】

When the signals CSLi and CSLi + 1 become H (t26), the first read subdata is output to the data input / output line IOL and the second read subdata is output to the data input / output line IOU. It is output to the outside from the data input / output terminal 5 via the output buffer 4. Table 6 shows the relationship between the quaternary data of the memory cell and the first and second read sub-data.

【0104】

[Table 6]

<img file="JPP3409986B2_D0006.tif" />【0105】

FIG. 18 shows the initial setting and writing operation of the control data to the data storage circuit 10. Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. If the memory level is limited to 3 levels, ternary memory can be easily performed.

【0106】

The initial setting of the control data in the data storage circuit 10 provided in the bit line BLi is performed as follows. The initial sub data of the first sub data circuit 20 is transferred to the data input / output line IOL, the initial sub data of the second sub data circuit 21 is transferred to the data input / output line IOU, and the signal CSLi + 1 becomes H. , The initial sub-data is stored in the first and second sub-data circuits 20 and 21. Initial control data is set in any number of data storage circuits 10 by changing the selection of the signal CSL. At this time, the relationship between the initial control data and the initial sub data is shown in Table 7 below.

【0107】

[Table 7]

<img file="JPP3409986B2_D0007.tif" />【0108】

Here, it is desirable to set the signal PRST to H and reset the control data of all the data storage circuits 10 to 0 before setting all the initial control data. As will be described later, the state of the memory cell M cannot be changed by the control data 0. Therefore, if the initial control data is set from the outside only in the desired data storage circuit 10 among the 2112 data storage circuits 10. Good. Of course, initial control data may be set externally in all 2112 data storage circuits 10. The signal SEN1 is H, LAT1 is H, VRFY1 is L, SEN2 is H, LAT2 is H, VRFY2 is L, voltage VREG is 0V, and VFF is VCC. The display to is omitted.

【0109】

In the write operation, the signal PRE1 first becomes L and the bit line BLi and the voltage VBL1 are separated (t1). At the same time, the signal BLC1 becomes H and the bit line BLi is selected (t1). In addition, the signal DRSTB becomes L and the data detection circuit 9 is reset (t1 to t2). The voltage VBL2 becomes VCC, and the non-selection bit line BLi + 1 is charged to VCC via the n-channel MOS transistor Qn44 (t2 to t3). In addition, the signal PRO1 becomes H, and the selected bit line BLi is charged according to the first sub data (t2 to t3). At this time, the bit line BLi is charged to VCC when the control data is 0 or 3, and is set to 0V when the control data is 1 or 2. Also, the selection gate SG1 and the word lines WL1 ~ 4 are set to VCC (t2 ~ t3). The selection gate SG2 remains at 0V. After this, the signal PRO2 becomes 1.8V, and the voltage of the selected bit line BLi is changed according to the second sub data (t3). When the second sub data is 0, the bit line BLi, which was 0V in advance, is charged to 0.8V, which is lower than 1.8V by the threshold value (for example, 1V) of the n-channel MOS transistor Qn40. When the second sub-data is 0, the bit line BLi, which was previously VCC, remains VCC because the n-channel MOS transistor Qn40 is non-conducting. When the second sub data is 1, the bit line BLi is 0V because the n-channel MOS transistor Qn40 is conductive.

【0110】

As a result, the bit line BLi is set to VCC when the control data is 0, 0.8V when the control data is 1, 0V when the control data is 2, and when the control data is 3. It becomes 0V. The selected word line WL2 is set to 20V and the non-selected word line is set to 10V, and electron injection into the floating gate of the memory cell starts according to the control data (t3 to t7). When the bit line BL is 0V, electron injection occurs when the potential difference between the memory cell channel and the word line is 20V. When the bit line BL is 0.8V, electron injection occurs when the potential difference between the memory cell channel and the word line is 19.2V, but it is smaller than when the potential difference between the memory cell channel and the word line is 20V. When the bit line BL is VCC, electron injection does not substantially occur because the potential difference between the channel of the memory cell and the word line is small.

【0111】

While the selected word line WL2 is set to 20V (t3 to t7), the control data stored in the data storage circuit 10 is detected. The column decoder 3 selects CSL0 and CSL1 to CSL4222 and CSL4223 in order, and the control data is transmitted to the data detection circuit 9 via the data input / output lines IOL and IOU. As an example, the case where CSLi and CSLi + 1 are selected is shown in FIG. When CSLi and CSLi + 1 become H (t4), control data is output to the data input / output lines IOL and IOU, and when the signal DT becomes H, the control data is detected by the data detection circuit 9 (t4). t5 ~ t6). If even one of the data storage circuits 10 stores data "1", the signal FR1 becomes "H". If even one of the data storage circuits 10 stores data "2", the signal FR2 becomes "H". If even one of the data storage circuits 10 stores data "3", the signal FR3 becomes "H".

【0112】

After the word lines WL1 ~ 4 are dropped to VCC (t7 ~ t8), the voltage VBL2 becomes 0V, the signal PRE1 becomes H, and the bit lines BLi and BLi + 1 are reset to 0V (t8 ~ t9). .. The voltage VBL1 is 0V. Word lines WL1 ~ 4 are also reset to 0V (t8 ~ t9).

【0113】

19, 20 and 21 show a write verification operation for detecting the write state of the memory cell after the write operation performed at the times t1 to t9 shown in FIG. Here, the case where the bit lines BL0, BL2, ..., BLi, ..., BL4222 are selected (BLi is shown as a representative) and the word line WL2 is selected is shown. If the memory level is limited to 3 levels, ternary memory can be easily performed. Here, the voltage VBL2 is 0V, BLC2 is "L", PRE2 is "H", PRST is "L", CSLi is "L", CSLi + 1 remains "L", and the bit line BLi + 1 is Since it remains at 0V, the display in FIGS. 19 to 21 is omitted.

【0114】

First, the voltage VBL1 becomes 1.3V and the bit line BLi is charged to H (t1). In addition, the signal BLC1 becomes H and the bit line BLi is selected (t1). The voltage VFF is fixed at 2.0V. Subsequently, the signal PRE1 becomes L and the bit line BLi and the voltage VBL1 are separated. Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 2.0V (t2).

【0115】

When the selected word line WL2 reaches 2.0V, the bit line BLi will be changed if the memory cell corresponding to the data storage circuit 10 that stores the control data of "3" has reached the state of storing the "3" data. It remains "H". If the memory cell corresponding to the data storage circuit 10 storing the control data of 3 has not reached the state of storing the 3 data, the bit line BLi becomes L. Since the memory cell corresponding to the data storage circuit 10 storing the control data of 2 or 1 does not reach the state of storing the 3 data, the bit line BLi becomes L. After the selection gates SG1, SG2 and word lines WL1 to WL4 are reset to 0V (t3), the signal VRFY2 becomes H and the bit line BLi becomes H only when the second sub data is 0. To be (t4). Here the voltage VREG is VCC. The signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t6). When the signal PRO2 becomes H (t7) and the signal SEN2 becomes H (t8), the clock synchronous inverter CI3 is activated and the voltage of the bit line BLi is sensed. When the signal LAT2 becomes H (t9), the clock synchronous inverter CI4 is activated and the logic level of the sensed bit line BLi signal is latched. Detection of whether or not the signal PRO2 becomes L (t10) and the memory cell corresponding to the data storage circuit 10 storing the control data of 3 has reached the state of storing 3 data. (Verify reading of data "3") ends. At this point, only when it is detected that the memory cell corresponding to the data storage circuit 10 that stores the control data of "3" has reached the state of storing the "3" data, is "3". The control data of the data storage circuit 10 that stores the control data is changed to 0 data, and in other cases, the control data is retained (not changed).

【0116】

Then, the operation of detecting whether or not the memory cell corresponding to the data storage circuit 10 storing the control data of 2 has reached the state of storing the 2 data is started. The voltage VBL1 becomes 1.3V (t10), the signal PRE1 becomes H, and the bit line BLi becomes H (t11). Subsequently, the signal PRE1 becomes L and the bit line BLi and the voltage VBL1 are separated. Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 1.2V (t12). At the same time, the signal VRFY1 is set to 1.3V and the n-channel MOS transistor Qn34 becomes conductive. As a result, the potential of the bit line BLi becomes L by the n-channel MOS transistors Qn34 and Qn35 only when the first sub-data is 0 (t12 to t13).

【0117】

When the selected word line WL2 reaches 1.2V, the bit line BLi becomes the bit line BLi if the memory cell corresponding to the data storage circuit 10 that stores the control data of "2" has reached the state of storing the "2" data. It remains "H". If the memory cell corresponding to the data storage circuit 10 storing the control data of 2 has not reached the state of storing the 2 data, the bit line BLi becomes L. Since the memory cell corresponding to the data storage circuit 10 storing the control data of 1 does not reach the state of storing the 2 data, the bit line BLi becomes L. After the selection gates SG1, SG2 and word lines WL1 to WL4 are reset to 0V (t13), the signal VRFY2 becomes H and the bit line BLi becomes H only when the second sub data is 0. To be (t14). Here the voltage VREG is VCC. The signals SEN2 and LAT2 become L and the clock synchronous inverters CI3 and CI4 are deactivated (t16). When the signal PRO2 becomes H (t17) and the signal SEN2 becomes H (t18), the clock synchronous inverter CI3 is activated and the voltage of the bit line BLi is sensed. When the signal LAT2 becomes H (t19), the clock synchronous inverter CI4 is activated and the logic level of the sensed bit line BLi signal is latched. Detection of whether or not the signal PRO2 becomes L (t20) and the memory cell corresponding to the data storage circuit 10 storing the control data of 2 has reached the state of storing 2 data. (Verify reading of data "2") ends.

【0118】

At this point, if it is detected that the memory cell corresponding to the data storage circuit 10 that stores the control data of "3" has reached the state of storing the "3" data, the data storage circuit 10 The control data has been changed to "0" data. Only when it is detected that the memory cell corresponding to the data storage circuit 10 storing the control data of "2" has reached the state of storing the "2" data, the control data of the data storage circuit 10 is displayed. It has been changed to "1" data. Otherwise, the control data is retained (unchanged).

【0119】

Subsequently, the operation of detecting whether or not the memory cell corresponding to the data storage circuit 10 storing the control data of 1 has reached the state of storing the 1 data is started. The voltage VBL1 becomes 1.3V (t20), the signal PRE1 becomes H, and the bit line BLi becomes H (t21). Subsequently, the signal PRE1 becomes L and the bit line BLi and the voltage VBL1 are separated. Then, the selection gates SG1 and SG2 of the selected block, and the non-selection word lines WL1, 3, and 4 are set to the power supply voltage VCC, and the selection word line WL2 is set to 0.4V (t22).

【0120】

When the selected word line WL2 becomes 0.4V, the bit line BLi becomes the bit line BLi if the memory cell corresponding to the data storage circuit 10 that stores the control data of "1" has reached the state of storing the "1" data. It remains "H". If the memory cell corresponding to the data storage circuit 10 storing the control data of 1 has not reached the state of storing the 1 data, the bit line BLi becomes L. After the selection gates SG1, SG2 and word lines WL1 to WL4 are reset to 0V (t23), the signal PRO2 becomes 1.3V (t24), and when the second sub data is 1, the bit line BLi is L. Will be reset. If the second subdata is 0 and the bit line BLi is originally H, the bit line BLi remains H. When the second sub data is 0 and the bit line BLi is originally L, if the threshold value of the n-channel MOS transistor Qn40 is 1V, the bit line BLi is at most 0.3 due to the 1.3V signal PRO2. Only V. 0. If the clock synchronous inverter CI1 is set so that the voltage of the 3V bit line BLi is detected as L, the bit line BLi remains L. Subsequently, the bit line BLi is changed to H only when the signal VRFY1 becomes H and the first sub data is 0 (t26). The signals SEN1 and LAT1 become L and the clock synchronous inverters CI1 and CI2 are deactivated (t28). When the signal PRO1 becomes H (t29) and the signal SEN1 becomes H (t30), the clock synchronous inverter CI1 is activated and the voltage of the bit line BLi is sensed. When the signal LAT1 becomes H (t31), the clock synchronous inverter CI2 is activated and the logic level of the bit line BLi signal is latched. Whether or not the signal PRO1 becomes L (t32) and the memory cell corresponding to the data storage circuit 10 storing the control data of 1 has reached the state of storing 1 data. The operation to detect (verify reading of data "1") is completed. At this point, when it is detected that the memory cell corresponding to the data storage circuit 10 storing the control data of "3" has reached the state of storing the "3" data, and when it is detected as "2". When it is detected that the memory cell corresponding to the data storage circuit 10 storing the control data has reached the state of storing the "2" data, and the data storing the control data of "1". Only when it is detected that the memory cell corresponding to the storage circuit 10 has reached the state of storing "1" data, the control data of the data storage circuit 10 is changed to "0" data, and in other cases, the control data is changed to "0" data. , Control data is retained (not changed).

【0121】

The signal BLC1 is L, the signal PRE1 is H, the voltage VFF is VCC, and the write verification operation ends. In the write verify operation, the control data stored in the data storage circuit 10 is changed from the write state of the memory cell as shown in Table 8.

【0122】

[Table 8]

<img file="JPP3409986B2_D0008.tif" />【0123】

Therefore, by repeating the write operation shown in t1 to t9 of FIG. 18 and the write verify operation shown in FIGS. 19 to 21 until all the control data becomes 0, data writing to the memory cell M ( Program) is done. However, preferably, similarly to the first embodiment as described above, the verify read of the data 3, the verify read of the data 2, and the verify read of the data 1 are selectively performed as follows. Execute. (1) In order to execute the verify read of the data "3", the verify read of the data "2", and the verify read of the data "1", all of them may be as shown in FIGS. 19 to 21. (2) In order to execute only the verify reading of the data 3 and the verify reading of the data 2, it is sufficient to perform as shown in FIGS. 19 to 21. (3) In order to execute only the verify reading of the data 3 and the verify reading of the data 1, the times t11 to t21 may be omitted from those shown in FIGS. 19 to 21. (4) In order to execute only the verify reading of the data 3, the times t11 to t34 may be omitted from those shown in FIGS. 19 to 21. However, at t11, the voltage VBL1 is reset to 0V, VFF is reset to VCC, the signal PRE1 is reset to H, and BLC1 is reset to L. (5) In order to execute only the verify reading of the data 2 and the verify reading of the data 1, the times t1 to t11 may be omitted from those shown in FIGS. 19 to 21. However, at t11, set the voltage VBL1 to 1.3V, VFF to 2.0V, and BLC1 to "H". (6) In order to execute only the verify reading of the data 2, the times t1 to 11 may be omitted from those shown in FIGS. 19 to 21. However, at t11, set the voltage VBL1 to 1.3V, VFF to 2.0V, and BLC1 to "H". (7) In order to execute only the verify reading of the data 1, the times t1 to t21 may be omitted from those shown in FIGS. 19 to 21. However, at t21, set the voltage VBL1 to 1.3V, VFF to 2.0V, and BLC1 to "H".

【0124】

Here, in the write verification operation according to the second embodiment of the present invention, only the second sub data circuit 21 senses the bit line potential when executing the verify read of the data 2. That is, if the sense sensitivity is deviated between the first sub data circuit 20 and the second sub data circuit 21 constituting the data storage circuit 10, the memory cell is in a state of storing "2" data. If it has reached, even if you try to change the control data of the data storage circuit 10 from "2" to "0" by using these two sub data circuits together when verifying and reading the data "2", the control data will be, for example. It may be changed from "2" to "3". Therefore, there is a possibility that the data "3" will be written to the memory cell in which the data "2" is to be written.

【0125】

In order to avoid such a problem, in the second embodiment of the present invention, only the second sub data circuit 21 senses the bit linear potential for the verify reading of the data 2 in the write verification operation, and the memory cell. When has reached the state of storing "2" data, the control data of the data storage circuit 10 is temporarily changed from "2" to "1" when the verify reading of the data "2" is performed. Then, when the verify read of the data "1" is executed after the verify read of the data "2", the control data previously changed from "2" to "1" is always changed to "0" here. Become. That is, the control data of the data storage circuit 10 is correctly converted, and a stable write verification result can be obtained.

【0126】

FIG. 22 shows the detailed flow of the program for the multi-valued memory in the second embodiment of the present invention. The flow of this program is controlled by the control signal and control voltage generation circuit 7 shown in FIG. Here, unlike the program flow shown in FIG. 10, it is set so that when the verify read of data 2 is executed, the verify read of data 1 is always executed subsequently. ..

【0127】

The program starts with the program start command input to the control signal input terminal 8. The counter circuit that counts the variable IWT provided in the control signal and control voltage generation circuit 7 is reset and the IWT is set to 0 (S1). The 4224 bits of initial control data input to the data input / output terminal 5 are loaded into the data storage circuit 10 (S2).

【0128】

After loading the data, a write operation is performed, at which time the variable IWT is incremented by 1 (S3). It is checked whether the output FR3 of the data detection circuit 9 is H (S4). If the output FR3 of the data detection circuit 9 is H and the data 3 remains in the data storage circuit 10, it is checked whether the variable IWT is equal to or higher than the predetermined W3 (S5). If the variable IWT is W3 or higher, the verify read of data 3 is performed (S6). If FR3 is L or the variable IWT is smaller than W3, the verify read of data 3 is omitted.

【0129】

Subsequently, it is checked whether or not the output FR2 of the data detection circuit 9 is H (S7). If the output FR2 of the data detection circuit 9 is H and the data 2 remains in the data storage circuit 10, it is checked whether the variable IWT is equal to or higher than the predetermined W2 (S8). If the variable IWT is W2 or higher, the verify read of data 2 is performed (S9). If FR2 is L or the variable IWT is smaller than W2, the verify read of data 2 is omitted.

【0130】

Subsequently, it is checked whether or not the output FR1 of the data detection circuit 9 is H (S10). If the output FR1 of the data detection circuit 9 is H and the data 1 remains in the data storage circuit 10, it is checked whether the variable IWT is equal to or higher than the predetermined W1 (S11). If the variable IWT is W1 or higher, the verify read of data 1 is performed (S12). If FR1 is L or the variable IWT is smaller than W1, the verify read of data 1 is omitted. However, when the verify read (S9) of the data "2" is performed, the verify read (S12) of the data "1" is always performed.

【0131】

Subsequently, if all of the outputs FR3, FR2, and FR1 of the data detection circuit 9 are L, the program ends (S13, S14, S15). If any one of the outputs FR3, FR2, and FR1 of the data detection circuit 9 has "H", the write operation (S3) is returned again. As the variable IWT increases by one, the writing voltage applied to the selected word line (the voltage of the selected word line between times t3 and t7 shown in FIG. 17) is increased by 0.4V to 1. , "2", "3" The threshold value of the memory cell M to be written increases by about 0.4V. The predetermined W1, W2, and W3 are determined as follows.

【0132】

This will be described again with reference to FIG. FIG. 11 shows an example of the write characteristics of the memory cell M. The horizontal axis is the write operation count IWT. The vertical axis shows the threshold values of the memory cell (white circle) that is the easiest to write and the memory cell (black circle) that is the most difficult to write after the number of write operations IWT. The most writable memory cell threshold reaches 0.1V after the first write operation. At this time, the threshold value of the memory cell that is the most difficult to write is -1.5V. As the number of write operations increases by 1, the voltage at the time of writing the selected word line increases by 0.4 V, so the threshold value of the memory cell also increases by approximately 0.4 V. However, the threshold value of the memory cell M connected to the data storage circuit 10 that stores the control data of 1 is 0.8V lower.

【0133】

After the first write operation, the threshold of any memory cell does not reach 0.4V, so it is not necessary to verify and read data "3", data "2", and data "1". From the 4th time onward, the threshold value of the memory cell that is the easiest to write exceeds 1.2V, so it is necessary to verify and read the data "2". Further, since the threshold value of the memory cell M connected to the data storage circuit 10 that stores the control data of 1 exceeds 0.4V, it is necessary to verify and read the data 1. Therefore, W1 and W2 are predetermined as 4. From the 6th time onward, the threshold value of the memory cell that is the easiest to write exceeds 2.0V, so it is necessary to verify and read the data "3". Therefore, W3 is predetermined to be 6.

【0134】

After the 9th write operation, that is, after IWT = 9, the outputs FR1 and FR2 of the data detection circuit become L. After the 10th write operation, even the most difficult memory cell threshold exceeds 2.0V. Therefore, at least after IWT = 11, the output FR3 of the data detection circuit becomes L.

【0135】

FIG. 23 shows the flow of the program when the data detection circuit 9 shown in FIG. 12 is used. Steps S4, S7, and S10 are executed by examining the signals FR3, FR2, and FR1 with the signals DEC3B, DEC2B, and DEC1B as L, respectively. Step S13 is executed by examining the signal PT with the signal DECB as L. Other than that, the flow is the same as that shown in FIG. 22, and the program is executed in the same flow as that of the first embodiment.

【0136】

In the second embodiment of the present invention, the writing operation shown in time t1 to t9 in FIG. 18 and the writing verification operation shown in FIGS. 19 to 21 are repeated until all the control data becomes 0. Data may be written. In this case, as the data detection circuit 9 shown in FIG. 1, the circuit configuration shown in FIG. 24 can be used. That is, in the data detection circuit shown in FIG. 24, the gate electrode of the n-channel MOS transistor Qn47 and one end of the current path of the n-channel MOS transistor Qn49 are connected to the node Nai in the first sub-data circuit 20, and the second sub-data circuit 20 is connected. The gate electrode of the n-channel MOS transistor Qn48 and one end of the current path of the n-channel MOS transistor Qn50 are connected to the node Nai + 1 in the sub-data circuit 21. The n-channel MOS transistors Qn47 and Qn48 are circuits for detecting whether or not all sub-data circuits store "0" sub-data. When all the sub data circuits store "0" sub data, the signal line PT and the ground level become non-conducting, and even one of the 4224 sub data circuits stores "1" sub data. If so, the signal line P T and the ground level become conductive. The n-channel MOS transistors Qn49 and Qn50 are circuits for storing "0" sub-data in all sub-data circuits. When the signal PRST becomes H, 0 sub-data is set in the 4224 sub-data circuits.

【0137】

Further, the circuit configuration of the data storage circuit can be easily implemented by using the one of the first embodiment shown in FIG. On the contrary, in the first embodiment, it can be easily implemented by using a data storage circuit using a clock synchronous inverter as a sense amplifier as shown in FIG.

【0138】

As described above, the multi-valued memory in the first invention of the present application is an electrically writable memory cell (M) having at least an erase state, a first write state, and a second write state, and the memory cell. A write operation in which a write voltage is applied to (M) to perform a predetermined write, and a first write confirmation operation for confirming whether or not the memory cell (M) has reached the first write state after the write operation. Alternatively, a write circuit (2, 3,) that writes data while repeating the second write confirmation operation for confirming whether or not the memory cell (M) has reached the second write state after the write operation. It is a multi-valued memory provided with 6, 7, 9), and the write circuit (2, 3, 6, 7, 9) performs the second write confirmation operation during the first period at the beginning of data writing. The write operation and the first write confirmation operation are repeated, and the second period after the first period includes the write operation, the first write confirmation operation, and the second write confirmation operation. It is characterized by repeating.

【0139】

Further, as a desirable embodiment of the present invention, the following can be mentioned. (1) The writing circuit (2, 3, 6, 7, 9) omits the first writing confirmation operation in the third period after the second period, and performs the writing operation and the first Repeat the write confirmation operation of 2. (2) When the writing circuit (2, 3, 6, 7, 9) confirms that the memory cell (M) has reached the predetermined first writing state or the second writing state, the memory cell Change the write voltage applied to (M).

【0140】

Alternatively, the multi-valued memory in the first invention of the present application includes a plurality of memory cells (M) having at least an erase state, a first write state, and a second write state and being electrically writable, and the plurality of memories. A write operation in which a write voltage is applied to the cell (M) to perform a predetermined write, and a memory cell (M) that should be in the first write state among the plurality of memory cells (M) after the write operation are the first. The first write confirmation operation for confirming whether or not the write state has been reached, or the memory cell (M) to be in the second write state among the plurality of memory cells (M) after the write operation is described above. A multi-valued memory equipped with write circuits (2, 3, 6, 7, 9) that write data while repeating the second write confirmation operation to confirm whether or not the second write state has been reached. , The writing circuit (2, 3, 6, 7, 9) omits the second writing confirmation operation during the first period at the beginning of data writing, and performs the writing operation and the first writing confirmation operation. Repeatedly, the second period after the first period is characterized in that the writing operation, the first writing confirmation operation, and the second writing confirmation operation are repeated.

【0141】

Further, as a desirable embodiment of the present invention, the following can be mentioned. (1) The writing circuit (2, 3, 6, 7, 9) omits the first writing confirmation operation in the third period after the second period, and performs the writing operation and the first Repeat the write confirmation operation of 2. (2) When the write circuit (2, 3, 6, 7, 9) confirms that the memory cell (M) to be in the first write state has reached the first write state, the first When the write voltage applied to the memory cell (M) to be in the second write state is changed and it is confirmed that the memory cell (M) to be in the second write state has reached the second write state, the first Change the write voltage applied to the memory cell (M) that should be in the write state of 2. (3) The first period is predetermined. (4) When the writing circuit (2, 3, 6, 7, 9) confirms that all of the memory cells (M) to be in the first writing state have reached the first writing state, the writing circuit (2, 3, 6, 7, 9) is described. The first write confirmation operation is omitted, and the write operation and the second write confirmation operation are repeated. (5) The writing circuit (2, 3, 6, 7, 9) collectively determines whether or not all of the memory cells (M) that should be in the first writing state have reached the first writing state. To detect. (6) The writing circuit (2, 3, 6, 7, 9) collectively determines whether or not all of the memory cells (M) that should be in the second writing state have reached the second writing state. To detect. (7) The write voltage applied to the memory cell (M) to be in the first write state is equal to the write voltage applied to the memory cell (M) to be in the second write state. (8) The writing circuit (2, 3, 6, 7, 9) terminates the writing operation after confirming that all of the written memory cells (M) have reached a predetermined writing state. .. (9) The writing circuit (2, 3, 6, 7, 9) collectively detects that all of the written memory cells (M) have reached a predetermined writing state.

【0142】

Further, the multi-valued memory in the second invention of the present application includes a memory cell array (1) composed of a plurality of non-volatile memory cells (M), each capable of storing n-value (n 3) data, and the memory. A data storage circuit (10) for storing control data that determines a write control voltage applied during a write operation to a selected memory cell (M) in the cell array (1) is provided, and the data storage circuit (10) is provided. , The data storage circuit that stores the first control data by applying the write control voltage to the memory cell (M) selected based on the control data stored in the data storage circuit (10). (10) detects whether or not the write state of the selected memory cell (M) has reached the first state, and if so, changes the control data to the second control data. The data storage circuit (10) that stores the control data of 2 detects whether or not the write state of the selected memory cell (M) has reached the second state, and controls if the write state has reached the second state. It is characterized by changing the data to the third control data.

【0143】

Further, as a desirable embodiment of the present invention, the following can be mentioned. (1) The first state has a first threshold level, and the second state has a second threshold level lower than the first threshold level. (2) The data storage circuit (10) is composed of a first sub data circuit (CI1, CI2, Qn33, Qn34, Qn35) and a second sub data circuit (CI3, CI4, Qn40, Qn41, Qn42). , The first sub-data circuit (CI1, CI2, Qn33, Qn34, Qn35) stores the first logic level sub-data, and the second sub-data circuit (CI3, CI4, Qn40, Qn41, Qn42) stores the first logic level sub-data. The sub-data of the first logic level is stored, the first control data is stored, and the sub-data of the first logic level is stored in the first sub-data circuit (CI1, CI2, Qn33, Qn34, Qn35). The second sub-data circuit (CI3, CI4, Qn40, Qn41, Qn42) stores the second logic level sub-data, stores the second control data, and stores the first sub-data circuit (CI3, CI4, Qn40, Qn41, Qn42). CI1, CI2, Qn33, Qn34, Qn35) stores the sub-data of the second logic level, and the second sub-data circuit (CI3, CI4, Qn40, Qn41, Qn42) stores the sub-data of the second logic level. Is stored, and the third control data is stored. (3) The data storage circuit (10) detects whether or not the write state of the selected memory cell (M) has reached the first state, on one of the first and second sub-data circuits. Then, whether or not the write state of the selected memory cell (M) has reached the second state is detected by the other of the first and second sub-data circuits. (4) Further, it is collectively determined whether or not all the sub-data stored in the first and second sub-data circuits constituting the data storage circuit (10) are at the second logic level. It is provided with a circuit for detecting. (5) The memory cell (M) can store four values, and the first and second sub data circuits each include one flip-flop circuit. (6) The memory cell (M) can store three values, and the first and second sub data circuits each include one flip-flop circuit.

【0144】

The present invention is not limited to the first and second embodiments as described above. For example, a multi-valued storage non-volatile semiconductor storage device having a NOR type memory cell array and a hot electron injection writing type multi-valued storage non-volatile semiconductor storage device can be similarly implemented, and other gist of the present invention is not deviated. It is possible to carry out various modifications within the range.

【0145】

[Effect of the invention]

The multi-valued memory according to the first invention of the present application performs write verification by paying attention only to a write state that requires write verification performed after writing. That is, the data "1", "2", and "3" verification read is selected and executed. Since there is a difference in the time it takes for the memory cells to reach their respective write states, only the necessary verify reads are executed in consideration of this. As a result, redundant write verification time can be omitted, and a multi-valued memory that can be written at high speed can be realized.

【0146】

Further, the multi-valued memory according to the second invention of the present application performs a sense operation with only one sub data circuit to detect a certain write state at the time of write verification performed after writing. As a result, the write verification result is stable, and a highly reliable multi-valued memory can be realized.

[Simple explanation of drawings]

[Figure 1]

The block diagram which shows the schematic structure of the multi-valued memory of this invention.

[Figure 2]

The circuit diagram which shows the structural example of the memory cell array and the bit line control circuit shown in FIG. 1 in the 1st Embodiment of this invention.

[Fig. 3]

Sectional drawing of the memory cell and the selective transistor shown in FIG.

[Fig. 4]

Sectional view of the NAND cell unit shown in FIG.

[Fig. 5]

A circuit diagram for explaining a more specific configuration example of the memory cell array and the data storage circuit shown in FIG.

[Fig. 6]

The figure which shows the structural example of the data detection circuit shown in FIG.

[Fig. 7]

A timing chart showing a read operation of quaternary data stored in a memory cell in the first embodiment of the present invention.

[Fig. 8]

A timing chart showing an initial setting and writing operation of control data to a data storage circuit in the first embodiment of the present invention.

[Fig. 9]

A timing chart showing a write verification operation in the first embodiment of the present invention.

[Fig. 10]

The flowchart which shows the flow of the program with respect to the multi-valued memory in the 1st Embodiment of this invention.

[Fig. 11]

A diagram showing write characteristics of a memory cell in the first embodiment of the present invention. [Fig. 12]

The figure which shows the modification of the data detection circuit shown in FIG.

[Fig. 13]

The flowchart which shows the modification of the program flow with respect to the multi-valued memory in the 1st Embodiment of this invention.

[Fig. 14]

A circuit diagram for explaining a specific configuration example of the memory cell array and the bit line control circuit shown in FIG. 1 in the second embodiment of the present invention.

[Fig. 15]

The symbol diagram of the clock synchronous inverter shown in FIG. 14 and its detailed circuit diagram.

[Fig. 16]

A timing chart showing a read operation of quaternary data stored in a memory cell in the second embodiment of the present invention.

[Fig. 17]

A timing chart showing a read operation of quaternary data stored in a memory cell in the second embodiment of the present invention.

[Fig. 18]

A timing chart showing an initial setting and writing operation of control data to a data storage circuit in the second embodiment of the present invention.

[Fig. 19]

A timing chart showing a write verification operation in the second embodiment of the present invention.

[Fig. 20]

A timing chart showing a write verification operation in the second embodiment of the present invention.

[Fig. 21]

A timing chart showing a write verification operation in the second embodiment of the present invention.

[Fig. 22]

The flowchart which shows the flow of the program with respect to the multi-valued memory in the 2nd Embodiment of this invention.

[Fig. 23]

The flowchart which shows the modification of the program flow with respect to the multi-valued memory in the 1st Embodiment of this invention.

[Fig. 24]

The figure which shows the modification of the data detection circuit shown in FIG.

[Explanation of symbols]

1 ... memory cell array, 2 ... Bit line control circuit, 3 ... column decoder, 4 ... Data I / O buffer, 5 ... Data input / output terminal, 6 ... Word line control circuit, 7 ... Control signal and control voltage generation circuit, 8 ... Control signal input / output terminal, 9 ... Data detection circuit, 10 ... data storage circuit, 11 ... p-type semiconductor substrate, 12 ... n-type diffusion layer, 13 ... insulating film, 14 ... Floating gate, 15 ... insulating film, 16 ... Control gate, 17 ... insulating film, 18 ... selection gate, 20 ... 1st sub data circuit 21 ... 2nd sub data circuit M ... memory cell, S ... Selective transistor, WL ... word line, BL ... bit line, SG ... selection gate, SRC ... common source line, Qn ... n-channel MOS transistor, Qp ... p channel MOS transistor, I ... Inverter, G ... logic gate, VCC ... power supply voltage, CI ... Clock synchronous inverter.