Sound encoding method and sound decoding method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a voice coding method and a voice decoding method for predictively coding and compressing a voice signal.

【0002】

[Conventional technology]

As a method for predictively coding an audio signal, the present inventor applied for a prior application (Japanese Patent Application No. 9-289159) with respect to one channel (channel) of the original digital audio signal by using a plurality of predictors having different characteristics. Multiple linear predicted values of the current signal are calculated from the past signals in the region, and the predicted residuals for each predictor are calculated from the original digital audio signal and the plurality of linear predicted values, and the predicted residuals of the plurality of predicted residuals are calculated. We propose a method to select the minimum value.

【0003】

[Problems to be Solved by the Invention]

However, with the above method, when the original digital audio signal has a sampling frequency of 96 kHz and the number of quantization bits is about 20 bits, a certain degree of compression effect can be obtained, but with recent DVD-Audio discs, sampling is twice this. Since the frequency (= 192kHz) is used and the number of quantization bits tends to be 24 bits, it is necessary to improve the compression ratio.

【0004】

Therefore, an object of the present invention is to provide a voice coding method and a voice decoding method capable of improving the compression rate when predictively coding a voice signal.

【0005】

[Means for solving problems]

The present invention comprises the means described in 1) and 2) below in order to achieve the above object. That is, [0006]

1) A step of matrix-calculating the first and second audio signals of the same sampling frequency to convert them into two correlated channels that are correlated with each other, and an audio signal containing the two correlated channels converted by the step. , For each channel, the first sample value is obtained in frame units of a predetermined time in response to the input audio signal, the first sample value is obtained in response to the input audio signal, and a plurality of linear predictions having different characteristics are obtained. The frame is a linear prediction method in which the linear predicted values of the past to present signals in the time region are predicted by the method, and the predicted residuals obtained from the predicted linear predicted values and the voice signal are minimized. Is made into a data structure including a step of selecting and predictively coding in subframe units further divided, header information, and user data including a compressed PCM access unit, and of each channel selected by the step. A voice coding method comprising a linear prediction method, a step of storing prediction coding data including a prediction residual and a predetermined head sample value in a subpacket arranged in the compressed PCM access unit, and a step of storing the prediction coding data. 2) A voice decoding method for decoding the original voice signal from the data encoded by the voice coding method according to claim 1, wherein the predicted coded data of each stored channel is extracted, and the above. A voice decoding method comprising a step of calculating a predicted value from the extracted predicted coded data of each channel and a step of restoring the original multi-channel voice signal from the calculated predicted value.

【0007】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a voice coding device to which the present invention is applied and a voice decoding device corresponding to the present invention, FIG. 2 is a block diagram showing a detailed encoder of FIG. 1, and FIG. 3 is a multiplexer of FIG. An explanatory diagram showing the format of one frame multiplexed by, FIG. 4 is an explanatory diagram showing the format of the DVD pack, FIG. 5 is an explanatory diagram showing the format of the audio pack of the DVD, and FIG. 6 shows the decoder of FIG. 1 in detail. It is a block diagram which shows.

【0008】

The channel correlation circuit A shown in FIG. 1 has an adder circuit 1a and a subtractor circuit 1b. In the adder circuit 1a, for example, each channel (hereinafter, ch) calculates the sum signal (L + R) of stereo 2ch signals L and R with sampling frequency = 192kHz and quantization bit number = 24 bits, and 1ch lossless for sum ch. The output is output to the encoder 2D1, and the subtraction circuit 1b calculates the difference signal (LR) and outputs it to the 1ch lossless encoder 2D2 for the difference channel. As shown in detail in FIG. 2, the encoders 2D1 and 2D2 predictively encode the difference Δ (L + R) and Δ (LR) of the sum signal (L + R) and the difference signal (LR), respectively, to record and communicate with each other. Is transmitted via.

【0009】

Then, on the decoding side, as shown in detail in FIG. 6, the decoders 3D1 and 3D2 decode the predicted encoded data of each channel into a sum signal (L + R) and a difference signal (LR), respectively, and then the channel correlation circuit B This sum signal (L + R) and difference signal (LR) are restored to stereo 2ch signals L and R.

【0010】

The encoders 2D1 and 2D2 will be described in detail with reference to FIG. The sum signal (L + R) and the difference signal (LR) are stored in the 1-frame buffer 10 for each frame. Then, each sample value (L + R) and (LR) of one frame is applied to the differential calculation circuits 11D1 and 11D2, respectively, and the difference between this time and the previous time Δ (L + R) and Δ (LR), that is, the differential PCM ( DPCM) data is calculated. Further, the first sample values (L + R) and (LR) of each frame are applied to the multiplexer 19.

【0011】

The difference Δ (L + R) calculated by the difference calculation circuit 11D1 is applied to a plurality of predictors 12a-1 to 12a-n and subtractors 13a-1 to 13a-n having different prediction coefficients. Then, the predictors 12a-1 to 12a-n calculate each predicted value of the difference Δ (L + R) based on each predicted coefficient, and the subtractors 13a-1 to 13b-n calculate each predicted value, respectively. Each predicted residual of the difference Δ (L + R) is calculated. The buffer / selector 16D1 temporarily stores the plurality of predicted residuals, selects the minimum predicted residual for each subframe specified by the selection signal generator 17, and outputs the minimum predicted residuals to the packing circuit 18. Note that this subframe has a sample length of about one tenth of the frame, and one frame is 80 subframes as an example. Here, the predictors 12a-1 to 12a-n and the subtractors 13a-1 to 13a-n constitute the prediction circuit 15D1 of the sum signal ch, and the prediction circuit 15D1 and the buffer selector 16D1 form the sum signal ch. Consists of the predictive coding circuit of.

【0012】

Similarly, the difference Δ (LR) calculated by the difference calculation circuit 11D2 is applied to a plurality of predictors 12b-1 to 12b-n and subtractors 13b-1 to 13b-n having different prediction coefficients. Then, the predictors 12b-1 to 12b-n calculate each predicted value of the difference Δ (LR) based on each predicted coefficient, and the subtractors 13b-1 to 13b-n calculate each predicted value and the difference Δ, respectively. Each predicted residual of (LR) is calculated. The buffer / selector 16D2 temporarily stores the plurality of predicted residuals, selects the minimum predicted residual for each subframe specified by the selection signal generator 17, and outputs the minimum predicted residuals to the packing circuit 18. The predictors 12b-1 to 12b-n and the subtractors 13b-1 to 13b-n constitute the prediction circuit 15D2 of the difference signal ch, and the prediction circuit 15D2 and the buffer selector 16D2 form the prediction code of the difference signal ch. It constitutes a signal circuit.

【0013】

The selection signal generator 17 applies a bit number flag (5 bits) of the predicted residual to the packing circuit 18 and the multiplexer 19, and a predictor selection flag (the number n) indicating the predictor having the minimum predicted residual. 3 bits as 2 to 9) are applied to the multiplexer 19. The packing circuit 18 packs the predicted residuals for 2 channels selected by the buffer selectors 16D1 and 16D2 with a specified number of bits based on the bit number flag specified by the selection signal generator 17.

【0014】

Subsequent multiplexer 19 is for one frame as shown in FIG. Frame header (40 bits) and The first sample value (25 bits) of one frame of the sum signal ch (L + R) and The first sample value (25 bits) of one frame of the difference signal ch (LR) and Predictor selection flag (3 bits x 80) for each subframe of sum signal ch (L + R), Predictor selection flag (3 bits x 80) for each subframe of the difference signal ch (LR), -The number of bits flag (5 bits x 80) for each subframe of the sum signal ch (L + R), -The number of bits flag (5 bits x 80) for each subframe of the difference signal ch (LR) and Predicted residual data string (variable bit number) of sum signal ch (L + R) and -The predicted residual data string (variable number of bits) of the difference signal ch (LR) is multiplexed as an access unit and output as a variable rate bit stream. The predicted residual data string constitutes a sub-packet. According to such predictive coding, when the original signal is, for example, a sampling frequency = 192 kHz, the number of quantization bits = 24 bits, and 2 channels, a compression rate of 59% can be realized.

【0015】

When recording this variable rate bitstream data on a DVD audio disc, it is packed in the compressed PCM audio (A) pack shown in FIG. This pack contains 2034 bytes of user data (A packet, V packet), 4 bytes of pack start information, 6 bytes of SCR (System Clock Reference) information, and 3 bytes of Mux rate (3 bytes). It is composed by adding a total of 14 bytes of pack header of rate) information and 1 byte of stuffing (1 pack = total of 2048 bytes). In this case, the time of the A pack in the same title can be managed by setting the SCR information which is the time stamp as "1" in the first pack in the ACB unit and making it continuous in the same title.

【0016】

As shown in detail in FIG. 5, the compressed PCM A packet is composed of a 17-, 9- or 14-byte packet header, a private header, and 1 to 2015-byte audio-compressed PCM data in the format shown in FIG. The private header of compressed PCM is 1-byte substream ID and 2-byte UPC / EAN-ISRC (Universal Product Code / European Article Number-International Standard Recording Code) number, UPC / EAN-ISRC data, and 1 byte private header length and -A 2-byte first access unit pointer and 4 bytes of audio data information (ADI) and It is composed of 0 to 7 bytes of stuffing bytes. In this way, the ADI of the compressed PCM A packet is selected as 4 bytes, which is 4 bytes shorter than the ADI of the normal uncompressed PCM A packet. Therefore, the audio data can be increased by 4 bytes.

【0017】

Next, the decoders 3D1 and 3D2 will be described with reference to FIG. The variable rate bitstream data in the format shown in FIG. 3 is separated by the demultiplexer 21 based on the frame header. Then, the first sample values of one frame of the sum signal ch (L + R) and the difference signal ch (LR) are applied to the cumulative arithmetic circuits 25a and 25b, respectively, and the sum signal ch (L + R) and the difference signal ch (LR) are applied. ) Predictor selection flags are applied as each selection signal of the predictors (24a-1 to 24a-n) and (24b-1 to 24b-n), respectively, and the sum signal ch (L + R) and the difference signal ch ( The bit number flag of LR) and the predicted residual data string are applied to the unpacking circuit 22. Here, the predictors (24a-1 to 24a-n) and (24b-1 to 24b-n) are the predictors (12a-1 to 12a-n) and (12b-1 to 12b-) on the coding side, respectively. It has the same characteristics as n), and the one with the same characteristics is selected by the predictor selection flag.

【0018】

The unpacking circuit 22 separates the predicted residual data strings of the sum signal ch (L + R) and the difference signal ch (LR) based on each bit number flag and outputs them to the addition circuits 23a and 23b, respectively. In the adder circuits 23a and 23b, the current predicted residual data of the sum signal ch (L + R) and the difference signal ch (LR) from the unpacking circuit 22, and the predictors (24a-1 to 24a-n), respectively. Of (24b-1 to 24b-n), the previous predicted value predicted by each one selected by the predictor selection flag is added to calculate the current predicted value. The predicted values this time are the differences Δ (L + R) and Δ (LR), that is, DPCM data calculated by the difference circuits 11a and 11b shown in FIG. 2, respectively, and are predictors (24a-1 to 24a-n). , (24b-1 ~ 24b-n) and are applied to the cumulative arithmetic circuits 25a and 25b.

【0019】

In the cumulative arithmetic circuits 25a and 25b, the difference Δ (L + R) and Δ (LR) are cumulatively added for each sample to the first sample value of one frame, respectively, and the sum signal ch (L + R) and the difference signal ch are added. Output each PCM data of (LR). As shown in FIG. 1, the sum signal (L + R) and the difference signal (LR) are calculated as 2L signals by the addition circuit 4a and 2R signals by the subtraction circuit 4b. Then, the 2L signal and the 2R signal are divided into 1/2 by the dividers 5a and 5b, respectively, and the original stereo 2-channel signals L and R are restored.

【0020】

Next, the second embodiment will be described with reference to FIGS. 7 and 8. In the above embodiment, only the sum signal (L + R) and the difference signal (LR) difference Δ (L + R), Δ (LR), that is, the DPCM data is predictively encoded. , In this second embodiment, the sum signal (L + R), the difference signal (LR), that is, the PCM data, or the difference Δ (L + R), Δ (LR), that is, the DPCM data thereof is selectively predicted and encoded. It is configured to do.

【0021】

Therefore, in the coding device shown in FIG. 7, the prediction circuits 15A and 15S and the buffer selector for predictively coding the sum signal (L + R) and the difference signal (LR) with respect to the configuration shown in FIG. 2 respectively. 16A and 16S have been added. Further, the selection signal generator 17 has a sum signal (L + R) and a difference signal (LR) selected by the buffer / selectors 16A and 16S, respectively, and a difference Δ (difference Δ () selected by the buffer / selectors 16D1 and 16D2, respectively. Based on the minimum value of each predicted residual of L + R) and Δ (LR), it is determined whether the PCM data or the DPCM data has the higher compression ratio, and the higher data is selected. At this time, the PCM / DPCM selection flag (prediction circuit selection flag) is added for multiplexing.

【0022】

Here, the sum signal (L + R) prediction circuit 15A and the difference Δ (L + R) prediction circuit 15D1 shown in FIG. 7 have the same configuration, and the difference signal (LR) prediction circuit 15S and the difference. When the Δ (LR) prediction circuit 15D2 has the same configuration, it is not necessary to provide a prediction circuit for both PCM data and DPCM data in the decoding device as shown in FIG. 8, and a prediction circuit for one data is sufficient. .. Then, the selectors 26a and 26b select the outputs of the cumulative arithmetic circuits 25a and 25b in the case of DPCM data based on the prediction circuit selection flag transmitted from the encoding device, and the adder circuits 23a and 23a in the case of PCM data. Select the output of 23b.

【0023】

In the third embodiment, as shown in FIG. 9, the original signals L and R (PCM data), the sum signal (L + R), the difference signal (LR) (PCM data), and their respective differences Δ (L +) It is configured to selectively predict encode one of three groups, R) and Δ (LR) (DPCM data).

【0024】

Therefore, in the coding device shown in FIG. 9, prediction circuits 15L and 15R and buffer / selectors 16L and 16R for predictively coding the original signals L and R are added to the configuration shown in FIG. 7, respectively. .. The selection signal generator 17 includes the original signals L and R selected by the buffer / selectors 16L and 16R, and the sum signal (L + R) and difference signal (LR) selected by the buffer / selectors 16A and 16S. Then, the data of the group having a high compression ratio is selected based on the minimum value of each predicted residual of each difference Δ (L + R) and Δ (LR) selected by the buffer selectors 16D1 and 16D2. At this time, the selection flag (prediction circuit selection flag) is added for multiplexing.

【0025】

Further, when the prediction circuits of the three groups shown in FIG. 9 have the same configuration, it is not necessary to provide the prediction circuits for the three groups as shown in FIG. 10, and the prediction circuits for one group may be used. Then, based on the prediction circuit selection flag transmitted from the encoding device, the outputs of the cumulative arithmetic circuits 25a and 25b are selected in the case of DPCM data, and the outputs of the addition circuits 23a and 23b are selected in the case of PCM data. Then, the original signals L and R are restored by the channel correlation circuit B. Then, the selectors 27a and 27b select the outputs of the adder circuits 23a and 23b in the case of the groups of the original signals L and R, and select the outputs of the channel correlation circuit B in other cases. [0026]

When the variable rate bitstream data predicted and encoded by the coding side is transmitted via the network, the coding side packets the data for transmission as shown in FIG. 11 (step S41), and then the packet header. Is given (step S42), and then this packet is sent out on the network (step S43). On the decryption side, as shown in FIG. 12, the header is removed (step S51), then the data is restored (step S52), and then this data is stored in the memory and waits for decryption (step S53).

【0027】

FIG. 13 shows a mode different from that of FIG. 3 in the compressed PCM (PPCM) audio (A) packet shown in FIG. In this different aspect, the audio data area in the compressed PCM (PPCM) audio (A) packet is composed of a plurality of PPCM access units as shown in FIG. 13, and the PPCM access unit is composed of PPCM sync information and subpackets. ing. The first subpacket in the PPCM access unit consists of a directory, bitstream BS0, CRC, and extra information, and bitstream BS0 consists only of PPCM blocks. The second and subsequent sub-packets in the PPCM access unit are composed of bitstream BS0, CRC, and extra information except for the directory. Substream BS0 at the beginning of the frame is the restart header and PPCM block (sample value at the beginning of the frame). Including).

【0028】

PPCM sync information (hereinafter, also referred to as synchronization information) includes the following information. -Number of samples per packet: 40, 80 or 160 is selected depending on the sampling frequency fs. -Data rate: "0" in the case of VBR (identifier indicating that the data in the subpacket is compressed data) Sampling frequency fs and number of quantization bits Qb Channel allocation information The restart header has information that specifies the channel correlation circuit A (having an adder circuit and a subtractor circuit) for each frame. The variable rate bitstream data in the format shown in FIG. 13 is decoded into the original 2-channel audio signal by the decoders 3D1 and 3D2 having the configuration of the demultiplexer 21 or less in FIG.

【0029】

FIG. 14 is a block diagram showing a second embodiment of the voice coding device and the voice decoding device according to the present invention. The channel correlation circuit A-1 shown in FIG. 14 has an adder circuit 1a and a subtractor circuit 1b. The adder circuit 1a calculates the sum signal (L + R) of the stereo 2ch signals L and R, divides this sum signal (L + R) by 1/2 by the divider 5a, and then outputs it to the lossless encoder 2D. Then, the subtraction circuit 1b calculates the difference signal (LR), divides this difference signal (LR) by 1/2 by the divider 5b, and then outputs it to the lossless encoder 2D. The lossless encoder 2D uses 1/2 (L + R) and 1/2 (LR) to multiplex these to create a multiplexed signal 250. The multiplexed signal 250 is decoded by the lossless decoder 3D to obtain the original 1/2 (L + R) and 1/2 (LR), which are the adder circuits 4a that make up the channel correlation circuit B-1. And are given to the subtraction circuit 4b, respectively, and the stereo 2ch L signal and R signal are obtained as output signals. In addition, the calculation of the difference, the calculation of the predicted value, the selection of the minimum predicted residual, the calculation of the predicted value using the minimum predicted residual, etc., which are a series of operations in the lossless encoder 2D and the lossless encoder 2D, are the first. It is carried out in the same manner as in the embodiment of. The variable rate bitstream data in the format shown in FIG. 13 should be identified by the identifier stored in the restart header of the PPCM access unit, for example, whether the channel correlation circuit of FIG. 1 was used or the channel correlation circuit of FIG. 14 was used. Since it is set to, it can be reliably decoded in any case. Although the lossless compression for each frame has been described as an example, the section may have a variable length instead of being fixed.

【0030】

[Effect of the invention]

As described above, according to the present invention, in particular, two systems of audio signals having the same sampling frequency are mixed and converted into channels that are correlated with each other. Two correlated signals are input for each channel. The first sample value is obtained in response to the voice signal, and lossless compression is performed by a linear prediction method that minimizes the predicted residual among multiple predicted values of the current signal predicted from the past signal in the time region. Therefore, when predictively coding an audio signal, the compression rate can be improved and the original signal can be restored.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows 1st Embodiment of the voice coding apparatus to which this invention was applied, and the voice decoding apparatus corresponding thereto.

[Figure 2]

It is a block diagram which shows the encoder of FIG. 1 in detail.

[Fig. 3]

It is explanatory drawing which shows the format of one frame multiplexed by the multiplexer of FIG.

[Fig. 4]

It is explanatory drawing which shows the format of a DVD pack.

[Fig. 5]

It is explanatory drawing which shows the format of the audio pack of a DVD.

[Fig. 6]

It is a block diagram which shows the decoder of FIG. 1 in detail.

[Fig. 7]

It is a block diagram which shows the encoder of the 2nd Embodiment.

[Fig. 8]

It is a block diagram which shows the decoder of the 2nd Embodiment.

[Fig. 9]

It is a block diagram which shows the encoder of the 3rd Embodiment.

[Fig. 10]

It is a block diagram which shows the decoder of the 3rd Embodiment.

[Fig. 11]

It is a flowchart which shows the voice transmission method.

[Fig. 12]

It is a flowchart which shows the voice transmission method.

[Fig. 13]

It is a format explanatory view which shows the mode different from FIG. 3 of the audio (A) packet of the compressed PCM (PPCM) shown in FIG.

[Fig. 14]

It is a block diagram which shows the 2nd Embodiment of the voice coding apparatus to which this invention was applied, and the voice decoding apparatus corresponding thereto.

[Explanation of symbols]

1a, 4a adder circuit (addition means) 1b, 4b subtraction circuit (subtraction means) 5a, 5b divider 11D1 differential calculation circuit (first differential calculation means) 11D2 differential calculation circuit (second differential calculation means) 12a-1 ~ 12a-n predictors (consisting the first predictive coding means together with the subtractors 13a-1 ~ 13a-n and the buffer / selector 16D1) 12b-1 ~ 12b-n predictors (consisting a second predictive coding means with subtractors 13b-1 ~ 13b-n and buffer / selector 16D2) 13a-1 ~ 13a-n, 13b-1 ~ 13b-n subtractor 16D1,16D2,16A, 16S, 16L, 16R buffer / selector 15A prediction circuit (consists of a third prediction coding means together with the buffer selector 16A) 15S Prediction Circuit (Consists of a fourth predictive coding means together with the buffer selector 16S) 15L prediction circuit (Consists of a fifth prediction coding means together with the buffer / selector 16L) 15R Prediction Circuit (Consists of a sixth predictive coding means together with the buffer selector 16R)