Distribution decoder for multiplexed compressed image-audio data

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a device involved in decoding of multiplexed image and audio data after being compressed and encoded, and distributes these image and audio data to their respective decoding devices.

【0002】

[Conventional technology]

In recent years, in the fields of broadcasting and communication, it has become possible to remove the redundancy of moving image signals, compress data, and perform digital transmission. As an image data compression method, a discrete cosine transform (DCT) such as the MPEG standard and motion compensation prediction coding are generally performed. With a high compression ratio as shown by the same method, it is possible to multiplex and transmit a plurality of broadcasting programs on one transmission channel. The program here means a set of an image and related audio and / or textual information. Multiplexing of multiple programs in the MPEG standard is ITU-T Rec.H.222.0 | ISO / IEC13818-1: 1994 Information technology --Coding of moving pictures and associated audio --Part 1: It is described in Systems that it is performed in units of 188-byte fixed-length packets, which are transport stream (hereinafter abbreviated as TS) packets. Based on the same standard, a device that separates TS packets supplied from broadcasting stations into image and audio data and then distributes them to a video decoder and an audio decoder to obtain image and audio output, a device called a so-called set-top box. Figure 2 shows the block configuration representing ,. Hereinafter, the conventional technique will be described with reference to FIG.

【0003】

The tuner 1 selects one transmission channel from the data distributed from the transmission medium such as CATV or satellite channel, and supplies it to the demodulation device 2. The demodulation device 2 decodes the channel data encoded in the transmission line by QAM, QPSK, or the like, performs error correction processing using a redundant code, and then supplies the data to the distribution device 3. The data supplied here is the bitstream data in the TS packet format. The format of the TS packet is shown in Fig. 3. The contents of TS packets are classified into Fig. 3 (a) or (b) according to the type of information to be transmitted. FIG. 3A shows a case where character information data such as image data, voice data, or teletext, which is a component (element) of the program, is transmitted. A 188-byte TS packet consists of a transport stream header (abbreviated as TS header) and a payload containing the elements. The TS header always contains a packet ID (abbreviated as PID) that represents the attributes of the TS packet, and is a program clock reference that is time information for restoring the system clock used as the time keynote during element coding on the decoding side. May include (abbreviated as PCR). The payload is part of the packetized elementary stream (PES) packet. A PES packet is a unit of elements determined by each element and the format of the recording medium, and is a variable-length packet. The PES packet consists of the data of each element and the PES header. The PES header contains the stream ID that describes the contents of the element, the PES packet length, and the time stamp information (PTS) that describes the time when the element should be displayed. The unit of the element indicated by PTS is called an access unit. For example, an image means one picture, and an audio means one frame of audio. on the other hand, Figure 3 (b) shows the data format for transmitting program specific information (abbreviated as PSI), which is additional information for system control. The payload of a TS packet is part of a PSI described in sections, which consist of a section header, a PSI, and a cyclic redundancy check (CRC), which is an error detection means. The section header represents the PSI attributes and section length that follow. The PSI has a hierarchical structure and is a program association table (PAT) that describes the program information (specifically, the PID of PMT described later) contained in the bitstream data transmitted as TS and the elements in each program. Contains essential information for system control, such as a program map table (PMT) that represents the correspondence between PID and PID. The distribution device 3 in FIG. 2 receives the multiplexed TS packet and sends the PSI data to the system decode buffer allocated inside the RAM 7 via the data bus to the image data and audio data which are the constituent elements of the program selected by the user. Is distributed to the video decoder 8 and the audio decoder 10, respectively. Further, the distribution device 3 extracts time information from the header of the TS packet including the PCR and supplies a control signal to the clock generator 4 to restore the system clock. The PSI data sent to the system decode buffer inside RAM7 is stored inside RAM7 as data in a format that can be used by the software program that controls the system after the CPU12 decodes the contents. In addition to supplying the PID for extracting the TS packet of the program using the above data to the distribution device 3, the CPU 12 follows the instruction from the user input via the user interface device 13. A control signal for selecting a channel is supplied to the tuner 1. The video decoder 8 and the audio decoder 10 output images and sounds using the video decode buffer 9 and the audio decode buffer 11 for decoding and display, respectively. Here, the data transmission rate in the transmission line is different from the bit rate when each element is encoded due to the multiplexing of the program. Therefore, if the transmission speed is directly supplied to the video decoder 8 and the audio decoder 10, the video decode buffer 9 and the audio decode buffer 11 may locally overflow or underflow, resulting in image and audio output. Invite turbulence. Therefore, as shown in FIG. 2, packet reception buffers 5 and 6 are provided in the path between the distributor and each decoder, speed conversion is performed based on the buffer capacity of the decoder, and then element data is input to the video decoder 8 and the audio decoder 10. Need to be supplied. In the MPEG standard, multiplexing is performed on the assumption that a packet reception buffer having a capacity of 512 bytes is provided for each element.

【0004】

[Problems to be Solved by the Invention]

However, in this configuration, since the packet reception buffers 5 and 6 are independently provided as dedicated memory elements, the number of parts constituting the system increases, which leads to an increase in price. Further, even when the packet reception buffer is included in the circuit of the distribution device 3, the circuit scale is increased due to the built-in memory, and the component price is inevitably increased.

【0005】

[Means for solving problems]

In the present invention, the packet reception buffer is provided inside the RAM used by the CPU for system control to reduce the number of parts or suppress the increase in the price of parts due to the built-in memory.

【0006】

[Action]

Since the RAM used as the main memory by the CPU is required to have a capacity of several megabits because it stores operating system software, 512 bytes required as a packet reception buffer is used as an element without adding the number of memory elements. It is easy to secure the number. Therefore, the number of parts does not increase.

【0007】

[Example]

Hereinafter, examples of the present invention will be described with reference to the drawings.

【0008】

FIG. 1 is a block diagram showing the configuration of the first embodiment. The tuner 1 selects one transmission channel from the data distributed from the transmission medium such as CATV or satellite channel, and supplies it to the demodulation device 2. The demodulation device 2 decodes the channel data encoded in the transmission line by QAM, QPSK, or the like, performs error correction processing using a redundant code, and then supplies the data to the interface device 14. The data supplied here is bitstream data in TS packet format. The interface device 14 receives the control signal from the CPU 12 and transfers all the TS packet data to the packet reception buffer provided in the RAM 7 which is the main memory. Figure 4 shows the internal state of the packet reception buffer. The packet receive buffer constitutes First-In-First-Out (FIFO), and one packet per line is written in the order of arrival and read in the same order. Video # 1 in the figure represents a packet containing the video of program number # 1. A row address is assigned to the buffer, one row is updated for each write, and it wraps at N. Number of lines N is 188 bytes * N> It is set to a value that satisfies 512 bytes * (maximum number of elements per program + 1) * (maximum number of programs per TS). An information byte indicating the arrival time of the packet is added to each line in the packet reception buffer to enable restoration of the system clock. The method of writing to the packet reception buffer will be described with reference to FIG. FIG. 5 is a block diagram showing details of the interface device 14, the CPU 12, the clock generator 4, and the RAM 7 in FIG. The interface device 14 includes a TS header discrimination circuit 140 and a transmission buffer circuit 141 inside. The TS header discrimination circuit 140 searches the TS packet header by a bit pattern using the TS packet data and the TS packet transmission clock tsClock, and supplies the timing when the first byte of the TS packet arrives to the CPU 12 as an interrupt signal. The CPU 12 uses the interrupt signal as a trigger pulse to transfer the contents of the timer 123 to the register 124. The timer 123 is a counter that counts up at the frequency of the system clock, and the arrival time measured by the timer 123 is transferred to the register 124. The interrupt signal counts up the value of the write address counter 122 by one line. As a result, the row address synchronized with the beginning of the packet is updated, and even if an error occurs in which the packet length is not 188 bytes, normal writing is guaranteed from the packet immediately after the error occurs without failure. The transmission buffer circuit 141 is a buffer for outputting TS packets on the data bus, performs data bit width conversion and time axis conversion from the transmission path clock tsClock to the data bus clock busClock, and directly accesses RAM7. Performs high-speed transfer by (DMA). The write timing to RAM7 is controlled by a handshake with the DMA controller 121. That is, the transfer request signal DREQ is output when the data transfer preparation in the transmission buffer circuit 141 is completed. When the transfer permission signal DACK is returned from the DMA controller 121, the data is written to RAM 7 without going through the registers of CPU 12. As the line address at the time of writing, the one counted up by the above mechanism is used. When one packet of data is transferred, the CPU 12 adds information byte data indicating the arrival time in the register 124 to the packet data in the buffer.

【0009】

From the TS packet data written in the packet reception buffer as described above, the CPU 12 extracts only the elements belonging to the program selected by the user and distributes them to each decoder. As shown in Fig. 6, the timing of reading the TS packet is such that the read address follows the write address. The write address is updated every time a packet arrives, regardless of the read side, so as not to overflow the TS packet arriving from the transmission line. Therefore, the CPU 12 compares both addresses and monitors the read address so that it does not overtake the write address. In this way, the CPU 12 reads the packet data and performs packet distribution processing by the algorithm shown in FIG. FIG. 7 shows a distribution processing algorithm when the user selects a program number #k that includes only image data and audio data as elements. CPU12 fetches the PID in the packet header (S1). Refer to the program map table (PMT) and check whether it corresponds to program #k or contains PSI (S2). If the packet is of an element that does not correspond, processing is skipped and the packet proceeds to the next line address (S9). If it is related to program #k, check whether the clock reference information PCR is included, that is, whether it is PCR_PID (S3). If PCR is included, proceed to the clock restoration routine (S4) described later. If PCR is not included, proceed to element separation processing (S5). CPU12 refers to PMT and proceeds to video packet transfer processing routine (S6) / audio packet transfer processing routine (S7) / PSI packet processing routine (S8) as PID indicates image / audio / PSI, respectively. The video packet transfer processing routine (S6) extracts the payload of the TS packet and transfers it. The transfer speed is adjusted by the CPU 12 or DMA controller 121 performing a handshake with the decoder after each transfer. As a result, the average transfer rate matches the decoding rate. Alternatively, the bit rate shown as additional information may be used for each element, and the CPU 12 may input at a constant rate by the built-in timer.

【0010】

The data format to be transferred depends on the video decoder 8. That is, if the decoder accepts the PES packet as an input, it forwards the entire PES packet including the PES packet header, or if the decoder accepts the element data as an input, it forwards the payload of the PES packet excluding the PES header. In this case, CPU12 interprets the PES header. Therefore, the PTS information indicating the decoding timing is managed, and the timing at which the picture indicated by the PTS should be decoded is given to the video decoder 8. Regarding the audio packet transfer processing routine (S7), the transfer processing of the CPU 12 is different as in the case of video according to the data format accepted by the audio decoder 10 as an input. FIG. 8 is a diagram showing the timing of data output when both the video decoder 8 and the audio decoder 10 receive element data as inputs. To simplify the explanation, it is assumed that a certain picture data and audio frame data are specified by the same PTS, that is, they should be output at the same time t = PTS (v) = PTS (a). In the MPEG method, the video decode buffer 9 includes a buffer defined as a video buffering verifier (vbv), and decoding is performed by reading data from this vbv buffer. The amount of data read depends on the type of picture (I, P, B), that is, the degree of compression, but if the CPU 12 gives the decoding timing so that the picture is displayed at the PTS time as specified, the vbv buffer overflows / underflows. It will not be (depleted). In FIG. 8, the picture input to the video decoder 8 starts decoding at the time t = PTS (v) in the vbv buffer after a delay of Tvbv, and the audio frame is decoded at the same time t = PTS (a) in the audio decoder 10. To start. However, the video decoder 8 cannot display at the same time as decoding, and is always output via the display buffer. There is a decoder-specific delay time Tdisp between decoding and the actual display. Furthermore, Tvid delay generally occurs in the entire video system by adding digital / analog conversion after decoder output, system conversion corresponding to the display device, and system-specific delay Text generated in the image synthesizer. Similarly, the Taud delay occurs in the voice system. Therefore, the CPU 12 must consider the difference Tadj between the two in order to obtain the synchronized output of the image and the sound. In the present invention, synchronous output is realized by providing a delay buffer for compensating the Tadj inside the RAM 7. That is, since the delay peculiar to the decoder and the delay peculiar to the system become known at the time of configuring the system, Tadj may be calculated and the timing of supplying data to the video or audio decoder may be delayed by Tadj. Specifically, the data may be transferred from the packet reception buffer to the delay buffer and then transferred to the decoder, or the capacity of the packet reception buffer may be increased by the amount equivalent to Tadj and the data may be read from the buffer twice. Good. In either case, it is not necessary to add a memory element because the delay processing for synchronization is possible by manipulating the data in the main memory by software. The timing of supplying data to the video or audio decoder should be delayed by Tadj. Specifically, the data may be transferred from the packet reception buffer to the delay buffer and then transferred to the decoder, or the capacity of the packet reception buffer may be increased by the amount equivalent to Tadj and the data may be read from the buffer twice. Good. In either case, it is not necessary to add a memory element because the delay processing for synchronization is possible by manipulating the data in the main memory by software. You only have to delay the timing of supplying data to the video or audio decoder by Tadj. Specifically, the data may be transferred from the packet reception buffer to the delay buffer and then transferred to the decoder, or the capacity of the packet reception buffer may be increased by the amount equivalent to Tadj and the data may be read from the buffer twice. Good. In either case, it is not necessary to add a memory element because the delay processing for synchronization is possible by manipulating the data in the main memory by software.

【0011】

The PSI packet processing routine (S8) interprets the section data, and if there is PSI data to be updated, rewrites the data in the table as appropriate. As described above, when the processing of one TS packet is completed according to the PID, the read line address of the packet reception buffer is advanced by one line and the processing of the next TS packet proceeds (S9).

【0012】

The clock restoration process (S4) will be described with reference to FIGS. 9 and 10. The clock restoration process (S4) is performed when the read packet contains PCR. CPU12 reads the PCR value and calculates the difference from the arrival time data added to the packet. Let this be the current difference value DIFcur (S11). Take the difference between the previous difference value DIFpre and the DIFcur, and let this be ERR (S12). FIG. 10 shows the progress of timer 123 inside the CPU 12 (solid line) and the progress of PCR on the transmitting side (broken line). If the frequencies of the clocks that count up both are equal, the slopes will be equal, and the difference values DIFpre and DIFcur will not change regardless of the packet arrival time. Therefore, ERR is an index for measuring the difference between the two frequencies. The comparison with the threshold value of ERR (S13) represents the reset operation including the initial value setting, and the frequency is not corrected. Frequency deviation is detected by positive / negative comparison (S14), and if positive, the clock frequency is accelerated (S15) to cancel the increase in the difference value, and if negative, the clock frequency is decelerated (S16). Do. If ERR is zero, do nothing and update DIFpre (S17) and return to the main process (S18). The CPU 12 supplies an acceleration / deceleration control signal to the clock generator 4, and the generated clock counts up the timer 123 to form a feedback loop.

【0013】

As described above, by providing the packet reception buffer inside the RAM used by the CPU for system control according to the present invention, data distribution to the decoder is realized without increasing the number of parts or the price of parts.

【0014】

Further, as a side effect, by providing a delay buffer inside the RAM for correcting the synchronization deviation between the video and audio due to the delay peculiar to the decoder or the delay peculiar to the system, the synchronous output control by software becomes possible. By updating the write address of the packet receive buffer using the timing of the packet header, a write mechanism that does not break due to data errors is obtained. By adding the packet arrival timing to the packet reception buffer, the reference clock can be restored by software.

【0015】

Next, a second embodiment of the present invention will be described. FIG. 11 is a block diagram showing a second embodiment. The same reference numerals are given to the blocks common to the first embodiment, and the description thereof will be omitted. In this embodiment, the output of the demodulation device 2 is supplied to the program packet sorting device 15. The program packet extraction device 15 extracts TS packets and PSI packets including an element of one program (program number # k) selected by the user from the transmitted TS packets and sends them to the interface device 14. FIG. 12 shows the extraction process in the program packet extraction device 15. Figure 12 (a) shows the input TS packet, and Figure 12 (b) shows the output after processing. The TS packets transferred by the interface device 14 to the RAM 7 are only the packets related to the program #k and the PSI packets, and the contents of the packet reception buffer are as shown in FIG. The packet reception buffer is in the FIFO format that wraps at N lines, which is the same as in the previous embodiment, but N only needs to satisfy 188 bytes * N> 512 bytes * (number of elements per program + 1), and TS packets. Compared to the previous example where it was necessary to receive all, the capacity is small. Further, in this embodiment, since the clock generator 4 is connected to the program packet extraction device 15 and the restoration process is performed by hardware, the information byte indicating the packet arrival time is not added to the packet reception buffer. The details of the processing method are shown in FIG. The program packet extraction device 15 includes a TS header discrimination circuit 151 for searching the header of a TS packet, a PID filter circuit 152, a PCR counter 153, and a comparison circuit 154. The arrival timing signal of the TS packet output from the TS header discrimination circuit 151 counts up the write address counter 122 inside the CPU 12 by one line, and also It is a trigger pulse that samples the count value of the PCR counter 153. The sampled count value is sent to the comparison circuit 154. The PID filter circuit 152 supplies the packet related to the program #k and the PSI packet to the transmission buffer circuit 141 in the interface device 14 using the PID data from the CPU 12, and further extracts the PCR value from the packet having the PCR_PID and compares the circuit. Send to the other of the 154 inputs. The comparison circuit 154 compares the sampled count value with the PCR value, and supplies the clock generator 4 with a frequency control signal that accelerates if the count value <PCR value and decelerates if the count value> PCR value. A feedback loop is configured by counting up the PCR counter 153 with the output clock of the clock generation circuit 4. The transfer from the transmission buffer circuit 141 to the RAM 7 is controlled by a handshake with the DMA controller 121. That is, when the data transfer preparation in the transmission buffer circuit 141 is completed, the transfer request signal DREQ is output, and when the transfer permission signal DACK is returned from the DMA controller 121, the data is written to RAM 7 without passing through the register of the CPU 12. Is done. As the line address at the time of writing, the one counted up by the above mechanism is used. The CPU 12 reads the PID data corresponding to the program #k selected by the user from the program map table provided in the RAM 12 into the register 123, and supplies the PID data to the PID filter circuit 152 from the output port. This PID data can also be supplied via the data bus. In this embodiment, the program packet separation circuit 15 separates the packets of program #k and also performs clock restoration processing. Therefore, the algorithm for data distribution from RAM 7 to the decoder is as shown in FIG. Only the distribution processing of elements and PSI packets in the program. Since the processing contents from steps S5 to S9 after capturing the PID of the packet are the same as the processing shown in FIG. 7, the description thereof will be omitted. As described above, also in the second embodiment, by providing the packet reception buffer inside the RAM used by the CPU for system control, data distribution to the decoder is realized without increasing the number of parts or the price of parts.

【0016】

Further, as a side effect, by providing a delay buffer inside the RAM for correcting the synchronization deviation between the video and audio due to the delay peculiar to the decoder or the delay peculiar to the system, the synchronous output control by software becomes possible. By updating the write address of the packet receive buffer using the timing of the packet header, a write mechanism that does not break due to data errors is obtained.

【0017】

[Effect of the invention]

By providing the packet reception buffer inside the RAM used by the CPU for system control, data distribution to the decoder is realized without increasing the number of parts or the price of parts.

[Simple explanation of drawings]

[Figure 1]

The block diagram which shows the 1st Example in this invention.

[Figure 2]

A block diagram showing a conventional example.

[Fig. 3]

Explanatory diagram of the configuration of the transport stream packet.

[Fig. 4]

Explanatory diagram showing an array of packet receive buffers.

[Fig. 5]

An explanatory diagram showing signal reception between an interface device, a CPU, and RAM.

[Fig. 6]

The conceptual diagram which shows the write / read timing of a packet receive buffer.

[Fig. 7]

A flow chart showing an algorithm for packet distribution processing.

[Fig. 8]

Explanatory drawing of synchronous output of image and sound.

[Fig. 9]

A flow chart showing an algorithm for clock restoration processing.

[Fig. 10]

Explanatory drawing which shows frequency tracking by comparison of the difference value.

[Fig. 11]

The block diagram which shows the 2nd Example in this invention.

[Fig. 12]

Explanatory drawing which shows the program corresponding packet separation.

[Fig. 13]

Explanatory diagram showing an array of packet receive buffers.

[Fig. 14]

An explanatory diagram showing signal reception between an interface device, a CPU, and RAM.

[Fig. 15]

A flow diagram showing an algorithm for element distribution processing.

[Explanation of symbols]

1 ... Tuner, 2 ... Demodulator, 7 ... RAM, 8 ... Video Decoder, 9 ... Video Decode Buffer, 10 ... Audio Decoder, 12 ... CPU