Hybrid integrated circuit parts
3 claims: 2 independent, 1 dependent
- 1(57)【特許請求の範囲】 【請求項1】 1つの基板上に、積層型コンダクタ、積層型インダクタあるいは抵抗のうち少なくとも1つを具備する積層体と、複数個の機能の異なる薄膜集積回路とを搭載した混成集積回路部品において、 積層体に複数の接続用の端子を設け、 複数個の薄膜集積回路をこの端子のうち、選択したものと接続したことを特徴とする混成集積回路部品。
- 2【請求項2】 前記積層体は、前記複数個の薄膜集積回路の受動回路として接続されることを特徴とする請求項1記載の混成集積回路部品。
- 3【請求項3】 1つの基板上に、1つの薄膜集積回路と、複数の積層体を設け、薄膜集積回路はこれらの複数の積層体の1つまたは複数と接続可能に構成されることを特徴とする混成集積回路部品。
Independent claims3
91 paragraphs, as filed
Description: TECHNICAL FIELD [Detailed description of the invention]
【0001】
[Industrial application field]
The present invention relates to a mixed integrated circuit component, and in particular, a mixed integrated circuit component having a structure in which a laminate functioning as a passive circuit in a mixed integrated circuit component equipped with a plurality of thin film integrated circuits having different functions can also be used as the thin film integrated circuit. Regarding.
【0002】
[Conventional technology]
As a hybrid integrated circuit component, a structure in which a thin film integrated circuit chip is connected one-to-one on a substrate composed of a laminated capacitor, a laminated inductor, a resistor, or a composite thereof has been conventionally known.
【0003】
FIG. 6 shows an example of a conventional hybrid integrated circuit component 500. In FIG. 6, 501 is a laminated capacitor, 502 is a laminated inductor, 504 is a thin film integrated circuit chip, 505 is a take-out terminal of a thin film integrated circuit chip, 506 is an electrode pad of a laminated body, and 508 is a package.
【0004】
In FIG. 6, a bare thin film integrated circuit chip 504 is mounted on a laminate composed of a laminated capacitor 501 and a laminated inductor 502, and the take-out terminal 505 of the thin film integrated circuit chip 504 and the electrode pad 506 of the laminated body are attached. Are connected by a method such as wire bonding. Further, the thin film integrated circuit chip 504 is covered with a plastic or ceramic package 508 to form a hybrid integrated circuit component 500.
【0005】
A laminated body such as a laminated capacitor is formed as follows. First, for example, BaTiO in which the raw material is calcined at a relatively low temperature.<sub>3 </sub>A powder of a dielectric material made of a ceramic is mixed with a binder to form a paste, and this dielectric paste is printed in a sheet shape on a temporary support substrate that can be easily peeled off.
【0006】
Next, the paste of the conductor for the electrode is printed on this, and the above-mentioned dielectric paste is further laminated. This is alternately performed to form a laminated body. In the same manner, the magnetic material and the conductor material paste are laminated and printed on this, and the inductance portion is laminated. For example, a laminated inductance can be formed by using Ni-Cu-Zn-based ferrite as a magnetic material. Then, after drying this laminate, it is peeled off from the temporary support plate and fired at, for example, 800 ° C to 900 ° C to obtain a composite laminate. In this way, a laminate including an LC circuit is formed.
【0007】
As described above, the bare thin film integrated circuit chip 504 is mounted on the formed laminate, electrically connected, and packaged to complete the hybrid integrated circuit component.
【0008】
[Problems to be Solved by the Invention]
As is clear from FIG. 6, in the conventional mixed integrated circuit, one thin film integrated circuit chip is directly mounted on one laminate, and the thin film integrated circuit chip and the laminate are appropriately connected on the substrate according to the circuit design. The desired parts were constructed.
【0009】
However, since passive element components such as multilayer capacitors and inductors are thick-film laminates, it is possible to design each function with a considerable margin in terms of characteristics, but the thin film integrated circuit chip is formed on a semiconductor substrate. Circuit functions can usually only have a single function. Therefore, one hybrid integrated circuit component is formed as a component having one function.
【0010】
Therefore, an object of the present invention is to provide a cheaper and more compact hybrid integrated circuit component by effectively utilizing a laminate having a margin of function.
【0011】
[Means for solving problems]
In order to achieve the above object, in the present invention, a laminated body composed of at least one laminated passive element and a plurality of thin film integrated circuit chips having different functions are provided in parallel on one substrate.
【0012】
[Action]
By forming a hybrid integrated circuit component having a plurality of functions by using the laminate as a laminate on one substrate in this way, it is possible to realize cost reduction and compactification of the circuit component.
【0013】
[Example]
Examples of the present invention will be described with reference to FIGS. 1 to 4. 1 and 2 are schematic explanatory views of the hybrid integrated circuit component of the present invention, FIG. 1 (A) is a plan explanatory view, and FIG. 1 (B) is a cross-sectional structure explanatory view along the A-A'line. ..
【0014】
In FIG. 1, 100 is a substrate, 101 is a laminate, 102 and 103 are thin film integrated circuits, 104 is an output terminal, 105 is a resin, 111 is a multilayer capacitor, 112 is a multilayer inductor, and 113 is a resistor.
【0015】
In FIG. 1, for example, on a substrate 100 such as alumina, a laminated body 101 having a laminated capacitor 111 and a laminated inductor 112, and a circuit designed to function as a drive circuit of, for example, a DC-DC converter. A thin film integrated circuit 102 formed on a crystalline silicon substrate and a thin film integrated circuit 103 formed on a polycrystalline silicon substrate whose circuit is designed to function as a magnetic head drive circuit are mounted.
【0016】
In the laminated body 101, for example, terminals (111-1 to 111-5) for 10 μF, 50 μF, 100 μF, 500 μF, 1000 μF are on the laminated capacitor 111 side, and 10 μH, 50 μH, for example, on the laminated inverter 112 side. Terminals (112-1 to 112-5) for 100 μH, 200 μH, and 300 μH are provided.
【0017】
In the present invention, when this hybrid integrated circuit component is used as, for example, a DC-DC converter, as shown in FIG. 1 (A), the terminals of the thin film integrated circuit 102 are the terminals 111-1 of C = 1000 μF of the laminate 101, respectively. And L = 200μH terminal 112-4 for practical use.
【0018】
When this hybrid integrated circuit component is used as a magnetic head drive circuit, the terminals of the thin film integrated circuit 103 are connected to terminals 111-1 of C = 10 μF and terminals 112-2 of L = 50 μH, respectively, as shown in FIG. do it.
【0019】
FIG. 3 is a schematic structural diagram of a thin film transistor which is a part of the thin film integrated circuit used in the present invention, and FIG. 4 is an explanatory diagram of a manufacturing process of this thin film transistor. In FIGS. 3 and 4, 301 is a polycrystalline silicon substrate, 302 is a silicon oxide film, 303 is an active silicon layer, 304 is a gate insulating film, 305 is a gate electrode, 306 and 309 are source / drain regions, and 307 is phosphor. Silicate glass film (PSG film), 308 indicates an aluminum wiring layer.
【0020】
The structural process of this thin film transistor will be described with reference to FIG. First, a silicon oxide film 302 having a thickness of 1000 to 5000 Å is formed on the polycrystalline silicon substrate 301 by a sputtering method. Next, an amorphous silicon film (α-Si film) 303'is formed on this film to a thickness of 500 to 6000 Å by the reduced pressure CVD method (see Fig. 4 (A)).
【0021】
The film forming conditions at this time are as follows. Si<sub>2 </sub>H<sub>6 </sub> 100 ~ 500 SCCM He 500 SCCM Reaction pressure 0.1 ~ 1 Torr Film formation temperature 430 ~ 500 ° C Next, this α-Si film 303'is patterned into a predetermined island shape, and then heat-treated at a temperature of about 600 ° C. for about 40 hours in a nitrogen atmosphere to crystallize it into an active silicon layer 303. (See Figure 4 (B)).
【0022】
After that, as a gate insulating film, a silicon oxide film 304'with a film thickness of 500 to 2000 Å is formed by dry oxidation. The conditions for forming the gate insulating film are as follows.
【0023】
O<sub>2 </sub> 2.5 SLM Film formation temperature 850 ~ 1100 ° C Next, a P or B-doped silicon film 305', which is a gate electrode, is formed on the silicon film 305'by a reduced pressure CVD method to a thickness of 1000 to 4000 Å (see FIG. 4 (C)).
【0024】
Then, the gate electrode 305 and the gate insulating film 304 are formed by an etching step according to a predetermined pattern (see FIG. 4 (D)). Using this gate electrode 305 as a mask, for example, P is injected into a portion to be a source / drain region by an ion doping method to form source / drain regions 306 and 309 (see FIG. 4 (E)).
【0025】
The substrate is heated at 600 ° C for 12 hours in a nitrogen atmosphere to activate the dopant, and then heat-treated at 400 ° C for 1 hour in a hydrogen atmosphere to perform hydrogenation treatment to achieve the defect level density of the semiconductor layer. To reduce.
【0026】
Next, a PSG film 307 is formed on the entire substrate by a normal pressure CVD method to a thickness of 4000 to 8000 Å, and then patterned according to a wiring pattern to make holes for electrodes (see FIG. 4 (F)).
【0027】
Aluminum is vapor-deposited on this and patterned to form a wiring layer 308 to complete a thin film transistor as shown in FIG. The thin film integrated circuits 102 and 103 and the laminated body 101 configured in this manner are arranged as shown in FIG. 1 (A), for example. Any one of Cr, Ni, CrNiAu, Ti, and Cu is vapor-deposited and patterned on the electrical connection portion (terminal) of these thin film integrated circuits with the laminate 101, and the thin film integrated circuit and the laminate are connected.
【0028】
Furthermore, SiO as a passivation film<sub>2 </sub>Membrane, Si<sub>3 </sub>N<sub>4 </sub>At least one of the film, PSG film, etc. is formed by the CVD method, and only the electrical connection with the laminate is etched to open holes and solder bump. Finally, the output terminal 104 is provided and molded with the resin 105 to complete the hybrid integrated circuit component.
【0029】
The connection between the thin film integrated circuit and the laminated body 101 is not limited to the above description, and may be performed by wire bonding as shown in FIG. 1 (B). Further, in the above embodiment, a plurality of thin film integrated circuits are provided in parallel on the same substrate for one laminated body in which at least one of a laminated inductor, a laminated capacitor, and a resistor is combined, so that selective connection is possible. Although arranged, this can also be reversed.
【0030】
That is, as shown in FIG. 5, the thin film integrated circuit 201 and the plurality of laminated bodies 202 and 203 are arranged on the substrate 200. The laminated bodies 202 and 203 are arranged so that the passive element portions have different sizes. Then, the thin film integrated circuit 201 is selectively connected to any one of them depending on the application.
【0031】
In addition, in order to have various functions in the above thin film integrated circuit, the mobility characteristic is 100 cm.<sup>2 </sup>Those with / v · sec or more are preferable. For this reason, the TFT is preferably formed in a non-single crystal silicon substrate.
【0032】
In the above description, an example in which the laminate is placed on the substrate has been described, but it can also be placed on the thin film integrated circuit depending on the size. Further, when a plurality of laminated bodies are placed on the substrate, the laminated bodies are not limited to the same ones, and those having different values such as LCR can be placed.
【0033】
[Effect of the invention]
A plurality of thin film integrated circuit chips having different functions and a laminated body composed of a laminated passive element are mounted on one substrate, and one laminated body is shared as a passive element of a plurality of thin film integrated circuits. As a result, the laminate can be effectively used, and the cost and compactness of the mixed thin film integrated circuit component can be reduced.
【0034】
Since the size of the laminate is determined by the package area of the thin film integrated circuit, it is not necessary to increase the size of the package by placing the laminate. Further, since the thin film integrated circuit can be formed on the same substrate by the same process because the substrate is not selected, a plurality of thin film integrated circuits can be formed on the same substrate. Therefore, it is possible to reduce the size as compared with the case where one laminated body is selectively connected by different individual thin film integrated circuits.
[Simple explanation of drawings]
[Figure 1]
It is a schematic explanatory drawing of the hybrid integrated circuit component of this invention.
[Figure 2]
It is another schematic explanatory drawing of another hybrid integrated circuit component of this invention.
[Fig. 3]
It is a schematic explanatory drawing of the thin film transistor used in this invention.
[Fig. 4]
It is explanatory drawing of the manufacturing process of the thin film transistor used in this invention.
[Fig. 5]
It is another embodiment of the present invention.
[Fig. 6]
It is a schematic explanatory drawing of the conventional hybrid integrated circuit component.
[Explanation of symbols]
100 boards 101 laminate 102 Thin film integrated circuit 103 Thin film integrated circuit 104 output terminal 111 Multilayer Capacitor 112 Multilayer inductor
8 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8
Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| JP5109923A | Cites | Japan |
| JP590485A | Cites | Japan |
| JP4313157A | Cites | Japan |
| JP4303960A | Cites | Japan |
| JP63115357A | Cites | Japan |
17 members in 3 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 19129793 | Japan | A | |
| JP19930191297 | – | – | – |
Members17
| Document | Office | Kind | |
|---|---|---|---|
| JPH06333740A | Japan | A | |
| KR940027163A | Republic of Korea | A | |
| JPH0745783A | Japan | A | |
| JPH0745784A | Japan | A | |
| JPH0745785A | Japan | A | |
| JPH0745786A | Japan | A | |
| JPH0745787A | Japan | A | |
| US5643804A | United States of America | A | |
| US5877533A | United States of America | A | |
| KR100273826B1 | Republic of Korea | B1 | |
| KR100311675B1 | Republic of Korea | B1 | |
| JP3290514B2This record | Japan | B2 | |
| US6410960B1 | United States of America | B1 | |
| KR100351399B1 | Republic of Korea | B1 | |
| JP3343282B2 | Japan | B2 | |
| JP3499255B2 | Japan | B2 | |
| JP3597874B2 | Japan | B2 |
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Numbers
- Publication
- 3290514
- Publication, DOCDB
- 3290514
- Publication, EPODOC
- JP3290514B
- Application
- 19129793
- Application, DOCDB
- 19129793
- Application, EPODOC
- JP19930191297
Titles2
- Japanese
- 混成集積回路部品
- English
- [Title of Invention] Hybrid integrated circuit component
Classification
- CPC, 1
- H10W90/754
- IPC, 3
- H01L25 00
- H01L25 04
- H01L25 18
