Method for transmitting video, method for receiving video, video transmitter and video receiver

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a scramble system and an apparatus suitable for digital television broadcasting.

【0002】

[Conventional technology]

FIG. 17 shows a signal processing block (video transmitter and video receiver) in conventional digital television broadcasting. The video transmission device includes a codec (compression) block 11, a scramble circuit 117', an ECC addition circuit 118, and a modulation circuit 119. The codec (compression) block 11 includes a scan conversion circuit 112, a DCT conversion circuit 113, a quantization circuit 114, a code amount control circuit 115, and a variable length coding (VLC) circuit 116.

【0003】

In the video transmitter, the original image (original video signal) 111 is scanned-converted by the scan conversion circuit 112, DCT-converted by the DCT transform circuit 113, and quantized by the quantization circuit 114 in the codec (compression) block 11. A compressed video signal is obtained by controlling the code amount with the code amount control circuit 115 and performing variable length coding with the variable length coding circuit 116. Further, the compressed video signal is scrambled by the scramble circuit 117', ECC is added by the ECC addition circuit 118, and the compressed video signal is modulated by the modulation circuit 119 to obtain the transmission signal 120.

【0004】

On the other hand, the video receiving device has a demodulation circuit 122, an ECC processing circuit 123, a descramble circuit 124', and a codec (extension) circuit 12. The codec (extension) circuit 12 includes a variable length decoding (VLD) circuit 125, an inverse quantization circuit 126, an inverse DCT transform circuit 127, and a scan inverse transform circuit 128.

【0005】

In the video receiver, the received signal 121 is demodulated by the demodulation circuit 122, ECC processing is performed by the ECC processing circuit 123, and the contractor having the scramble decoder performs the correct descramble by the descramble circuit 124'and is descrambled. Obtain a signal (compressed video signal). Further, in the codec (extension) circuit 12, the descrambled signal (compressed video signal) is variable-length decoded by the variable-length decoding circuit 125, dequantized by the dequantization circuit 126, and reverse-quantized by the inverse DCT transform circuit 127. The reproduced image 129 is restored by DCT and scanning inverse transform with the scan inverse transform circuit 128.

【0006】

The scramble block and the ECC block (scramble circuit 117'and ECC additional circuit 118 and descramble circuit 124' and ECC processing circuit 123) can be interchanged.

【0007】

Here, various methods have been proposed for scrambling in the scramble circuit 117', but the simplest method is to add Mod2 to the data to be transmitted such as video / audio by adding the random data generated by a specific generated polynomial to the data to be transmitted. .. For example, the generated polynomial is given in Equation 1 below. [0008]

[Number 1]

<img file="JPP3283771B2_D0001.tif" />Then, there is a method of generating random data with the preset data set to all bits "1".

【0009】

By distributing the descramble (scramble decoding) circuit 124'by the generation polynomial represented by the above equation 1 to the receiving contractor, the contractor can obtain data to be transmitted such as normal video / audio. However, if you do not have a reception contract, you will not know the generated polynomial expressed by Equation 1 above, and you will only be able to obtain scrambled, completely meaningless data, and you will not be able to obtain data that should be transmitted, such as normal video / audio. .. Here, scrambling to completely meaningless data is called "hard scrambling". Hard scrambling is also referred to as complete or strong scrambling. That is, the conventional scramble circuit 117'applies a hard (complete or strong) scramble to the compressed video signal.

【0010】

Various prior arts related to the present invention are known. For example, Japanese Patent Application Laid-Open No. 7-111647 (hereinafter referred to as Prior Art 1) relates to a scrambling device for limiting the playback of video data, and scrambles that can control the appearance according to the purpose. And a "signal processing device" that performs descramble processing is disclosed. In the prior art 1, the original signal is a video signal conforming to the MPEG standard, and the code detection device reads each code, detects the "det type" signal, and sends the detection signal to the random number generator. The random number generator generates a random number based on the scramble key, and exclusively ORs the signal from the random number generator to the original signal via the exclusive OR circuit to obtain a scrambled signal. The playback side performs reverse conversion processing with the same configuration. With such a configuration, it can be used not only as a scramble effect control but also as a special effect.

【0011】

Further, Japanese Patent Application Laid-Open No. 7-67096 (hereinafter referred to as Prior Art 2) relates to a scrambling device for limiting the playback of video data, and the scrambled data matches the reserved word. It discloses a "scramble device" that prevents malfunction of the regenerator due to the above. In the prior art 2, the code detection device reads the input signal for the input MPEG-compliant image data, detects the part that does not match the reserved word when scrambled, and scrambles it. Transmit the instruction to the random number generator. The random number generator generates a random number only when there is a scramble instruction from the code detection circuit, and performs an exclusive OR operation on the data. The playback side performs the inverse conversion.

【0012】

Further, Japanese Patent Application Laid-Open No. 4-8029 (hereinafter referred to as prior art 3) has high confidentiality and low-speed processing of the encryption unit by encrypting and transmitting only the initial value in the encoding method with an encryption key. However, it discloses an "encryption coding device" that reduces the size of hardware and reduces costs. In the prior art 3, the data compression means is composed of a compressor that compresses an 8-bit digital signal into a 4-bit code, and the signal converted by the signal conversion means is compressed by a coding method and transmitted. The encryption means encrypts only the initial value with a 64-bit key that is secretly determined between the sender and the receiver in advance. In the case of television, this initial value gives the initial value for each scanning line or for each fractional scanning line, so confidentiality is maintained by encrypting only the initial value of this coded data with an encryption key. Dripping.

【0013】

Japanese Patent Application Laid-Open No. 5-145923 (hereinafter referred to as Prior Art 4) proposes a replaceable security module. In Prior Art 4, the program signal is scrambled by the key. The key is encrypted twice and multiplexed with the scrambled program signal. The decoder performs a first key decryption using the second secret sequence signal stored therein, and then replaceable security using the first secret sequence number stored in the replaceable security module. Decrypted by the module. The decoder then descrambles the program with the decrypted key twice.

【0014】

[Problems to be Solved by the Invention]

As mentioned above, traditional scrambling methods provide only hard (completely or strongly) scrambled, completely meaningless data for those who do not have a subscription.

【0015】

However, it is said that if you can get a video that gives you a certain overview rather than random data that is completely meaningless, the viewer will want to make a contract and see the complete video / audio, and the number of reception contracts will increase. ing.

【0016】

For example, in analog broadcasting, WOWOW broadcasting has already broadcast video that gives an overview to some extent, and its effect is recognized in terms of increasing reception contracts.

【0017】

Further, since the prior arts 1 and 2 scramble using a random number generator, the scrambled data is completely meaningless data as in the conventional scrambling method. Prior art 3 is a technical idea of encrypting and transmitting only the initial value of encoded data with an encryption key, which is different from the technical idea of scrambling. Further, the prior art 4 is a technical idea of scrambling a program signal by a key, and the data to be scrambled is completely different from the present invention.

【0018】

Therefore, an object of the present invention is to make a non-contractor want to contract and watch a complete video / audio.

【0019】

[Means for solving problems]

The present invention solves the above-mentioned problems, and in a video transmission method of compressing an original video signal and transmitting a compressed video signal, the compressed video signal and / or the original video signal is converted into a compressed video signal and / or before the compression. On the other hand, it is a video transmission method characterized by scrambling.

【0020】

【0021】

As a specific example, when the compressed video signal is a signal obtained by orthogonally converting the original video signal and then quantization and variable length coding, the low frequency component is not scrambled in each orthogonal conversion block. The high frequency component is to be scrambled and transmitted. Then, in particular, scramble the only no low-frequency component, to a run / level combinations of numbers defined from the DC component and the low frequency side or the high-frequency component scrambling, the high-frequency side of the end-of-block-side It is characterized by having a specified number of run / level combinations from the to the low frequency side.

【0022】

[Action]

On the receiving side, if the receiving contractor decodes with a scramble decoder, the entire area data, that is, data such as complete video / audio can be reproduced, and if people who do not have a receiving contract decode without a scramble decoder, some patterns will appear. An image that can be discriminated can be played. As a result, it is possible to increase the desire to see the complete video / audio of those who do not have a reception contract and increase the reception contract.

【0023】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

【0024】

FIG. 1 shows a video transmitting device and a video receiving device according to an embodiment of the present invention (first embodiment).

【0025】

The video transmission device has a codec (compression) block 21, an ECC addition circuit 217, and a modulation circuit 218. The codec (compression) block 21 includes a scan conversion circuit 212, a DCT conversion circuit 213, a quantization circuit 214, a code amount control circuit 215, and a variable length coding (VLC) + scramble circuit 216.

【0026】

In the video transmission device, the original image (original video signal) 211 is subjected to video data compression processing by orthogonal conversion + quantization (Q) + variable length coding (VLC) in the codec (compression) block 21. There is a (motion compensation) DCT as a typical example of orthogonal conversion, and there is an MPEG2 method as a typical example of a compression format. In FIG. 1, the original image (original video signal) 211 is scan-converted by the scan conversion circuit 212, DCT-converted by the DCT transform circuit 213, quantized by the quantization circuit 214, and code amount controlled by the code amount control circuit 215. Is shown. After that, it is scrambled when the VLC table (not shown) is selected by the variable length coding (VLC) + scramble circuit 216. An error correction code is added to the output of the codec (compression) block 21 from the ECC addition circuit 217, and the transmission video data 219 is obtained after the modulation circuit 218 performs, for example, OFDM modulation processing peculiar to digital broadcasting.

【0027】

The video receiver has a demodulation circuit 221, an ECC processing circuit 222, and a codec (extension) block 22. The codec (extension) block 22 has a descramble + variable length decoding (VLD) circuit 223, an inverse quantization circuit 224, an inverse DCT circuit 225, and a scan inverse conversion circuit 226.

【0028】

In the video receiving device, for example, OFDM demodulation is performed on the received signal 220 by the demodulation circuit 221, code error correction processing is performed by the ECC processing circuit 222, and then decompression processing is performed by the codec (decompression) block 22. Here, the contractor with the scramble decoder uses the correct table in the discrete + variable length decoding (VLD) circuit 223 for variable length decoding, dequantized in the inverse quantization circuit 224, and inversely in the inverse DCT circuit 225. A complete reproduced image 227 can be restored by DCT conversion and scan reverse conversion by the scan reverse conversion circuit 226. On the other hand, non-contractors who do not have a scramble decoder can perform variable length decoding of low frequency components using the correct table and high frequency components using the wrong table in the discrete + variable length decoding (VLD) circuit 223. An incomplete reproduced image 227 is restored by inverse quantization by the inverse quantization circuit 224, inverse DCT conversion by the inverse DCT circuit 225, and scan inverse conversion by the scan inverse transform circuit 226.

【0029】

Figure 2 shows a block diagram of the VLC + scramble circuit 216. The VLC + scramble circuit 216 has a high-frequency / low-frequency component separation circuit 32, a timing adjustment memory 35, a VCL shift circuit 36, a scramble circuit 37, and an integrated circuit 38.

【0030】

Next, the operation of the VLC + scramble circuit 216 will be described with reference to FIG. The orthogonally converted and quantized video data 31 is separated into a low frequency component 33 and a high frequency component 34 by the high frequency / low frequency component separation circuit 32. Then, another table data having the same number of bits is assigned to the high frequency component 34 by the VLC shift circuit 36. Which table data is assigned is determined by the output data of the scramble circuit 37. The low frequency component 33 is delayed by the timing adjustment memory 35 while the high frequency component is subjected to the above processing. The low-frequency component delayed by the timing adjustment memory 35 and the high-frequency component scrambled by the VLC shift circuit 36 are integrated by the integrated circuit 38 and output to the ECC circuit 217 (Fig. 1) as the VLC + scrambled circuit output signal 39. ..

【0031】

Figure 3 shows a block diagram of the descramble + VLD circuit 223. The descramble + VLD circuit 223 includes a high-frequency / low-frequency component separation circuit 42, a timing adjustment memory 45, a VLD shift circuit 46, a descramble circuit 47, and a high-frequency / low-frequency component integrated circuit 48.

【0032】

Next, the operation of the descramble + VLD circuit 223 will be described with reference to FIG. The video data 41 input from the ECC processing circuit 222 (FIG. 1) is separated into a low frequency component 43 and a high frequency component 44 by the high frequency / low frequency component separation circuit 42. Then, the high frequency component 44 is converted into table data before scrambling having the same number of bits by the VLD shift circuit 46, and is subjected to variable length decoding. Which table data is the table data before scrambling is determined by the output data of the descramble circuit 47. The low frequency component 43 is delayed by the timing adjustment memory 45 while the high frequency component 44 is subjected to the above processing. The low-frequency component delayed by the timing adjustment memory 45 and the high-frequency component descrambled by the VLD shift circuit 46 are integrated by the high-frequency / low-frequency component integrated circuit 48, and are used as the descramble + VLD circuit output signal 49. It is output to the dequantization circuit 224 (Fig. 1).

【0033】

[Example]

Next, a specific example on the transmitting side will be described in the case where the orthogonal transform is a two-dimensional DCT transform in which 4 pixels × 4 lines are one block.

【0034】

FIG. 4 shows the matrix data 31 after the two-dimensional DCT transform and further the quantization. A zigzag scan of the data in FIG. 4 yields 15, -2,0,0,0, -1,0,0, -3,0,0,2,0,1,0,0 in order. Since this is variable-length coded by Huffman code, DC = 15, run = 0 / level = -2, run = 3 / level = -1, run = 2 / level = -3, Run = 2 / level = 2, run = 1 / level = 1, EOB. This is used as a luminance signal and is encoded by, for example, an MPEG2 variable length coding table. The MPEG2 variable length coding table is shown in Fig. 6 for the DC component and Fig. 7 for the AC component.

【0035】

In FIG. 6, the transmission code is assumed to be a sequence of the "codeword" 71 and the "additional bit" 72.

【0036】

In FIG. 7, R / L 81 indicates a 0 run / level combination, and length 82 indicates the bit length of the codeword. The transmission code is the data indicated by "codeword" 83. In addition, "escape" 84 is the transmission data for combinations that cannot be represented in this table, and details are shown in 85. Here, "R" 86 is 0 run and "L" 87 is level. The continuous arrangement of 88 and 89 is the transmission data. Note that FIG. 7 shows Note 1) + when the last bit s is 0 and-when it is 1 . Note 2) This code used in the first coefficient overlaps with EOB. Note 3) This is the code used from the second time onward. There is a caution like. Note that FIGS. 6 and 7 are transcribed versions of "ISO / IEC 13818".

【0037】

Now, using these figures, the coding results are in order, 1101 111,0100 1, 0011 11,0000 0010 111, 0000 1000,0110,10 Will be.

【0038】

Next, the low frequency components are not scrambled, only the high frequency components are scrambled. As an example, in the above data, DC and run / level shall be transmitted as one pair and then scrambled. That is, first, 1101 111,0100 1 Is sent as it is. Next, scramble is applied. At this time, the random data generated by the generated polynomial using the key is separated by 5 bits, and as a result, random data from 0 to 31 is generated. Random data generated by the generated polynomial, for example 00010,10010,00110,00011 Then, if it is divided into 5 bits, it becomes 2,18,6,3.

【0039】

First, scramble "001111", which has run = 3 / level = -1.

【0040】

0011 11 is 6 bits. The output with a bit length of 6 bits is also included, and the total is "0010 10" (run = 0 / level = 3), "001011" (run = 0 / level = -3), "0011 10" (run = 3). 3 / level = 1), 0011 11 (run = 3 / level = -1), 0011 00 (run = 4 / level = 1), 001101 (run = 4 / level = -1) There are 6 patterns. The underlined pattern indicates the pattern of run = 3 / level = -1.

【0041】

Since the random data for scrambling is initially 2, the patterns are arranged in the order shown in FIG. 7 of the MPEG2 variable length coding table, and the second data from 0011 11, that is, 0011 01 is extracted. Send.

【0042】

Next, scramble "0000 0010 111" with run = 2 / level = -3.

【0043】

This is 11 bits. The total output with a bit length of 11 bits is "0000 0010 100", "0000 0010 101", "0000 0011 000", "0000 0011 001", "0000 0010 110", "0000 0010 111". , "0000 0011 110", "0000 0011 111", "0000 0010 010", "0000 0010 011", "0000 0011 100", "0000 0011 101", "0000 0011 010", "0000 0011 011", There are 16 patterns of "0000 0010 000" and "0000 0010 001".

【0044】

Therefore, since the second random data for scrambling is 18, the patterns are arranged in the order of FIG. 7 in the MPEG2 variable length coding table, and the 18th data from 0000 0010 111, that is, 0000 0011 111. "Extract and send. When it reaches the end (0000 0010 001), it wraps around to the beginning (0000 0010 100).

【0045】

Next, scramble "0000 1000" with run = 2 / level = 2.

【0046】

Since the third random data for scrambling is 6, arrange them in the order shown in Fig. 7 of the MPEG2 variable length coding table in the same way as above, and send the sixth data from "0000 1000" to "0000 1100". To do.

【0047】

Next, scramble "0110" where run = 1 / level = 1.

【0048】

Since the fourth random data for scrambling is 3, arrange them in the order shown in FIG. 7 of the MPEG2 variable length coding table in the same manner as described above, and transmit the third data "0111" from "0110".

【0049】

And finally, EOB (End of Block, 10) is sent. That is, 0011 01,0000 0011 111,0000 1100,0111, 10 To send. To summarize all the transmitted data, 1101 111,0100 1, 0011 01,0000 0011 111, 0000 1100,0111,10 Will be. This is VLC + scramble circuit output data 39.

【0050】

Next, the operation on the receiving side will be described.

【0051】

The descramble + VLD circuit input data 41 is the same as the VLC + scramble circuit output data 39.

【0052】

As for the receiving contractor, since the key is known, the operation is reversed from that of the transmitting side, and the descramble + VLD circuit output data 49 is displayed. 1101 111,0100 1, 0011 11,0000 0010 111, 0000 1000,0110,10 From which, DC = 15, Run = 0 / Level = -2, Run = 3 / Level = -1, Run = 2 / Level = -3, Run = 2 / Level = 2, Run = 1 / level = 1, EOB, and the data in Fig. 4 can be completely restored.

【0053】

However, for those who do not have a reception contract, the key is unknown and 1101 111,0100 1, 0011 01,0000 0011 111, 0000 1100,0111,10 The descramble + VLD circuit input data 41 will be decoded as it is. That is, when the variable length data is variable length decoded according to FIGS. 6 and 7, the descramble + VLD circuit output data 49 has DC = 15, run = 0 / level = -2, run = 4 / level = -1. , Run = 4 / Level = -2, Run = 0 / Level = 4, Run = 1 / Level = -1, EOB, and the data shown in Fig. 5 can be obtained. Then, this data is inversely quantized and two-dimensional DCT transform is performed. This is because the low-frequency component is correct data but the high-frequency component is incorrect data, so when it becomes a video signal, a rough outline of the video can be obtained, but the detailed content cannot be understood.

【0054】

Next, another embodiment will be described.

【0055】

FIG. 8 shows a video transmitting device and a video receiving device according to the second embodiment of the present invention. The difference between the video transmitting device and the video receiving device shown in FIG. 17 is that the scramble circuit 117 is provided before the codec (compression) block 11 instead of after the codec (compression) block 11, and the descramble circuit 124 is provided at the codec (decompression) block 12 It is not in front of, but after. The scramble circuit 117 rearranges the picture data in the group-of-picture in a specific order according to the scramble for the video signal compressed by the MPEG2 method. The descramble circuit 124 returns the order rearranged by the scramble circuit 117 to the original order.

【0056】

Assume that the number of pictures in the group of pictures is 15. At this time, the scrambled output is divided into 4 bits and the order of the pictures is set. Suppose that the scrambled output separated by 4 bits continues, for example, 3,11,8,15,0,14,8,2, .... At this time, the transmission picture order continues as 3,11,8. However, when the number of pictures in the group of pictures is 15, 0 to 14 are valid, so the 4th "15" is skipped, and the 7th "8" which is the second appearance before all the pictures are made. Is also skipped.

【0057】

You can continue to send in the order of scrambling, or you can memorize the order in which the scramble output goes through one cycle and use that order forever.

【0058】

As a result, if the receiving side decodes using the scramble decoder (descrambling circuit 124), the images can be reproduced in the original order, and if decoded without the scramble decoder, the images in which the frame order is changed are reproduced, and the images are difficult to see. Is reproduced.

【0059】

FIG. 9 shows a video transmitting device and a video receiving device according to the third embodiment of the present invention. The difference between the video transmitter and the video receiver shown in FIG. 17 is that the scramble circuit 117A is provided after the scan conversion circuit 112 in the codec (compression) block 11A, not after the codec (compression) block 11. The descramble circuit 124A is provided in front of the scan inverse conversion circuit 128 in the codec (decompression) block 12A, not in front of the codec (decompression) block 12. The scramble circuit 117A rearranges the slice data in the picture in a specific order according to the scramble for the video signal compressed by the MPEG2 method. The descramble circuit 124A returns the order rearranged by the scramble circuit 117A to the original order.

【0060】

Suppose the number of slices in the picture is 30. At this time, the scrambled output is divided into 5 bits to form the order of the pictures. Suppose that the scrambled output separated by 4 bits continues, for example, 16,5,31,21,12,27,7,16, .... At this time, the transmission picture order continues as 16,5. However, when the number of slices in the picture is 30, 0 to 29 are valid, so the third "31" is skipped, and the eighth "16", which is the second appearance before all the pictures are made, is also skipped. Will be done.

【0061】

You can continue to send in the order of scrambling, or you can memorize the order in which the scramble output goes through one cycle and use that order forever.

【0062】

As a result, if the receiving side decodes using the scramble decoder (descrambling circuit 124A), the images can be played back in the original order, and if decoded without the scramble decoder, the images with the slice order changed are played back, which makes it difficult to see. Is reproduced.

【0063】

Referring to FIG. 10, the video transmitting device and the video receiving device according to the fourth embodiment of the present invention are shown in FIG. 9 except that the scrambling method of the scramble circuit and the descramble method of the descramble circuit are different. It has a configuration similar to that shown. Therefore, the scrambled circuit and the descrambled circuit are designated by reference numerals 117B and 124B, respectively. The scramble circuit 117B rearranges the macroblock data in the slice in a specific order according to the scramble for the video signal compressed by the MPEG2 method. The descramble circuit 124B returns the order rearranged by the scramble circuit 117B to the original order.

【0064】

Suppose the number of macroblocks in a slice is 45. At this time, the scrambled output is divided into 6 bits in the order of the pictures. Suppose that the scrambled output separated by 6 bits continues, for example, 42,34,18,6,59,24,37,51,29,32,11,42, .... At this time, the transmission picture order continues as 42,34,18. However, when the number of macroblocks in the slice is 45, 0 to 44 are valid, so the 5th "59" is skipped, and the 12th "42", which is the second appearance before all the pictures are made, is also It will be skipped.

【0065】

You can continue to send in the order of scrambling, or you can memorize the order in which the scramble output goes through one cycle and use that order forever.

【0066】

As a result, if the receiving side decodes using the scramble decoder (descrambling circuit 124B), the images can be reproduced in the original order, and if decoded without the scramble decoder, the images in which the macroblock order is changed are reproduced, which is difficult to see. The image is reproduced.

【0067】

Further, two or more combinations may be performed for scrambling the picture in the group of pictures, scrambling the slices in the picture, and scrambling the macroblock data in the slices.

【0068】

Figure 11 shows an example of a combination of scrambling a picture within a group of pictures and scrambling slices within a picture. That is, in this example, the scramble circuits 117 and 117A are arranged before and after the scan conversion circuit 112, and the descramble circuits 124A and 124 are arranged before and after the scan inverse conversion circuit 128, respectively.

【0069】

In addition, FIG. 12 shows an example of combining scrambling of slices in a picture and scrambling of macroblock data in slices. The scrambled and descrambled circuits are labeled with 117C and 124C references, respectively.

【0070】

As described above, it is assumed that the number of slices in the picture is 30 and the number of macroblocks in the slice is 45. At this time, 5 bits are taken out from the scrambled output once to obtain a slice number, and then 6 bits are taken out 45 times to obtain a macroblock number in the slice, which is continued 30 times. Alternatively, 11 bits (slice number 5 bits + macroblock number 6 bits) may be taken out and repeated 1350 (30 × 45) times. Further, the number of macroblocks 1350 in the picture may be serially numbered, and 11-bit extraction may be repeated 1350 times.

【0071】

The same applies to other combinations. As described above, applying soft scrambling to the original video signal by rearranging predetermined block units in a predetermined block in a specific order is also referred to as "shuffling" the original video signal.

【0072】

Further, a method of applying soft scrambling by selecting the variable-length coding table shown in the first half of the example and a method of applying soft scrambling (shuffling) by changing the block order shown in the latter half of the example may be combined. ..

【0073】

FIG. 13 shows an example in which the first embodiment (FIG. 1) and the second embodiment (FIG. 8) are combined. FIG. 14 shows an example in which the first embodiment (FIG. 1) and the third embodiment (FIG. 9) are combined. FIG. 15 shows an example in which the first embodiment (FIG. 1) and the fourth embodiment (FIG. 10) are combined. FIG. 16 shows an example in which the first embodiment (FIG. 1), the second embodiment (FIG. 8), and the third embodiment (FIG. 9) are combined.

【0074】

The division position of the low frequency component and the high frequency component can be arbitrarily selected. For example, the low-frequency component may be only a DC component and the high-frequency component may be other than that, or all the components may be high-frequency components. The low frequency component may be a combination of a specified number of runs / levels from the low frequency side, or may be a combination other than the combination of the number of runs / levels specified from the high frequency side.

【0075】

The orthogonal transform may be other than the DCT transform. Further, in the DCT conversion, one block is 4 pixels × 4 lines here, but 8 pixels × 8 lines, 16 pixels × 8 lines, 16 pixels × 16 lines, etc. can be arbitrarily selected.

【0076】

A VLC code table other than that shown in the examples may be used.

【0077】

The compression is not limited to the MPEG method, but is preferably an orthogonal transformation + quantization + variable length code method. For example, it can be applied to JPEG (Joint Photographic coding Experts Group) and the like.

【0078】

The scramble circuit may be preset in units of 1 macroblock, in units of 1 slice, in units of 1 picture, or in units of 1 group of pictures. The generation polynomial of the random data generation circuit in scrambling may be any expression, and it is also possible to support a scramble circuit that does not use the generation polynomial.

【0079】

The present invention is not limited to the above-described embodiment, and various modifications and modifications can be made without departing from the spirit of the present invention.

【0080】

[Effect of the invention]

As described above, the present invention is transmitted by applying the above-mentioned scrambling after and / or before compressing the original video signal. As a result, if the receiving contractor decodes using a scramble decoder (descramble circuit) on the receiving side, the entire area data, that is, complete video / audio data can be reproduced, but the receiving contract is not made. If people decode without a scramble decoder, it is possible to reproduce an image that can distinguish some patterns. Therefore, it has the effect of increasing the desire of people who do not have a reception contract to see the complete video / audio, etc., and increasing the number of reception contracts.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device by one Embodiment (1st Example) of this invention.

[Figure 2]

It is a block diagram which shows the VLC + scramble circuit used for the video transmission apparatus shown in FIG.

[Fig. 3]

It is a block diagram which shows the descramble + VLD circuit used for the video receiving apparatus shown in FIG.

[Fig. 4]

It is a figure which shows the matrix data when the 2D DCT transform is performed by the image transmission device, and is further quantized.

[Fig. 5]

It is a figure which shows the matrix data before dequantization when the descramble circuit does not exist in a video receiver.

[Fig. 6]

It is a figure which shows the variable length coding table (DC component) of the MPEG-2 system.

[Fig. 7]

It is a figure which shows the variable length coding table (AC component) of the MPEG-2 system.

[Fig. 8]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device by 2nd Embodiment of this invention.

[Fig. 9]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device according to 3rd Example of this invention.

[Fig. 10]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device according to 4th Embodiment of this invention.

[Fig. 11]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device which combined the 2nd Example (FIG. 8) and the 3rd Example (FIG. 9) of this invention.

[Fig. 12]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device which combined the 3rd Example (FIG. 9) and the 4th Example (FIG. 10) of this invention.

[Fig. 13]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device which combined the 1st Example (FIG. 1) and the 2nd Example (FIG. 8) of this invention.

[Fig. 14]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device which combined the 1st Example (FIG. 1) and the 3rd Example (FIG. 9) of this invention.

[Fig. 15]

It is a block diagram which shows the structure of the image transmitting device and the image receiving device which combined the 1st Example (FIG. 1) and the 4th Example (FIG. 10) of this invention.

[Fig. 16]

A block diagram showing a configuration of a video transmitting device and a video receiving device in which a first embodiment (FIG. 1), a second embodiment (FIG. 8), and a third embodiment (FIG. 9) of the present invention are combined. is there.

[Fig. 17]

It is a block diagram which shows the structure of the conventional video transmitting apparatus and video receiving apparatus.

[Explanation of symbols]

11,11A, 11B, 11C codec (compression) block 111 Original image (original video signal) 112 Scan conversion circuit 113 DCT transform circuit 114 Quantization circuit 115 Code amount control circuit 116 Variable Length Coded (VLC) Circuit 117,117A, 117B, 117C Scramble circuit 118 ECC additional circuit 119 Modulation circuit 120 transmission signal 12,12A, 12B, 12C codec (decompression) block 121 Received signal 122 Demodulation circuit 123 ECC processing circuit 124,124A, 124B, 124C descramble circuit 125 Variable Length Decoding (VLD) Circuit 126 Inverse quantization circuit 127 Inverse DCT transform circuit 128 Scan inverse conversion circuit 129 Playback image 21,21A, 21B codec (compression) block 211 Original image (original video signal) 212 scan conversion circuit 213 DCT transform circuit 214 Quantization circuit 215 Code amount control circuit 216 Variable Length Coded (VLC) + Scrambled Circuit 217 ECC additional circuit 218 Modulation circuit 219 Transmission signal 22,22A, 22B codec (decompression) block 220 Received signal 221 Demodulation circuit 222 ECC processing circuit 223 Desk rumble + variable length decoding (VLD) circuit 224 Inverse quantization circuit 225 Inverse DCT transform circuit 226 Scan inverse conversion circuit 227 Playback image 31 VLC + scrambled circuit input data 32 High / low frequency component separation circuit 33 Low frequency component 34 High frequency component 35 Timing adjustment memory 36 VLC shift circuit 37 scramble circuit 38 Integrated circuit 39 VLC + scrambled circuit output data 41 Desk rumble + VLD circuit input data 42 High / low frequency component separation circuit 43 Low frequency component 44 High frequency component 45 Timing adjustment memory 46 VLD shift circuit 47 Desk rumble circuit 48 High / low frequency component integrated circuit 49 Desk rumble / VLD circuit output data