Parallel arithmetic unit using memory array

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a parallel arithmetic unit using a memory array, and can switch between a first operation of sending a common instruction and a second operation of sending individual instructions at high speed, particularly for a plurality of arithmetic circuits. It relates to a parallel arithmetic unit.

【0002】

[Conventional technology]

Conventionally, as a parallel arithmetic unit using a memory array, for example, it is entitled Computational Ram described in the 1992 series 30.6.1 to 30.6.4. Paper (Duncan G. Elliott, W. Martin Snelgrove and Michael Stumm, "Computational Ram: A Memory-SIMD Hybrid and its Application to DSP", CICC 30.6.1-30.6.4; May, 1992). This is a semiconductor chip in which a two-dimensional memory array and a large number of arithmetic circuits are arranged. By selecting a word line, the two-dimensional memory array can read each information from a large number of memory elements connected to the word line at the same time, so that data can be simultaneously read to a large number of arithmetic circuits. Has the advantage of being able to supply. As a result, if the large number of arithmetic circuits are operated in parallel with a common instruction, arithmetic processing can be performed at high speed. As described above, a computer that causes a plurality of arithmetic units to calculate the same instruction in parallel at the same time is known.

【0003】

[Problems to be Solved by the Invention]

The above-mentioned conventional example is a so-called SIMD (Single Instruction Multiple Data) on a semiconductor chip. stream) It forms a calculator. This is a single instruction multiple data flow calculator, which is one of the parallel processing methods, and each arithmetic unit performs the same arithmetic in parallel with instructions issued by the control unit to many arithmetic units having the same structure. Execute. Each arithmetic unit reads different data by accessing the shared storage device via the coupling unit, performs the arithmetic operations, and then stores the results. This method is suitable when the same processing is applied to all the image elements in the image, and is suitable for a field that requires an operation on a set such as a vector or an array. For example, specialized machines for scientific and technological calculation processing, image processing, signal processing, data search, pattern matching, associative processing, etc. have been developed. With these processing devices, if the degree of parallelism of the problem is sufficiently high, processing can be performed at a much higher speed than in the case of performing sequential processing with a normal CPU. However, for example, in the drawing process of 3D computer graphics, the process with a high degree of parallelism such as changing the color of the entire screen according to the same rule and the drawing of polygons are limited in the screen. Processing with a low degree of parallelism, in which processing is performed for each part, is mixed. In such a case, even if the above-mentioned conventional example is used, a sufficient effect cannot be expected. That is, when drawing an object in which triangles (polygons) are attached to a curved surface for polyhedron approximation, all the polygons displayed on the same screen are not the same, and therefore cannot be drawn according to the same rules by parallel processing. Must be drawn separately. When performing such processing, MIMD (Multiple Instruction Multiple Data) stream) It is desirable to process with a computer, that is, a computer with multiple instructions and multiple data flows. The MIMD calculator includes the entire system with distributed controls. An object of the present invention is to solve such a conventional problem, and even when processing in which SIMD operation and MIMD operation are mixed is performed, there is no time loss due to switching of operations, and the degree of parallelism of a given problem is achieved. In addition, it is an object of the present invention to provide a parallel arithmetic unit using a memory array that can efficiently control an arithmetic circuit.

【0004】

[Means for solving problems]

In order to achieve the above object, the parallel arithmetic unit of the present invention may (a) operate in parallel by receiving a plurality of data and a memory array (MAR in FIG. 1) capable of reading a plurality of data in parallel. A plurality of possible arithmetic circuits (PE1 to PEn), a first bus (LS) for transmitting a common first instruction signal to a plurality of arithmetic circuits (PE1 to PEn), and a plurality of second instruction signals, respectively. Multiple instruction buffers (BUF) for holding and multiple second buses for transmitting multiple second instruction signals held in multiple instruction buffers (BUF) to multiple arithmetic circuits (PE1 to PEn). And a switching means (SW-OP) for selecting either the first bus or a plurality of second buses and connecting them to a plurality of arithmetic circuits (PE1 to PEn), and the arithmetic circuits (PE1 to PEn) are provided. ) And the first bus are connected, and the plurality of instruction buffers (BUFs) are characterized in that a plurality of second instruction signals can be written. In addition, (b) a memory array (MAR) for storing multiple data and a plurality of arithmetic circuits capable of receiving multiple data read in parallel from the memory array (MAR) and operating in parallel (each). PE1 ~ PEn), the first bus (LS) for transmitting common instructions to multiple arithmetic circuits (PE1 ~ PEn), the instruction buffer (BUF) for storing multiple instructions, and the instruction buffer (instruction buffer). Multiple second buses for transmitting multiple instructions stored in BUF) to multiple arithmetic circuits (PE1 to PEn), and multiple buses by selecting either the first bus or the second bus. The instruction buffer (BUF) while the first switch means (SW-OP) for connecting to the arithmetic circuit (PE1 to PEn) and a plurality of arithmetic circuits (PE1 to PEn) are operating in response to a common instruction. ), A means for inputting new instructions to the instruction buffer (BUF), a third bus (LM) for transmitting multiple instructions to the instruction buffer (BUF), and multiple switches connecting the instruction buffer (BUF) and the third bus. Select one of the second switch means (SW-BUF) and the second switch means (SW-BUF).

【0005】

[Action]

In the present invention, the data of the memory cells on the word line read in parallel from the two-dimensional memory array is sent from the transfer network to the arithmetic circuit group, so that the arithmetic circuit group is transferred data. Perform arithmetic processing in parallel using. In that case, the arithmetic circuit group has a first operation mode in which common instructions are processed in parallel and a second operation mode in which different instructions are processed in parallel for each arithmetic circuit. In that case, the first operation mode and the second operation mode are switched by the operation of the switch, and in the first operation mode, the same parallel processing is performed by the common instruction transferred to the arithmetic circuit group at the same time via the switch. In the second operation mode, different instructions are transferred from the instruction buffer written during the first operation mode to the arithmetic circuit group via the switch, and then parallel processing of each different arithmetic is performed. .. As a result, a large amount of information can be read out at the same time by selecting a word line in the two-dimensional memory array, so that data can be supplied to a large number of arithmetic circuits formed on the same semiconductor substrate at the same time. There is an advantage. Further, the arithmetic circuit group can perform so-called SIMD operation when inputting an instruction from a signal line for transmitting a common instruction by a switch, and input a plurality of different instructions from the above instruction buffer. In some cases, it is possible to perform so-called MIMD operation. Further, while the arithmetic circuits are performing SIMD operation with a common instruction, the instruction at the time of MIMD operation can be written in the above instruction buffer. Therefore, even when SIMD operation and MIMD operation are performed continuously, high-speed processing is possible.

【0006】

[Example]

Hereinafter, examples of the present invention will be described in detail with reference to the drawings. FIG. 1 is a basic configuration diagram of a parallel arithmetic unit showing a first embodiment of the present invention. The memory-based parallel computing chip according to this embodiment can continuously perform SIMD operation and MIMD operation at high speed. In this embodiment, as shown in FIG. 1, a sense amplifier SA for reading and latching data on one word line of a two-dimensional memory array-MAR and a two-dimensional memory array-MAR in parallel, and a read data. Transfer network TN that transfers data to arithmetic circuits PE1, PE2, .., PEn, stores serially input data and transfers it to arithmetic circuits PE1 to PEn in parallel, or arithmetic circuits Serial access memory SAMe for transferring the output of the group in parallel and outputting it serially, switch group SW-OP for switching between SIMD operation and MIMD operation, instruction OP-s common to the arithmetic circuit group during SIMD operation Signal line to be transmitted LS, instruction buffer BUF for storing instructions for MIMD operation, switch group SW-BUF for transferring instructions to instruction buffer BUF, instruction OP-m for MIMD operation It consists of a recorder PEdec that inputs the signal line LM and the address PEadd of the arithmetic circuit and selects the switch that transfers the instruction OP-m.

【0007】

Hereinafter, the operation of this embodiment will be described with reference to FIG. The arithmetic circuit groups PE1, PE2, .., and PEn in this embodiment perform parallel arithmetic using data from the two-dimensional memory array MAR and a plurality of data read from the serial access memory SA Min. The arithmetic circuit groups PE1 to PEn can be controlled by two operation modes, SIMD operation and MIMD operation. The two operation modes, SIMD operation and MIMD operation, can be switched by controlling the switch group SW-OP with the operation mode switching signal φS / M. That is, when the operation mode switching signal φS / M becomes high level, SIMD operation is performed, and the common instruction OP-s is transmitted to the arithmetic circuit group PE1 to PEn through the signal line LS, and the arithmetic circuit group PE1 to PEn. Then, common processing is performed for the given data. On the other hand, when the operation mode switching signal φS / M becomes low level, MIMO operation occurs, and multiple instructions are transmitted in parallel from the instruction buffer BUF to the arithmetic circuit groups PE1 to PEn via the switch group SW-OP, and the operation is performed. In the circuit groups PE1 to PEn, different processing can be performed for each arithmetic circuit for the given data. Instructions are written to the instruction buffer BUF by giving the address of the arithmetic circuit from the decoder PEdec to the switch group SW-BUF while the operation mode switching signal φS / M is performing SIMD operation at a high level. This can be done by opening the contacts of the corresponding switch group SW-BUF and writing the individual instructions OP-m to the specified position in the buffer BUF.

【0008】

In this way, different instructions OP-m during MIMD operation are input from the signal line LM and written to the instruction buffer BUF through the switch group SW-BUF. The position of the instruction buffer BUF to which the instruction OP-m is written can be controlled by inputting the addresses PEadd of the arithmetic circuits PE1 to PEn to the recorder PEdec. As a result, the instruction can be transferred to the arithmetic circuits PE1 to PEn corresponding to the address PEadd. The instruction is transferred by writing the necessary instruction to the instruction buffer BUF and then lowering the operation mode switching signal φS / M. As described above, in this embodiment, it is possible to perform processing in which SIMD operation and MIMD operation are mixed. Further, since the instruction required for the next MIMD operation can be written to the instruction buffer BUF during SIMD operation or another MIMD operation, it is possible to switch the operation mode at high speed. In this embodiment, the above devices are formed on the same semiconductor substrate, and the arithmetic circuit groups PE1 to PEn, the serial access memory SAMe, and the instruction buffer BUF are arranged directly under the two-dimensional memory array-MAR. It is possible to easily increase the number of signal wirings between the arithmetic circuit group PE1 to PEn, the memory array-MAR, the serial access memory SAMein, and the instruction buffer BUF. Therefore, it is possible to perform SIMD operation and MIMD operation with a very high degree of parallelism. In addition, the data transfer distance from the two-dimensional memory array-MAR to the arithmetic circuit PE1 to PEn and the instruction transfer distance from the instruction buffer BUF to the arithmetic circuit PE1 to PEn can be made almost constant and extremely short. , The distance between the arithmetic circuits PE1 to PEn is also constant and extremely short. Therefore, in addition to the advantage that the delay time related to the transfer is small, there is also an advantage that the variation between the arithmetic circuits is small and it is easy to synchronize between the arithmetic circuits. Furthermore, the present invention can be applied to various other processing modes.

【0009】

FIG. 2 is a configuration diagram of a parallel arithmetic unit that performs drawing processing of three-dimensional computer graphics showing a second embodiment of the present invention, and FIG. 3 is a diagram showing a configuration of a transfer network in FIG. , FIG. 4 is an explanatory diagram showing an arithmetic circuit for α blending and Z buffer, and FIGS. 5 and 6 are diagrams showing a configuration of the arithmetic circuit in FIG. The drawing process of 3D computer graphics is a process of writing a 3D scene viewed from a certain viewpoint into a frame memory corresponding to a 2D screen. Hereinafter, an example in which the Z-buffer processing for expressing the depth and the α-blending processing for expressing the transparency of the object are performed at high speed will be described with reference to FIGS. 2 to 6. First, in the Z-buffer processing, the Z-coordinate of the newly input pixel data (coordinates representing the depth) is compared with the Z-coordinate of the pixel data of the same address in the frame memory, and the newly input pixel data is newly input. Only when the Z coordinate of the pixel data is small, the newly input pixel data is written to the frame memory. This makes it possible to express the image of a three-dimensional space in which the object in the foreground hides the object in the back. Next, in the α blend process, the weighted linear sum of the newly input pixel data and the existing pixel data is used as the new pixel value, so that the object in the foreground is transparent and the back is displayed. It shows the effect of seeing an object.

【0010】

In the embodiment of FIG. 2, a plurality of arithmetic circuits are prepared and high-speed drawing processing is performed so that pixel data on one line of the screen can be processed in parallel. In this embodiment, the arithmetic circuit group can be controlled by switching between SIMD operation and MIMD operation as needed. Therefore, when changing the value of the entire screen or the pixel data in a wide range, common parallel processing is performed for each line by SIMD operation, while it differs for pixels in a limited range such as polygon processing. When drawing with parameters, parallel processing for one line over multiple polygons can be performed by MIMD operation. In this embodiment of FIG. 2, a serial access memory SAMout for outputting image data, a two-dimensional memory array-FMAR for storing image data for one screen, and a sense amplifier SAfm, 2 for a two-dimensional memory array-FMAR. Switch group SW-tr for transferring data between dimensional memory array-FMAR and buffer memory array-BMAR, buffer memory array-BMAR sense amplifier SAbm, buffer memory array-BMAR and arithmetic circuit group PE1, PE2, .., Transfer network for transferring data between PEn TNbm, Switch group for switching between SIMD operation and MIMOD operation SW-OP, Instruction OP-s common to arithmetic circuit group during SIMD operation Signal line to be transmitted LS, serial access memory SAMin that stores image data input serially, transfer circuit TNin for transferring data in parallel from the serial access memory SAMin to the arithmetic circuit group, for MIME operation operation Input the instruction buffer BUF for storing the instructions, the switch group SW-BUF for transferring the instructions to the instruction buffer BUF, the signal line LM for inputting the instruction OP-m during MIMOD operation, and the address PEadd of the arithmetic circuit. It is composed of a decorator PEdec that selects the switch that transfers the instruction OP-m.

【0011】

The operation of the embodiment of FIG. 2 will be described below. The screen display in FIG. 2 is performed by sequentially reading out the information of the two-dimensional memory array FMAR that stores the image data for one screen. That is, the two-dimensional memory array-FMAR word lines may be selected in order, transferred to the serial access memory to SAMout, and read serially. Here, as the information representing the pixel, there are R, G, B representing the density of each of the red, green, and blue of the pixel and Z representing the depth, so p bits representing R, G, and B (usually each). Transfer 8 bits (24 bits in total) to the serial access memory SAMout. On the other hand, when the screen is switched or the viewpoint or the object on the screen changes, it is necessary to rewrite all or part of the contents of the 2D memory array-FMAR. To switch the screen that was displayed until then to a completely new screen, write the new pixel data input to the serial access memory SAMini directly to the 2D memory array-FMAR. For that purpose, first, the switch group SW-OP is switched, the arithmetic circuit group is set as the SIMD operation mode, and the instruction OP-s is set as NOP (no operation).

【0012】

In that state, conduct the switch group SW-tr, and through the data lines of the transfer network TNin, TNbm and buffer memory BMAR, the new pixel data input to the serial access memory SAMin is the two-dimensional memory array-FMAR. Write in parallel to the memory cells on the word line. You can switch to a new screen by selecting the 2D memory array-FMAR word lines in order and writing. In addition, when the viewpoint or the object on the screen changes, SIMD operation or MIMD operation is processed depending on the situation. For example, when another screen is superimposed on the entire screen that has been displayed so far, α processing may be performed on the entire screen as the mode of SIMD operation. On the other hand, when only the object constituting a part of the image changes, only the pixels in the vicinity of the object need to be changed. In this case, as the mode of MIMD operation, the processing of the corresponding part is rewritten line by line. In this case, since it is MIMD operation, the arithmetic circuit of the part that does not change for each pixel on one line is set to NOP (no operation), or α processing is performed with different parameters for each pixel. It is possible. Therefore, even if there are a plurality of polygons on one line and different processing is performed for each polygon, parallel processing can be performed for each line. Furthermore, since one line of instructions can be prepared in the instruction buffer BUF before shifting to the new MIMD operation, high-speed processing is possible.

【0013】

FIG. 3 shows the configuration of the transfer circuit in FIG. As described above, in the embodiment of FIG. 2, when the arithmetic circuit groups PE1 to PEn are arranged directly under the buffer memory BMAR, the delay time related to the transfer becomes small, the variation between the arithmetic circuits is small, and the arithmetic is performed. It becomes easy to synchronize between circuits. However, since the pitch of the data line of the memory array FMAR is generally small, the arithmetic circuits PE1 to PEn cannot be arranged within the pitch of the data line for one pixel. In that case, as in the embodiment of FIG. 3, the arithmetic circuits PE1 to PEn may be arranged within the pitch of the data lines for h pixels. In Fig. 3, the transfer network TNbm switches the correspondence between the data line of the buffer memory BMAR and the arithmetic circuits PE1 to PEn. The transfer circuit TRC-S is an h-to-1 selector, and TRC-B is a temporary buffer circuit. Is. When transferring data from the buffer memory BMAR to the arithmetic circuits PE1 to PEn, the data for h pixels read from the buffer memory BMAR is 1 from the data for h pixels by the transfer circuit TRC-S. The data for the pixels is selected and transferred to the arithmetic circuits PE1 to PEn through the temporary buffer circuit TRC-B. Conversely, when transferring data from the arithmetic circuits PE1 to PEn to the buffer memory BMAR, the transfer circuit TRC-S selects the data line for one pixel from the data line for h pixels. Is written to the buffer memory BMAR. As described above, according to this embodiment, since the arithmetic circuits PE1 to PEn may be arranged within the pitch of the data lines for h pixels, there is an advantage that the layout can be easily performed.

【0014】

The examples of FIGS. 4 and 5 are detailed explanatory views for giving the arithmetic circuit the functions of Z-buffer processing and α-blending processing in the embodiment of FIG. Fig. 4 (a) shows the functions of the arithmetic circuit (input / output relationship), Fig. 4 (b) shows the output contents corresponding to the instructions, and Fig. 5 shows an example of the specific configuration of the arithmetic circuit. Each is shown. In FIG. 4 (a), (R, G, B, Z), (R', G', B', Z'), (R , G, B , Z), Op-s / OP -m is the pixel input from the buffer memory BMAR to the arithmetic circuits PE1 to PEn, the component of the pixel input from the serial memory SAMein, the arithmetic result pixel, and the instruction during SIMD operation / instruction during MIMO operation, respectively. is there. R, R', R "are the red density, G', G, G" is the green density, B, B', B "is the blue density, and Z, Z', Z" is the depth. It is a coordinate value. In each calculation circuit PEi, depending on the content of the instruction, the calculation result pixels (R , G, B , from the components of the pixels input from the buffer memory BMAR to the calculation circuit PEi and the pixels input from the serial memory SAMein, Calculate Z ). Figure 4 (b) shows an example of the contents of instructions and processing. Although the instructions are written in alphabets here for convenience, they are actually defined in binary code. Here, the instruction INS-z is an instruction for performing Z-buffer processing. As shown in the table, this instruction compares Z and Z'and outputs the smaller pixel component. As a result, the effect that the object in the back is hidden by the object in the foreground can be realized. Instructions (INS-α, α, β) are instructions for performing α-blending processing. As shown in the table, this instruction outputs a linear combination in which the B, G, and R components of the two input pixels are weighted with coefficients α and β. As a result, it is possible to realize the effect that the object in the back can see through the object in the foreground. Coefficient α, Transparency can be adjusted by changing β. The smaller value of Z at this time is the output value. The instruction NOP means no operation, and the pixels (R', G', B', Z') input from the serial memory SAMe are sent as they are as the output without doing anything in the arithmetic circuit. As described above, this instruction is transmitted to the arithmetic circuit corresponding to the pixel to be left as it is when the screen is rewritten or when only a part of the pixel for one line is processed in the MIMD operation.

【0015】

FIG. 5 shows an example of a specific configuration of the arithmetic circuit. In FIG. 5, the data register REG-data is a register for temporarily storing the components of the input pixel and the coefficient of the α blend processing. The instruction register REG-ins is a register for storing instruction codes and controlling switches and circuits according to the instruction codes. The comparison circuit COM is a circuit that compares the values of Z and Z'. The multiplier MT and accumulator ACC use the values of R, R', G, G', B, B'from one input terminal of the multiplier MT and the coefficients from the other input terminal in the case of α-blending processing. By inputting α and β, the product-sum calculation of the pixel data and the coefficient is performed, R ", G", B "is calculated, and then temporarily stored in the accumulator ACC. Z-buffer processing In the case of, the switch SW-1 is conducted, and SW-3 or SW-4 is conducted depending on the result of the comparison circuit COM. Therefore, when Z Z as the output Z , Z and the output R, G, B are sent as R , G , B , and Z , and R , G , B are sent when Z> Z (see Fig. 4 (b)). In the case of α blend processing, switches SW-1 and SW-5 are conducted. As a result, αR + βR , αG + βG , αB + as outputs R , G , B . When Z Z as βB and Z , Z, Z> When Z', Z'is sent respectively (see Fig. 4 (b)). In the case of NOP, the switches SW-2 and SW-3 are conducted. As a result, R G B Z is sent as the output R G B Z (see FIG. 4B). As described above, according to this embodiment, when changing the value of the pixel data of the entire screen or a wide range, common parallel processing is performed for each line by SIMD operation, and it is limited to polygon processing. When drawing with different parameters for the pixels in the specified range, parallel processing for one line over a plurality of polygons can be performed by the MIMD operation. Therefore, the drawing process of the three-dimensional computer graphics can be performed at high speed. For example, if the image memory formed on the semiconductor chip of this embodiment is used for a personal computer, a game device, or a mobile information device, a complex three-dimensional image that responds in real time is displayed. be able to.

【0016】

In the embodiment of FIG. 5, a product-sum operation is required to perform the α-blending process. In Fig. 5, the multiply-accumulate calculator is composed of the multiplier MT and the accumulator ACC, but in general, the area occupied by the multiplier is large, and it is difficult to lay out the calculator PEi at a narrow pitch depending on the circuit used. It is possible that The embodiment of FIG. 6 shows a method of realizing a product-sum operation for α-blending processing with a shift register and an adder, and has a configuration suitable for laying out the arithmetic unit PEi in a narrow pitch. is there. That is, in FIG. 6, the pixel components (R, G, B), (R', G', B') are sent to the shift registers SR1, SR2, SR3, SR4 for each RGB component through the selector SELECT. The figure shows the case where the R component and the R'component are blended at a ratio of α = 1/4 and β = 3/4. For the sake of explanation, it is assumed that the R component and the R'component are (00001100) and (00100000) in binary notation, respectively. When the R component and R'component are sent to the shift registers SR1, SR2, SR3, SR4, the signal from the instruction decoder DEC shifts two digits to the right for SR1 and one and two digits to the right for SR3 and SR4, respectively. Be shifted. As a result, the output of SR1 is 1/4 of the R component, and the outputs of SR3 and SR4 are 1/2 and 1/4 of the R'component, respectively.

【0017】

When these are input to the adders ADD1 and ADD2 through the switch, the outputs of the adders ADD1 and ADD2 are 1/4 of the R component and 3/4 of the R'component, respectively. Furthermore, by adding these with the adder ADD3, the sum (00011011) of 1/4 (= α) times the R component and 3/4 (= β) times the R component is output as R . Can be done. The G and B components may be calculated in the same way. Here, the case of α = 1/4 and β = 3/4 has been described, but by controlling the shift amount and the opening / closing of the switch according to the values of α and β, (α, β) = (3 / 3 / The blend amount of 4,1 / 4), (1/2, 1/2), etc. can be changed. In the above, the number of digits of the shift register is set to be larger than the number of digits of the input pixel component, but this is to prevent overflow at the time of shifting. As described above, in the present embodiment, the product-sum operation for the α-blending process can be realized by using a shift register, an adder, or the like having a small circuit scale. Therefore, it is suitable for laying out the arithmetic circuit PEi at a narrow pitch.

【0018】

As shown in FIG. 1, according to the parallel arithmetic unit of this embodiment, the arithmetic circuits PE1, PE2, .., PEn are read out in parallel from the two-dimensional memory array-MAR formed on the same semiconductor substrate. By using a large amount of information and performing SIMD operation or MIMD operation, it is possible to execute parallel operations according to the problem. That is, these arithmetic circuits operate with a common instruction OP-s during SIMD operation, and operate with a plurality of different instruction OP-m supplied from the instruction buffer BAF during MIMD operation. Since the instruction OP-m during MIMD operation can be written to the instruction buffer BUF while the arithmetic circuit group is performing SIMD operation or MIMD operation, processing in which SIMD operation and MIMD operation are mixed is performed. Even in this case, there is no time loss due to switching of operations, and high-speed processing is possible. Although the two examples have been described above, in FIGS. 1 and 2, the detailed configuration of the two-dimensional memory array, the method of generating the control signal, and the like are omitted. This is because these can be easily configured by the technology used in ordinary LSIs. For example, as the two-dimensional memory array, a SRAM array, a DRAM array composed of one transistor cell, or the like can be used. When a DRAM array is used, there is an advantage that a two-dimensional memory array can be highly integrated as compared with the case where a SRAM array or the like is used.

【0019】

[Effect of the invention]

As described above, according to the present invention, since the arithmetic circuit can be efficiently controlled according to the degree of parallelism of a given problem, for example, it is possible to perform drawing processing of 3D computer graphics at high speed. Furthermore, high-speed processing is possible even when SIMD operation and MIMD operation are performed continuously.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of the memory-based parallel arithmetic chip which shows 1st Embodiment of this invention.

[Figure 2]

It is a block diagram of the image memory which shows the 2nd Example of this invention.

[Fig. 3]

It is a block diagram of the transfer network in the Example of FIG.

[Fig. 4]

It is explanatory drawing which shows the input / output and function of the arithmetic circuit for α blending and Z buffer in this invention.

[Fig. 5]

It is a detailed block diagram which shows the Example of the arithmetic circuit in FIG.

[Fig. 6]

It is a block diagram which shows the Example of the α processing circuit in FIG.

[Explanation of symbols]

MAR1 2D memory array- SA, SAfm, SAbm sense amplifier TN, TNbm, TNin Transfer Network PE1, PE2, .., PEn arithmetic circuit SAMin, SAMout serial access memory BUF instruction buffer PEdec decorator FMAR frame memory SW-BUF, SW-OP, SW-tr switch group LS, LM signal line PEdec decoder PEadd arithmetic circuit address Xadd, Yadd Word and data line addresses BMAR buffer memory TRC-S, TRC-1 h to 1 selector TRC-B temporary buffer circuit SELECT selector SR1 ~ SR4 shift register ADD1 ~ ADD3 adder DEC instruction decoder