Digital multirate-multiplexing/demultiplexing method.

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to multiplexing a large number of parallel digital channels with different primary rates into a single digital frame having a predetermined period and period, and vice versa. ..

【0002】

[Conventional technology]

Due to the multiplexing of multiple digital channels, current technology allows multiple digital channels bit by bit, or byte by byte, and more generally word by word with a given number of bits, above the maximum common multiple of the primary rate. It is multiplexed into one frame with a high predetermined high bit rate. The bit rate is constant within the frame. The frame is divided into multiple sectors to manage the frame, and management data is inserted at regular intervals, and this management data is characterized by the transmission quality of the frame and data for the state of at least one digital channel. Is related to.

【0003】

A central station with a large number of terminals connected Regardless of the value of the primary rate of the terminal station receiving one frame generated by the central station, the terminal station needs to match the transmission and reception to the high online bit rate of the frame. .. The terminal station has a frame multiplex separator, which is adjusted to the layer level of the digital channels, and each digital channel is taken out.

【0004】

[Problems to be Solved by the Invention]

Another way to separate multiple digital channels with different bit rates coming from the central station is to physically distinguish the transmitters placed between each station as a function of the channel bit rate. In this case, a star-shaped transmission network whose online rate corresponds to the channel rate is added to each group of terminal stations connected to digital channels having the same rate. When a new bit rate is adopted for a terminal station, it is necessary to newly configure a network transmission network.

【0005】

[Purpose of Invention]

The main object of the present invention is to eliminate the above-mentioned drawbacks by constructing one multi-rate frame, which is called a modulation rate and is added to various types of terminal stations. Online rates are mixed, and these various online rates are transmitted between the central station and the terminal station through one transmission line. Conversely, in the conventional technique, one frame obtained by time-division multiplexing of primary source data having various low rates has a constant binary bit rate, that is, all the bits in the frame arrive. It is specifically based on the fact that the pulse widths are equal regardless of the primary source rate.

【0006】

[Means for solving problems]

Here, we propose a method for multiplexing a large number of parallel digital channels having a plurality of different primary rates into one digital frame having a predetermined period and period. This frame has a plurality of sectors for a predetermined period, and a plurality of digital channels are assigned to these sectors from among a large number of channels. The multiple online rates within a sector are each greater than the primary rate of the assigned channel, but these multiple online rates differ from and are divisors of the higher online rates.

【0007】

According to a preferred embodiment, this method essentially constitutes one predetermined frame based on each of the following steps: (1) In order to form a group stored in parallel from serial channel bits, channel bits are stored during one frame period preceding a predetermined frame at various primary rates, respectively, (2). By reading in parallel the channel bits of the group on and off for each primary rate of the channel throughout each period of the sector within a given frame, this results in the same number of bits as the sector within the frame. Each of the groups is repeated, (3) multiple digital channels from each of a large number of digital channels are assigned to sectors of a predetermined frame, and (4) repeated from each of the allocated channels throughout the period of each sector. By selecting one of the bits in a parallel group, this multiplexes the bits in the selected group into a given frame containing a group of one selected bit per sector.

【0008】

This method can be used for both full-duplex mode transmission and half-duplex mode transmission, and the frame duration is less than half the frame period.

【0009】

The present invention also relates to a multiplexing device that implements the above-mentioned multiplexing method. The multiplexing device consists of: (1) Multiple devices for storing multiple channel bits in parallel, (2) Multiple devices for writing multiple channel parallel group bits to multiple storage devices at primary rate during each frame period Devices, (3) Multiple devices for reading a group of bits into the storage device at each online rate corresponding to multiple primary rates of the channel throughout each period of the sector of the frame, and thereby the sectors within the frame. A device for storing the addresses of a plurality of digital channels assigned to a frame sector from a large number of channels, (5) a frame, in which the group of bits is repeated the same number of times as the above. A device for reading the allocated channel address corresponding to the period of each sector of (6) for multiplexing the bits of each read group according to the allocated channel address and throughout the period of the sector of the frame. apparatus.

【0010】

On the contrary, the present invention presents a method of multiplexing a digital channel from a predetermined frame having the same sector as the sector obtained by the multiplexing method of the present invention, and a multiplex separation for carrying out this multiplexing method. Regarding the conversion device.

【0011】

The multiple separation method consists of the following steps: By (1) storing the channel bits contained in multiple sectors of the frame at the highest online rate, and (2) reading each group of series bits related to the bit rank to all sectors. The rank is defined for the bits in the sector with the highest online rate, each group has bits of the same rank in the sector, and the reading of the group is done with the highest primary rate. As a result, the multiplexed signal in which the sector is multiplexed bit by bit during the frame period is taken out. (3) Bits of the multiplexed signal are periodically rotated in the direction of the digital channel assigned to the sector. To switch.

【0012】

The demultiplexer consists of: (1) A device that converts the series channel bits in each sector of the frame into a contiguous group of NB parallel channel bits, and the number of bits NB is a fraction of the number of channel sectors NS of the frame (2). A device that stores NB parallel bit groups during a frame period, (3) Number of bits To write NB parallel bit groups to the storage device with a rate that is a fraction of the highest online rate of the frame sector for NB. Device, (4) Number of sectors A device for reading NB parallel bit groups to the storage device with a rate that is a multiple of the highest primary channel rate for NS, and reading the group is NS frame sectors. NS groups of NB parallel bits containing NB bits of the same rank are continuously read at a rate that is a multiple of the above to form a set of NS groups, and ranks. Is defined for the bits in the sector with the highest online rate, and each of the NS group pairs is read NB times in a row with the highest primary rate, (5) continuously. A device that continuously selects NB series, each of which has NS consecutive bits in the same set of NBs read, in one series with the same rank in the above sector. The NB series is selected in ascending order of the rank of the bits in the sector, which allows the sector to retrieve the multiplexed signal that is multiplexed bit by bit during the frame period. (6) A device for switching the bit of the multiplexed signal in the direction of the digital channel according to the matching relationship between the address of the frame sector and the address of the channel.

【0013】

Furthermore, a communication network is given to the central station for multiple terminal stations that communicate with the central station via a multi-rate three-layer structure communication medium and work in both directions, but this communication network has various primary rates. It is connected to digital incoming and outgoing channels. Each terminal station is associated with a primary rate and matches an online rate higher than the primary rate. The central station has the above-mentioned multiplexing device and multiplex separation device according to the present invention.

【0014】

Due to these conditions, the terminal station is connected to one of a set of bidirectional digital channels, and one of the primary rates of this set of channels is associated with one of the given online rates, but to this terminal station. Outcomes from a device that retrieves a sector at the associated online rate from the first frame leaving the central station, a device that converts the retrieved sector into a group of bits at the associated primary rate of the incoming channel, and an outgoing channel. There is a device that converts a group of bits of the related primary rate into the sector of the second frame with the related online rate, and a device that introduces the outgoing channel sector into the second frame that enters the central station.

【0015】

[Example]

The present invention will be described in more detail below with reference to the drawings. The following specific numbers for duration, bit rate, frequency, and number of bits are for constructing a multi-rate digital frame TCT that implements the present invention, as shown in FIG. 1, and are shown as non-limiting examples. ..

【0016】

The frame TCT has a period PT = 500 μs corresponding to a frequency of 2 kHz and a duration DT = 195.31 μs much shorter than this period PT. The period DT is determined to correspond to transmitting 800 bits of constant rate DF = 4.096 Mbit / s, which is the minimum online rate in each sector of the frame.

【0017】

The frame TCT consists of the management sector SG at the beginning of the frame and the digital channel sector of NS = 8 from S1 to S8.

【0018】

The management sector consists of a frame alignment word MUT that is synchronized to the timebase of the terminal station, which is a multiplexing that forms a frame TCT via a three-layer transmission medium SUT, such as a fiber optic medium. It is connected to the central station that has the device. The reception / transmission rates DE and DF of the terminal station are different from each other. The management sector is further composed of a plurality of words exchanged between one of the central stations and one of the terminal stations according to a predetermined protocol, but these words are for performing an operation, for example, and one of the channel sectors is a terminal. This is to return to the station, and further to set the transmission amplitude level for the transmission circuit in the terminal station. This sector SG includes, in particular, the number and rate of sectors related to the parity of the frame sector and the address of the terminal station, and other management words related to the maintenance alarm of each station.

【0019】

The bits of the management sector SG are composed of PT = 500 μs at each station, the primary rate is dG = 64 kbit / s, and the number is nbG = 64 × 0.5 = 32. The duration of the management sector is DG = 7.81μs by equalizing the online rate DG in the sector SG to the minimum rate DF = 4.096Mbit / s in the channel sector so that the management sector is judged by all terminals. That is, it is one-third of the period DS = 23.44 μs of each channel sector.

【0020】

For the examples described here, the digital channel is one of two primary rates dF = 16kbit / s, dE = 2.048Mbit / s.

【0021】

For other embodiments, the number of various primary rates in a sector, and thus the number of online rates, can be greater than or equal to the number of sectors NS = 8. The online rate is a fraction of the maximum online rate DE = 49.152Mbit / s, which can be, for example, 4.096Mbit / s; 8.192Mbit / s; 12.288Mbit / s; 16.384Mbit / s; 24.576Mbit / s. ..

【0022】

The digital channels in the late dF and dE are divided into groups of nbF = 160 × 0.5 = 80 bits and nbE = 2048 × 0.5 = 1024 bits in the period DT of each frame. Groups of bits at low primary rate dF are housed in one sector, as shown in sector 2 in Figure 1, and are transmitted at low online rate DF = 4.096 Mbit / s; therefore this sector is NBF = (DF.DS). ) = 96 bits and contains nbF = 80 channel data bits. Similarly, a group of bits at a high primary rate is housed in one sector as shown in sector 8 of Figure 1 and transmitted at a high online rate DE = 49.152 Mbit / s; therefore this sector is NBE = (DE. DS) = 1152 bits and contains nbE = 1024 channel data bits. The number of additional bits in each sector is NBF-nbF = 16 and NBE-nbE = 128, respectively, and these additional bits are filling bits that have no meaning, but some of them are used for maintenance purposes. Is preferred and is placed at the end of the sector.

【0023】

The various online rates, which are determined by the operating conditions of the various types of terminals, are multiples of the low online rate DF, more specifically the multiples of the online rate DG of the management sector, because all terminals form a management sector. It should be noted that it is preferable to do so. In this example, one bit in the low bit late DF is equal to DE / DF = 12 consecutive bits for the same late DE in logical state, that is, the bit width in the low late DF is 12 times the bit width in the high rate in the frame. large.

【0024】

In fact, some central stations according to the implementation of the present invention are in a telephone exchange center linked to the telephone switching network, and each central station is connected to some terminal stations via a three-layer structure transmission medium. There is. Typically, at least NS = 8 digital channels for each of the primary rates dF, ..., dE in a design are connected to multiple ports in the central station, with various types of terminal stations taking values greater or less than NS. Even so, one frame contains NS = 8 sectors due to the rate required by the terminal station to access the network at the same online rate or at various online rates. According to the above embodiment, for example, an incoming digital channel with NS = 8 from CEE1 to CEE8 is designed with NS = 8 from CEF1 to CEF8, as if it were designed with a high primary rate dE = 2.048Mbit / s. Incaming digital channels can also be designed with a low primary rate dF = 160kbit / s.

【0025】

As shown in FIG. 2, the multiplexing transmitter of the central station includes a multilayer multiplexing device DM and a frame transmitter. The time-based BT and the communication management unit UG are located in the central station and are common to both the multiplexing transmitter and the receiving multiplex separator shown in FIGS. 2 and 3, respectively.

【0026】

Regarding synchronization, the timebase BT acts as a master clock for the sleeve timebase of the terminal station. With a high online rate of 49.152MHz, the time-based BT supplies all the clock signals needed for multiplexing / multiplexing and frame transmission / reception processing, the frequencies for these processing are described below.

【0027】

The management unit UG manages the communication and especially the synchronization of the transmitter of the terminal station as a distance relationship with the central station, avoids sector overlap within the frame TTC received by the central station, and further manages the transmitter of the terminal station. The power of the terminal station is remotely controlled, and the receiving device of the terminal station is operated so that the central station receives a digital signal having the same amplitude regardless of the distance from the terminal station to the central station. This management is performed via the bits of the management sector SG of the frame by bidirectional transmission. From the point of view of communication, the management unit UG takes out the number of operating terminal stations, returns one sector to each operating terminal station, and then each sector and the channel requested by the terminal station, and therefore the request. Associate the late rate.

【0028】

The multiplexing device DM shown in FIG. 2 has many storage circuits 1F, 1E so that there are various primary rates dF, dE, that is, various online rates DF, DE.

【0029】

Each storage circuit 1F, 1E has two buffer RAM memories 2FA and 2FB, 2EA and 2EB, respectively, and each memory receives 8-parallel-bit cell addresses supplied by counters 3FA and 3FB, 3EA and 3EB, respectively. The memories 2FA and 2FB, 2EA and 2EB have data inputs and are connected to parallel input channels CEF1 to CEF8 and CEE1 to CEE8, respectively. There is also data output and they are connected to NS = 8 data inputs of multiplexers 4F and 4E.

【0030】

The two memories of each storage circuit alternately write and read at each frame cycle. Thus, during the first frame period PTA = 500 μs, the nbF = 80 series bits for each channel from CEF1 to CEF8 and the nbF = 1024 series bits for each channel from CEE1 to CEE8 have a frequency of 160 kHz and 2.048 MHz. The frequencies are written to memory 2FA and 2EA, respectively, while the equivalent number of bits already written are read to memory 2FB and 2EB at frequencies of 4.096MHz and 49.152MHz, respectively. Conversely, during the second frame period PTB = 500 μs after the first frame period PTA, the nbF bits written from each channel from CEF1 to CEF8 and each channel from CEE1 to CEE8 are written. The nbE bits are read by memory 2FA and 2EA at frequencies of 4.096MHz and 49.152MHz, respectively, while the other bits are written to memory 2FB and 2EB at frequencies of 160kHz and 2.048MHz, respectively. There is. In this way, the group of nbF and nbE series bits of each channel accommodated in the sector period DS is repeated at least NS = 8 times for one frame cycle at each input of the multiplexer 4F and 4E. The group is input to the dynamic in every frame sector via the multiplexer 4F, 4E.

【0031】

To perform these write and read operations, the counters 3FA, 3FB, 3EA, 3EB are reset when the associated memory 2FA, 2FB, 2EA, 2EB is write enabled, and the associated memory is read enabled for each sector. It is reset at the start and end. At this moment, a copy of the first bit in the stored group is filled. The write clocks are 160kHz and 2.048MHz, and the read clocks are 4.096MHz and 49.152MHz. The write / read control is performed by the time-based BT. The counters 3FA and 3FB generate a 7-bit address and become the counter of the module nbF, while the counters 3EA and 3FA generate an 11-bit address and become the counter of the module nbE.

【0032】

Multiplexers 4F and 4E each receive eight 4-bit incoming addresses at the beginning of sectors S1 through S8 of the formed frame. The channel address is continuously read by RAM memory 5, which has a sector frequency of 1 / DS = 42.66kHz during the frame period DT and 3 bits at the start of the frame after the management sector DG period. Addressed by sector counter 6. If communication is established in advance, the management unit UG writes the channel address according to the sectors available in the frame. In this way, the channel address added to the multiplexers 4F and 4E by memory 5 consists of 3 bits and 1 bit, 3 bits select 1 channel from 8 channels with the same rate, and 1 bit selects 2 channels. Select one multiplexer from the multiplexer, and thus the channel rate.

【0033】

When the 96-bit group and the 1152-bit group were repeated at least 8 times at the input of the multiplexer and at the sector frequency, the 8-channel address read and selected 8 channels selected from 16 channels in memory 5 during the frame cycle. Eight groups of bits generated from the channel are time-division-multiplexed into eight frame sectors S1 to S8 at the output of the multiplexers 4F and 4E connected to the 2-input logic OR circuit 7. The group thus multiplexed and having various online rates is added to the input of the encryption circuit 8 of the transmission circuit CT.

【0034】

According to a preferred embodiment, the encryption circuit 8 encrypts eight multiplexed frame sectors by the data sectors S1 to S8 in the frame TTC received by the reception multiplex separator of the central station bit by bit.

【0035】

For example, cryptographic circuit 8 has an exclusive OR gate, which has a first input and a second input, but the first input is connected to the output of OR circuit 7 and transmitted. It receives the output sector of the frame TTC, and the incoming frame sector received in synchronization with the frame sector transmitted by the data output of the buffer RAM memory 9 is added to the second input. The data input of memory 9 receives the frame TTC received by the receiving device of the central station. The write / read counter 10 writes the bits of the frame received by the memory 9, which is done during the time interval of receiving the sector of the received frame TTC at the end of the frame period PT as shown in FIG. At the beginning of the next frame cycle, counter 10 reads and addresses the bits of the received frame during the time interval corresponding to the sector of the frame TCT to be transmitted. The writing and reading of the bits in memory 9 is controlled by the clock signal of 49.152MHz.

【0036】

The frame sector encrypted in circuit 8 is analyzed by the transmission quality circuit 11 which basically consists of adding a parity bit to each sector from S1 to S8, and this parity bit is a predetermined value at the end of the sector. Is placed in one of the 16 or 128 last filled bits of a sector of, for example, 4.096 Mbit / s or 49.152 Mbit / s. Circuit 11 also has a conventional bistable latch whose complementary output is loop-coupled to the data input, which is equivalent to a bistable frequency divider.

【0037】

The SG bit of the management sector is generated by the management unit UG, which is the input of the insertion circuit 12 with other inputs connected to the output of circuit 11 equal to the OR gate during the time interval of 7.81 μs at the beginning of the frame. It is done via.

【0038】

The frame TCT configured in this way is transmitted in the transmission medium SUT that reaches the terminal station through the conventional transmission circuit 13. For example, if the transmission medium is an optical fiber and constitutes a relay line of a three-layer optical network connected to a terminal station, the circuit 13 is an LED or laser diode type optical electron emitter having an amplification and bias circuit. It is composed of.

【0039】

Related to Fig. 1 again, the multi-rate frame TTC, which is composed of terminal stations through the transmission medium and is received by the central station, has a period DT like the frame TCT, and also has management sectors SG and eight data sectors from S1 to S8. There is. At the central station, the frame TTC is received at the last 195.31 μs of the end of the period PT.

【0040】

As shown in FIG. 3, the receiving multiplex separator of the central station includes a receiving device that performs an operation opposite to that performed by the transmitting device. The receiving circuit 14 receives the frame TTC supplied by the terminal station. Circuit 14 includes, for example, a PIN photodiode type photodetector when the medium SUT consists of an optical fiber. The digital frame TTC passes through the management bit extraction circuit 15 and the quality inspection circuit 16.

【0041】

Circuit 15 extracts various words from the frame TTC, which consists of the management sector SG formed by the management unit UG. There is no alignment word in the management sector SG of the frame TTC, and all protocol words exchanged between one of the terminal stations and the central station take various positions in the sector SG depending on the distance from the terminal station to the central station. ..

【0042】

Circuit 16 specifically checks the parity of each sector from S1 to S8 of the frame, which compares the parity bit received at the end of the sector from S1 to S8 with the parity calculated from the sector of the received frame. In addition, this circuit 16 inspects the management unit UG and outputs all abnormalities that occur.

【0043】

The receive multi-late frame TTC, which has the management bit and the parity bit removed and has data bits in the sectors S1 to S8, is added in series to the memory 9 (FIG. 2) of the transmitter and the series-parallel converter 17.

【0044】

In addition to the converter 17, two buffer memories 18A and 18B related to the address counters 19A and 19B, and a group counter 21 with 8 multiplexing bits are included in the central station multiplex separator DD according to the implementation of the present invention. , The channel bit switching circuit 22 is included. The purpose of the circuits 17 to 21 is to form a multiplexed signal SM, in which the data bits in the sectors from S1 to S8 of the receive frame TTC have a frame period of PT = 500 μs ( It is multiplexed bit by bit at a frequency of 1024 × 8) /500=16.384MHz, which means that each sector of NS = 8 has 1024 pieces because NS × dE = 16.384MHz regardless of the online rate of the sector. By considering it to consist of a group of significant bits of. The bits of the sector are naturally switched at this frequency to the outgoing channel selected by the switching circuit 22.

【0045】

(r, s) will indicate the effective bit of rank r of the Sth sector of the received frame TTC thereafter, but the integer r changes from 1 to nbE = 1024, and the integer S changes from 1 to NS = 8. To do.

【0046】

Converter 17 receives sector bits at a high frequency of DE = 49.152MHz and NB from I0 to I3 of RAM memory 18A and 18B in the form of a group of parallel bits of NB = 4 at a frequency of 49.152 / 4 = 12.288MHz. Send to data entry. In a more general way, the number of bits NB in a group is equal to a divisor of the number of channel sectors NS in the frame, ie 8 or 4 or 2.

【0047】

The memories 18A and 18B alternately perform write and read functions like the two memories of the memory circuits 1F and 1E (Fig. 2). During a given frame period of PT = 500 μs, one of the 18A of the memory stores a given frame received in a contiguous group of NS = 4 parallel bits at the DE / DS frequency; therefore, during the subsequent frame period, the memory The bits written in 18A are read out in the default order as a group of NB = 4 bits at the frequency NS × dE = 16.384 MHz of the multiplexed signal SM. During these consecutive frame cycles, the other memories 18B are read and written, respectively, retransmit the received frame preceding the predetermined frame, and further store the subsequent received frame of the predetermined frame.

【0048】

To do this, the address counters 19A and 19B give 11-bit addresses to write and read operations at different rates.

【0049】

In the write operation, the counters 19A and 19B are activated at the start of the first sector S1 7.81 μs after the start of the frame TTC. Counters 19A and 19B give write addresses from 0 to 255, write nbE / NB = 256 groups of 4 parallel bits from sector S1 if sector S1 has an online rate equal to 49.152 Mbit / s, and sector S1 If the online rate is equal to 4.096 Mbit / s, write the nbF bits of sector S1, but each of these bits is actually NB = 4 bits 3 = (DE / DF) in memory at a frequency of 12.288 MHz. / Written continuously in the form of NB group. The counter then stops while receiving 128/4 = 32 groups of fill bits for sector S1 with an online rate equal to 49.152 Mbit / s, which is a sector with an online rate equal to 4.096 Mbit / s. It corresponds to 16/4 = 4 groups of filling bits of S1. The write address is timed at a frequency of 12.288 MHz. Similarly, counters 19A and 19B give write addresses from 256 to 511, ..., 1792 to 2043 while receiving valid data bits in sectors S2 to S8. The memories 18A and 18B store the next valid bit added to the input of I0 to I3, respectively, but the filling bit in the sector is not written in the memory. I0 = (1,1). (5,1) ... (1021,1). (1,2) ...... (1021,8); I1 = (2,1). (6,1) ... (1022,1). (2,2) ...... (1022,8); I2 = (3,1). (7,1) ... (1023,1). (3,2) ...... (1023,8); I3 = (4,1). (8,1) ... (1024,1). (4,2) ...... (1024,8). [0050]

In the read operation, the counters 19A and 19B also give an 11-bit read address. Each read address for a group of NB = 4 bits is divided into a first part consisting of the high-order bits of 3 bits and a second part consisting of the low-order bits of 8 bits of the address. The 3-stage counter corresponding to the first part of the address acts as a module 8 counter at a frequency of (NS × dE) = 16.384 MHz, while the other 8-stage counter states are four consecutive module 8 counters. The same set of NB = 4, each with NS = 8 groups of NB = 4 parallel bits, is continuously read without change during the cycle, but the bits in these groups are NB within the write sector of NS = 8. It is placed in the same rank of = 4. Under these conditions, each output of the corresponding memory 18A, 18B repeats the same series of NS = 8 bits NB = 4 times, but these 8 bits initially have the same rank in the sector. .. The other 8 stages of counters 19A and 19B are (NS × dE) / (NS × NB) = 16384 / (8 × 4) = 512kHz frequency module-(nbE / NB) = module-256 Read address that acts as a counter Corresponds to the second part of, and reads eight 4-bit groups in succession.

【0051】

Based on this read operation, the outputs of O0 to O3 corresponding to memories 18A and 18B give the following bits to the input of NB = 4 of the multiplexer 20 during the frame period PT: 00 = (1,1). (1,2). (1,3). (1,4) ... (1,8). (1,1) ... (1,8). (1) , 1) ... (1,8). (1,1) ... (1,8). (5,1). (5,2). (5,3). (5,4). .. (5,8). (5,1) ... (5,8). (5,1) ... (5,8). (5,1) ... (5,8). ..... (1021,1). (1021,2). (1021,3). (1021,4) ... (1021,8). (1021,1) ... (1021,8) . (1021,1) ... (1021,8). (1021,1) ... (1021,8); 01 = (2,1). (2,2). (2,3). (2,4) ... (2,8). (2,1) ... (2,8). (2 , 1) ... (2,8). (2,1) ... (2,8). (6,1). (6,2). (6,3). (6,4). .. (6,8). (6,1) ... (6,8). (6,1) ... (6,8). (6,1) ... (6,8). ..... (1022,1). (1022,2). (1022,3). (1022,4) ... (1022,8). (1022,1) ... (1022,8) . (1022,1) ... (1022,8). (1022,1) ... (1022,8); 02 = (3,1). (3,2). (3,3). (3,4) ... (3,8). (3,1) ... (3,8). (3 , 1) ... (3,8). (3,1) ... (3,8). (7,1). (7,2). (7,3). (7.4) ... (7,8). (7,1) ... (7,8). (7,1) ... (7,8). (7,1) ... (7,8) ... ... (1023,1). (1023,2). (1023,3). (1023,4) ... (1023,8). (1023,1) ... (1023,8). ( 1023,1) ... (1023,8). (1023,1) ... (1023,8); 03 = (4,1). (4,2). (4,3). (4,4) ... (4,8). (4,1) ... (4,8). (4 , 1) ... (4,8). (4,1) ... (4,8). (8,1). (8,2). (8,3). (8,4). .. (8,8). (8,1) ... (8,8). (8,1) ... (8,8). (8,1) ... (8,8). ..... (1024,1). (1024,2). (1024,3). (1024,4) ... (1024,8). (1024,1) ... (1024,8) . (1024,1) ... (1024,8). (1024,1) ... (1024,8). [0052]

The selective input of the multiplexer 20 is connected to the stage of counter 21 which receives the clock signal at dE = 16.384 / 8 = 2.048MHz. Counter 21 selects four groups, each with an 8-bit sector multiplexed and serialized, which corresponds to a continuous cycle of NB = 4 for the second part of the 8-bit of counters 19A, 19B. It is performed during the period of PT / (nbE / NB) = 1 / (512kHz). In this way, the counter 21 periodically selects the four outputs of the memories 18A and 18B, and only 8 bits in each of these outputs are retransmitted in the multiplexed signal SM during the period of the counter 21. Since the 8-bit group is repeated four times at the output of the memories 19A and 19B, the first 8-bit group is selected at the output O0, the second 8-bit group is selected at the output O1, and so on. Only one 8-bit group is selected at each output from O0 to O4 at a frequency of 512 kHz, but the bits of the group are always transmitted at a frequency of NS × dE = 16.384 MHz. The multiplexed signal SM consists of the following bits during the full frame period PT: SM = (1,1). (1,2). (1,3). (1,4) ... (1,8). (2,1) ... (2,8). (3 , 1) ... (3,8). (4,1) ... (4,8). (5,1). (5,2). (5,3). (5,4). .. (5,8). (6,1) ... (6,8). (7,1) ... (7,8). (8,1) ... (8,8). ..... (1021,1). (1021,2). (1021,3). (1021,4) ... (1021,8). (1022,1) ... (1022,8) . (1023,1) ... (1023,8). (1024,1) ... (1024,8). [0053]

Each bit of an online sector with an online rate smaller than the maximum rate DE is repeated in proportion to the ratio of the maximum rate to the online rate; for example, for an online rate DF = 4.096 Mbit / s, each bit is 49.152 / 4.096 = Repeated 12 times; if sector S_SIf is equal to a small value of this ratio, for example, the bits from (1, S) to (12, S) are sector S._CRepresents the first bit of, and then sector S_CTakes a binary state equal to the state of the first bit of.

【0054】

As shown in FIG. 4, the switching circuit 22 has a pair of bistable flip-flops from 23F1-24F1 to 23F8-24F8, which are connected to the outgoing digital channels from CSF1 to CSF8 at low rates, respectively, and further. This switching circuit has a pair of bistable flip-flops from 23E1-24E1 to 23E8-24E8, which are connected to the outgoing digital channels from CSE1 to CSE8 at a high rate. The data input D of the first flip-flop from 23F1 to 23F8 and further from 23E1 to 23E8 is connected to the output of the multiplexer 20. The output Q of the first flip-flop is connected to the data input of the second flip-flop from 24F1 to 24F8 and then from 24E1 to 24E8, respectively.

【0055】

The clock inputs H of the first flip-flops from 23F1 to 23F8 and from 23E1 to 23E8 are connected to the 16 outputs of the 4-bit decoder 25, respectively. The decoder decodes the 4-bit channel address into the strobe of high logic state "1" at the corresponding output. As in the case of the multiplexing device DM, the channel address is read into the RAM memory 26 under the control of the sector counter 27. Counter 27 gives sector addresses from 0 to 8 at a frequency of NS × dE = 16.384 MHz so that each corresponding channel corresponds to each sector of the receive frame TTC. The channel address is written to the memory 26 by the management unit UG when communication is established.

【0056】

In this way, the first flip-flop from 23F1 to 23E8 in which the input H receives the clock strobe corresponds to each sector address given by the counter at the same frequency as the bit of the multiplex signal SM. The corresponding channel bits in the signal SM are added to the second corresponding flip-flop from 24F1 to 24F8 and then read to the clock input H of the second flip-flop at a frequency of dE = 16.384 / NS = 2.048MHz. Will be done.

【0057】

The output Q of the second flip-flop from 24E1 to 24E8 is directly connected to the high late outgoing channel from CSE1 to CSE8.

【0058】

The output Q of the second flip-flop from 24F1 to 24F8 is connected to the low late-outgoing channel from CSF1 to CSF8 through the FIFO buffer queue, and the 8 parallel bitwords from the flip-flop in this buffer queue. Is written at 2.048MHz and then read at the binary frequency of the channel equal to 160kHz.

【0059】

The transmitter / receiver of the terminal station that matches the online rate of DE = 49.152 Mbit / s is described below with reference to FIGS. 5 and 6.

【0060】

The terminal station has a time-based BTT, which reproduces a 49.152 MHz master clock signal from the multi-late signal transmitted by the central station's multiplexing transmitter through the transmission medium SUT. The time-based BTT is added to all the clock signals required for the transmitter / receiver to extract each sector of the receive frame TCT and to insert the management sector SG. This extraction and insertion is performed by the terminal station of the central station. This is done when changing the protocol word and the sector in the frame TTC belonging to the terminal station. For example, S8 indicates that it is a sector belonging to the above-mentioned terminal station.

【0061】

The management unit UGT is also included in the terminal station, which specifically processes the changed protocol words in the central station and monitors the transmission quality.

【0062】

As shown in FIG. 5, the receiving device is, in order from the transmission medium SUT, the receiving circuit 29, the sector extraction circuit 30, the attribution sector parity check circuit 31, the series-parallel converter 32, the decryption circuit 33, the FIFO type buffer memory 34, and the terminal. It is composed of a parallel series converter 35 that retransmits the incoming channel data bit CEE at a primary rate of 2.048 Mbit / s belonging to the station.

【0063】

The functions of circuits 29,30,31 are the same as those of circuits 14,15,16 (Fig. 3) of the central station. In particular, the extraction circuit 30 extracts the management sector SG and the attribution sector S8 from the frame TCT and distributes them to the management unit UGT and the parity check circuit 31, respectively. For the digital signal reproduced by the receiving circuit 29, the circuit 31 checks the parity of the belonging sector S8 of the receiving frame TCT at the same time as the management unit UGT.

【0064】

The converter 32 receives the bits of the attribution sector S8 at a frequency of 49.152 MHz. The converter converts only the valid bits of nbE (or nbF) received from the sector mentioned above into 8 parallel bitwords at a frequency of 6.144 MHz. In circuit 33, the 8-bit word is decrypted by the 8-bit word of the same rank in the sector of the frame TTC, but this rank is the same as the rank stored in the terminal station, and the frame period further preceded. It was received by the central station during the period. Cryptanalysis is performed by eight exclusive OR gates corresponding to the encryption of circuit 8 of the central station.

【0065】

The eight parallel bitwords decrypted by the attribution sector from circuit 33 are written to memory 34 at a frequency of 6.144 MHz and are constantly read at a frequency of 2048/8 = 256 kHz. The converter 35 converts 8 parallel bitwords with a frequency of 256 kHz into series bits of the corresponding digital channel CEE with a frequency of 256 × 8 = 2048 kHz.

【0066】

The transmitter of the terminal station shown in FIG. 6 consists of a 2.048 Mbit / s digital channel CSE input, a transmission quality circuit 36, and a series-parallel converter 37. The circuit 36 calculates the parity bit BP for each frame period PT = 500 μs for each nbE = 1024 bits of the channel CSE. The converter 37 converts the 2.048 MHz series bits coming from circuit 36 into eight parallel bitwords with a frequency of 256 kHz.

【0067】

Each of the 8 parallel bitwords generated by the converter 37 is written to two FIFO buffer memories 38,39 at a frequency of 2048/8 = 256kHz, at the frequency of the 8 bitwords of the online sector, ie 49.152 / 8 = 6.144MHz. Read by frequency. However, the reads of these two memories are both done during the frame period after the writing of the same word, but these reads are independent of each other.

【0068】

In the first memory 38, the read is performed while receiving the attribute sector S8 of the frame TCT received by the terminal station, that is, (DG + 7DS) μs after the start MVT of the frame TCT. The read 8-bit word is added to the second input of the eight exclusive OR gates contained in the decryption circuit 33, and the 8-bit word of the receiving sector S8 added by the converter 32 is decrypted. ..

【0069】

In the second memory 39, the read is performed by the central station as a function of the propagation time between the terminal station and the central station indicated by the management unit UGT, that is, between the strobes corresponding to the attribution sector S8 of the frame TTC. However, this is to ensure that the read word arrives during the last DS = 23.44 μs of the central station frame period PT. The transmission device of the terminal station further includes a sector bit multiplexer 40, a parallel series converter 41, a management sector insertion circuit 42, and a transmission circuit 43 ahead of the buffer memory 39. During the period DS of the attribution sector, the multiplexer 40 receives a word of significant bits read into memory 39 by the 8-wire bus, and control and check bits, which are less than NBE-nbE but about. It is added by the management unit UGT and quality circuit 36 via a bus with 10 wires. The selection of buses in the multiplexer 40 is controlled by the time-based BTT, which adds filling bits to the edges of the sector, which are copies of the last significant bit.

【0070】

The 8-bit word added by the multiplexer 40 at a frequency of 6.144 MHz is serialized by the converter 41 and becomes a sector of NBE = 1152 bits with an online rate of 8 × 6.144 = 49.152 Mbit / s.

【0071】

The series bits of the attribution sector S8 enter the insertion circuit 42, which is equal to the OR gate, while the other inputs of the insertion circuit receive the SG bits of the frame TTC management sector, which is 8DS μs, at frequency DF. The insertion circuit 42 inserts several bits at a predetermined position so that the central station determines the propagation time between the central station and the terminal station.

【0072】

Finally, the transmission circuit 43 transmits the attribution sector S8, which may precede the management bits, to the medium SUT, mixes the sectors from other operating terminals with the coupler of the tree-like network, and outputs the return frame TTC. Form.

【0073】

For terminals with an online rate lower than late DE, that is, for terminals with a rate of DF = 4.096 Mbit / s, the transmitter / receiver is the same as the transmitter / receiver shown in FIGS. 5 and 6 above. .. In this case, the frequencies of 49.152MHz, 6.144MHz, 256kHz and 2.048MHz are replaced with the frequencies of 4.096MHz, 512kHz, 20kHz and 160kHz.

【0074】

However, in less complex embodiments, the transducers 32,35,37,41 can be removed for such a low rate. Bits at the terminal station are processed by three FIFOs with frequencies of 4.096MHz and 160kHz. The FIFO of the receiver is in place of the converter 32. The multiplexer 40 is removed in the transmitter and replaced with the equivalent series function of the insertion circuit 42.

【0075】

The present invention can be applied when the transmission between the central station and the terminal station is a transmission medium SUT having a three-layer structure, that is, two directions (bidirectional) through a conventional coaxial cable medium. -43 Can be a modem or a medium SUT with two optical fibers. In this case, the period of the frame DT can be substantially equal to the period of the frame period PT.

【0076】

According to another application of the present invention, the communication network is a semi-double network and can be composed of one three-layer coaxial cable or an optical cable. In this case, the forward frame TCT, the reverse frame TCT, the return frame TTC, and the reverse frame are also alternately between the central station and the terminal station during each half cycle of the frame. Will be exchanged. In this method, as shown in FIG. 1, the central station sends a frame TCT at the beginning of the period PT and receives a frame TTC at the end of the frame period PT. Such a transmission mode is more specifically called a "group half-double time division multiplex access mode".

【0077】

The period of TP = PT-2DT = 109.375 μs is given between the two frames TCT and TTC. Due to the period TP, the terminal station farthest from the central station receives the frame TCT, and after a shorter preparation time, at least the belonging sector is transmitted according to the time interval of the frame TTC.

[Simple explanation of drawings]

[Figure 1]

The details of the multi-late frame in which the present invention is carried out with respect to one frame period and various sectors constituting the frame period are shown.

[Figure 2]

The block diagram of the multiplex multiplexing apparatus and the transmitting apparatus included in the central station in relation to the method and apparatus of multiplexing and multiplex separation of this invention is shown.

[Fig. 3]

The block diagram of the multi-late receiver and the multiplex separator included in the central station is shown.

[Fig. 4]

The details of the channel bit switching circuit included in the receiving device and the multiplex separator are shown below.

[Fig. 5]

FIG. 6 shows a schematic block diagram of a terminal station receiver according to the practice of the present invention and associated with the highest online rate.

[Fig. 6]

A schematic block diagram is shown for the transmitter of the terminal station associated with the highest online rate.

[Explanation of symbols]

1E, 1F storage circuit 2EA, 2EB, 2FA, 2FB buffer RAM memory 3EA, 3EB, 3FA, 3FB counter 4E, 4F multiplexer 5,26 RAM memory 7 OR circuit 8 Cryptographic circuit 9 buffer RAM memory 10 write / read counter 11 Transmission quality circuit 12 Insert circuit 13 Transmission circuit 14,29 Receiving circuit 15 Management bit extraction circuit 16 Quality inspection circuit 17 Series-parallel circuit 18A, 18B buffer memory 19A, 19B address counter 20 multiplexer 21 group counter 22 channel bit switching circuit 23E1-23E8 Bistable flip-flop 23F1-23F8 Bistable flip-flop 24E1-24E8 Bistable flip-flop 24F1-24F8 Bistable flip-flop 25 4-bit decoder 27 sector counter 30 sector extraction circuit 31 Attribution sector parity check circuit 32 Series-parallel conversion circuit 33 Cryptanalysis circuit 34 FIFO type buffer memory 35 parallel series converter 36 Transmission quality circuit 37 series converter 38,39 FIFO buffer memory 40 sector bit multiplexer 41 Parallel series converter 42 Management sector insertion circuit 43 Transmission circuit BP parity bit BT, BTT time base DE Receive Late (Online Late) dE primary rate DF transmission rate (online rate) Minimum primary rate in dF channel sector DG online rate dG primary rate CEE1-CEE8 Parallel input channel CEF1-CEF8 parallel input channel DM multiplexing device DT period Number of NS sectors PT cycle SG management sector SUT 3-layer transmission medium TCT Multirate Digital Frame TTC receive multi-rate frame UG communication management unit