BiCDMOS process technology.

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention is a partial continuation application of US Patent Application No. 08 / 226,419, which is currently patented as US Patent No. 5,426,328, and is a supplementary bipolar transistor, CMOS transistor, DMOS power transistor, embedded Zena diode, And the processes that can be used to produce the relevant structures on a single wafer. In particular, the present invention relates to transistor structures produced using this process and related isolation structures.

【0002】

[Conventional technology]

In a number of industries, including the telecommunications industry, the automotive industry, and the computer industry, there are devices that require high power digital switching circuits, analog amplifier circuits, and digital logic circuits. In many such devices, all the necessary circuits are provided on one IC chip, and if the IC chip is reliable enough and not very expensive, it can improve the performance of the device. It can be miniaturized.

【0003】

In today's disk drive industry, for example, disk drive controllers are often implemented by incorporating them into multiple chips. The problem caused by integrating the power transistor and digital logic transistor of the disk drive controller is that the CMOS digital logic circuit will be incorporated in a chip different from the chip in which the DMOS power circuit is incorporated. .. Similarly, the analog amplifier circuit of the disk drive controller is located on the third chip, which is a single circuit that combines a high-quality bipolar analog amplifier with a high-performance CMOS digital logic transistor and / or a DMOS power transistor. This is because it is difficult to mount it on the chip. Therefore, there is a need for a process that allows DMOS power circuits, CMOS digital logic circuits, and complementary bipolar analog circuits to be integrated into a single circuit chip.

【0004】

[Problems to be Solved by the Invention]

Therefore, an object of the present invention is to provide a process-based integrated circuit forming method that enables a DMOS power circuit, a CMOS digital logic circuit, and a supplementary bipolar analog circuit to be integrated into one circuit chip. That is.

【0005】

[Means for solving problems]

Bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, Zena diodes, and thin film resistors, or a combination of more than necessary elements are all formed on the same IC chip at the same time. The process (hereinafter referred to as "BiCDMOS process") is disclosed here. This process forms a high performance transistor structure with a small number of mask steps and also yields high yields. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, Zener diode structures, and thin film resistor structures are also disclosed herein.

【0006】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described, but here, refer to the accompanying drawings. In addition, there are many different embodiments of the present invention, and the present invention is not limited to the examples described below. In other words, it is intended that the applicant completes this specification by providing a detailed description of the preferred embodiments and fully conveys the scope of the invention to peers. Also, in the drawings, the thicknesses of the various layers are exaggerated for the sake of simplicity.

【0007】

1. BiCDMOS process Table 1 shows the multiple process steps of the BiCDMOS process.

【0008】

[table 1]

<img file="JP2947741B2_D0001.tif" />【0009】

For the convenience of the reader of this specification, the various process steps in Table 1 are numbered, but in some embodiments, some process steps may be omitted and the various processes may be omitted. It should be understood that the order of the steps may be reversed and several process steps may be combined into one step. Therefore, the process step numbers in Table 1 are provided solely to help readers of this specification understand the examples of the BiCDMOS process described below. The individual process steps listed in Table 1 shall be indicated by enclosing the step numbers in parentheses below.

【0010】

Figure 1A and Figure 1B show the first step in the BiCDMOS process. It has been shown that substrate (step 1) 10 has an upper surface 11. This substrate is, for example, a P-doped polysilicon back-coated substrate having a resistance of 1 to 5 Ω-cm. The substrate 11 is a region arranged continuously in the horizontal direction, that is, an embedded Zener region 10F, a DMOS region 10A, a relatively high voltage MIMO region 10E, a relatively high voltage MIMO region 10G, and a relatively low voltage MIMO region 10H. It is believed to have a relatively low voltage MIMO region 10D, a vertical PNP bipolar region 10B, and a vertical NPN bipolar region 10C.

【0011】

Next, the first oxidation step (step 2) is performed to form the first oxide layer 12 on the upper surface of the substrate . This initial oxide layer is made, for example, by thermal growth to have a thickness of approximately 300 Å.

【0012】

Next, the N + embedded layer mask (step 3) step is formed from the photoresist. This mask is used to form openings 12A, 12B, and 12C through the initial oxide layer to the upper surface 11 of the substrate 10. The first oxide layer 12 is etched by, for example, dry etching or wet etching. After the openings 12A, 12B, and 12C are formed, the photoresist mask is removed.

【0013】

Figures 2A and 2B show the next steps in the BiCDMOS process. The N + embedded layer ion implantation step (step 4) is performed by using the oxide layer 12 as an implantation mask to form the embedded layer regions 21A, 21B, and 21C at openings 12A, 12B, and 12C, respectively. To do. For example, antimony ion is 1 cm with energy of 80 KeV.²1 ~ 2 * 10 per¹⁵The dose is injected into the upper surface 11 of the substrate.

【0014】

Next, the N + embedded layer drive-in diffusion step (step 5) is performed. During this diffusion step, the thin oxide layer 22A grows in the opening 12A, the thin oxide layer 22B grows in the opening 12B, and the thin oxide layer 22C grows in the opening 12C. The thickness of these thin oxide layers 22A-22C is, for example, approximately 4000 Å. The N + embedded layer regions 21A, 21B, and 21 extend vertically, for example, into the substrate to a depth of 3.5-4.0 μm.

【0015】

Figures 3A and 3B show the subsequent steps of the BiCDMOS process. Since the photoresist layer 30 is formed in the P + embedded layer mask (step 6), the openings 30D and 30B are formed up to the upper surface 11 of the substrate. Since the opening 30B is made smaller than the opening 12B, the outer boundary of the opening 30B will fit inside the outer boundary of the opening 12B. Next, the oxide layer is etched to remove the portion exposed by the opening 30B of the oxide layer 22B. The oxide layer etching also removes the portion exposed by the opening 30D of the initial oxide layer 12. Once all the oxide layers have been removed at the openings 30B and 30D, the photoresist mask layer is removed. The injected oxide layer (not shown in FIGS. 3A and 3B) is then thermally grown at openings 30B and 30D to have a thickness of, for example, approximately 10,000 Å.

【0016】

Next, a P + implant layer ion implantation step (step 7) is performed, and a part of the N + implant layer region 21B increases the P + ion concentration by P + ion implantation. Similarly, P + ions are injected into the opening 30D on the upper surface of the substrate 10. This P + ion implantation is, for example, 1 cm with an energy of 140 KeV.²1 * 10 per¹⁴Doze boron ions are injected.

【0017】

After the photoresist mask is removed (step 8), a drive-in diffusion step is performed to diffuse the injected P + boron ions vertically and laterally inside the substrate 10. This drive-in step is carried out until an oxide layer having a thickness of 6500 Å is formed on the exposed silicon substrate surface of the openings 10D and 10B. Next, the oxide layer is removed (step 9), and the oxide layer grown in the openings 30D and 30B and all the oxide layers including the initial oxide layer 12 are removed from the upper surface 11 of the substrate 10. Will be done.

【0018】

Figures 4A and 4B show the steps that follow the BiCDMOS process. An epitaxial layer 42 of silicon is grown on the upper surface 11 of the substrate 10 (step 10). In the 60 volt embodiment of the present invention, this epitaxial layer is, for example, 5 * 10¹⁵~1*10¹⁶cm³It is N-doped silicon with a thickness of approximately 10.2 μm ± 0.9 μm, which is doped within the range of. In the 20 volt embodiment of the present invention, this epitaxial layer is, for example, 5 * 10¹⁵~2*10¹⁶cm³It is N-doped silicon with a thickness of approximately 8.0 μm ± 0.7 μm, which is doped within the range of.

【0019】

Next, an epitaxial reoxidation step (step 11) is performed to form the epitaxial reoxidation layer 40 on the upper surface 41 of the epitaxial layer 42. Therefore, the three N + embedded layer regions 21A, 21B, and 21C will be inside the structure. These N + embedded layers extend downward from the boundary 11 between the substrate and the epitaxial layer to the inside of the substrate layer 10, and also extend upward from the boundary between the substrate and the epitaxial layer to the inside of the epitaxial layer 42. doing. During the growth of the epitaxial layer, the N + embedded layer region diffuses upwards. Similarly, the P + embedded layer region 43D is also present inside the structure. The P + embedded layer region 43D extends downward from the boundary between the substrate and the epitaxial layer to the inside of the substrate layer, and extends upward from the boundary between the substrate and the epitaxial layer to the inside of the epitaxial layer.

【0020】

However, there are two P + regions 43B and 44B formed from a single P + ion implantation performed on the upper surface of the N + embedded layer region 21B. Since the P-type ions diffuse faster than the N-type ions, the P + dopant in the P + ion implantation step diffuses upward and downward in the total embedded region 21B faster than the N + dopant. In the region where P + ions diffuse beyond the boundary of the more heavily doped N + region 21B, the P + ions form the P + region. The opening 30B used for P + injection is sufficiently smaller than the opening 12B used for N + injection in N + region 21B and is contained within so that the injected P + ions are laterally N + region 21B. It does not spread beyond the lateral range of. However, these injected P + ions diffuse vertically beyond the vertical range of N + region 21B. As a result, the two P + regions 43B and 44B are formed in a form separated by the N + regions 21B.

【0021】

Figures 5A and 5B show the steps that follow the BiCDMOS process. A photoresist layer (not shown) is formed on the epitaxial reoxidized layer 40 to form a P-wellmask layer (not shown) with three openings (step 12). One of these openings is above the high voltage MIMO region 10E. The second of these openings is above the low voltage MIMO region 10D. A third of these openings is placed on top of the P + embedded layer region 44B in the vertical PNP region 10B. Next, an oxide layer etching is performed, and the underlying epitaxial reoxidized layer 40 is selectively etched, and three openings 52E, 52D, and 52B extending from the epitaxial reoxidized layer 40 to the upper surface of the epitaxial layer 42 are formed. It is formed. The photoresist is then removed and a thin infused oxide layer (not shown) is grown at the three openings 52E, 52D, and 52B. This thin injected oxide layer has a thickness of, for example, 300 Å.

【0022】

A P-well ion implantation step (step 13) is then performed through a thin implantation oxide layer of openings 52E, 52D, and 52B to form P-well regions 51E, 51D, and 51B. The portion of the epitaxial reoxidized layer 40 that remains unetched serves as an injection mask. This ion implantation step is, for example, 1 cm at an energy of 100 KeV.²1 ~ 2 * 10 per¹³Doze boron implantation is performed.

【0023】

Next, a P-well drive-in diffusion step (step 14) is performed so that the P-well region 51D diffuses from the upper surface of the epitaxial layer and comes into contact with the P + embedded layer region 43D. Similarly, the P-well diffusion step diffuses the P-well 51B into the epitaxial layer until it contacts the top of the P + embedded layer region 44B. This P-well drive-in diffusion step is carried out until an oxide layer with a thickness of approximately 4000 Å is formed at the ion-injected openings 52E, 52D, and 52B.

【0024】

The P + isolation mask (step 15) injection (step 16) and drive-in diffusion (step 17) are then performed so that the isolation P + region (not shown) is around the selected transistor region of the epitaxial layer. It is formed inside an epitaxial layer that spreads laterally. These isolation structures are omitted in FIGS. 1 to 16 for the sake of simplicity.

【0025】

Figures 6A and 6B show the steps that follow the BiCDMOS process. A photoresist layer (not shown) is formed on the epitaxial reoxidized layer 40, and an N + sinker mask layer (not shown) having two openings is formed (step 18). One of these openings is located on the BMOS region 10A and the other is located on the vertical NPN region 10C. Next, an oxide layer etching is performed to selectively remove a part of the epitaxial reoxidized layer 40 exposed by the N + sinker mask layer. Therefore, the two openings 60A and 60C will be formed in the epitaxial reoxidized layer 40. The photoresist covering the P-wells 51E, 51D, and 51B is not removed, and the thinner oxide layer covering the P-wells 51E, 51D, and 51B remains protected and is not etched. After the etching step is complete, the photoresist mask is removed but the oxide layer 40 with two openings remains.

【0026】

Next, N + sinker regions 61A and 61C are formed at openings 60A and 60C, respectively. These N + sinker regions are POCl into openings 60A and 60C using, for example, HF immersion.₃Is formed by re-adhering (step 19). POCl₃Phosphorus is POCl at almost 950 ° C₃It is diffused downward from the layer toward the upper surface of the epitaxial layer so that the upper surface of the epitaxial layer at openings 60A and 60C has a surface resistance of approximately 2.1Ω / area.

【0027】

An N + sinker drive-in diffusion step (step 20) is then performed to diffuse the phosphorus dopant downward from the upper surface of the epitaxial layer. The N + sinker region 61A is formed on the N + embedded layer region 21A, and the lower part of the N + sinker region 61A comes into contact with the N + embedded layer region 21A as shown in the cross-sectional views of FIGS. 6A and 6B. Similarly, the N + sinker region 61C is formed on top of the N + embedded layer region 21C, and the lower part of the N + sinker region 61C comes into contact with the N + embedded layer region 21C. During this N + sinker region drive-in diffusion step, the oxide layer is grown on the exposed upper surface of the epitaxial layer at openings 60A and 60C. This oxide layer is made to have a thickness of, for example, approximately 5000 Å.

【0028】

7A and 7B show the above-mentioned next steps of the BiCDMOS process. A photoresist layer (not shown) is formed on the epitaxial reoxidized layer 40 to form a P + embedded Zenamask layer (not shown) with two openings (step 21). One of the openings is located on the embedded Zener region 71F and the other of the openings is located on the vertical PNP region 71B. Oxidative etching is then performed to remove the portion of the reoxidized layer 40 that remains exposed by the P + embedded Zenamask layer. Therefore, the two openings 70F and 70B will be formed inside the reoxidized layer 40. The photoresists covering the sinkers 61A, P-wells 51E, P-wells 51E, P-wells 51D, and sinker regions 61C are not removed, and the oxide layers covering these regions remain protected and are not etched.

【0029】

However, the photoresist mask is not removed after the etching step is complete. It is also not necessary for a thin injection oxide layer to be formed on the exposed portion of the upper surface of the epitaxial layer. Next, a P + embedded Zenaion injection step (step 22) is performed. This step is, for example, 1 cm with an energy of 80 KeV.²1 ~ 3 * 10 per¹⁵Doze's boron ions are injected. After the embedded Zener injection step, the embedded Zener photoresist mask is removed.

【0030】

Next, a P + embedded Zener drive-in diffusion step (step 23) is performed to diffuse the P + ions injected in the P + embedded Zener injection step downward into the epitaxial layer, and the P + embedded Zener anode region. Form 71F and P + collector contact area 71B. This drive-in step is carried out until an oxide layer having a thickness of approximately 500 Å is formed on the region 71F at the opening 70F and on the region 71B at the opening 70B.

【0031】

Figures 8A and 8B show the next steps in the BiCDMOS process. All the oxide layers forming the upper layer of the upper surface of the epitaxial layer, including the reoxidation layer 40, are all removed (step 24). Next, a base oxidation step (step 25) is performed to form the base oxide layer 80 on the upper surface of the epitaxial layer 40. The base oxide layer 80 is thermally grown at 950 ° C for approximately 125 minutes, for example, to a thickness of approximately 500 Å. Next, the silicon nitride layer 81 is adhered onto the base oxide layer 80 (step 26). The silicon nitride layer 81 has, for example, a thickness of approximately 1000 Å. The low temperature oxidation (LTO) layer 82 is then deposited onto the nitrided layer 81 (step 27). This LTO layer has a thickness of, for example, approximately 1000 Å.

【0032】

After the base oxide layer, nitrided layer, and LTO layer are formed, a pattern of a photoresist layer that serves as a mask for the active region (hereinafter referred to as "active area") on the upper surface of the LTO layer is provided (hereinafter, referred to as "active area"). Step 28). Next, the exposed portion of the LTO layer etched by the LTO layer is removed. Next, the nitrided layer is etched to remove the exposed portion of the nitrided layer. After the photoresist mask is removed, a plurality of active area mask regions 83A-83H are left on the surface of the base oxide layer 80. Each active area mask region has a nitride layer and an LTO layer forming an upper layer thereof.

【0033】

The N-field ion implantation step (step 29) is then performed through the portion of the base oxide layer located between the active area mask regions 83A-83H. This N-field injection step is, for example, 1 cm at an energy of 60 KeV.²1.7 * 10 per¹²Doze's phosphorus ion injection is performed.

【0034】

Figures 9A and 9B show the next steps in the BiCDMOS process. The photoresist layer 90 is formed on the upper surface of the structures of FIGS. 8A and 8B to form a P-field injection mask (step 30). In the structures shown in FIGS. 9A and 9B, this P-field injection mask has three openings 91E, 91D, and 91B.

【0035】

Next, the P-field ion implantation step (step 31) is performed. In some embodiments, the P-field oxidative photoresist injection mask may not be removed prior to the P-field ion implantation step. Regions 83E, 83D, and 83B serve as injection masks for the injection of P-type ions through the openings 91E, 91D, and 91B, respectively. P-field injection is, for example, 1 cm at an energy of 40 KeV.²8 * 10 per¹³It is used to inject doze boron ions. The photoresist may be removed after the P-field injection step (step 32).

【0036】

Figures 10A and 10B show the next steps in the BiCDMOS process. The mask areas 83A-83H of each active area are exposed at this stage, and the LTO layer of the mask areas 83A-83H of each active area can be removed by LTO etching (step 33). Therefore, the mask regions 83A to 83H of each active area have only a thin nitrided layer 81 forming an upper layer of the base oxide layer.

【0037】

Next, a field oxidation step (step 34) is performed to form a field oxide layer on the field region of the epitaxial layer that is not protected against oxidation by the nitride layer 81. Field Oxide Layers 100F / A, 100A / E, 100E / G, 100G / H, 100H / D, 100D / B, 100B, and 100B / C were formed on June 10, 1992 by Michael Chang, "Low Temperature Oxide Layer Over Field Implant" filed by David Grasso and Jun-Wei Please refer to the US patent application entitled "Mask)". The resulting field oxide layer has a self-aligned field injection region located beneath the field oxide layer according to the field injection steps of FIGS. 8A and 8B, 9A and 9B. In a P-well region such as region 51E, the field injection region underlying the field oxide layer is P-type silicon. Other regions that form the upper layer of N-type silicon, such as the field oxidation region that forms the upper layer of a part of the L-epitaxial layer, are doped to become N-type silicon. A growth step of the field oxide layer above the field injection region is performed, and the field oxide layer 100 has a thickness of approximately 8000 Å.

【0038】

Next, a thin oxide layer etching step (step 35) is performed to remove any oxide layer grown on the upper surface of the nitride layer 81 during the field oxidation step. A field oxide layer with a thickness of approximately 500 Å ± 100 Å is also etched in this step. Subsequent nitride layer etching steps (step 35) are then performed to remove all parts of the nitride layer 81 without further removal of the oxide layer.

【0039】

Next, after removing the nitrided layer to form an N-based injection mask (step 36), a photoresist layer 101 is formed on the upper surface of the structure. This N-base injection mask has one opening 102B formed over a portion of P-well 51B. This opening exposes part of the thin base oxide layer. An N-base ion implantation step (step 37) is then performed through the opening 102B to implant into the base region 103 within the P-well 51B. This injection step is, for example, 1 cm at 100 KeV energy.²2 ~ 3 * 10 per¹³Doze's phosphorus ion is injected. After the N-base injection step is complete, the photoresist mask is removed (step 38).

【0040】

Figures 11A and 11B show the next steps in the BiCDMOS process. Next, a polysilicon layer (not shown) is provided over the structure (step 43), which has a thickness of approximately 4000 Å. Next, the polysilicon layer is doped. In some examples, POCl₃Layer predeposition is done (step 48), POCl₃Phosphorus is diffused downward toward the inside of the polysilicon layer so that the surface resistance of the polysilicon layer is approximately 10 to 30 Ω / area. In another example, an injection step was performed, 1 cm with an energy of 80 KeV.²5 * 10 per¹⁵Doze's arsenic ions are injected into the polysilicon layer.

【0041】

Next, a photoresist layer (not shown) is formed on the photoresist and polysilicon layers formed in the polysilicon mask (step 49). Next, polysilicon gates 110A, 110E, 110G, 110H and 110D are formed by polysilicon etching. The polysilicon gate 110A is the gate of the DMOS transistor, the polysilicon gate 110E is the gate of the relatively high voltage polysilicon transistor, the polysilicon gate 110G is the gate of the relatively high voltage MIMO transistor, and the polysilicon gate 110H. Is the gate of a relatively low voltage PMOS transistor and the polysilicon gate 110D is the gate of a relatively low voltage NMOS transistor. After forming the polysilicon gate, the photoresist mask is removed.

【0042】

Figures 12A and 12B show the next steps in the BiCDMOS process. The photoresist layer 120 is formed on the polysilicon gate, and the photoresist layer 120 is formed in the DMOSP-body injection mask (step 50). The DMOSP-body injection mask has an opening 121A, which exposes the polysilicon gate 110A of the DMOS transistor. The mask also exposes the surface area on the upper surface of the epitaxial layer on each side of the polysilicon gate 110A. The mask also has an opening 121F, which exposes part of the embedded Zener anode region 70F.

【0043】

The DMOSP-body ion implantation step (step 51) is then performed, which forms the P-body region 122, which is self-aligned with the polysilicon gate 110A of the DMOS transistor. The body region 122 exhibits an annular shape that surrounds the region of the epitaxial layer beneath the polysilicon gate 110A. In other embodiments, the outer border of this annular body region 122 has other shapes, such as polygons, which may be square, rectangular, striped, pentagonal, hexagonal. Such shapes are included. This DMOSP-body injection step is, for example, 1 cm with energy of 60 KeV.²0.5 ~ 1.5 * 10 per¹⁴Doze's boron ion is injected. After the P-body region 122 of the DMOS transistor is injected, the photoresist 120 is removed (step 52) and the DMOS P-body drive-in diffusion step (step 53) is performed to make the P-body region 122 the epitaxial layer. It diffuses inward vertically and horizontally.

【0044】

Figures 13A and 13B show the next steps in the BiCDMOS process. After the P-body region 122 of the DMOS transistor is diffused into the epitaxial layer, a thin N-doped blanket ion implantation step (step 54) is performed. Since no injection mask is used, all parts of the upper surface of the epitaxial layer that are not protected by the field oxide layer or polysilicon gate will be injected with the N-type dopant. This thin N-doped drain blanket ion implantation step is, for example, 1 cm at an energy of 120 KeV.²0.5 ~ 5 * 10 per¹²Doze's phosphorus ion is injected.

【0045】

Figures 14A and 14B show the next steps in the BiCDMOS process. The photoresist layer 140 is provided on top of the structures of FIGS. 13A and 13B and then formed in a P-based injection mask (step 55). In the examples shown in FIGS. 14A and 14B, this P-based injection mask has two openings 141G and 141C.

【0046】

The P-base ion implantation step (step 56) is then performed through openings 141G and 141C to form a self-aligned, thinly doped drain region 142G for the high voltage PCOS transistor, forming a vertical NPN bipolar transistor. Form P-base region 142C for.

【0047】

As shown in FIGS. 13A and 13B, this N-dopping blanket injection reverse-dops the P-body of the DMOS transistor, reverse-dops the P-base of the NPN transistor, and increases the N-base doping concentration of the PNP transistor. This results in the formation of a lightly doped drain of the 16 volt MIMO transistor and the reverse doping of the source and drain of the 5 volt and 6 volt PMOS transistors. The effect of this blanket N-doping must be analyzed as the P body of the DMOS transistor, the NPN and the dopant concentration of the base of the PNP transistor have a significant effect on performance. More specifically, the blanket injection of the N-dopant into the base of the NPN transistor increases the N-base concentration, which reduces the gain of the NPN transistor and reduces the base resistance. In the case of DMOS body and NPN transistor based reverse doping, P-body dopant injection for DMOS transistors and P-type base injection for NPN transistors are selected to compensate for this N-dopant blanket injection. It must be. Therefore, with proper selection of doping levels in the various transistor regions, the N-type drift required to increase the breakdown voltage of a 16 volt NMOS transistor shown in Figure 16A without compromising the operating characteristics of other transistors. Blanket injection N-doping can be used to create the (drift) region. Therefore, the thin N-doped drain region of the 16 volt NMOS transistor in FIG. 16A is formed without additional cost or a large number of masking steps. Since the 5 volt NMOS transistor is formed without producing a drifted drain, the 5 volt NMOS transistor will have a lower on-resistance than the 16 volt NMOS transistor shown in FIG. 16A. This drift region is a 16 volt MIMO

【0048】

In other embodiments, it is also possible to position the 16 volt MIMO gate of FIG. 13A more centrally to form a lightly doped source and a lightly doped drain region. is there. As a result, the N + dopant mask can be formed in FIG. 15A so that the N + source and drain are formed at positions away from the gate. The drifted source, along with the drifted drain, allows higher voltage to be applied between the source and drain as well as between the source and gate. However, the drifted source will cause the NMOS transistor to have a higher on-resistance.

【0049】

Part of the polysilicon gate 110G and part of the field oxidation region 110G / H are exposed by the opening 141G, and the boundary of the lightly doped drain region 142G is self-aligned with the boundary of the polysilicon gate 110G, resulting in a thin doping. Another boundary portion of the drain region 142G made will be self-aligned with the boundary of the field oxidation region 110G / H. Similarly, the opening 141C exposes part of the field oxide region 110B / C so that the boundary of the base region 142C is self-aligned with the boundary of the field oxide layer. This P-based injection step is 1 cm at an energy of 100-150 KeV, for example.²5 ~ 9 * 10 per¹²Doze's boron ion is injected. In other examples, the P-based injection step is 0.5-5 * 10 per cm at 40 KeV energy, in addition to high energy deep injection.¹⁴It involves the injection of a second boron ion in the dose. After completion of the injection step, the P-based injection photoresist mask is removed (step 57).

【0050】

Figures 15A and 15B show the next steps in the BiCDMOS process. The photoresist layer 150 is provided on top of the structure and is formed to serve as an injection mask for N + sources, drains and emitters (step 58). In the embodiments shown in FIGS. 15A and 15B, this N + source, drain and emitter injection mask has openings 151F, 151A1, 151A2, 151E1, 151E2, 151D, 151B, 151C1 and 151C2. Since the opening 151F is located above the P + anode portion 71F of the embedded Zener diode, subsequent N + dopant injection forms an embedded diode that joins the upper N + cathode region 72F. The opening 151A1 is formed on the region A of the epitaxial layer on which the MIMO transistor is being formed. The opening 151A1 exposes the polysilicon gate 110A of the DMOS transistor, along with a portion of the P-body region 122 of the DMOS transistor. Therefore, subsequent N + injections form an N + source region 152 inside the P-body region 122. The opening 151A2 is located on the upper surface of the N + sinker 61A and increases N doping in this area. The opening 151E1 exposes the source region on the upper surface of the epitaxial layer with a portion of the polysilicon gate 110E, and the subsequent N + injection steps form a self-aligned source region 153 for the high voltage MIMO transistor. become. The opening 151E2 exposes the drain contact region on the upper surface of the previous thinly doped drain region 154, which can be formed laterally separated from the channel region 156 of the NMOS transistor. It becomes. The opening 151D is provided above the region D of the epitaxial layer on which relatively low voltage NMOS transistors are being formed. The opening 151D exposes the polysilicon gate 110D along with the source and drain regions on the upper surface of the epitaxial layer. A self-aligned source region 157 and a self-aligned drain region 158 can be formed for the low voltage MOSFETs by the subsequent N + injection. The opening 151B is provided on the region B of the epitaxial layer on which the vertical PNP transistor is being formed. The opening 151B exposes a portion of the previously formed N-base region 103, followed by N + injection to form the base contact region 159. The opening 151C1 is provided above the region C of the epitaxial layer on which the vertical NPN transistor is being formed. The opening 151C1 exposes a portion of the previously formed P-base region 142C and a subsequent N + injection step forms an emitter region 1700 for the NPN transistor.

【0051】

The N + source, drain and emitter ion implantation step (step 59) is then performed through the openings in the N + source, drain and emitter mask. This injection, for example, with an energy of 60 KeV, 1 cm²5 ~ 8 * 10 per¹⁵Doze's arsenic ion is injected. Injection of N + ions removes the N + source, drain and emitter mask photoresist (step 60).

【0052】

Figures 16A and 16B show the next steps in the BiCDMOS process. After the polyreoxidation step (step 61) is performed, the photoresist layer 160 is adhered and adapted to the P + source, drain and emitter masks (step 62). In the embodiments shown in FIGS. 16A and 16B, the mask has openings 16A1, 161A2, 161G1, 161G2, 161H, 161B1, 161B2, and 161C. The openings 161A1 and 161A2 have two cross-sectional positions of a substantially annular opening to form an annular P + body contact region 162 arranged to contact the annular P-body region 122 of the PCOS transistor. It actually contains. The opening 161G1 and part of the polysilicon gate 110G and part of the field oxidation region 100E / G are exposed to form a self-aligned source region 163 by subsequent P + injection. The opening 1G1G2 exposes a portion of the upper surface of the drain region 142G, followed by a P + injection step that provides a small drain contact area 164 laterally separated by the drift region from the transverse boundary of the polysilicon gate 110G. Form. The opening 161H, along with a portion of the upper surface of the epitaxial layer between the polysilicon gate 110H and the field oxidation regions 100G / H and 100H / D, exposes the polysilicon gate 110H by subsequent P + injection. It forms a self-aligned source region 166 and drain region 167. The opening 161B1 extends from the field oxidation region 100D / B to the field oxidation region 100B, which will add an additional P-type dopant to the P + collector contact region 71B in the subsequent P + injection step. The opening 161B2 exposes the surface area of the base region 103, followed by P + injection to form an emitter region 168 formed in the region within the base region 103 but laterally separated from the base contact region 153. .. Opening 161C is

【0053】

The P + source, drain and emitter ion implantation steps (step 63) are then performed through the openings in these masks 160. This injection is, for example, 1 cm with an energy of 60 KeV.²3 * 10 per¹⁵Doze's boron ion is injected. After injection, the photoresist mask 160 is removed.

【0054】

FIG. 17 is a cross-sectional view of the thin film resistor structure formed by the BiCDMOS process. In an embodiment of the process of forming a resistor structure, a layer of borated phosphorylated silicate glass (BPSG) 170 is adhered (step 64) and reflows on the epitaxial layer 40 at a temperature of 900-950 ° C. Is done (step 65). A layer of silicon-chromium (Si-Cr) is then deposited over the BPSG layer (step 66). The BPSG layer has, for example, a thickness of approximately 6500 Å. The Si-Cr layer has, for example, a thickness of about 200 to 300 Å and a surface resistance value of about 2 KΩ / area. The titanium-tungsten (Pi-W) layer is then sputtered onto the top of the Si-Cr layer. This Pi-W layer has, for example, a thickness of approximately 1000 Å. The photoresist layer (not shown) is then adhered onto the top of the Pi-W layer, and the photoresist layer is in a form adapted to the thin film mask covering the resistor being formed. .. Next, all parts of the Pi-W that are not mask protected are removed by etching. A second etching corrosive solution is used to remove all parts of Si-Cr that are not protected by the photoresist mask. The structure (not shown) resulting from such treatment is a sandwich structure of the resistance layer region of the resistant Si-Cr forming the lower layer and the conductive layer of Pi-W forming the upper layer. Then, the photoresist mask is removed.

【0055】

An interconnect metal layer, such as aluminum, is then deposited over the Pi-W layer of the structure (step 68). The interconnect metal layer is, for example, a layer of 0.8 μm thick of aluminum doped with 1% silicon and 0.5% copper. The attachment of this interconnect metal layer is the same metal coating step, with various transistors and other structures formed in the above steps by depositing the interconnect metal on other parts of the die. It is an interconnect between them.

【0056】

The photoresist layer is then formed on top of the interconnect metal layer, which is formed to fit the metal mask (step 69). This metal mask creates an unprotected Pi-W layer portion between the two protected Pi-W layer portions. Therefore, when the next metal etching step is performed to form a connection with the metal interconnect line and other parts on the die, the exposed portion of the aluminum layer on which the metal etchant forms the upper layer of the Pi-W layer. And the lower Pi-W corrodes. As a result, a part of the underlying resistant Si-Cr is not covered with the conductive Pi-W layer. One end of this portion of the resistant Si-Cr region 171 is connected to the metal-coated aluminum interconnect portion 173A through the first portion 172A of the Pi-W layer, whereas the resistant Si-Cr region 171 of the resistant Si-Cr region 171. The second end is connected to the second metal-coated aluminum interconnect portion 173B through the second portion 172B of the Pi-W layer.

【0057】

The insulating oxide layer is then adhered to the metal interconnect portion at the thin film resistor region and other portions on the die. This insulating oxide layer is, for example, an adhered TEOS oxide layer (step 70) having a thickness of approximately 7,000 Å, which is covered with a 600 Å TEOS oxide layer. After a viamask step (step 73) has been performed to form openings through the insulating oxide layer to various selected positions of the underlying structure, the second interconnect metal layer is placed on the insulating oxide layer. It is sputtered (step 70) and masked to form a second level of metal interconnect (step 75).

【0058】

A protective film layer is then formed over the entire upper surface of the structure (step 76). The protective film layer is, for example, a PSG with a thickness of 8000 Å, a sandwich of undoped PSG with a thickness of 2000 Å and 4% PSG with a thickness of 6000 Å, or a PE CVD nitride layer with a thickness of 8000 Å. One BiCDMOS process of the embodiments of the present invention uses a pad mask and etching step (step 77) to form an opening in the protective film layer, exposing the metal bonding pad for wire bonding through the underlying protective film layer. It will end after doing.

【0059】

According to one embodiment of the BiCDMOS process above, the relatively deep body region of the DMOS transistor is compared without the dopant from the polysilicon gate of the CMOS transistor passing through the gate oxide layer to the underlying epitaxial layer. It is diffused into the epitaxial layer at a high temperature. As shown in FIGS. 12A and 12B, the polysilicon gate 110A is used as an injection mask when the body region 122 of a 20 volt DMOS transistor is injected. The polysilicon gate 110H is formed at the same time that the polysilicon gate 110A of the DMOS transistor is formed, when the source and drain regions of the MIMO transistor are injected as shown in FIGS. 16A and 16B. It is also used as an injection mask in the manufacture of 5-volt MIMO transistors. Polysilicon transistor poly is the result of heavy doping of the polysilicon gate with phosphorus ions (or arsenic ions that prevent boron ions from diffusing through the gate oxide layer and changing the threshold voltage of the 5-volt P-channel MOSFET). Dopants from silicon gates pass through the upper gate oxide layer and simultaneously on the same wafer with high reliability, with a small number of process steps, without reducing functional area yields, DMOS transistors and CMOS. It will be possible to manufacture transistors.

【0060】

According to another embodiment of the BiCDMOS process, if a high breakdown voltage CMOS transistor is made on the same wafer with a relatively low breakdown voltage CMOS transistor, then a blanket ion injection step is used to create a high breakdown voltage. The lightly doped drain of a CMOS transistor can be doped. As shown in FIGS. 13A and 13B, the polysilicon gate 110E of the 16 volt MIMO transistor and the polysilicon gate 110H of the 5 volt MIMO transistor serve as masks in the N-dopant blanket ion implantation steps of FIGS. 13A and 13B. Used. Therefore, a thinly doped drain region 154 of the high voltage MOSFET is formed. However, in the subsequent P-type implantation steps shown in FIGS. 16A and 16B, the source and drain regions 166 and 167 of the 5-volt PMOS transistor are doped with the P-type dopant, but in FIGS. 13A and 13B. It must be doped with a P-type dopant to overcome the N-type dopant in the blanket ion implantation step and the N-type dopant in the epitaxial layer. To remove the process mask, the BiCDMOS process is approximately 1 cm³5x10 per¹⁵~1×10¹⁶Starting with a very lightly doped epitaxial layer containing N-type doping of the ions, a subsequent blanket ion implantation step is performed to form a lightly doped drain region 154 of the high voltage NMOS transistor. You will get it. As a result, the N-type blanket ion implantation step does not dope the source and drain regions of the low-voltage PMOS transistor too heavily, so the P-type implantation step of FIGS. 16A and 16B is the source and drain regions of the low-voltage PMOS transistor. It will not be sufficient to form the drain regions 166 and 167.

【0061】

According to another embodiment of the BiCDMOS process, the base region of the bipolar transistor is formed at the same time as the thinly doped drain of the relatively high voltage CMOS transistor is formed. As shown in FIGS. 14A and 14B, the P-base injection region 142C of the vertical NPN bipolar transistor is formed at the same time as the thinly doped drain region 142G of the PCOS transistor with a relatively high breakdown voltage is formed. To. Note that the same injection mask is used here. Therefore, the BiCDMOS process allows both bipolar transistors and relatively high voltage CMOS transistors to be manufactured using the same wafer with fewer process steps. Note that such step sharing can also lead to the next process step being shared. The P-type injection step shown in FIGS. 16A and 16B forms, for example, the base contact region 169 of the vertical NPN bipolar transistor and also the drain contact region 164 of the PCOS transistor with a relatively high breakdown voltage.

【0062】

According to another embodiment of the BiCDMOS process, the embedded Zener diode is formed on the same wafer at the same time that a CMOS transistor with a relatively high breakdown voltage is formed. As shown in FIGS. 13A and 13B, blanket N-type ion injection was performed and the lightly doped drain region 154 of the 16 volt NMOS transistor was lightly N-doped on the P-type anode region 71F of the Zener diode. It is formed together with the Zener part 130F. Next, in the N-type injection step of FIGS. 15A and 15B, a heavily doped N-type Zener cathode region 72F is formed, and an N-type drain contact region 155 and an N-type source region 153 of a 16-volt NMOS transistor are formed. It is formed at the same time as the Therefore, the BiCDMOS process effectively provides an embedded Zener diode on the same wafer as the high voltage CMOS transistor, or multiple matched embedded Zener diodes separately, without the use of additional mask steps or process steps. To do.

【0063】

According to other embodiments of the BiCDMOS process, embedded Zener diodes can be made in a special way to reduce defects so that multiple Zener diodes can match each other. After injecting N-type ions into the P + anode region 71F, the damage caused by the silicon injection is heat treated by a thin oxide layer located on the embedded Zener region rather than the rest of the active area. The thickness of the oxide layer on the Zener region should be 1000 Å or less, for example about 500 Å. In addition, the breakdown voltage at the boundary between the lightly doped region 130F and the underlying epitaxial layer should be high and completely independent of the silicon surface. Therefore, the N + injection dopants of FIGS. 15A and 15B will be injected beneath the silicon surface to a depth of approximately 0.4-0.5 μm. The depth of the P + anode region 71F should be 3-4 μm, whereas the depth of the P-body region 122 of the DMOS transistor should be approximately 1.5 μm. Thus, the P + anode region 71F is more heavily doped and the P-body region 122 is lighter doped, ensuring that each region has the desired depth in the same diffusion step. You can do it.

【0064】

2. Additional structure FIG. 18 is an enlarged cross-sectional view of an embodiment of the isolation structure. It is shown that the vertical PNP bipolar transistor located in region B of FIG. 16B is located inside the isolation structure of FIG. Therefore, the method of forming the isolation structure of FIG. 18 is described in the description of the BiCDMOS process of FIGS. 1 to 16.

【0065】

The isolation structure of FIG. 18 includes an N + embedded layer region 21B, a first P + embedded layer region 43B, a second P + embedded layer region 44B, and a P-well region 51B. The N + embedded layer region 21B extends downward from the boundary 191 between the substrate and the epitaxial layer toward the substrate layer 10, and also extends upward in the epitaxial layer 40. The first P + embedded layer region 43B extends downward from the lower surface of the N + embedded layer region 21B, and the P + embedded layer 44B extends upward from the upper surface of the N + embedded layer region 21B. Therefore, the N + embedding layer 21B divides the upper embedding well region 44B and the lower embedding well region 43B. The P-well region 51B extends downward from the upper surface of the epitaxial layer 40 toward the epitaxial layer 40 and is in contact with the P + embedded well 44B. The P + embedding layer region 44B is therefore referred to as the embedding well region.

【0066】

The field oxide layers 100D / B and 100B / C shown in FIG. 18 are arranged on the upper surface of the epitaxial layer 40 in some examples. This field oxide layer is provided on the upper surface of the epitaxial layer 40 so as to surround the P-well 51B, and defines an active area 180 on the well-side surface of the P-well region. The P-type field injection regions 181D / B and 181B / C are located below the field oxide layers 100D / B and 100B / C, where the field oxide layer forms the upper layer of the P-well region 51B. Similarly, the N-type field injection regions 182D / B and 182B / C are the field oxide layers 100 / B and 100B / C at the positions where the field oxide layer forms the upper layer of the N-epitaxial layer outside the P-well region. Placed under C.

【0067】

Therefore, the P-well region 44B is separated from the underlying substrate 10 by the N + embedded layer region 21B and the N-epitaxial layer 40. Thus, the isolation structure forms an active area on the surface of the P-well region 51B, which allows the semiconductor material on which the transistors are provided to be electrically isolated from other structures on the die. When it should be, it is the position where an electrical device such as the transistor is formed. It will be understood that if all P-type regions are changed to N-type regions, N-type wells will also be provided on the N-type substrate.

【0068】

FIG. 19 is an enlarged cross-sectional view of an embodiment of the first vertical bipolar transistor structure shown in region B of FIGS. 1 to 16. The P-type field injection regions 181D / B, 181B, and 181B / C are located below the field oxide layers 100D / B, 100B, and 100B / C, respectively, and here the underlying silicon of the P-well 51B It has a P-type conductive type. The N-type field injection regions 182D / B and 182B / C are arranged below the field oxide layers 100D / B and 100B / C, where the silicon of the underlying N-epitaxial layer 40 has an N-type conductive type. .. The collector contact region 71B extends downward from the upper surface of the epitaxial layer to the inside of the P-well region 51B. In the embodiment shown in FIG. 19, the P + collector contact region 71B extends deeper inside the P-well region 51B than the field injection region 181B. The N-base region 103 extends downward from the upper surface of the epitaxial layer between the field oxide layer 100B and the field oxide layer 100B / C of the P-well 51B. Since the N + base contact region 159 and the emitter region 168 extend downward toward the base region 103, the emitter region 168 is laterally separated from the base contact region 159. The metal electrodes connected to the emitter region, base region, and collector region of the structure of FIG. 19 are omitted in the figure for simplicity.

【0069】

FIG. 20 is a cross-sectional view of an embodiment of the second vertical bipolar transistor structure. The N + embedded layer region 190, which is similar to the N + embedded layer 21C of FIGS. 1 to 16, extends upward from the boundary 191 between the substrate and the epitaxial layer to the inside of the epitaxial layer 40, and extends downward to the inside of the epitaxial layer 40. It extends inside the. The N + sinker region 192, which is similar to the N + sinker region 61C, extends downward from the upper surface of the epitaxial layer 40 to the inside of the epitaxial layer 40 and is in contact with the N + embedded layer region 190. Thick field oxide layers 193 and 194 are formed on the field region 195 of the epitaxial layer 40 and surround the active area 196 of the epitaxial layer. The N-type field injection regions 197 and 198 are arranged between the field oxide layer and the N-epitaxial layer under the field oxide layers 193 and 194.

【0070】

The P-base region 199 extends downward from the upper surface of the epitaxial layer 40 to the inside of the epitaxial layer 40 in the active area 196. This P-base region is formed at the same time that the P-base region 142C is formed in the process of FIGS. 1 to 16. The thin N-doped region 198 is optionally located on the upper surface of the epitaxial layer 40 between the N + sinker region 192 and the lateral boundary of the P-base region 199. This lightly doped N-region 198 is formed, for example, in the N-blanket doping step of the process of FIGS. 1-16.

【0071】

The gate oxide layer is arranged on the upper surface of the epitaxial layer 40 in the active area 196. This gate oxide layer is divided into two parts, 200 and 201. An emitter contact opening 202 is formed in the gate oxide layer portion 200, and the gate oxide layer portion 200 surrounds the emitter contact opening 202. Since the base opening 203 surrounds the gate oxide layer portion 200, in the cross-sectional view of FIG. 20, one end of the base opening 203 is between the gate oxide layer portion 200 and the field oxide layer portion 193. The other end is arranged between the gate oxide layer portion 200 and the gate oxide layer portion 201. The collector contact opening 204 is formed between the gate oxide layer portion 201 and the field oxide layer portion 194.

【0072】

The polysilicon layer 205 having almost the same shape as the lower gate oxide layer portion 200 is arranged on the gate oxide layer portion 200, and both the polysilicon layer 205 and the gate oxide layer portion 200 are substantially vertical. The side walls 206 and the substantially vertical side walls 207 are formed, and these side walls extend to the upper surface of the epitaxial layer.

【0073】

The N + emitter region 208 extends downward from the upper surface of the epitaxial layer into the base region 199 below the emitter opening 202. The emitter region 208 extends laterally to below the gate oxide layer portion 200. The base contact region 209 extends downward into the base region 199 from the upper surface of the epitaxial layer under the base contact opening 203. This base contact region also extends laterally below the gate oxide layer portion 200. As shown in FIG. 20, the base region 209 surrounds the emitter region 208 in a horizontal plane.

【0074】

The base electrode 210 of an electrically conductive material such as aluminum connects to the base contact region 209 through the base contact opening 203. Similarly, the collector electrode 211 connects to the N + sinker region 192 through the collector contact opening 204. The emitter electrode 212 connects to the emitter region 208 through the emitter contact opening 202, which is such that the emitter contact opening 202 is directed downward from the upper surface of the polysilicon layer 205 to the emitter region 208 on the upper surface of the epitaxial layer. Due to the fact that it has been extended all the way. The insulating layers 213 and 214 are arranged such that at least a part thereof is between the polysilicon layer 205 and the base contact electrode 210, and insulates the base electrode 210 from the emitter electrode 212.

【0075】

The structure of FIG. 20 is made by forming the polysilicon layers 205 at the same time that the polysilicon gates 110A, 110E, 110G, 110H, and 110D are formed based on the process of FIGS. 1-16. The N + dopant is then injected into the base region 199 to form the self-aligned base emitter region 208, and the P + dopant is injected into the base region to form the self-aligned base contact region 209. The gate oxide layer portion 200 may or may not define part of the substantially vertical boundary of the injection mask that demarcates the boundary of the emitter region 208 and the base contact region 209. If the gate oxide layer 200 is not part of the injection mask, the boundaries of the injection mask are formed only by the boundaries of the polysilicon layer 205 formed as a pattern. Such a method of forming the vertical bipolar transistor of FIG. 20 allows the polysilicon layer 205 to have a minimum line width W for the process used. Therefore, the distance between the self-aligned base contact region 209 and the self-aligned emitter region 208 is minimized. By controlling the distance between the laterally diffused emitter region and the base contact region, the distance between the base contact region and the emitter region can be reproducibly controlled in a reproducible and controllable manner, much more than the minimum line width W. It can be small. Therefore, with the structure of FIG. 20, a structure in which the distance between the base contact region and the emitter region is small can be easily formed repeatedly and while being controlled. Therefore, the bipolar transistor made by the structure of FIG. 20 can be easily formed. Base-emitter resistance and capacitance can be minimized. In this way, a high frequency transistor with a high cutoff frequency is produced.

【0076】

FIG. 21 is a cross-sectional view of an embodiment of the third vertical bipolar transistor structure. This isolation structure similar to the isolation structure of FIG. 18 has an N + embedding layer region 210 that separates the P + embedding well region 212 from the P + embedding layer region 211. The P-well region 213 extends downward from the upper surface of the epitaxial layer 40 and contacts the upper surface of the P + embedded well region 212. The N-field injection regions 214 and 215 form the lower layers of the field oxide layers 215 and 216, and here, the N-type semiconductor material of the N-epitaxial layer 40 forms the lower layer of the field oxide layer. The P-field injection regions 217 and 218 form the lower layers of the field oxide layers 215 and 216, and here the P-type semiconductor material of the P-well region 213 forms the lower layer of the field oxide layer. In the vertical bipolar transistor of FIG. 21, the field oxide layers 219 and 220 form an emitter opening 221 on the upper surface of the P-well region 213. The N-base region 222 is formed in the P-well region 213 through the opening 221. After this, a P + -type emitter region 223 is formed in the upper portion of the N-base region 222 through the same opening 221. The N-base region 222 is, for example, an injection region that is implanted during the N-blanket ion implantation step shown in FIG. The P + emitter region is formed, for example, in the P + injection step of FIG.

【0077】

The N-type injection regions 224 and 225 below the oxide layer portions 219 and 220 form a lateral connection between the N-base region 222 and the laterally located N + base contact region 226, respectively. The N-type injection areas 224 and 225 are injected at the same time as the N-type field injection areas 214 and 215 are injected, for example. The N + base contact region 226 is injected, for example, through the opening 227 of the field oxide layer in the N + injection step of FIG. The sideways arranged P + collector contact area 228 is formed in the P-well area 213, the P-well area 213 acts as a collector for the bipolar transistor, and the collector contact area 228 is the collector for the bipolar transistor. Serves as a contact part. The P + collector contact region 228 is formed, for example, in the same process step in which the P + emitter region 223 is formed. Therefore, both the P + emitter region 223 and the N-base region 222 are self-aligned with the opening 221 and the N + base contact region 226 is self-aligned with the opening 227. The emitter, base, and collector electrodes are omitted in the figure for simplicity.

【0078】

FIG. 22 is a cross-sectional view of the first lateral DMOS structure. The N-epitaxial layer 40 having an upper surface is arranged on the substrate layer 40. The P-well region 230 extends downward from the upper surface of the epitaxial layer into the epitaxial layer 40. The field oxide layer having the field oxide layer portions 231 and 232 and the field oxide layer portion 233 is arranged on the upper surface of the epitaxial layer 40. Field oxide layers 231 and 233 define the active area 234. The P-type field injection regions 235 and 236 are arranged below the field oxide layer portions 231 and 233, and here the field oxide layer portions 231 and 233 form an upper layer of P-type silicon in the well region 230. ing. Similarly, the N-type field injection regions 237 and 238 are arranged below the field oxide layer portions 231 and 233, in which the field oxide layer portions 231 and 233 form an upper layer of the epitaxial layer of N-type silicon. It has become.

【0079】

Here, the body region 239, which is a P-body region, extends downward from the upper surface of the epitaxial layer into the well region 230 in the active area. Here, the drain contact region 240, which is an N + drain contact region, extends downward from the upper surface of the epitaxial layer into the well region 230 in the active area. The body region 239 is located within the well region 230 and is laterally separated from the drain contact region 240 to form a shape. The well region 230 drift region portion 241 is located between the body region 239 and the lightly doped drain injection region 242. The lightly doped drain injection region 242 is located between the drift region 241 and the drain contact region 240, and the lightly doped drain injection region 242 connects to the drain contact region 240. Here, the lightly doped drain injection region 242, which is an N-type injection region, is arranged below the field oxide layer portion 232 in the active area.

【0080】

Here, the source region 243, which is an N + source region, is arranged in the body region 239, and the source region 243 extends from the upper surface of the epitaxial layer into the body region 239. The channel portion 252 of the body region 239 separates the source region 243 from the drift region 241. Here, the source contact region 244, which is the P + source contact region, extends from the upper surface of the epitaxial layer into the body region 239, and the source contact region 244 connects to the source region 243.

【0081】

The gate oxide layer 245 is arranged on the upper surface of the epitaxial layer 40 in the active area 234, but the field oxide layer 232 does not extend here. Two openings 246 and 247 are formed in the gate oxide layer 245. The opening 246 is located above at least a portion of the source contact area 244 and above at least a portion thereof of the source region 243. The opening 247 is located above at least a portion of the drain contact area 240. The polysilicon gate layer 248 is arranged on the gate oxide layer 245 and the field oxide layer portion 232, from the source region 234, on the channel portion 252 of the body region 239, on the drift region 241 and on the field oxide layer portion 232. It extends over a part of the field oxide layer portion 232 and extends upward. An insulating layer 249 made of an insulating material such as phosphite booxide silicate glass (BPSG) is placed on top of the polysilicon gate layer 248, from above the opening 246 of the gate oxide layer 245 to above the source region 243. It extends above the gate oxide layer 245, above the polysilicon gate layer 248, above the field oxide layer portion 232, and up to the opening 247, and extends upward above the polysilicon gate layer 248. It has become. The source electrode 2500 made of an electrically conductive material such as aluminum connects to the source contact area 244 and the source area 243 at the position of the opening 246. The drain electrode 2510 made of an electrically conductive material connects to the drain contact region 240 at the opening 247. The gate electrode is connected to the polysilicon gate layer 248. These electrodes are not shown in the cross section of FIG.

【0082】

During operation, the voltage applied to the polysilicon gate layer 248 causes the channel to form a channel region 2520 of the body region 239 between the source region 243 and the drift region 241. Therefore, current can flow from the source electrode 2500 through the channels of the source region 243, the channel region 2520, the drift region 241, the field injection region 242, and the drain contact region 240 to the drain electrode 2510. The current also flows in the opposite direction from the drain electrode to the source electrode.

【0083】

Therefore, the structure of FIG. 22 uses the field injection region 242 located below the field oxide layer portion 232 as a lightly doped drain region. The lightly doped field injection region 242 is formed when the N-type field injection region 238 is formed. The N-type field injection region is formed at the same time as the N-type field injection region is formed, for example, as shown in FIG. The body region 239 is formed at the same time as the region 122 is formed, for example, as shown in FIG. Regions 243 and 240 are formed at the same time that the N-type region is formed, for example, as shown in FIGS. 13 and 15. The source contact region 244 is formed at the same time as the P + region is formed, for example, as shown in FIG. The structure of FIG. 22 is made using the BiCMOS process described above, but other wafer manufacturing processes may be used to form this structure. The N-channel lateral DMOS transistor is shown in FIG. 22, but a P-channel lateral DMOS transistor is also realized by replacing all the N-type regions with P-type regions and vice versa for the P-type regions.

【0084】

FIG. 23 is a cross-sectional view of a second embodiment of the lateral DMOS transistor structure. In the example of FIG. 23, the P-well region 230 is not given. Here, unlike the P-type substrate shown in FIG. 22, an N-type substrate layer is used. As shown in FIG. 23, this N-type substrate is either a relatively thin N-doped substrate or a relatively dense N + -doped substrate.

【0085】

FIG. 24 is a cross-sectional view of a third embodiment of the lateral DMOS transistor structure. In the embodiment of FIG. 24, a P-channel lateral DMOS transistor is shown. The N-type epitaxial layer is arranged on the N + type substrate layer. The source contact area is N + type silicon, the source area is P + type silicon, the body area is N-type silicon, the drift area is N-type silicon of the epitaxial layer, and the drain injection area is lightly doped. 242 is the field injection area. In the embodiment of FIG. 24, the P + drain contact region 240 does not extend downward until it is deeper than the P-type field injection portion 242. The P + drain contact region 240 is not connected to the underlying N-type epitaxial layer 40. The P-region 283 is also located below the P + drain contact region 240 and extends downward into the N-type epitaxial layer 40 from the underside surface of the lightly doped P-type field injection region 242. ing.

【0086】

The P-region 238 is formed, for example, at the same time that the P-well regions 51E, 51D and 51B shown in FIG. 5 are formed. The thin P-type doped drain injection region 242 is formed, for example, at the same time as the P-type field injection shown in FIG. 9 is performed. The N-body region 239 is formed, for example, at the same time that the region 103 shown in FIG. 10 is formed. The N + source contact region 244 is formed, for example, at the same time as the N + injection step shown in FIG. The P + source region 243 and the P + drain contact region 240 are formed, for example, at the same time as the P + injection shown in FIG. Although the P-channel lateral DMOS transistor is shown in FIG. 24, the N-channel lateral DMOS transistor is also realized by replacing all the P-type regions with the N-type region and similarly replacing the N-type region. The above structures are manufactured using the BiCDMOS process described above, but other wafer manufacturing processes can also be used to form these structures.

【0087】

FIG. 25 is a cross-sectional view of an embodiment of the lateral DMOS transistor structure. Here, the epitaxial layer, which is an N-epitaxial layer, is arranged on the substrate layer 10. The P-type embedded layers 250 and 251 extend upward from the boundary 191 between the substrate layer and the epitaxial layer. The P-type isolation sinker regions 252 and 253 extend downward from the upper surface of the epitaxial layer and are connected to the P-embedded layers 250 and 251 to form a bonded isolation sinker and P-type embedded layer structure. , It extends from the other portion 255 of the epitaxial layer to the isolated region 254 of the epitaxial layer. The field oxide layers 256, 257, and 258 are arranged on the upper surface of the epitaxial layer. In FIG. 25, the field oxide layer forms two parts. The portions 256 and 258 extend around the outer boundary portion of the P sinker regions 252 and 253 to define the active area 258 and the portion 257 within the active area 258. The N-type field injection regions 259 and 261 are arranged below the field oxide layer portions 256 and 258, in which the field oxide layer portions 256 and 258 form an upper layer of the N-type silicon of the epitaxial layer. Similarly, the N-type field injection region 260 is located below the field oxide layer portion 257, where the field oxide layer portion 257 forms an upper layer of N-type silicon in the insulated region 254 in the active area.

【0088】

The N + type embedded layer 262 similar to the embedded layer region 21C and the N + sinker region 263 similar to the sinker region 61C are arranged in the insulating region 254. The N + drain contact region 264 is located in the upper surface of the insulating region 254 above the N + sinker region 263, and the lightly doped drain region 265 is also located in the upper surface of the insulating region 254 and is lightly doped. The drain region is arranged between the drift region 254A and the drain contact region 264. The P-type silicon body region 266 is arranged in the insulating region 254 and extends downward from the upper surface of the insulating region 254 into the insulating region 254. The N + source region 267 extends downward from the upper surface of the P body region 266 into the P body region 266, and the channel region 268 of the P body region 266 separates the source region 267 and the drift region 254A. Become a shape. At least a part of the body contact area 269 is also arranged inside the P body area 266, and the body contact area 269 extends downward from the upper surface of the body area 266 to the inside of the body area 266 to P +. The body contact area 269 is connected to the N + source area 269. In the embodiment shown in FIG. 25, the P + body contact region 269 extends from the P body region 269 to the P sinker region 253. Similarly, the P body region 266 is connected to the P sinker region 253.

【0089】

The thin gate oxide layer has portions 270, 272, and 271, which are located on the upper surface of the epitaxial layer in the active area 258. The gate oxide layer portions 270 and 272 are arranged on the upper surface of the P sinker regions 252 and 253. Part 271 is above the N + source region 267, above the channel region 268 of the P body region 266, above the drift region 254A, above the lightly doped drain region 265, and part of the drain contact region 264. It will be in the form of extending above. The polysilicon gate layer 273 is placed on the gate oxide layer portion 271 and the polysilicon gate layer 273 extends from a position above the N + source region 267 over the channel region 268 and over the drift region 254A. Then, it reaches a position above the thin N-doped drain region 265. The first portions 274 and 276 of a thick insulating layer of insulating material such as BPSG are above the field oxide layers 256 and 258, above the gate oxide portion above the sinker regions 252 and 253, and above the field oxide layer. Extends to. The second portion 275 of the insulating material extends over the polysilicon gate layer 273 and over the gate oxide layer portion 271. As a result, the two openings 277 and 278 are formed in the gate oxide layer and the thick oxide layer, the opening 277 is formed on the P + body contact area 269 and the N + source area 267, and the opening 278 is formed. , N + The shape is formed on the drain contact area 264.

【0090】

The source electrode 279, made of an electrically conductive material such as aluminum, extends over the thick insulating layer portion 276 and connects to the N + source region 267 and the P + source contact region 269 through the opening 277. Similarly, the drain electrode 280 of the electrically conductive material extends over the thick oxide layer portion 274 and connects to the N + drain contact region 267 through the opening 278. The gate electrode is connected to the polysilicon gate layer 273, but such a gate electrode is not present in the cross section of FIG.

【0091】

During operation, the lateral DMOS structure of FIG. 25 operates by controlling the current between the source region 267 and the drain contact region 264. The voltage applied to the polysilicon gate layer 273 causes the channel to form channel region 268 of P body region 266. The current then flows from the source electrode 279 to the drain electrode 280 through the N + source region 267, the channel in the channel region 268 of the P body region 266, the drift region 254, the lightly doped drain region 265, and the N + drain contact region 264. It flows. The current may flow from the drain electrode 280 to the source electrode 279 in the opposite direction. The N + embedding layer 262 extends substantially parallel to the lightly doped drain region 265 on the upper surface 281 and substantially parallel to the lower surface 282 on the drain contact region 264 in part in the lateral direction. Although it exists, the N-embedded layer 262 serves to reduce the resistance value between the source and drain when the transistor is turned on and operating. In the structure of FIG. 25, the P + body contact region 269 serves to electrically connect the source region 267 and the substrate layer 10 through the sinker region 253 and the embedded layer region 251. Therefore, in some examples, the source electrode 279 and the opening 277 may not be provided. In these embodiments, the voltage applied to the N + source region is substantially maintained at the voltage of the substrate layer.

【0092】

FIG. 26 is a cross-sectional view of a second embodiment of the lateral DMOS transistor structure. The structure of FIG. 26 is similar to that of FIG. 25, but the P + body contact region 269 does not extend outside the P body region 266 and does not connect to the sinker region 253. The P + body contact area 269 is not connected to the N + source area 267, but the P + body contact area 269 is completely contained inside the P body area 266. In some embodiments, the field oxide layer region 3000 is located on the upper surface of the insulating region 254 between the sinker region 253 and the P body region 266. The N-type field injection region 3010 is located below the field oxidation region 3000, and a layer of thick insulating material such as BPSG 3020 is located above the top surface of the field oxidation region 3000. Therefore, the source electrode 277 is not connected to the P substrate 10 through the P + body contact region 269, sinker region 253, and P embedded layer 251. Therefore, the substrate layer 10 and the source electrode 277 are maintained at different voltages. In some embodiments, sinker region 253 is provided as a means of access to the electrodes. In these examples, the substrate electrode 3030 extends over the BPSG layer 276 and is an opening in the BPSG layer between the field oxide layer portion 258 and the field oxide layer portion 3000, and the gate oxide layer. Through 3040, it connects to the upper surface of sinker region 253.

【0093】

The structures of FIGS. 25 and 26 are made, for example, by the BiCDMOS process described above. The sinker regions 252 and 253 are formed at the same time as the well regions 51B are formed, for example, as shown in FIG. 5, and the P embedded layer regions 250 and 251 are formed, for example, as shown in FIG. 4, the regions 44B. The N + embedded layer 262 is formed at the same time as the formation of the region 21C, for example, as shown in FIG. 4, and the N + region 263 is formed at the same time as the formation of the region 21C, for example, as shown in FIG. The field oxide layers 256, 257, and 258 are formed at the same time as the region 61C is formed, and the field oxide layers 10D / B, 10B, and 10B / C are formed, for example, as shown in FIG. Formed at the same time as the N-type field injection region 259, 260, And 261 are injected at the same time as the N-type field region is formed, for example, as shown in FIG. 8, and the polysilicon gate layer 273 is, for example, a polysilicon layer 100A, as shown in FIG. The P-body region 266, which was formed at the same time as the formation, was formed at the same time as the region 122 was formed, and the thin N-doped drain region 265 was formed, for example, as shown in FIG. As shown in FIG. 13, regions 154 are formed at the same time as regions 154 are formed, and N + regions 264 and 267 are formed at the same time as regions 155 are formed, for example, as shown in FIG. 14, and P + body contacts. The region 269 is formed at the same time as the region 162 is formed, for example, as shown in FIG. The N-channel lateral DMOS transistor structure is shown in FIGS. 25 and 26, but the P-channel lateral DMOS transistor structure is made by replacing the P-type structure with an N-type structure and vice versa for the N-type structure. ..

【0094】

Additional structures formed using the general method described above are shown in FIGS. 27-35.

【0095】

FIG. 27 is a cross-sectional view of a part of the wafer, showing the structures of the lateral DMOS transistor 300, the vertical DMOS transistor 302, and the vertical NPN transistor 304. The structure of FIG. 27 is intended to show the difference between the P-body region 308 for DMOS 300 and 302 and the P-base injection region 310 for NPN transistors 304. In a preferred embodiment of FIG. 27, the injection of P-body region 308 is self-aligned with gates 312 and 314. Boron ions are 1 cm at an energy of 60 KeV as described above to form the P-body region 308.²0.5 ~ 1.5 * 10 per¹⁴Doze is injected.

【0096】

After these boron dopants have been diffused to form the P-body region 308 with the desired physical and electrical properties, an epitaxial layer is used using a masking and doping process as described above with respect to FIG. 14B. The surface of 42 is exposed and doped to form the P-base 310. For high frequency NPN transistors (eg 100MHz ~ 3GHz), the P-base 310 should be shallower and less resistant than the P-body region 308. In one of the examples, the depth of the junction of the P-body region 308 is approximately 1.5-2 μm. The first injection of boron ions to form the P-base 310, with an energy of approximately 100-150 KeV, 1 cm²5 ~ 9 * 10 per¹²Doze. The second injection of boron ions causes the surface of the P-base 310 to be doped. In this second injection, the boron ion has an energy of approximately 40 KeV, 1 cm.²0.5 ~ 5 * 10 per¹⁴Doze is injected. As a result, surface doping is shown as P + base 318.

【0097】

In a preferred embodiment, the injection parameters and heat diffusion cycle for the P-body region 308 are incompatible with those of the two injections for the P-base 310. A low threshold by integrally integrating a two-step process for forming P-bases 310 and 318, which follows (and is virtually independent of) the process for forming P-body region 308. It can be a process of forming voltage-bearing DMOS transistors 300 and 302 with high-performance NPN transistors.

【0098】

The P + base contact area 320 and the P + body contact area 322 are then, for example, 1 cm at an energy of 60 KeV, as described with respect to FIG.²Approximately 3 * 10¹⁵Formed by injection of dose, it provides the desired ohmic contact between the aluminum metal layer, the P-base 310, and the body region 308.

【0099】

The various oxidation regions, source regions, drain regions, emitters, connectors, sinkers, embedded layers, and gates shown in FIG. 27 are formed using the relevant processes described above. High-frequency NPN transistors 304 and bipolar high-speed DMOS transistors 300 and 302 are suitable for use in power supply switching, but here, low-on-resistance DMOS transistors are suitable for use as power switches, and NPN transistors are compared. It is suitable for use in transistors and error amplifiers. In a high-performance switching power supply, the uniform gain frequency of the NPN transistor 304 is on the order of 3 GHz by selecting the appropriate P-base 310 characteristics.

【0100】

The same idea as described for FIG. 27 is also used to form P-channel DMOS transistors (with N-body) and PNP vertical transistors on the same substrate, where the N-body region and N- are used. The base region is optimized separately to obtain the desired performance of each transistor.

【0101】

FIG. 28 is a cross-sectional view of a portion of the wafer integrated with the vertical PNP transistor 330, showing a novel isolation technique that significantly reduces the operation of the parasitic bipolar transistor. The N-base region 332, N + base contact 334, P + emitter 336, P + collector 338, N embedding layer 340, P embedding layer 342, and P-well 344 have been described above with respect to FIGS. 16B, 19 and 21. , Formed using these techniques. In the embodiment of FIG. 28, a heavily doped sinker 346 is formed to extend downward towards the P-embedded layer 342 and is of a parasitic NPN transistor (based on the P-well 344). The gain is very small and the collector resistance is reduced. The P + sinker 346 surrounds the PNP transistor 330. This step, which is used to form the P + sinker 346, is also used to form Zener diodes elsewhere on the wafer. Due to the large amount of time required for diffusion, these P + sinkers 346 should be formed at a relatively early stage of the wafer manufacturing process, eg, before or immediately after the N-doping injection of FIG.

【0102】

Further, in order to reduce the effect of the parasitic PNP transistor (having the N-epitaxial layer 42 as a base), the N + sinker 348 is formed so as to extend from the surface of the wafer to the N embedded layer 340. Such N + sinker 348 is formed using the process described above with respect to FIG. N + sinker 348 surrounds P-well 344. The N-sinker 348 also helps remove the electrons injected into the P-well 344 when the transistor is operating in saturation. This increases the switching speed of the PNP transistor 330. The N-sinker 348 also helps to suppress the operation of the parasitic PNP transistor when electrons are injected into the P-well 344 and the N-epitaxial layer 42 if a forward bias is applied to the junction.

【0103】

An insulated N-epitaxial tub is obtained by extending the P + sinker 350 from the wafer surface towards the P-type substrate 10, which surrounds the PNP transistor 330.

【0104】

The PNP transistor 330 structure of FIG. 28 can also be formed as an NPN transistor by reversing the conductive form in various regions.

【0105】

The structure of FIG. 28 is formed on a wafer having the structure shown in FIGS. 16 to 27. The PNP transistor 330 is formed in place of or with the NPN transistor 304 of FIG. 27.

【0106】

In the preferred embodiment of FIG. 28, the N-base region 332 is formed before forming the P-body region 304 (FIG. 27) or the P-base region 310 (FIG. 27), which is P-. This is because an elongated N-type base can be formed by slow diffusion of arsenic or antimony dopants, even when in the diffusion step used to form the body region 308 and P-base 310.

【0107】

FIG. 29 is a cross-sectional view of a portion of the wafer, which adjusts the threshold voltage of the MIMO transistor 353, which can be used to form the doped base and body regions on the same wafer. It shows a method of adjusting without being affected by the heating and diffusion steps. It is conventional practice to adjust the threshold voltage of the MOSFET by injecting a dopant into the channel region before forming the gate. However, these dopants become diffused during the next drive-in step used to form the base region, body region, or other region that is doped after the formation of the gate. Therefore, in the conventional threshold voltage adjustment method, the ultimate threshold adjustment cannot be controlled.

【0108】

In FIG. 29A, the polysilicon gate 351 is formed on the gate oxide layer 357 using conventional techniques. The field oxide layer portion 355 is then grown using prior art. As shown in FIG. 29B, a pattern of the photoresist layer 360 is provided to expose the gate 351 and the area surrounding the gate 351. Boron ions are then injected using prior art to form a heavily doped self-aligned source region 352 and drain region 354. Boron ions are, for example, 1 cm at an energy of 20-60 KeV.²Approximately 3 * 10¹⁵Doze is injected. The injection energy should be low enough that boron ions do not penetrate the polysilicon gate 351. This boron ion implantation to form the shallow source region 352 and drain region 354, in preferred embodiments, is performed after the implantation and diffusion steps to form the body or base region of the DMOS and bipolar transistor. Will be done.

【0109】

Preferably, immediately before or immediately after this boron doping step, high energy injection at an energy of approximately 80-200 KeV (energy value depends on the gate oxide layer and gate thickness) is performed in the channel regions of FIGS. 29A and 29C. The desired amount of boron ions is injected into the surface portion of 360. Figure 29C shows this high energy injection process. The injection volume in this step is 1 cm to shift the threshold by the desired magnitude in order to lower the threshold of the MIMO transistor 353.²2 ~ 3 * 10 per¹²Should be an amount of. Even if boron ions are injected through the source 352 and drain 354 by high energy injection, the small amount of doping does not significantly affect the electrical properties of the source region 352 or drain region 353.

【0110】

Since this high energy injection can be performed at any time after the gate 351 is formed, the dopant drive-in step of forming the self-aligned body region or base region can be performed in advance of this high energy injection. Therefore, the drive-in step performed before this does not affect the adjustment of the threshold value of the MIMO transistor 353.

【0111】

Since the amount of doping should be low in this high energy injection, it is not necessary to use additional masking steps to mask the P or N-type regions of other transistors from the boron injection. Preferably, this small amount of boron injection does not significantly affect the properties of these other regions. Therefore, this threshold voltage adjustment step is performed without an additional mask step, without adversely affecting the characteristics of the DMOS, PNP, or NPN transistor formed on the same wafer as the MIMO transistor 353. No special diffusion step is required for the diffusion of the ions injected under the gate 351, but this is due to the heating step used to complete the subsequent wafer production of the ions under the gate 351. This is because sufficient diffusion is performed.

【0112】

The N + body contact region 356, the N embedding layer 340, and the P + sinker 350 are formed as described above. This threshold adjustment method can also be used to adjust the threshold of an NMOS transistor by injecting arsenic or antimony ions through the gate.

【0113】

FIG. 30 shows a method and structure for manufacturing a high-performance 5-volt PMOS transistor and a high-performance 12-15 volt PMOS transistor in a form that minimizes the difference between these two devices. .. Each element of FIG. 30A, shown with the same reference numerals as these elements in FIG. 29A, is formed using the method described above. N-field doped regions 361 and 362 are formed using the process described above with respect to FIG. The channel length L separates the source 352 and drain 354 so that device breakdown does not occur when operating at a planned operating voltage of, for example, 5-8 volts or 12-15 volts. Must be sufficient for.

【0114】

FIG. 30B is a graph in which the channel length is on the horizontal axis and the breakdown voltage is on the vertical axis, assuming doping of a typical N epitaxial layer 42. At a length of about 2.5 μm, the graph does not show a significant relationship between channel length and breakdown voltage. Here, it is assumed that the breakdown voltage is not limited by the breakdown of the diode D1 formed between the source 352 and the N-epitaxial layer 42 or between the drain 354 and the N-epitaxial layer 42. ing. Further, it is assumed that the gate oxide layer formed between the gate 351 and the N-epitaxial layer 42 has a sufficient thickness (for example, 400 Å) to withstand the operating voltage.

【0115】

In conventional devices, the gate length L has been set to be the minimum required to maintain an operating voltage and provide a low threshold and low on-resistance MIMO or MIMO transistor. By minimizing the gate length L, the manufacturing yield is reduced due to process changes that sometimes cause the MOSFET breakdown voltage to be smaller than the minimum required. However, by using the technique shown in FIG. 29, the threshold voltage (or indirectly the on-resistance) of the MIMO transistor shown in FIG. 30A is determined independently of the gate length L. It will be. Therefore, the channel length of the MIMO transistor is made on the order of approximately 2.5 μm, and a breakdown voltage of 15 volts (minimum value) is secured without fear of causing typical process changes, while FIGS. 29A-C. The desired threshold voltage (and reduced on-resistance) can also be obtained by using the method shown in.

【0116】

For a 5 volt PMOS device, the channel length of the preferred embodiment is approximately 2 μm. The length of this channel leaves room for changes in the manufacturing process and makes the final threshold voltage of the PCOS transistor independent for high energy boron injection. In one of the examples, the threshold voltage of the 2.0 μm and 2.5 μm transistors is approximately 0.8 volts.

【0117】

In a preferred embodiment, the injection for threshold adjustment shown in FIG. 29C is the same for both the 5-volt and 12-volt MIMO devices, and both devices perform the same threshold adjustment. Even so, the slightly elongated channel length of the 5-volt PMOS device improves its on-resistance by approximately 30-40% compared to the on-resistance of the 12-volt device. This method of obtaining a higher break voltage with little effect on the threshold voltage or on-resistance is a conventional technique using a deeper junction to increase the break down voltage or an extension of a lightly doped drain. It replaces. Therefore, a low threshold voltage 12 volt PMOS transistor and a low threshold voltage 5 volt PMOS transistor are both formed using the same process steps.

【0118】

FIG. 31 is a cross-sectional view of a portion of the wafer containing the densely doped P + Zener region 370 and the Zener diode formed by the N-epitaxial layer 42. The structure of FIG. 31 also shows that the P + Zener region 370 is used as the bottom plate of the capacitor 372. The P + Zener region 370 is formed using the same steps used to form the P + embedded Zener anode region 71F shown in FIG. 7A. P + Zener region 370 is 1 cm with an energy of approximately 80 KeV²Approximately 0.5 ~ 3 * 10¹⁵Formed by injection of dose boron ions. Next, as described above for FIG. 7A, the boron ions are driven in to provide a breakdown voltage at the Zener PN junction of approximately 6-9 volts. The P + contact region 374 is then formed in the P + Zener region 370 using the same injection steps used to form the P-type emitter region, eg, emitter 168 in FIG. 16B. The N + contact region 376 is then formed to form a connection with the N-epitaxial layer 42, which in this case functions as the cathode of the Zener diode. The N + contact region 376 is formed during the same injection steps used to form the N-type emitter region, such as the emitter 170 shown in FIG. 15B. The metal electrode 377 is connected to the N + contact area 376. Zener diodes exhibit the desired reverse breakdown voltage used by well known methods.

【0119】

The formation of the capacitor structure of FIG. 31 will be described in more detail here. Capacitor 372 includes P-board 10, N-embedded layer 378, N-epitaxial layer 42, deep P + Zener region 370, gate oxide layer 380, field oxide layer 382, electrically conductive polysilicon layer 384, oxide layer 385, P + contacts. Includes area 374, upper plate connector 386, and lower plate connector 388. The N-embedded layer 378 is formed at the same time as the embedded layers 21a to 21c are formed (FIGS. 3A, 3B, 4A, 4B). The deep P + Zener injection described above with respect to FIG. 7 is used to form the P + Zener region 370. The P + injection described above for FIG. 16 is used to form the P + contact region 374. The P + Zener region 370 is used as the bottom plate of the MOS capacitor 372. The polysilicon layer 384 (adhered and formed in FIG. 11) forms the top plate of the MOS capacitor 372. FIG. 8 The polysilicon layer 384 is separated from the deep Zener region 370 by the gate oxide layer 381 formed in the epitaxial surface oxidation step described above.

【0120】

Since the gate oxidation region 380 is formed on the deep P + Zener region 370, enhanced oxidation (which usually occurs when the oxide layer is grown in the heavily doped N region) does not occur. Oxidative growth on the heavily doped N region is generally 60% thicker than on the deep P + Zener region 370 given the same oxidation cycle. The slow oxidation of the deep P + Zener region 370 produces a thinner oxide layer 380, which results in an increase in the capacitance of the MOS capacitor 372 in the given fixed capacitor region. In one example, the gate oxide layer 380 has a thickness of approximately 400 Å between the P + Zener region 370 and the polysilicon layer 384.

【0121】

Capacitors that use even properly densely doped silicon regions as plates have a high voltage coefficient due to changes in the depth of the airborne region provided in the diffused plate. Therefore, when a lightly or moderately doped silicon layer is used as a plate for a MOS capacitor, the capacitance in each unit region will vary depending on the voltage applied to each capacitor. Due to this characteristic, it is very difficult to use such MOS capacitors in analog circuits.

【0122】

Since the deep P + Zener region 370 is very heavily doped, the voltage coefficient of the capacitor 372 using the deep P + Zener region 370 as the bottom plate is very small. Therefore, the voltage applied to the terminals 386 and 388 of the MOS capacitor 372 drops almost at the thickness portion of the gate oxide layer 380. Therefore, the MOS capacitor 372 has a high capacitance per unit area, and this capacitance is relatively unlikely to change with respect to the voltage applied to the capacitor 372.

【0123】

The safe electric field that can be applied through the gate oxide layer 380 is limited to approximately 4 megavolts per cm for silicon dioxide. Therefore, when the gate oxide layer 372 is silicon dioxide having a thickness of 400 Å, the formed MOS capacitor 372 has a withstand voltage of approximately 16 volts. Therefore, the rated voltage of the MOS capacitor 372 is equal to the rated voltage of the gate oxide layer of the MOSFET provided on the same substrate as the capacitor 372. These MOSFETs include the MOSFETs shown in FIG. For these reasons, the MOS capacitor 372 is a useful element in analog circuits integrated with other MOSFETs formed on the same substrate. MOS capacitors 372 can be used in charge pumps and other circuits required in power integrated circuits.

【0124】

In a preferred embodiment, the P + Zener injection used to form the Zener region 370 is also used to dope more heavily in the P + sinker regions such as sinkers 350 and 252 in FIGS. 29A, 25, and 26. Be done. This reduces the parasitic NPN effect between two adjacent N-epitaxial tabs.

【0125】

32, 33, 34, and 35 relate to methods and structures for improving the breakdown voltage of NPN or PNP transistors. This method of improving the breakdown voltage is used with respect to FIGS. 1-16 without using the additional process steps described above.

【0126】

Referring to FIG. 16B, the P + base contact region 169 of the NPN transistor is located relatively close to the N-type field dopant (formed as shown in FIG. 8B) under the field oxide layer 100B / C shown in FIG. 14B. Is located in. This N-type field dopant region is shown as region 400 in FIG. Since the P + base contact region 169 is provided close to the N-type field dopant region shown in FIG. 16B, the electric field between the two regions is increased, and therefore the breakdown that occurs between the two regions is likely to occur. Become. Therefore, this causes BV_CESIt tends to lower (ie, the breakdown voltage between the collector and the emitter if the base is shorted to the emitter). As shown in FIG. 32, the annular P + base contact region 402 is located at a greater distance L from the N-type field dopant region 400.₁By taking and forming, the previous structure is improved. The breakdown voltage between the base contact region 402 and the collector 404 (or the N sinker 406 connected to the collector), or the breakdown voltage between the base contact region 402 and the field doping region 400, is the operating voltage. Distance L so that it is greater than the voltage at the predetermined distance required to avoid breakdown₁Is secured. In the structure of FIG. 32, the field doping region 400 is sufficient to extend the depletion region between the P + base contact region 402 and the N sinker 406 or collector 404 without causing a breakdown in operating voltage. Length L₂Is formed to have. Distance L₁And L₂By the combination of, a high voltage bipolar transistor is generated without adversely affecting the operation.

【0127】

FIG. 33 is a modification of the configuration of FIG. 32, where the N-field doping region 400 is replaced by an N-drift region 410 (formed as shown in FIG. 13A). N-drift injections are also used to form thinly doped drain regions in high voltage NMOS transistors. Those skilled in the art will appreciate how to form the drift region 410 of FIG. 33 by using the N-blanket injection shown in FIG. Length L of field dopant region 400 or N-drift region 410 in the devices of FIGS. 32 and 33₂Can be varied to obtain the desired breakdown voltage without significantly affecting the operation of the NPN transistor. Distance L of 1-2 μm₁Or L₂The breakdown voltage can be increased by 16 to 20 volts or more.

【0128】

The structures of FIGS. 32 and 33 are perfectly compatible with the processes described above with respect to FIGS. 1-16 and are formed without the addition of additional masks or process steps. Therefore, these structures are formed with the various MOSFETs and bipolar transistors described above.

【0129】

The PNP transistor structures of FIGS. 34 and 35 are shown to have the same principles as described for FIGS. 32 and 33, respectively. In FIG. 34, the N + base contact region 412 of the PNP transistor is selected distance L from the P field doping region 414 (formed in the step shown in FIG. 9).₁It is provided so as to increase the breakdown voltage. Distance L₂Is selected to obtain the desired breakdown voltage between the N + base contact region 412 and the P + collector 416 or P + sinker 418.

【0130】

In FIG. 35, the N-drift injection mentioned with respect to the N-drift region 410 collects the N + base region 412 in order to extend the N-base region 420 of the PNP transistor and further increase the breakdown voltage. Used to separate from 416 and field doping region 414. The structures of FIGS. 34 and 35 are formed together with the other structures described with respect to FIGS. 1-16 and the remaining structures described herein. By increasing the breakdown voltage of the device using the structures shown in FIGS. 32 to 35, a device that previously had a rated breakdown voltage of 16 volts can be 20 volts without significantly compromising the performance characteristics of the device. It can be increased to the above rated breakdown voltage.

【0131】

Note that the P-field doping region 414 is heavily doped than the N-field doping region 400 shown in FIG. Therefore, in the devices of FIGS. 33 and 35, there is almost no voltage drop absorbed by the P-field doping region 414.

【0132】

The breakdown voltage of the transistors in Figures 33 and 35 can easily be equal to the breakdown voltage of the 16 volt NMOS transistors in Section E shown in Figure 16A, which means that these devices all have the same N-drift injection. Because of the use, this N-drift injection can be formed to the same length. For example, the N-drift region for various transistors has a length of 2-3 μm to obtain a breakdown voltage in excess of 12 volts.

【0133】

Although the present invention has described examples of the BiCDMOS process and the various structures described above, the invention is not limited to these examples. The above N-type silicon region can be made into a P-type silicon region, and the P-type silicon region can be made into a reverse conductive type as well. Moreover, the type of particular manufacturing process equipment is not important in performing the above processes or in manufacturing the disclosed structures. The range of parameters on the various processes is shown above. Various steps within the process steps can be omitted or combined with other semiconductor process steps without departing from the spirit and scope of the invention. Therefore, other examples not described in the present specification, modifications of the examples described in the specification, may be included in the scope of the present invention described in the claims.

【0134】

[Effect of the invention]

Therefore, the present invention provides a process-based integrated circuit forming method that allows a DMOS power circuit, a CMOS digital logic circuit, and a supplementary bipolar analog circuit to be integrated into a single circuit chip.

[Simple explanation of drawings]

[Figure 1]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the first stage of this process is shown. ing.

[Figure 2]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the second stage of this process is shown. ing.

[Fig. 3]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the third stage of this process is shown. ing.

[Fig. 4]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the fourth stage of this process is shown. ing.

[Fig. 5]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the fifth stage of this process is shown. ing.

[Fig. 6]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the sixth stage of this process is shown. ing.

[Fig. 7]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the seventh stage of this process is shown. ing.

[Fig. 8]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the eighth stage of this process is shown. ing.

[Fig. 9]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the ninth stage of this process is shown. ing.

[Fig. 10]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the tenth stage of this process is shown. ing.

[Fig. 11]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the eleventh stage of this process is shown. ing.

[Fig. 12]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the twelfth stage of this process is shown. ing.

[Fig. 13]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the thirteenth stage of this process is shown. ing.

[Fig. 14]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the 14th stage of this process is shown. ing.

[Fig. 15]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the fifteenth stage of this process is shown. ing.

[Fig. 16]

There is a cross-sectional view of a part of the wafer consisting of A and B, each processed according to one of the examples of the BiCDMOS process based on the present invention, and the cross-sectional view of the wafer in the 16th stage of this process is shown. ing.

[Fig. 17]

It is sectional drawing of 1 Example of the thin film resistor structure based on this invention.

[Fig. 18]

It is sectional drawing of 1 Example of the isolation structure based on this invention.

[Fig. 19]

It is sectional drawing of 1 Example of the 1st vertical bipolar transistor structure based on this invention.

[Fig. 20]

It is sectional drawing of 1 Example of the 2nd vertical bipolar transistor structure based on this invention.

[Fig. 21]

It is sectional drawing of 1 Example of the 3rd vertical bipolar transistor structure based on this invention.

[Fig. 22]

It is sectional drawing of 1 Example of the 1st lateral DMOS structure based on this invention.

[Fig. 23]

It is sectional drawing of 1 Example of the 2nd lateral DMOS structure based on this invention.

[Fig. 24]

It is sectional drawing of 1 Example of the 3rd lateral DMOS structure based on this invention.

[Fig. 25]

It is sectional drawing of 1 Example of the 4th lateral DMOS structure based on this invention.

[Fig. 26]

It is sectional drawing of 1 Example of the 5th lateral DMOS structure based on this invention.

[Fig. 27]

It is sectional drawing of the wafer which formed the base of a bipolar transistor and the body of a DMOS transistor, and shows the place where the body and the base are formed independently of each other.

[Fig. 28]

It is sectional drawing of the wafer which formed the improved isolation structure which remarkably reduces the operation of a parasitic bipolar transistor.

[Fig. 29]

It is a cross-sectional view of a wafer consisting of A, B, and C, each showing a structure, and shows a method for adjusting the threshold voltage of a MOSFET performed at a relatively late stage of the wafer manufacturing process.

[Fig. 30]

Consisting of A and B, A is a cross-sectional view of the MOSFET showing how the gate length is adjusted to obtain the desired breakdown voltage of the MOSFET. B is a graph in which the channel length is taken on the horizontal axis and the breakdown voltage is taken on the vertical axis, and the concentration of a typical epitaxial layer dopant is processed.

[Fig. 31]

It is a cross-sectional view of a Zener diode and a capacitor, and shows that the Zener region is used as the bottom plate of the capacitor.

[Fig. 32]

It is a cross-sectional view of an NPN transistor showing that the base contact region is separated from the collector in order to increase the breakdown voltage.

[Fig. 33]

It is a cross-sectional view of an NPN transistor showing that the base contact region is separated from the collector in order to increase the breakdown voltage.

[Fig. 34]

It is a cross-sectional view of a PNP transistor, and shows the place where the base contact region is separated from a collector in order to increase the breakdown voltage.

[Fig. 35]

It is a cross-sectional view of a PNP transistor, and shows the place where the base contact region is separated from a collector in order to increase the breakdown voltage.

[Explanation of symbols]

10 board 10A DMOS region 10B PNP bipolar region 10C Vertical NPN Bipolar Region 10D low voltage MIMO region 10E high voltage MIMO region 10F embedded Zener area 10G high voltage EMCOS region 10H low voltage EMCOS region 11 Upper surface of the board 12 First oxide layer 12A, 12B, 12C openings 21A, 21B, 21C embedded layer area 22A, 20, 22B, 22C Thin oxide layer 30 photoresist layer 30B, 30D opening 40 Epitaxy reoxidized layer 41 Upper surface of epitaxial layer 42 epitaxial layer 43B, 44B P + area 43D P + embedded layer area 51B, 51D, 51E P-well area 52B, 52D, 52E openings 60A, 60C opening 61A, 61C N + sinker area 70B, 70F opening 71B Vertical PNP area 71F Embedded Zener region 80 base oxide layer 81 Nitride layer 82 Low Temperature Oxidation (LTO) Layer 83A ~ 83H Active area Mask area 91B, 91D, 91E openings 100F / A, 100A / E, 100E / G field oxide layer 100G / H, 100H / D, 100D / B field oxide layer 100B, 100B / C field oxide layer 101 photoresist layer 102B opening 110A, 110D, 110E, 110G, 110H polysilicon gates 120 photoresist layer 121A, 121F opening 122 P-body area 141C, 141G opening 142C P-base area 142G drain area 150 photoresist layer 151A1, 151A2, 151B, 151C1 openings 151C2, 151D, 151E1, 151E2, 151F openings 152 N + source area 153 Source area 154 Drain area 155 Drain contact area 156 channel area 157 Source area 158 Drain area 159 Base contact area 1700 Emitter region 160 photoresist layer 161A1, 161A2, 161A2, 161B openings 161B2, 161C, 161G1, 161G2, 161H openings 162 P + body contact area 163 Source area 164 Drain contact area 166 Source area 167 drain area 168 Emitter region 169 Base contact area 170 BPS G layer 171 Si-Cr region 172A, 172B Pi-W layer 173A, 173B Aluminum interconnect 180 active area 181B, 181B / C, 181D / BP type field injection area 182D / C, 182D / BN type field injection area 190N + embedded layer area 191 Boundary between substrate and epitaxial layer 192 N + sinker area 193, 194 Field oxide layer 195 field area 196 Active area 197, 198 N field injection area 199 P-base area 200, 201 gate oxide layer 202 Emitter contact opening 204 Collector contact opening 205 polysilicon layer 206, 207 Side wall 208 N + emitter area 209 Base contact area 210 base electrode 211 Collector electrode 212 Emitter electrode 213, 214 Insulation layer 215, 216 field oxide layer 217, 218 P field injection area 219, 220 field oxide layer 221 Emitter opening 222 N-Base area 223 P + emitter area 224, 225 N-type injection area 226 N + base contact area 227 Field oxide layer opening 228 P + collector contact area 230 P-well area 231, 232, 233 Field oxide layer part 234 Active area 235, 236 P-type field injection area 237, 238 N-type field injection area 239 Body area 240 drain contact area 241 Drift area part 242 Drain injection area 243 Source area 244 Source contact area 245 Gate oxide layer 246, 247 openings 248 polysilicon gate 249 Insulation layer 2500 source electrode 2510 Drain electrode 2520 channel area 250, 251 P-type embedded layer 252, 253 sinker area 254 Insulated area 255 epitaxial layer 256, 257, 258 field oxide layer 260 N-type field injection area 262 N + embedded layer 263 N + sinker area 264 N + drain contact area 265 drain area 266 P-type silicon body area 267 N + source area 268 channel area 269 Body contact area 270, 271, 272 Thin gate oxide layer 273 polysilicon gate layer 274, 276 First part of thick insulating layer 275 Second part of insulation layer 277, 278 openings 279 Source electrode 280 drain electrode 281 N + Upper surface of embedded layer 282 Lower surface of drain contact area 3000 field oxide layer 3010 Type N field injection area 3020 Insulation layer 3030 Substrate electrode 3040 opening 300 Lateral DMOS Transistor 302 Vertical DMOS Transistor 304 Vertical NPN Transistor 308 P-body area 310, 318 P-base 312, 314 gates 320 P + base contact area 322 P + body contact area 330 Vertical PNP Transistor 332 N-Base area 334 N + base contact area 336 P + emitter area 338 P + collector area 340 N type embedded layer 342 P-type embedded layer 344 P-well 346 P + sinker 348 N + sinker 350 P + sinker 351 polysilicon gate 352 Source area 353 epitaxial transistor 354 drain area 355 Field Oxidized Layer 356 N + body contact area 357 Gate oxide layer 360 channel area 361, 362 N field doped area 370 P + Zener region 372 Capacitor 374 P + contact area 376 N + contact area 378 N-type embedded layer 380 Gate oxide layer 382 Field Oxidized Layer 384 polysilicon layer 385 Oxidized layer 386 Top plate connector 388 Lower plate connector 400 N-field dopant region 402 Base contact area 404 collector 406 N sinker 408 P-base 410 N-drift area 412 N + base contact area 414 Field Doping Area 416 collector 418 P + sinker