Phase synchronization circuit having a short pull-in time and a low jitter.

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a phase-locked loop.

【0002】

[Conventional technology]

Generally, there are various proposals for a phase-locked loop, but a method of changing the constant of a loop filter by a synchronization determination circuit in order to realize high-speed pull-in and low jitter in a circuit in which the frequency of an input signal is multiplied and output. Is used (for example, JP-A-2-211718 and JP-A-2-211718).

【0003】

In such a conventional example, as shown in FIG. 6, a phase comparator 1, a synchronization determination circuit 2, and a discharge type constant current source 7 (current value: I) are used.₁) And suction type constant current source 10 (current value: I)₂), A charge pump circuit 3 including a MOSFET transistor 8, an NMOS transistor 9 and an inverter 35, a loop filter 11 including a resistor 12 and a capacitance 13, a voltage controlled oscillator 14, and a frequency divider 16.

【0004】

In FIG. 6, as the phase comparator 1, the circuit shown in FIG. 3 is well known, and is composed of NAND circuits 21, 22, 23, 24, 25, 26, 27, 28 and 29. In FIG. 3, the output UP and output DOWN are usually in the high level state corresponding to the input R by the predetermined input signal and the input V of the frequency divider signal output from the frequency divider 16, and the input R stands. If the fall is ahead of the fall of the input V, the output UP will be at the low level for that period, and conversely, if the fall of the input R is behind the fall of the input V, the output will be output. DOWN is at the low level for that period. The loop filter 11 is a circuit that removes noise generated in the phase comparator 1, and a low frequency filter is usually used. The voltage controlled oscillator 14 is an oscillator whose oscillation frequency is controlled by the output voltage of the loop filter 11 and outputs an oscillation signal having a frequency corresponding to the output voltage, and the frequency divider 16 determines the oscillation frequency of the voltage controlled oscillator 14. A synchronous counter is often used in a circuit that divides the frequency and outputs it to the phase comparator 1. Further, the synchronization determination circuit 2 is well known as the circuit shown in FIG. 2, and is composed of a NAND circuit 17, a resistor 18, a capacitance 19 and an inverter 20, and the output of the phase comparator 1 in FIG. 6 is increased or decreased. If is output at a low level for a long time, it is determined that the phase-locked loop is out of synchronization.

【0005】

Next, the operation of the phase-locked loop will be described. In FIG. 8, when the falling edge of the input R of the phase comparator 1 is ahead of the falling edge of the input V of the phase comparator 1, the output UP of the phase comparator 1 becomes a low level, and the output DOWN becomes a high level. The transistor 8 is turned on and the MEMS transistor 10 is turned off. As a result, the capacitance 13 is charged via the constant current source 7 and the MIMO transistor 8, and the potential V at the node B is charged._BIncreases, and the oscillation frequency of the voltage controlled oscillator 14 increases. On the contrary, when the falling edge of the input R of the phase comparator 1 is ahead of the falling edge of the input V of the phase comparator 1, the output UP of the phase comparator 1 becomes a high level, and the output DOWN becomes a low level. 8 is off and the NMOS transistor 10 is on. As a result, the electric charge of the capacitance 13 is discharged through the constant current source 10 and the NMOS transistor 9, and the potential V of the node B is discharged._BDecreases, and the oscillation frequency of the voltage controlled oscillator 14 becomes low. In this case, if the output UP or output DOWN of the phase comparator 1 is in the low level state for a long time, the synchronization determination circuit 2 determines that the phase synchronization circuit is not synchronized. The current values of the constant current source 7 and the constant current source 10 are increased via the control signal output from the synchronization determination circuit 2, so that synchronization can be achieved quickly. Then, when the phase-locked loop is in the synchronous state and the time during which the output UP or output DOWN of the phase comparator 1 is in the low level state becomes short, or when the phase synchronous circuit is always in the high level state, the synchronization determination circuit 2 The current values of the constant current source 7 and the constant current source 10 are reduced via the control signal output from the device, whereby low jitter control in the phase-locked loop is performed.

【0006】

The constant current source 7 and the constant current source 10 are set so that the current values are equal in order to make the phase adjustment amounts equal. In this case, equal current values are I (I)₁= I₂= I) and set the capacity value of capacity 13 to C₁₃, The natural angular frequency of the phase-locked loop is ω_n, The braking coefficient is ζ, the gain of the voltage controlled oscillator 14 is K, the frequency division ratio of the divider 16 is N, and the resistance value of the resistor 12 of the loop filter 11 is R.₁₂If you, satisfied the following formula one.

【0007】

I = ω_n² N C₁₃/ K .......................... (1) R = 2ζ / (ω_n C₁₃) .......................... (2) Further, the input voltage V of the voltage controlled oscillator 14_INIs the voltage V generated corresponding to the charge charged in the capacitance 13 for the time required for the current value I to be detected in the phase comparator 1._BIt is itself. This input voltage V_INThe oscillation frequency f of the voltage controlled oscillator 14 corresponding to is given by the following equation.

【0008】

f = V_IN K ...................................................... (3) Using the above equations (1), (2) and (3), N = 512 (input frequency 8KHz, output frequency 4.096MHz), C₁₃= 60pF, K = 2.0MHz / V, R = 25MΩ, constant current source current value I = 40nA in synchronous state, constant current source current value I = 400nA, ω in asynchronous state_nWhen the time change of the oscillation frequency f of the voltage controlled oscillator 14 is calculated under the conditions of = 2π × 256 rad / s and ζ = 1.2, the characteristic 20 in FIG. 9 is obtained, and the time t at which the oscillation frequency f becomes a constant value._rLet t be the pull-in time_r= 7ns.

【0009】

[Problems to be Solved by the Invention]

Conventionally, a phase-locked loop has been used for various purposes, but in a system that requires constant output at all times, such as when used for PCM CODEC, the output voltage of the loop filter 11 is used. V_BThe voltage level of is the voltage V shown in the voltage controlled oscillator characteristics of FIG. 4 in the synchronous state.₀Is held in a state equal to. However, in the conventional phase-locked loop, the charge / discharge operation corresponding to the capacitance 13 during synchronous pulling is performed only when the output UP or output DOWN of the phase comparator 2 is at a low level. Because of this, the voltage V_BLevel is the above V₀Even when there is a large voltage level difference with respect to the level of, when the output UP or output DOWN of the phase comparator 1 is at a high level, the charge / discharge corresponding to the capacitance 13 is not performed, and therefore the pull-in time for the phase synchronization is not performed. Has the disadvantage of becoming longer.

【0010】

[Means for solving problems]

The phase-locked loop of the present invention inputs the output of the digital phase-locked looper, the phase-locked loop that receives the output of the phase-locked looper, determines the phase-locked loop state, outputs a predetermined control signal, and outputs the predetermined control signal. Then, the charge pump circuit that outputs the phase difference signal via the control signal, the loop filter that outputs the phase difference signal of the charge pump circuit by limiting the frequency band, and the output voltage of the loop filter are used for frequency control. In a phase-locked loop including a voltage-controlled oscillator and a frequency divider that divides and outputs the oscillation frequency of the voltage-controlled oscillator and inputs feedback to the phase comparator, the charge pump circuit is the loop filter. The output voltage of is compared with a predetermined reference voltage, a comparator that outputs a predetermined level determination signal, the first output signal of the phase comparator, and the level determination signal are input to obtain a logical product. The first AND circuit to be output, the inverter that inverts and outputs the second output signal of the phase comparator, the output signal of the inverter, and the level determination signal are input and the logical product is taken. The output second AND circuit and the source are connected to the power supply via the first constant current source, the output signal of the first AND circuit is input to the gate, and the drain is on the input side of the loop filter. The connected PLLOS transistor and drain are connected to the input side of the loop filter, the output signal of the second AND circuit is input to the gate, and the source is connected to the ground point via the second constant current source. The OSPF transistor, the control signal whose current value is output from the synchronization determination circuit, the first constant current source whose current value is controlled by the level determination signal, and the current value are output from the synchronization determination circuit. It is characterized in that it is configured to include the second constant current source controlled by a control signal.

【0011】

Further, the phase-locked loop of the second invention includes a digital phase-locked loop, a synchronization determination circuit that receives the output of the phase-locked loop, determines the phase-locked state, and outputs a predetermined control signal, and the phase-locked loop. A charge pump circuit that inputs the output of the above and outputs a phase difference signal via the control signal, a loop filter that outputs the phase difference signal of the charge pump circuit with a frequency band limitation, and an output of the loop filter. In a phase-locked loop including a voltage-controlled oscillator whose frequency is controlled by a voltage and a frequency divider that divides and outputs the oscillation frequency of the voltage-controlled oscillator and inputs the feedback to the phase comparator, the charge pump circuit , A first comparator that compares the output voltage of the loop filter with a predetermined first reference voltage and outputs a first level determination signal, and an output voltage of the loop filter and a predetermined second reference voltage. The second comparator that outputs the second level determination signal, the first output signal of the phase comparator, and the first level determination signal are input to obtain a logical product. The first OR circuit that inputs the output AND circuit, the output signal of the AND circuit, and the second level determination signal and outputs them by logical summing, and the second output signal of the phase comparator. An inverter that inverts and outputs, a second OR circuit that inputs the output signal of the inverter and the second level determination signal and outputs them in a logical sum, and a constant current source whose source is the first. The output signal of the first OR circuit is input to the gate, the drain is connected to the input side of the loop filter, and the drain is connected to the input side of the loop filter. Then, the output signal of the second OR circuit is input to the gate, the source is connected to the ground point via the second constant current source, and the current value is output from the synchronization determination circuit. The first constant current source controlled by the control signal and the first level determination signal, and the current value are controlled by the control signal output from the synchronization determination circuit and the second level determination signal. With the second constant current source,It is characterized by being composed.

【0012】

[Example]

Next, the present invention will be described with reference to the drawings.

【0013】

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, the phase comparator 1, the synchronization determination circuit 2, the AND circuits 4 and 6, the inverter 5, the discharge type constant current source 7, and the suction type constant current source 10, It includes a charge pump circuit 3 including a facsimile transistor 8, an MIMO transistor 9 and a comparator 15, a loop filter 11 including a resistor 12 and a capacitance 13, a voltage controlled oscillator 14, and a frequency divider 16. As is clear from the comparison between FIGS. 1 and 6, the difference from the conventional example of this embodiment is the difference in the configuration of the charge pump circuit, which is one of the components of the phase-locked loop. That is, in the conventional example, the charge pump circuit is composed of constant current sources 7 and 10, a MOSFET transistor 8, an MIMO transistor 9, and an inverter 35, whereas in this embodiment, the charge pump circuit is charged. As described above, the pump circuit 3 includes NAND circuits 4 and 6, an inverter 5, constant current sources 7 and 10, a MOSFET transistor 8, an MIMO transistor 9, and a comparator 15.

【0014】

In FIG. 1, on the positive phase input side of the comparator 15, the potential V of the node B corresponding to the output end of the loop filter 11, that is, the input side of the voltage controlled oscillator 14_BThe level of is input, and the voltage V shown in FIG. 4 is input to the reverse phase input side of the comparator 15.₀Reference voltage V at a level lower than the level of₁Is entered. Now, the phase-locked loop is not in the phase-locked state, and the potential V at the node B_BThe level of the reference voltage V gradually decreases.₁When the level is lower than the level of, the output level of the comparator 15 becomes a low level, which is input to the AND circuits 4 and 6, and also controls the constant current source 7 so that the current value becomes a large current. Entered for. Therefore, the phase-locked loop is not in the synchronized state, and the potential V at node B_BLevel is the reference voltage V due to the discharge of capacity 13.₁In the state where the level is lower than the level of, the gate action of the AND circuits 4 and 6 cuts off the input path of the output UP and output DOWN of the phase comparator 1 to the MIMO transistor 8 and the MIMO transistor 9, and the low level signal is transmitted. , Are input to the gates of the POMS transistor 8 and the MIMO transistor 9, respectively. In this case, regardless of the output of the phase comparator 1, the MIMO transistor 8 is turned on, the MIMO transistor 9 is turned off, and the loop filter 11 and the voltage controlled oscillator 14 in the phase-locked loop are in phase pull-in operation. It becomes the state of. As a result, the large current I goes through the constant current source 7 and the MIMO transistor 8.₁Charging is performed for the capacity 13 by, and the potential V of node B_BRise and the reference voltage V₁The oscillation frequency of the voltage controlled oscillator 14 changes to a high frequency and is input as the input V of the phase comparator 1 via the frequency divider 16. In this way, when the output DOWN of the phase comparator 1 is stagnant in the low level state, the phase-locked loop is forcibly pulled back to the phase pull-in state through the level comparison action of the comparator 15 and synchronized. The time to reach the state is shortened.

【0015】

Also, the potential V at node B_BLevel is the reference voltage V input to the opposite phase side of the comparator 15.₁When the level becomes higher than the level of, the output level of the comparator 15 becomes a high level and is input to the AND circuits 4 and 6, and is also input to the constant current source 7 for current suppression. Therefore, in this case, the potential V at node B_BLevel is the reference voltage V₁Due to the gate action of AND circuits 4 and 6, the output UP and output DOWN of the phase comparator 1 are normally input to the gates of the MIMO transistors 8 and 9 and the original phase, respectively. It returns to the operating state as a synchronous circuit. In this case, the operation as a phase synchronization circuit is performed via the output UP and output DOWN of the phase comparator 1, and if the output UP or output DOWN stays at the low level for a long time, the synchronization determination is made. The circuit 2 determines that the phase synchronization circuit is out of sync, controls the current values of the constant current source 7 and the constant current source 10 to be large, and outputs UP or DOWN. When the time of stagnation at the low level is short, the synchronization determination circuit 2 determines that the phase synchronization circuit is synchronized, and the current values of the constant current source 7 and the constant current source 10 become small currents. The control action is performed as follows. In the phase-locked loop 2, as a condition for determining the phase synchronization, the phase difference detected by the phase comparator 1 is detected due to the jitter generated after the synchronization of the phase-locked loop or in a state where the synchronization cannot be achieved. In order to determine whether or not the phase is correct, the synchronous / asynchronous determination is switched using a value slightly larger than the jitter width generated in the phase-locked loop as a scale.

【0016】

FIG. 5 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 5, in this embodiment, the phase comparator 1, the synchronization determination circuit 2, the AND circuits 30 and 36, the OR circuits 31 and 33, the inverter 32, the discharge type constant current source 7 and the suction type are used. A charge pump circuit 3 including a constant current source 10, a PMOS transistor 8, an NMOS transistor 9, a comparator 15 and 34, a loop filter 11 including a resistor 12 and a capacitance 13, a voltage controlled oscillator 14, and a frequency divider 16. Be prepared. As is clear from the comparison between FIGS. 1 and 5, the difference from the first embodiment of this embodiment is the difference in the configuration of the charge pump circuit, which is one of the components of the phase-locked loop. .. That is, in the first embodiment, the charge pump circuit is composed of AND circuits 4 and 6, an inverter 5, constant current sources 7 and 10, a MIMO transistor 8, an MIMO transistor 9, and a comparator 15. On the other hand, in this embodiment, the charge pump circuit 3 includes the AND circuits 30 and 36, the OR circuits 31 and 33, the inverter 32, and the constant current sources 7 and 10 as described above. It is configured to include a waveguide transistor 8, an NMOS transistor 9, and comparators 15 and 34.

【0017】

In FIG. 5, on the positive phase input side of the comparator 15, the potential V of the node B corresponding to the output end of the loop filter 11, that is, the input side of the voltage controlled oscillator 14 is similar to the case of the first embodiment._BThe level of is input, and the voltage V shown in FIG. 4 is input to the reverse phase input side of the comparator 15.₀Reference voltage V at a level lower than the level of₁Is entered. Further, in the comparator 34, the potential V of the node B is on the positive phase side._BThe level of is input, and the voltage V shown in Fig. 4 is on the opposite phase side.₀Reference voltage V at a level higher than the level of₂Is entered. The operation in the comparator 15 is the same as in the case of the first embodiment, and the potential V at the node B_BThe level of the reference voltage V gradually decreases.₁When the level is lower than the level of, the output level of the comparator 15 becomes a low level, which is input to the AND circuit 30 and also acts as a large current for the constant current source 7 for control. It is input as a signal. In this state, the low level is also output from the comparator 34, so that the MIMO transistor 8 is turned on regardless of the output UP level of the phase comparator 1, and the loop filter 11 and the voltage controlled oscillator in the phase synchronization circuit are turned on. 14 is a state in which the phase pull-in operation is in progress. As a result, the large current I goes through the constant current source 7 and the MIMO transistor 8.₁Charging is performed for the capacity 13 by, and the potential V of node B_BRise and the reference voltage V₁The oscillation frequency of the voltage controlled oscillator 14 changes to a high frequency and is input as the input V of the phase comparator 1 via the frequency divider 16. Thus, V_B<V₁In the state of, the phase-locked loop is forcibly pulled back to the phase-pulled state through the level comparison action of the comparators 15 and 34, and the time to reach the synchronous state is shortened.

【0018】

Further, in the comparator 34, the potential V at the node B_BThe level of the above-mentioned reference voltage V gradually rises.₂When the level becomes higher than the level of, the output level of the comparator 34 becomes a high level and is input to the OR circuit 31 and the OR circuit 33, and the current value is set to a large current even for the constant current source 10. It is input as a control signal that acts. In this state, the high level is also output from the comparator 15, which causes the MIMO transistor 9 to be turned on regardless of the output DOWN level of the phase comparator 1, and the loop filter 11 and voltage control in the phase-locked loop. The oscillator 14 is in the phase pull-in operation, and the large current I2 is passed through the constant current source 10 and the comparator 9.Discharge from capacitance 13 is performed by, and the potential V at node B_BDecreases the reference voltage V₂The oscillation frequency of the voltage controlled oscillator 14 changes to a low frequency, and is input as the input V of the phase comparator 1 via the frequency divider 16. In this way, the phase-locked loop is forcibly pulled back to the phase pull-in state through the level comparison action of the comparators 15 and 34 in response to the situation where the output UP of the phase comparator 1 is stagnant in the low level state. , The time to reach the synchronization state is shortened.

【0019】

Through the above operation, the potential V at node B_BThat is, the input voltage to the voltage controlled oscillator 14 is V.₁And V₂At voltage levels between, the outputs of Comparator 15 and Comparator 34 are high and low levels, respectively, and the output UP of phase comparator 1 is directly on the MIMO transistor 8 via AND circuit 30 and OR circuit 31. A path input to the gate is formed, and the output DOWN of the phase comparator 1 is inverted by the inverter 32 to form a path directly input to the gate of the MIMO transistor 9 via the OR circuit 33. As a result, the phase-locked loop of this embodiment is in a state where the circuit is formed by the same circuit connection as the original phase-locked circuit, and the voltage V at the node B is formed._BIs V₀When it comes close to, it will be in a synchronized state in a short time.

【0020】

In the first and second embodiments described above, the numerical examples in the above equations (1) to (3) are N = 512 (input frequency: 8KHz, output frequency: 4.096MHz), C = 60pF, K = 2.0MHz. With / V and R = 25MHz, the current I = 40nA when synchronized, the current I = 400nA when not synchronized, and the natural angular frequency ω._nWhen the time change of the oscillation frequency f of the voltage controlled oscillator is calculated with = 2π × 256 rad / s and the braking coefficient ζ = 1.2, it becomes as shown in the oscillation frequency characteristic 102 of Fig. 7, and the oscillation frequency f becomes constant. Synchronous pull-in time up to t_rIs t_r= 4ns. This synchronous pull-in time t_rThe value of is 60% or less as compared with the value of the above-mentioned conventional example.

【0021】

[Effect of the invention]

As described above, in the present invention, the voltage level output from the charge pump circuit and input to the voltage controlled oscillator has a large level difference from the predetermined voltage level corresponding to the phase-locked loop, and the phase-locked loop By controlling the charge / discharge current with respect to the capacitance of the loop filter in response to the situation where it takes time for synchronous pull-in, the effect is that the synchronous pull-in time can be shortened while maintaining the low jitter characteristics after synchronous pull-in. is there.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the 1st Example of this invention.

[Figure 2]

It is a circuit diagram which shows an example of the synchronous detection circuit in this Example.

[Fig. 3]

It is a circuit diagram which shows an example of the phase comparator in this Example.

[Fig. 4]

It is a figure which shows the oscillation frequency characteristic of a voltage control oscillator.

[Fig. 5]

It is a block diagram which shows the 2nd Example of this invention.

[Fig. 6]

It is a block diagram which shows the conventional example.

[Fig. 7]

It is a figure which shows the synchronous pull-in characteristic of a phase-locked loop.

[Explanation of symbols]

1 Phase comparator 2 Synchronization judgment circuit 3 Charge pump circuit 4, 6, 30, 36 AND circuit 5, 20, 32 inverter 7, 10 constant current source 8 lithography transistor 9 NMOS transistor 11 Loop filter 12, 18 resistors 13, 19 capacity 14 Voltage Control Oscillator 15, 34 comparator 16 divider 17, 21 ~ 29 NAND circuit 31, 33 OR circuit