nigital data recording and/or reproduction apparatus and recording media.

Description: TECHNICAL FIELD [Detailed description of the invention]

[Industrial application field] The present invention relates to a digital data recording / playback device, and relates to, for example, a digital data recording / playback device that records / reproduces data on an optical recording medium in a form corresponding to a compact disc for music. [Outline of Invention] According to the present invention, in a digital data recording / playback device in which data is recorded / reproduced on a recording medium in a form corresponding to a compact disc, interleaving processing similar to that of a compact disc and a length corresponding to one recording unit (sector) are provided. By enabling the interleaving process and enabling sector-completed coding and decoding thereof, it is possible to easily perform the process of writing data to an arbitrary sector and the process of rewriting the data of an arbitrary sector. It is the one that was made. [Conventional technology] Compact discs in which audio signals are digitized and optically recorded are widely known. This compact disc is, for example, a recording medium having a diameter of 12 cm and capable of recording data of about 500 Mbytes or more. Therefore, this compact disc can be used as a digital data recording medium for recording a large amount of data. Focusing on this, CD-ROMs that can record digital data other than audio data in the music recording area of compact discs have been standardized. Digital data is recorded on a CD-ROM in the same manner as a compact disc for music. That is, in the CD-ROM, an optical disc having a diameter of 12 cm and a spiral track formed like a compact disc for music is used. The recorded data is doubly encoded by CIRC (Cross Interleave Reed-Solomon Code), EFM-modulated (8-14-modulated), and optically recorded on an optical disc. In such a CD-ROM, one sector (one block), which is a data recording unit, is composed of one subcode block consisting of 98 frames. In other words, compact discs for music have 8-bit subcodes from P to W per frame (R to W are also called user's bits). Since this subcode is one information unit (address) for 98 frames, 98 frames are called blocks. A CD-ROM is basically a read-only recording medium. CD-ROMs have features such as a large storage capacity, mass duplication, and little deterioration of information. Taking advantage of these characteristics, CD-ROMs are used to record data from various dictionaries and research material data. [Problems to be solved by the invention] In recent years, write-once optical recording media and optical recording media that can be erased and re-recorded, such as magneto-optical disks, have been developed. It has been proposed to use such a write-once optical recording medium or an optical recording medium that can be erased and re-recorded in the same manner as a compact disc to record digital data. Data can be added to a compact disc as a write-once data recording medium (hereinafter referred to as CD-WO) or a compact disc as a data recording medium that can be erased and re-recorded (hereinafter referred to as CD-erasable). Since it can be re-recorded, it can be expected to be used in a wider range of fields than a read-only CD-ROM. By the way, in CD-WO and CD-erasable, it is useful to be able to write / read data in sector units. On the other hand, compact discs for music are for playback only, and data is played back in chronological order. Compact discs for music are interleaved with up to 108 frames of recorded data so that they are ideal for sequential data such as music data. For this reason, when a CD-WO or CD-erasable is realized in exactly the same signal processing form as a compact disc for music, it is complicated to write data to an arbitrary sector or rewrite data in an arbitrary sector. Signal processing is required. To avoid the need for such complicated processing, changing a CD-WO or CD-erasable to a signal format that is completely different from that of a compact disc for music can be used for compact discs, CD-ROMs, CD-WOs, and CDs. -You will lose compatibility between eraseables. That is, on a compact disc, as described above, the symbols for each column on the two-dimensional array are C using the Reed-Solomon code.₂After generating and adding the parity of the series and performing the interleave delay, C is used using the Reed-Solomon code.₁CIRC is used to generate and add series parity. In such CIRC, up to 108 frames of interleaving are performed and convolutional coding is performed so as to optimize for sequential data such as music data. On the other hand, in CD-WO and CD-erasable, one sector, which is a unit for writing and reading data, is composed of a subcode block consisting of 98 frames. Therefore, rewriting the data of any one sector affects the front two sectors and the rear two sectors. That is, when the data of any one sector is rewritten, the C related to the data of the two sectors before and after it₁The parity of the series changes. From this, when rewriting the data of any one sector, the data of that sector and the data of the two sectors before and after it are taken in, and C₁It is necessary to re-find the parity of the series. Therefore, for example, as shown in Japanese Patent Application No. 62-244996, a sector of all "0" data in which two or more sectors are continuous is inserted between sectors for data recording, for example, sectors every three sectors are inserted. It has been proposed to use a sector for data recording. However, in this way, the process of recalculating the parity becomes unnecessary, but the data recording capacity is reduced to about 1/3 at worst. Therefore, an object of the present invention is digital data that does not require complicated processing and does not reduce the data recording capacity when recording data in an arbitrary sector or rewriting data in an arbitrary sector. To provide a recording / playback device. Further, in the past, since the convolutional code is used in this way, in order to capture the data of an arbitrary sector, it is necessary to capture the data of at least two consecutive sectors, which requires a long access time. Become. Still another object of the present invention is to provide a digital data recording / playback device capable of shortening the access time. [Means to solve problems] The present invention relates to a digital data recording apparatus having a coding means for adding a predetermined error correction code to input data and a means for recording the coded data on a recording medium. The coding means is a memory that temporarily stores input data and It has an address control means for controlling the address to the memory. The address control means is a digital data recording device in which a first address control and a second address control can be set. A selection signal for selectively setting the data recorded by the first address control and the data recorded by the second address control is recorded on the recording medium. The present invention also relates to a digital data reproduction device having a means for reproducing recorded data on a recording medium and a decoding means for decoding the reproduced data. Decoding means include a memory that temporarily stores playback data and It has an address control means for controlling the address to the memory. The address control means is a digital capable of selectively setting address control according to whether the playback data of the recording medium is the data recorded by the first address control or the data recorded by the second address control. It is a data playback device. The selection signal recorded on the recording medium is reproduced to determine whether the reproduction data of the recording medium is the data recorded by the first address control or the data recorded by the second address control. [Action] Digital data is recorded / reproduced using an optical disc having the same form as a compact disc. At this time, two first and second interleave processes can be set. In the first interleaving process, the total interleaving length is 108 frames. This first interleaving process is suitable when dealing with sequential data such as music data, or when it is desired to maintain perfect compatibility with a music compact disc or a CD-ROM. In the second interleaving process, the total interleaving length is 95 frames. Then, by processing Modulo 98, interleaving is performed while rotating at 98 frames. As a result, error correction coding is completed within one sector consisting of 98 frames. Since the error correction coding is completed within one sector, this second interleaving process is suitable for use when it is often necessary to write data to an arbitrary sector or rewrite the data of an arbitrary sector. .. [Example] Examples of the present invention will be described in the following order. Overview of recording / playback equipment b. Frame structure and sector structure c. About interleave processing d. Encoding and decoding process for the first interleaving process e. Encoding and decoding process for the second interleaving process f. Encoding / decoding processing in one embodiment Overview of recording / playback equipment FIG. 1 shows an outline of a digital data recording / reproducing device to which the present invention is applied. In FIG. 1, reference numeral 1 denotes an optical disc on which digital data is optically recorded / reproduced. As the optical disk 1, a write-once type optical disk or an erasable / re-recordable optical disk, for example, a magneto-optical disk can be used. The optical disc 1 has a form similar to that of a compact disc for music. That is, the diameter of the optical disc 1 is 12 cm, and a spiral track is formed on the optical disc 1. Then, the optical disk 1 is rotated by CLV (constant linear velocity). At the time of recording, the data to be recorded on the optical disk 1 is supplied to the data input terminal 2. This recorded data is supplied to the coding circuit 3. The coding circuit 3 is C₂Encoder 4, interleave delay circuit 5, and C₁It is composed of an encoder 6. The data from the input terminal 1 is expanded into a predetermined frame structure, and is C in the coding circuit 3.₁Series and C₂It is double-coded with the series. A selection signal is supplied from the terminal 7 to the interleave delay circuit 5. As will be described in detail later, the interleave delay circuit 5 can be subjected to two first and second interleave processes having different interleave lengths. In the case of the first interleaving process, a maximum of 108 frames of interleaving are applied. Then, in the case of the first interleaving process, convolutional coding is performed. In the case of the second interleaving process, the interleaving length is 98, and in the second interleaving process, the error correction coding is completed within one sector. The data to which the error correction code is doubled in the coding circuit 3 is EFM-modulated (8-14-modulated) in the EFM modulation circuit 8 and recorded on the optical disk 1. When the recorded data of the optical disk 1 is reproduced, the processing is performed in the reverse sequence of the above-mentioned recording. That is, the reproduced data of the optical disk 1 is supplied to the EFM demodulation circuit 9 and demodulated by EFM. The output of the EFM demodulation circuit 9 is supplied to the decoding circuit 10. Decoding circuit 10 is C₁Decoder 11, deinterleaved delay circuit 12, and C₂It is composed of a decoder 13. The deinterleaved delay circuit 12 can perform two first and second deinterleaved processes corresponding to the two interleaved processes that can be set by the interleaved delay circuit 5. A selection signal is supplied from the terminal 14 to the deinterleave delay circuit 12, and the two deinterleave processes can be switched by this selection signal. At the time of recording, data on which of the first and second interleaving processes was performed is written to a part of the optical disk 1, for example, the TOC (Table of Contents) on the innermost circumference of the disk, and at the time of playback, data is written. The deinterleaved delay circuit 12 may be switched according to this data. It is also possible to record the signal of the first interleaving process and the signal of the second interleaving process in a mixed manner on the optical disk 1. That is, for example, the optical disk 1 is provided with a data area in which predetermined data is recorded in advance and a user area in which a user can freely write data, and the area in which predetermined data is recorded in advance is subjected to the first interleaving process. The signal may be recorded, and the signal may be recorded in the user area by the second interleaving process. In this case, the data area can be mass-copied using a stamper in the same manner as the CD-ROM. The output of the decoding circuit 10 is taken out from the output terminal 15, and the reproduction data is obtained from the output of the output terminal 15. b. Frame structure and sector structure As shown in FIG. 2A, data is expanded on the optical disk 1 in a frame structure, EFM-modulated, and the data is recorded. This frame structure is similar to a compact disc for music. That is, as shown in Fig. 2A, one frame has 24 symbols (1 symbol is 8 bits, which corresponds to 6 samples each of L (left) and R (right) when audio data is sampled with 16 bits. It consists of EFM-modulated 14-channel bits) data bits, 8-symbol parity, 1-symbol subcode, 24-channel bit frame sync (not shown), and margin bits for DC component suppression. Therefore, the total number of channel bits in one frame is<img file="JP2829963B2_D0001.tif" />Will be. The subcode of one symbol of each frame has eight channels P to W. As shown in Fig. 2B, 98 subcodes of 8 channels P to W of each frame are collected to form one subcode block. This subcode block is one sector. Therefore, one sector corresponds to 98 frames. Subcode frame sync S₀, S₁Two patterns are selected that are not in the 256 patterns when the data is EFM-modulated. Of these subcodes from P to W, the P channel is a flag indicating the beginning. The Q channel is a control bit. That is, data / audio flags, addresses, track numbers, time codes, etc. are recorded on the Q channel. c. About interleave processing As described above, in one embodiment of the present invention, C₁Series and C₂Data is recorded with double error correction codes added to the series. Then, when performing such coding, two first and second interleaving processes can be set. In the first interleaving process, a maximum of 108 frames are interleaved. Then, in this case, convolutional coding is performed together with consecutive frames. This first interleaving process is exactly the same as a music compact disc or a CD-ROM. Therefore, it is suitable for handling sequential data such as music data, or when it is desired to maintain perfect compatibility with music compact discs and CD-ROMs. The second interleaving process provides up to 95 frames of interleaving. Then, by processing Modulo 98, interleaving is performed while rotating at 98 frames. As a result, error correction coding is completed within one sector consisting of 98 frames. Since the error correction coding is completed within one sector, this second interleaving process is suitable for use when it is often necessary to write data to an arbitrary sector or rewrite the data of an arbitrary sector. .. The basic encoding process and decoding process are the same regardless of whether the first interleaving process or the second interleaving process is performed. That is, the data are arranged two-dimensionally, parity Q is added by the (28,24,5) Reed-Solomon code, and C₂The sequence is coded. Then, interleaving is applied, and parity P is added by the (32,28,5) Reed-Solomon code, and C.₂The sequence is coded. In the case of the first interleaving process, a maximum of 108 frames are interleaved and convolutional coding is performed. Therefore, when recording data in an arbitrary sector or rewriting data in an arbitrary sector, the process becomes very complicated. That is, when the first interleaving process is performed, as shown in the conceptual diagram in FIG. 3, a maximum of 108 frames of interleaving are performed, and convolutional coding is performed together with the data of consecutive frames. For example, in Fig. 3, the data of sector m is arranged as shown by diagonal lines in Fig. 3 by interleaving up to 108 frames. When the data of sector m in the area indicated by this diagonal line is rewritten, all C of sector (m + 1)₁Part of C in series and sectors (m + 2)₁Along with the effect on the sequence, C in sector (m-1)₁The effect occurs on the series. Therefore, when rewriting the data of sector m, C of sector (m + 1), (m + 2), (m-1), (m-2)₁The parity of the series needs to be recalculated accordingly. On the other hand, in the second interleaving process, the interleaving length is 95 frames, which is less than or equal to the number of frames in one sector, and interleaving is applied while rotating with modulo 98. Therefore, as shown in the conceptual diagram in Fig. 4, error correction coding is completed in one sector. Therefore, for example, rewriting sector n has no effect on sectors (n + 1), (n + 2), (n-1), and (n-2). d. Encoding and decoding process for the first interleaving process The encoding process when encoding data in the first interleaving process will be described with reference to FIG. 12 16-bit data to be recorded L_6n, R_6n, L_{6n + 1}, R_{6n + 1}, ..., L_{6n + 5}, R_{6n + 5}Is the data W of the upper 8 bits and the lower 8 bits_12n, A, W_12n, B, ..., W_{12n + 11}, A, W_{12n + 11}, B is divided and sent to the delay block 21. The upper 8 bits are indicated by A and the lower 8 bits are indicated by B. Even numbered data L in delay block 21_6n, R_6n, L_{6n + 2}, R_{6n + 2}For, ..., delay elements D1 to D12 apply a delay of 2 frames. At the same time, the data is rearranged in the delay block 21. And the 24 symbols output from the delay block 21 are C₂Sent to encoder 22. C₂4-symbol parity Q with (28,24,5) Reed-Solomon code on encoder 22_12n, Q_{12n + 1}, ..., Q_{12n + 3}Is generated. In the center of the output data of 24 symbols of delay block 21, C₂4-symbol parity Q generated by encoder 22_12n, Q_{12n + 1}, ..., Q_{12n + 3}Is added to make 28 symbols. These 28 symbols are sent to delay block 23. The delay elements D21 to D47 of the delay block 23 interleave each of these 28 symbols by a multiple of 4 frames. 28 symbols output from delay block 23 are C₁Sent to encoder 24. C₁Parity P of 4 symbols by (32,28,5) Reed-Solomon code in encoder 24_12n, P_{12n + 1}, ..., P_{12n + 3}Is generated. At the end of the 28 symbols output from delay block 23, C₁4-symbol parity P generated by encoder 24_12n, P_{12n + 1}, ..., P_{12n + 3}Is added to make 32 symbols. These 32 symbols are sent to delay block 25. The delay elements D51 to D66 of the delay block 25 delay these 32 symbols by one frame for each symbol. Then, the parity symbols are inverted by the inverters I1 to I4 and I5 to I8, and the encoding process is completed. The decoding process is the reverse of the encoding process described above. The decoding process will be described with reference to FIG. The 32 reproduced symbols (24 data symbols plus 4 parity P symbols and 4 parity Q symbols) are sent to the delay block 31. The delay elements D71 to D86 of the delay block 31 delay the symbol for each symbol by one frame. Then, the parity symbols are inverted by the inverters I11 to I18. These 32 symbols are C₁Sent to decoder 32. C₁The 28 symbols output from the decoder 32 are sent to the delay block 33. The delay elements D91 to D116 of the delay block 33 solve the interleaving of multiple frames of 4. And the output of delay block 33 is C₂Sent to decoder 34. C₁Decoder 32 and C₂Error correction processing is performed by the decoder 34. C₂The 24 symbols output from the decoder 34 are sent to the delay block 35. Data is returned in chronological order at delay block 35. Then, the delay elements D121 to D132 delay the odd-numbered data by two frames, and the decoding process is completed. Fig. 7 shows each symbol encoded by the first interleaving process as a map on a two-dimensional array. As shown in FIG. 7, in the case of the first interleaving process, a maximum of 108 frames of interleaving are applied. Therefore, the coordinates of the symbols for one sector corresponding to the symbols in chronological order are as shown in the table below (Table 1). As shown in Fig. 8, M_{(i, j)}Indicates the row number i and column number j where the symbols are placed.<img file="JP2829963B2_D0002.tif" /><img file="JP2829963B2_D0003.tif" /> When each symbol is arranged two-dimensionally as shown in Fig. 7, interleaving is released by performing the address operation corresponding to the decoding process shown in Fig. 6 and reading / writing in the column direction. , Data can be decrypted. That is, corresponding to the delay block 31, the symbols in the even-numbered rows are delayed by one frame, the data is read in the column direction, and C is shown by line 81.₁The series can be decrypted. After that, (27 × 4 = 108) frames for the first line, (26 × 4 = 104) frames for the second line, and (25 × 4 =) for the third line corresponding to the delay block 33. 100) Frame, ..., by reading each with a delay, C as shown by line 82₂The series can be decrypted. Since the odd-numbered data is delayed by two frames corresponding to the delay block 35, the odd-numbered data indicated by a square in the broken line is output at the time of decoding. e. Encoding and decoding process for the second interleaving process The encoding process when encoding data in the second interleaving process will be described with reference to FIG. 12 16-bit data L_6n, R_6n, L_{6n + 1}, R_{6n + 1}, ..., L_{6n + 5}, R_{6n + 5}Is the data W of the upper 8 bits and the lower 8 bits_12n, A, W_12n, B, ..., W_{12n + 11}, A, W_{12n + 11}, B is divided and sent to the delay block 41. Even numbered data L in delay block 41_6n, R_6n, L_{6n + 2}, R_{6n + 2}For, ..., delay elements D151 to D162 apply a delay of 2 frames (delay block 41 is rotated by modulo 98). At the same time, the data is rearranged in the delay block 41. And the 24 symbols output from the delay block 41 are C₂Sent to encoder 42. C₂4-symbol parity Q with (28,24,5) Reed-Solomon code on encoder 42_12n, Q_{12n + 1}, ..., Q_{12n + 3}Is generated. In the center of the output data of 24 symbols of delay block 42, C₂4-symbol parity Q generated by encoder 42_12n, Q_{12n + 1}, ..., Q_{12n + 3}Is added to make 28 symbols. These 28 symbols are sent to delay block 43. The delay elements D171 to D197 of the delay block 43 interleave 4 frames, 3 frames, 4 frames, 3 frames, ... (The delay block 43 is rotated by the modulo 98). 28 symbols output from delay block 43 are C₁Sent to encoder 44. C₁Parity P of 4 symbols by (32,28,5) Reed-Solomon code on encoder 44_12n, P_{12n + 1}, ..., P_{12n + 3}Is generated. At the end of the 28 symbols output from delay block 43, C₁4-symbol parity P generated by encoder 44_12n, P_{12n + 1}, ..., P_{12n + 3}Is added to make 32 symbols. These 32 symbols are sent to delay block 45. The delay elements D201 to D216 of the delay block 45 delay these 32 symbols by one frame for each symbol (the delay block 45 is rotated by the modulo 98). Then, the inverters I21 to I24 and I25 to I28 invert the parity symbol, and the encoding process is completed. The decoding process is the reverse of the encoding process described above. The decoding process will be described with reference to FIG. The 32 reproduced symbols are sent to delay block 51. The delay elements D221 to D236 of the delay block 51 delay the symbol for each symbol by one frame (the delay block 51 is rotated by the modulo 98). Then, the parity symbols reproduced by the inverters I31 to I38 are inverted. These 32 symbols are C₁Sent to decoder 52. C₁The 28 symbols output from the decoder 52 are sent to the delay block 53. The delay elements D241 to D267 of the delay block 53 solve the interleaving of 4 frames, 3 frames, 4 frames, 3 frames, ... (The delay block 53 is rotated by the modulo 98). And the output of delay block 53 is C₂Sent to decoder 54. C₁Decoder 52 and C₂Error correction processing is performed by the decoder 54. C₂The 24 symbols output from the decoder 54 are sent to the delay block 55. Data is returned in chronological order at delay block 55. Then, the delay elements D271 to D282 delay the even-numbered data by two frames, and the decoding process is completed (delay block 55 is rotating in modulo 98). Fig. 11 shows each symbol encoded by the second interleaving process as a map on a two-dimensional array. As shown in FIG. 11, in the case of the second interleaving process, a maximum of 95 frames of interleaving are applied. Then, by taking modulo 98, if it is delayed to the frame of the 97th column, it returns to 0 frame. Therefore, the symbol W for one sector in chronological order_12n, A, W_12n, B, W_{12n + 1}Coordinates M of symbols for one sector corresponding to, B ..._{(i, j)}Is as shown in the table below (Table 2). M_{(i, j)}Indicates the coordinates of each symbol as shown in FIG. 12, where i is the row number, j is the column number, and n = 0 to 97.<img file="JP2829963B2_D0004.tif" /> When each symbol is arranged two-dimensionally as shown in Fig. 11, interleaving is released by performing the address operation corresponding to the decoding process shown in Fig. 10 and reading / writing in the column direction. , Data can be decrypted. That is, corresponding to the delay block 51, the symbols in the even-numbered rows are delayed by one frame, and the data is read in the column direction and C.₁The series can be decrypted. At this time, Modulo 98 is taken. After that, 95 frames for the first line, 91 frames for the second line, 88 frames for the third line, and so on corresponding to the delay block 53, respectively, by delaying and reading C.₂The series can be decrypted. At this time, the modulo 98 is also taken. FIG. 11 shows the decoding process when n = 0 and the decoding process when n = 60. When n = 0, C as shown by line 91₁The series is decrypted. At this time, since modulo 98 is taken, C from the symbols of the 0th column frame and the 97th column frame.₁The series is decrypted. When n = 0, C as shown by line 92.₂The series is decrypted. When n = 60, C as shown by line 93₁The series is decrypted. Also, when n = 60, C as shown by line 94.₂The series is decrypted. At this time, since modulo 98 is taken, W that should be delayed by 38 frames from 60 frames₇₂₉, B symbol is M_(11,0)Return to the position of. The following symbols are similar. f. Encoding / decoding processing in one embodiment The above-mentioned encoding process and decoding process are realized by storing data in RAM and controlling the address. That is, in the coding circuit 3 in FIG. 1, the encoding process in the case of the first interleaving process and the encoding process in the case of the second interleaving process can be selected, and the coding circuit 3 is , As shown in FIG. 13, the RAM 61, the encoder 62, the address generation circuit 63 that generates an address corresponding to the first interleaving process, and the address generation that generates an address corresponding to the second interleaving process. It consists of circuit 64. Then, the address corresponding to the first interleaving process output from the address generating circuit 63 and the address corresponding to the second interleaving process output from the address generating circuit 64 are selectively selected by the RAM 61 via the switch means 65. By supplying to, both the encoding process in the case of the first interleaving process and the encoding process in the case of the second interleaving process can be set. Further, the decoding circuit 10 in FIG. 1 can be selected from the decoding process in the case of the first interleaving process and the decoding process in the case of the second interleaving process described above. , As shown in FIG. 14, the RAM 71, the encoder 72, the address generation circuit 73 that generates an address corresponding to the first interleaving process, and the address generation that generates an address corresponding to the second interleaving process. It consists of a circuit 74. Then, the address corresponding to the first interleaving process output from the address generating circuit 73 and the address corresponding to the second interleaving process output from the address generating circuit 74 are selectively selected via the switch means 75. By supplying to RAM71, both the decoding process in the case of the first interleaving process and the decoding process in the case of the second interleaving process can be set. [Effect of the invention] According to the present invention, it is possible to set an interleave process in which error correction coding can be completed in one sector consisting of 98 frames. Since error correction coding can be completed within one sector, when data is written to any sector or data in any sector is rewritten, the effect does not affect other sectors and data is written to any sector. However, complicated signal processing is not required when rewriting data in an arbitrary sector, and the data recording capacity does not decrease. Further, since the error correction coding is completed within one sector, it is not necessary to take in the data of a plurality of sectors when reading / writing the data, and the access time can be shortened.

[Simple explanation of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention, FIG. 2 is a schematic diagram used for explaining a recording format of an embodiment of the present invention, and FIGS. 3 and 4 are of the present invention. A schematic diagram used for explaining an embodiment, FIGS. 5 and 6 are block diagrams used for explaining the first interleaving process, and FIGS. 7 and 8 are schematic lines used for explaining the first interleaving process. Figures, 9 and 10 are block diagrams used to explain the second interleaving process, FIGS. 11 and 12 are schematic diagrams used to explain the second interleaving process, and FIG. 13 is a coding device. A block diagram of an example, FIG. 14 is a block diagram of an example of a coding device. Description of the main symbols in the drawings 1 ...... Optical disc, 2 ...... Data input terminal, 3 ...... Coding circuit, 5 ...... Interleaved delay circuit, 8 ...... EFM Modulation circuit, 9 ... EFM demodulation circuit, 10 ... Decoding circuit, 12 ... Deinterleaved circuit, 15 ... Output terminal, 61,71. ..... RAM, 63,64,73,74 ...... Address generation circuit.