Radio data system receiver

Description: TECHNICAL FIELD [Detailed description of the invention]

(B) Industrial application fields The present invention relates to a receiver, and more specifically, when the reception state of a broadcast program currently being received deteriorates, the reception frequency is automatically set to the frequency of another broadcasting station broadcasting the same program. Regarding receivers that can be changed. (B) Conventional technology Conventionally, a system (Autofahrer Rundfunk Information; abbreviated as ARI) that multiplexes a data signal for identifying a traffic information station with an FM radio signal and broadcasts it has been implemented in West Germany and the like. This ARI uses the third harmonic (57KHz) of the FM broadcast pilot signal (19KHz) as a subcarrier, amplitude-modulates this subcarrier with a data signal for identifying the traffic information station, and frequency-converts this to the main carrier. After that, I was trying to multiplex and transfer to the FM radio signal. On the receiving side, the signal for identifying the traffic information station multiplexed with the FM radio signal was demodulated to facilitate the reception of the broadcast program supplying the traffic information. However, the ARI system provides only information on the identification of the Traffic Information Center, and does not provide any further services. Therefore, the same 57KHz subcarrier is subjected to carrier suppression type amplitude modulation with a data signal biphase coded to a phase 90 ° different from the phase of ARI, and the double-sided band signal of this modulated signal is multiplexed with the FM radio signal. A system (Radio Data System; abbreviated as RDS) was proposed. This RDS standard is the RDS specification (Specifications of the Radio Data System RDS for VHF-FM Sound Broadcasting, EBU Document) compiled by the European Broadcasting Union (EBU). Tech.3244-E, Mar.1984.). According to this specification, the service data supplied by RDS (hereinafter referred to as RDS data) forms one group with four blocks each consisting of 26 bits. As shown in FIG. 1, each block contains 16 bits of information words, 10 bits and check words and offset words. On the receiving side, various services can be supplied by demodulating the information word. The check word is a code for detecting and correcting an error in the data. The offset word is data indicating the starting point of the block and the number of the block in the group. The basic information of RDS data will be described based on the data format shown in Fig. 1. The program identification code (PI code) is given to the first block. This PI code is Country code (4 bits) Broadcast range code (4 bits) It consists of a total of 16 bits of the program reference number code (8 bits). That is, the PI code is a code based on predetermined rules that provides information such as which country the broadcast belongs to, whether the same broadcast is being performed in other countries, whether it is a local program or a major program, etc. Include as data. Therefore, the same number broadcast can be recognized by using this code. A group type identification code consisting of a total of 5 bits, a group type code (4 bits) and a version code BO (1 bit), is given to the second block. This group type identification code is for identifying what is included in the data sent thereafter. Theoretically 2 due to the 5-bit group type identification code⁵= 32 group types can be identified. However, definitions are now given for nine group types, and other group types are undefined for future use. Following the group type identification code Transportation program code (TP code: 1 bit) Program type code (PTY code: 5 bits) Traffic announcement code (TA code: 1 bit) Music / speech switch code (M / S code: 1 bit) Decoder identification code (DI code: 1 bit) The program service name segment address code (C1, C0: 2 bits) is given. In the above data, the TP code and the TA code indicate whether the station being broadcast is a traffic information station or whether it is currently being broadcast by a combination of the respective codes. The PTY code is for identifying 32 types of programs (music programs, news programs, sports programs, etc.) from 0 to 31, and is defined based on predetermined rules. The M / S code indicates that a speech is being broadcast if it is "0" and that music is being broadcast if it is "1". The DI code gives decoding information for demodulating the transmitted broadcast wave, and 1 bit is given, but by receiving this repeatedly 4 times, 4 bit information (16 ways) Decode information) can be obtained. The program service name segment address codes C1 and C0 have different functions depending on the group type described above, but in this embodiment, they indicate the address of the PS code described later. Two 8-bit Alternate Frequently's Codes (AF Codes) are given to the third block. For convenience, one AF code is referred to as the first AF code, and the other AF code is referred to as the second AF code. This AF code transmits the number of other broadcasting stations (hereinafter referred to as AF stations) that are broadcasting the same program as the station currently being broadcast, and their frequency data. The 8-bit AF code can represent numbers from 0 to 255, of which numbers from 0 to 205 correspond to frequency data every 100 KHz.<img file="JP2760552B2_D0001.tif" /> Of the numbers above this, 224 to 249 are given different meanings. That is, it corresponds to the information on how many AF stations exist as follows.<img file="JP2760552B2_D0002.tif" /> Now consider, for example, the case of transmitting information about four AF stations. In this case, the first AF code in the RDS data to be transmitted first is given a number 228 indicating the number of AF stations, and the second AF code is given a number indicating a carrier frequency. The second and third frequency data are given to the first and second AF codes in the RDS data to be transmitted next. The first AF code of the RDS data to be transmitted last is given the fourth frequency data, the second AF code is given the filler cord (number 205), and the transmission of the AF code ends. After that, the same transmission is cyclically repeated. Therefore, on the receiving side, if the AF code is repeatedly received and demodulated, the frequency data of another station broadcasting the same program as the currently being received broadcast program can be obtained as a list. The program service name code (PS code) to which the broadcasting station name is sent in ASCII code is given to the fourth block. Since the ASCII code requires 8 bits as a binary code for each character, only 2 characters can be transmitted in the 4th block. Since the broadcasting station name is given in 8 characters in RDS, ASCII data for 8 characters can be obtained only after receiving the data 4 times. At this time, it is the program service name segment address codes C1 and C0 of the second block described above that determine which character of the eight characters the PS code currently being sent corresponds to. Therefore, on the receiving side, by demodulating the PS code four times, it is possible to demodulate the broadcasting station name consisting of eight characters. If the above-mentioned RDS is used, when the reception level of the broadcast program currently being received by the radio receiver becomes low, the AF code is used to switch the reception frequency to the frequency of another broadcasting station that is broadcasting the same program. , You can continue to enjoy listening to the radio of your desired program. By the way, as a radio receiver having a function of automatically switching a reception frequency to a frequency of another broadcasting station by using an AF code, for example, there is one shown in Japanese Patent Application Laid-Open No. 63-136830. When the reception level of the broadcast program currently being received drops, the conventional radio receiver stores the current reception frequency in the memory and sequentially scans the reception band. Then, when a broadcast frequency having an electric field strength equal to or higher than a certain level is found, scanning is stopped. Then, the RDS data from the broadcasting station corresponding to the broadcasting frequency is demodulated and the frequency list included in the demodulation is read. The frequency data included in this frequency list is sequentially compared with the frequency data stored in the memory in advance, and if there is a matching frequency data, the broadcast of the broadcasting station is continuously received. On the other hand, if there is no matching frequency data as a result of comparison, the scan in the reception band is continued, and the same operation as above is repeated until a matching frequency data is found. However, it takes about 7 seconds for only one station to read the frequency list included in the RDS data. With conventional receivers such as those described above, it is rare that an alternative station is first found by scanning within the receiving band. If it is found in the third station, it will take 21 seconds after the reception frequency switching request is made. This interrupts the playback of the program for a long period of time and makes the listener uncomfortable. In addition, there is a risk of missing an important program. (C) Problems to be solved by the invention Therefore, an object of the present invention is to shorten the time from the request for switching the reception frequency to the switching of the reception frequency to the frequency of another broadcasting station broadcasting the same program. (D) Means for solving problems To summarize the present invention, various service information is added to the broadcast signal received by the receiver in addition to the program information. This service information includes at least a list of frequency data of other stations broadcasting the same program as the one currently being broadcast. The receiver extracts service information from the received broadcast signal, and searches in advance for frequency data whose reception level is equal to or higher than a predetermined value based on a list of frequency data included in the service information. When it is determined that the reception state of the receiving means has deteriorated and a request for switching the receiving frequency is issued, the receiving frequency of the receiving means is controlled by the frequency data searched in advance, thereby transmitting the broadcast currently being received to another broadcast. Change to broadcasting the same program on the broadcasting station. (E) Action According to the present invention, frequency data having a good reception level among other broadcasting stations broadcasting the same program as the currently received broadcast program is searched in advance, so that the reception frequency is deteriorated due to the deterioration of the reception state. When a change request is issued, the reception frequency can be changed extremely quickly. (F) Example First, the configuration of the radio receiver according to the first embodiment of the present invention will be described with reference to FIG. In the figure, the signal induced in the antenna 1 is given to the first and second tuner circuits 2 and 3. In the first and second tuner circuits 2 and 3, each local oscillator circuit is composed of a PLL synthesizer, and the multiplexer 4 that AM demodulates and FM demodulates the signal input from the antenna 1 is the first tuner circuit 2. Separate the output signal into R (right) and L (left) signals. The output signal of the multiplexer 4 is given to the amplifier 5 and amplified. The output signal of the amplifier 5 is given to the two left and right speakers 6 and 6. The RDS decoder 7 demodulates the RDS data from the FM demodulated output of the second tuner circuit 3, reproduces the clock, and performs group synchronization and error correction of the demodulated RDSS data. The indicator 8 includes a frequency indicator 8A, an RDS lamp 8B and an AF lamp 8C, as shown in FIG. The display 8 is driven by the drive circuit 9. The A / D converters 10 and 11 A / D convert the electric field strength signals from the first and second tuner circuits 2 and 3, respectively. Preset keys 12 and 13, memory key 14, band key 15, AF key 16 are connected to I / O port 17. The preset keys 12 and 13 are keys for instructing the reading of frequency data stored in the corresponding area of the data memory 20, respectively. The memory key 14 is a key for storing the data of the current tuning frequency of the first tuner circuit 2 in the data memory 20. The band key 15 is a key for switching between the AM band and the FM band. The AF key 16 is a key for instructing the subsequent operation to the AF search mode or the AF display mode and the cancellation of the AF search mode or the AF display mode. The key code data obtained from each of these keys 12 to 16 is input to the data bus via the I / O port 17. The CPU 18 has the first and second tuner circuits 2 and 3, the RDS decoder 7, the drive circuit 9, the A / D converters 10 and 11, the program memory 19, the data memory 20, and the select memory 21 via the above data bus. Connected to timer 22. The CPU 18 controls each of the above circuits according to a program written in a program memory 19 composed of a ROM (read-only memory). The data memory 20 is composed of RAM (random access memory) and stores various data required for data processing of the CPU 18. As a storage area of particular interest to the present invention, the data memory 20 is an area for storing frequency data corresponding to the preset keys 12 and 13, respectively, to be transmitted to the local oscillator circuits of the first and second tuner circuits 2 and 3. It includes an area for storing the frequency list of AF stations (including up to 25 alternative frequency data) included in the RDS data, and an area for storing the PI code. The select memory 21 stores frequency data of a predetermined reception level or higher among the frequency data of the AF station stored in the data memory 20. The timer 22 is used for time measurement when detecting that the reception level of the first tuner circuit 2 has dropped for a certain period of time (for example, 22 seconds) or more. Next, the first First, after the power is turned on, the CPU 18 sets 0 in the flag register F1 (for example, provided inside the CPU 18) (step S1). After that, when the FM band is selected by the band key 15 and the preset key 12 or 13 is operated, the frequency data is read out from the storage area of the data memory 20 corresponding to the preset key 12 or 13, and the first, It is sent to the local oscillation circuit and the drive circuit 9 of the second tuner circuits 2 and 3. As a result, the first and second tuner circuits 2 and 3 are tuned to that frequency, and the frequency is displayed on the frequency indicator 8A (steps S2, 4 and 5). Next, the operation step shifts to step S6. In this step S6, it is determined whether or not the receiving station (broadcasting station corresponding to the tuning frequency of the tuner circuit) in the first and second tuner circuits 2 and 3 is an RDS station (broadcasting station transmitting RDS data). Will be done. Here, when the RDS decoder 7 detects a 57 KHz subcarrier, it outputs a predetermined signal, and this signal determines whether the received station is an RDS station. If the receiving station is an RDS station, the PI code is extracted from the RDS data and stored in the data memory 20 (step S7). Subsequently, the RDS lamp lighting signal is output to the drive circuit 9, and the RDS lamp 8B is lit (step S8). Next, the group type code and version code BO included in the RDS data are decoded, and this RDS data includes a list of frequency data of other broadcasting stations broadcasting the same program (hereinafter referred to as AF list). Whether or not it is determined (step S10). If the RDS data includes the AF list, the AF list is read for 7 seconds, and the frequency data of the AF stations are stored in the data memory 20 in ascending order (step S11). By the way, in reading the AF list, if the data indicating the number of frequency data of the AF station located at the head of the AF list is first received, the time required to read the AF list is minimized. However, the probability of receiving such data first is low. Therefore, it is difficult to determine how many frequency data are included in the AF list at the start of receiving the AF list. Therefore, the time required to read the frequency data of up to 25 AF stations is set in advance, and the AF list is forcibly read regardless of the number of frequency data within that time. If the number of frequency data included in the AF list is 24 or less, the same frequency data will be read repeatedly. In this case, it is judged whether the same data is stored and the same. If the data is stored, the CPU 18 does not store the data in the data memory 20. When the operation of step S11 is completed, the operation step proceeds to step S12. In this step S12, the contents of the flag register F1 are determined. When 0 is set in the flag register F1, the operation status of the preset keys 12, 13 and the AF key 16 is monitored in steps S13 and S15. When the preset keys 12 or 13 are operated, if the AF lamp 8C is lit, the AF lamp extinguishing signal is output to the drive circuit 9, and the AF list stored in the data memory 20 is cleared (step S14). , The operation step returns to step S5 described above. If the AF key 16 is operated, that operation Whether or not the time is 2 seconds or more is determined in step S16. As a result of this judgment, if the operation time of the AF key 16 is less than 2 seconds, the operation mode shifts to the AF search mode, and if it is 2 seconds or more, the operation mode shifts to the AF display mode. First, the operation in the AF search mode will be described. In this AF search mode, 1 is first set in the flag register F1 (step S17). After that, the RDS lamp blinking signal is output to the drive circuit 9, and the AF lamp 8C is in the blinking state (step S18). Subsequently, the operation step shifts to step S19, and the select memory 21 is cleared. Next, the operation status of the AF key 16, the band key 14, and the preset keys 12 and 13 is monitored (steps S20 to S22). If neither key is operated, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value based on the output of the A / D converter 10 (step S23). As a result of this determination, if the reception level of the first tuner circuit 2 is equal to or higher than the predetermined value, the timer 22 is cleared in step S24, and if it is less than the predetermined value, the timer 22 is counted in step S25 (note that this). The timer 22 performs a counting operation from the beginning if it is cleared, and continuously counts it if it is performing a counting operation). Next, one frequency data (excluding the current reception frequency of the first tuner circuit 2) is read from the AF list stored in the data memory 20 in ascending order and sent to the second tuner circuit 3 (step S26). ). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). If the operation time is less than 2 seconds, the operation mode shifts to the AF search mode, and if it is 2 seconds or more, the operation mode shifts to the AF display mode. First, the operation in the AF search mode will be described. In this AF search mode, 1 is first set in the flag register F1 (step S17). After that, the RDS lamp blinking signal is output to the drive circuit 9, and the AF lamp 8C is in the blinking state (step S18). Subsequently, the operation step shifts to step S19, and the select memory 21 is cleared. Next, the operation status of the AF key 16, the band key 14, and the preset keys 12 and 13 is monitored (steps S20 to S22). If neither key is operated, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value based on the output of the A / D converter 10 (step S23). As a result of this determination, if the reception level of the first tuner circuit 2 is equal to or higher than the predetermined value, the timer 22 is cleared in step S24, and if it is less than the predetermined value, the timer 22 is counted in step S25 (note that this). The timer 22 performs a counting operation from the beginning if it is cleared, and continuously counts it if it is performing a counting operation). Next, one frequency data (excluding the current reception frequency of the first tuner circuit 2) is read from the AF list stored in the data memory 20 in ascending order and sent to the second tuner circuit 3 (step S26). ). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). If the operation time is less than 2 seconds, the operation mode shifts to the AF search mode, and if it is 2 seconds or more, the operation mode shifts to the AF display mode. First, the operation in the AF search mode will be described. In this AF search mode, 1 is first set in the flag register F1 (step S17). After that, the RDS lamp blinking signal is output to the drive circuit 9, and the AF lamp 8C is in the blinking state (step S18). Subsequently, the operation step shifts to step S19, and the select memory 21 is cleared. Next, the operation status of the AF key 16, the band key 14, and the preset keys 12 and 13 is monitored (steps S20 to S22). If neither key is operated, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value based on the output of the A / D converter 10 (step S23). As a result of this determination, if the reception level of the first tuner circuit 2 is equal to or higher than the predetermined value, the timer 22 is cleared in step S24, and if it is less than the predetermined value, the timer 22 is counted in step S25 (note that this). The timer 22 performs a counting operation from the beginning if it is cleared, and continuously counts it if it is performing a counting operation). Next, one frequency data (excluding the current reception frequency of the first tuner circuit 2) is read from the AF list stored in the data memory 20 in ascending order and sent to the second tuner circuit 3 (step S26). ). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). In the AF search mode of, 1 is first set in the flag register F1 (step S17). After that, the RDS lamp blinking signal is output to the drive circuit 9, and the AF lamp 8C is in the blinking state (step S18). Subsequently, the operation step shifts to step S19, and the select memory 21 is cleared. Next, the operation status of the AF key 16, the band key 14, and the preset keys 12 and 13 is monitored (steps S20 to S22). If neither key is operated, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value based on the output of the A / D converter 10 (step S23). As a result of this determination, if the reception level of the first tuner circuit 2 is equal to or higher than the predetermined value, the timer 22 is cleared in step S24, and if it is less than the predetermined value, the timer 22 is counted in step S25 (note that this). The timer 22 performs a counting operation from the beginning if it is cleared, and continuously counts it if it is performing a counting operation). Next, one frequency data (excluding the current reception frequency of the first tuner circuit 2) is read from the AF list stored in the data memory 20 in ascending order and sent to the second tuner circuit 3 (step S26). ). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). In the AF search mode of, 1 is first set in the flag register F1 (step S17). After that, the RDS lamp blinking signal is output to the drive circuit 9, and the AF lamp 8C is in the blinking state (step S18). Subsequently, the operation step shifts to step S19, and the select memory 21 is cleared. Next, the operation status of the AF key 16, the band key 14, and the preset keys 12 and 13 is monitored (steps S20 to S22). If neither key is operated, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value based on the output of the A / D converter 10 (step S23). As a result of this determination, if the reception level of the first tuner circuit 2 is equal to or higher than the predetermined value, the timer 22 is cleared in step S24, and if it is less than the predetermined value, the timer 22 is counted in step S25 (note that this). The timer 22 performs a counting operation from the beginning if it is cleared, and continuously counts it if it is performing a counting operation). Next, one frequency data (excluding the current reception frequency of the first tuner circuit 2) is read from the AF list stored in the data memory 20 in ascending order and sent to the second tuner circuit 3 (step S26). ). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). It is monitored (steps S20 ~ S22). If neither key is operated, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value based on the output of the A / D converter 10 (step S23). As a result of this determination, if the reception level of the first tuner circuit 2 is equal to or higher than the predetermined value, the timer 22 is cleared in step S24, and if it is less than the predetermined value, the timer 22 is counted in step S25 (note that this). The timer 22 performs a counting operation from the beginning if it is cleared, and continuously counts it if it is performing a counting operation). Next, one frequency data (excluding the current reception frequency of the first tuner circuit 2) is read from the AF list stored in the data memory 20 in ascending order and sent to the second tuner circuit 3 (step S26). ). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). It is monitored (steps S20 ~ S22). If neither key is operated, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value based on the output of the A / D converter 10 (step S23). As a result of this determination, if the reception level of the first tuner circuit 2 is equal to or higher than the predetermined value, the timer 22 is cleared in step S24, and if it is less than the predetermined value, the timer 22 is counted in step S25 (note that this). The timer 22 performs a counting operation from the beginning if it is cleared, and continuously counts it if it is performing a counting operation). Next, one frequency data (excluding the current reception frequency of the first tuner circuit 2) is read from the AF list stored in the data memory 20 in ascending order and sent to the second tuner circuit 3 (step S26). ). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). As a result, the second tuner circuit 3 is tuned to this frequency. Then, based on the output of the A / D converter 11, it is determined whether or not the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value (step S27). As a result of this determination, if the reception level of the second tuner circuit 3 is equal to or higher than a predetermined value, the data of the current reception frequency of the second tuner circuit 3 is stored in the select memory 21 (step S28). After that, the operations of steps S20 to 28 described above are repeated until all the frequency data included in the AF list stored in the data memory 20 (excluding the data of the current reception frequency of the first tuner circuit 2) are read. (Step S29). When 25 frequency data are included in the AF list, the processing time of the routines in steps S20 to S29 is about 8 seconds. Here, when the AF key 16 is operated again, it is determined in step S20, and the operation step shifts to step S30. In this step S30, 0 is set in the flag register F1, the AF lamp extinguishing signal is output to the drive circuit 9, and the AF lamp 8C is extinguished. When the operation of step S30 is completed, the operation step returns to step S13 described above, and the AF search mode ends. Further, when the band key 15 is operated, this is determined in step S21, and the operation step shifts to step S31. In this step S31, the RDS lamp extinguishing signal and the AF lamp extinguishing signal are output to the drive circuit 9, and the RDS lamp 8B and the AF lamp 8C are extinguished. Subsequently, the operation step shifts to step S32, and the AF list stored in the data memory 20 is cleared. After that, the operation step returns to the above-mentioned step S2, and the AM mode processing is performed in step S3. Further, when the preset key 12 or 13 is operated, it is determined in step S22, and the operation step returns to step S14 described above. If it is determined in step S29 that all the frequency data included in the AF list stored in the data memory 20 has been read, the operation step proceeds to step S33. In this step S33, it is determined whether or not the frequency data of the AF station is stored in the select memory 21. As a result of this determination, if frequency data is stored in the select memory 21, the AF lamp lighting signal is output to the drive circuit 9, and the AF lamp 8C is lit (step S35). Subsequently, 1 is set in the flag register F2. (Step S36). On the other hand, as a result of the determination in step S33, if the frequency data is not stored in the select memory 21, 0 is set in the flag register F2 (step S34). When the operation of step S34 or S36 is completed, the operation step proceeds to step S37. In step S37, it is determined whether or not the timer 22 is counting for 22 seconds or more. As a result of the determination in step S37, if the timer 22 has not counted for 22 seconds or more, it is not necessary to change the reception frequency, so the operation step shifts to S38. In this step S38, the contents of the flag register F2 are determined. As a result of the determination in step S38, if 1 is set in the flag register F2, the operation step returns to S19, and if 0 is set, the operation step returns to step S18. That is, if there is frequency data whose reception level is equal to or higher than a predetermined value, the AF lamp 8C is lit and if it is not present, the AF lamp 8C is blinking. On the other hand, as a result of the determination in step S37, if the timer 22 counts for 22 seconds or more, it is necessary to change the reception frequency of the first tuner circuit 2, so the operation step shifts to step S39 and the flag register F2 The content is judged. As a result of the determination in step S39, if 0 is set in the flag register F2, the operation step returns to step S18 described above. In other words, if the reception level of the 1st tuner circuit 2 has dropped for a long time (22 seconds) but there is no alternative broadcasting station with good reception, the AF lamp 8C blinks to notify that fact. .. Such a situation occurs when a vehicle equipped with the receiver of this embodiment passes through a place having poor reception conditions such as a tunnel. On the other hand, if 1 is set in the flag register F2 as a result of the determination in step S39, one frequency data is read from the select memory 21 in ascending order and sent to the second tuner circuit 3 (step S40). As a result, the second tuner circuit 3 is tuned to that frequency. After the operation of step S40 is completed, the PI code extracted from the RDS data is compared with the PI code stored in advance in the data memory 20 (the PI code of the receiving station in the first tuner circuit 2) (step S41). ). As a result of comparison in step S41, if both PI codes match, the first and second tuner circuits 2 and 3 are receiving the same program, so the reception frequency data of the second tuner circuit 3 is the first. It is sent to the local oscillation circuit and the drive circuit 9 of the tuner circuit 2 (step S42). This causes the first tuner circuit 2 to tune to that frequency. The frequency is displayed on the frequency display 8A. After that, the timer 22 is cleared (step S43), and the operation step returns to the above-mentioned step S18. On the other hand, if both PI codes do not match, the same frequency data as the reception frequency in the second tuner circuit is deleted from the select memory 21 (step S44). After that, in step S45, the frequency data is stored in the select memory 21. It is judged whether or not it is. If the frequency data is stored in the select memory 21 as a result of the determination in step S45, the operation step returns to step S40 described above, and the operation of steps S40, S41, S44, and S45 continues until a PI code match is detected. It is repeated. If there is no frequency data remaining in the select memory 21 due to the repetition of the operations of steps S40, S41, S44, and S45, the operation step returns to step S18 described above. Next, the operation of the AF display mode when it is determined that the operation time of the AF key 16 by the AF key 16 is 2 seconds or more in the above-mentioned step S16 will be described. First, in step S46, 1 is set in the flag register F1. Subsequently, the operation step shifts to step S47, the AF lamp lighting signal is output to the drive circuit 9, and the AF lamp 8C is lit. Next, the operation step shifts to step S48, and one frequency data (excluding the reception frequency of the first tuner circuit 2) is read from the data memory 20 in ascending order and sent to the drive circuit 9. As a result, the frequency is displayed on the frequency display 8A. Next, the operation step shifts to step S49, and the timer 22 performs a counting operation from the cleared state. Next, the operation status of the preset keys 12, 13, the band key, the AF key 16, and the memory key 15 is monitored (steps S50 to S53). The frequency display on the frequency display 8A and the monitoring of the operation status of each key are performed until the timer 22 clocks 2 seconds (step S54). When it is determined in step S54 that the timer 22 has clocked 2 seconds, the operation step shifts to step S55, and it is determined whether or not all the frequency data included in the AF list stored in the data memory 20 has been read. Will be done. If there is frequency data that has not been read yet in the AF list, the operation step returns to step S48 again, and the next frequency data is displayed and the operation status of each key is monitored for 2 seconds (step S48 ~). S54). Here, when the preset keys 12 or 13 are operated, the operation is determined in step S50, and the operation step returns to step S14 described above. After that, the operation step returns to step S5 described above. When the band key 15 is operated, the operation is determined in step S51, the RDS lamp 8B and the AF lamp 8C are turned off, and the AF list of the data memory 20 is cleared (steps S56 and 57), and the operation is performed. The step returns to step S2 described above. When the AF key 16 is operated again, the operation is determined in step S52, and the operation step shifts to step S58. In this step S58, the AF lamp 8C is similarly turned off. Subsequently, in step S59, 0 is set in the flag register F1. Then, in step S60, the data of the current reception frequency of the first tuner circuit 2 is sent to the drive circuit 9, and the frequency is displayed on the frequency display 8A again. After the operation of step S60 is completed, the operation step returns to step S13 described above. If the preset keys 12 or 13 are operated after the memory key 14 is operated, those operations are determined in step S53, and the operation step shifts to step S61. In step S61, the data of the current reception frequency of the second tuner circuit 3 is stored in the storage area of the data memory 20 corresponding to the preset key operated at that time. After that, the operation step proceeds to step S54. When the display of all frequency data included in the AF list stored in the data memory 20 is completed, that is determined in step S55, and the operation step proceeds to step S62. In this step S62, the data of the current reception frequency of the first tuner circuit 2 is sent to the drive circuit 9, and the frequency is displayed on the frequency display 8A. After that, the operation step returns to the above-mentioned step S12, and shifts to the AF search mode. According to the first embodiment of the present invention described above, the reception level of the first tuner circuit 2 drops to a predetermined value or less for 22 seconds or more. Also, when the reception level of all frequency data included in the AF list is below the specified value, the AF lamp 8C is blinked, so the radio receiver operates normally even if good reception is not possible. It is possible to inform the user that the user is present. As a result, the user may feel uneasy whether the AF function is operating normally, that is, whether the radio receiver is operating normally when the radio receiver cannot receive well. It disappears. Furthermore, since either AF search mode (steps S17 to S45) or AF display mode (steps S46 to S62) is executed according to the AF key operation time, these operations can be performed with a small number of keys. The mode can be switched. Also, key operation becomes easy. Furthermore, once the AF key 16 is operated to switch to the AF search mode or AF display mode, even if there is a band change or frequency change in the middle, the operation mode is automatically set after the change operation is completed. It will shift to AF search mode. This is because 1 is set in the flag register F1 when shifting to the AF search mode or the AF display mode, so 1 is set in the flag register F1 in step S12 after the band change operation or the reception frequency change operation is completed. This is because it is determined that the operation step has been performed, and the operation step shifts to the AF search mode routine without waiting for the operation of the AF key 16. As a result, the user does not have to operate the AF key 16 every time the band is changed or the reception frequency is changed, and complicated key operations can be eliminated. If you want to switch the operation mode from the AF search mode to another mode, you can operate the AF key 16 again (steps S20 and S30). Further, in the first embodiment of the present invention, the count of the timer 22 is detected in step S37 every time the search for all the frequency data included in the AF list is completed once in steps S20 to S29. The rate at which the reception frequency can be changed to other broadcasting stations increases. However, if the time counting time of the timer 22 is 21 seconds after the execution of steps S20 to 29, the frequency data is searched again in steps S20 to S29, so that the processing time (up to about 8 seconds) is the reception frequency. The change will be delayed. To solve this problem, the CPU 18 monitors the time of the timer 22 even during the frequency data search, and if the time exceeds 22 seconds, even during the frequency data search. The change control of the reception frequency may be performed based on the frequency data searched up to now. Examples for realizing such an operation are shown in FIGS. 5A to 5D. 5A to 5D are flowcharts for explaining the operation of the second embodiment of the present invention. The hard circuit adopted in the second embodiment is the same as the hard circuit of the first embodiment described above (see FIG. 2). That is, the operation program written in the program memory 19 is only changed to the one shown in FIGS. 5A to 5D. Hereinafter, the operation of the second embodiment of the present invention will be described with reference to FIGS. 5A to 5D. First, when the preset key 12 or 13 is operated after the power is turned on, the operation is determined in step S101. Next, in step S102, frequency data is read from the storage area of the data memory 20 corresponding to the operated preset key, and sent to the local oscillator circuits and the drive circuit 9 of the first and second tuner circuits 2 and 3. To. As a result, the first and second tuner circuits 2 and 3 are tuned to the frequency, and the frequency is displayed on the frequency display 8A. After step S102 In step S103, it is determined whether or not the current receiving station in the second tuner circuit 3 is an RDS station. If the receiving station is not an RDS station, the operation step returns to step S101, but if the receiving station is an RDS station, the operation step shifts to step S104. In step S104, the PI code extracted from the RDS data by the RDS decoder 7 is stored in the data memory 20. After step S104 In step S105, the RDS lamp lighting signal is output to the drive circuit 9, and the RDS lamp 8B is lit. After step S105 In step S106, it is determined whether or not the AF list is included in the RDS data. If the RDS data does not include an AF list, the operation step returns to step S101. If the RDS data includes an AF list, in step S107, the AF list is read for 7 seconds and stored in the data memory 20. After step S107 In step S108, the frequency data stored in the data memory 20 is counted and the total number is set as N. Here, when the AF key 16 is operated, the operation is determined in step S109, and the operation step shifts to step S110. In step S110, the select memory 21 is cleared. After that, the AF lamp 8C blinks, the flag register F (for example, installed in CPU18) is set to 0, and the counter n (provided in CPU18 like flag register F) is set to 1. (Steps S111 to S113). After step S113 In step S114, it is determined whether or not the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value. If the reception level of the first tuner circuit 2 is equal to or higher than a predetermined value, the timer 22 is cleared in step S115. If the reception level of the first tuner circuit 2 is less than a predetermined value, the timer 22 is counted in step S116. After step S115 and after step S116, in step S117, the frequency data fn of the AF list in the area corresponding to the count value of the counter n is read from the data memory 20. After step S117 In step S118, it is determined whether or not the current reception frequency of the first tuner circuit 2 and the frequency data fn are the same. When both frequencies are the same, the operation step directly shifts to step S125 without performing the operations of steps S119 to S124 described below. On the other hand, when both frequencies do not match, in step S119, the frequency data fn is sent to the local oscillation circuit of the second tuner circuit 3, and the second tuner circuit is tuned to this frequency. After step S119 In step S120, it is determined whether or not the reception level of the second tuner circuit is equal to or higher than a predetermined value. When the reception level of the second tuner circuit is equal to or higher than the predetermined value, it is determined in step S121 whether or not the frequency data fn is already stored in the select memory 21. If the frequency data fn is not stored in the select memory 21, the frequency data fn is stored in the select memory 21 in step S122. After that, the operation step shifts to step S125. If the frequency data fn is stored in the select memory 21, the operation step shifts to step S125. On the other hand, when it is determined in step S120 that the reception level of the second tuner circuit 3 is less than a predetermined value, it is determined in step S123 whether or not the frequency data fn is already stored in the select memory 21. If the frequency data fn is already stored in the select memory 21, the frequency data fn is deleted from the select memory 21 in step S124, and then the operation step shifts to step S125. If the frequency data fn is not stored in the select memory 21, the operation step directly shifts to step S125. In step S125, the counter n is incremented by 1. Step after step S125 In S126, it is determined whether or not the timer 22 is timing for 22 seconds or more. If the timer 22 has not clocked for 22 seconds or more, in step S127, whether or not the count value of the counter n is N + 1, that is, whether or not the total number N of frequency data stored in the data memory 20 has been exceeded. Is judged. If the count value of the counter n is not N + 1, it is determined in step S128 whether or not 1 is set in the flag register F. Since this flag register F1 is set to 0 until the first search for all frequency data included in the AF list stored in the data memory 20 is completed, the operation step returns to step S114 described above. That is, until the first search is completed, the AF lamp 16 keeps blinking in the preparatory stage regardless of whether the frequency data is stored in the select memory 21. The preparation stage is about 8 seconds, and the request to change the reception frequency in the first tuner circuit 2 is not made during this period (because the timer 22 counts 22 seconds). When the operations of steps S114 to S128 above are repeatedly executed and the search for all frequency data in the AF list stored in the data memory 20 is completed, the count value of the counter n becomes N + 1, which is determined in step S127. Then, the operation step shifts to step S129. In step S129, flag register F is set to 1. After step S129 In step S130, it is determined whether or not frequency data is stored in the select memory 21. That is, as a result of searching the AF list, it is determined whether or not frequency data whose reception level is equal to or higher than a predetermined value is found. When the frequency data is stored in the select memory 21, the AF lamp 8C is turned on in step S131. After that, the operation step returns to step S113. On the other hand, when the frequency data is not stored in the select memory 21, the blinking display of the AF lamp is maintained in step S132. After that, the operation step returns to S113. In this way, when the first search for the AF list is completed, the display state of the AF lamp 8C is controlled according to the contents of the select memory 21. That is, when the AF lamp 8C is lit, the user can know that the frequency data that can be changed exists. When the first search for the AF list is completed and the second search cycle is entered, it is determined whether or not the frequency data is stored in the select memory 21 even during the search (step S128). , S133). Then, when the frequency data is stored in the select memory 21, the AF lamp 8C is turned on in step S134. If the frequency data is not stored in the select memory 21, the AF lamp 8C blinks in step S135. After the end of steps S134 and S135, the operation step returns to step S114. Next, in step S126 described above, the operation when it is determined that the timer 22 has clocked for 22 seconds or more, that is, the operation when it is determined that the reception frequency of the first tuner circuit 2 needs to be changed will be described. .. First, in step S136, it is determined whether or not the frequency data is stored in the select memory 21. If the frequency data is not stored in the select memory 21, the AF lamp 8C blinks in step S137 to notify the fact. After step S137 In step S138, it is determined whether or not the count value of the counter n is N + 1. That is, it is determined whether or not the reception frequency change request is made in the middle of the AF list search. When the count value of the counter n is N + 1, the operation step returns to step S113 described above. That is, after the counter n is set to 1, the search for the AF list is performed again. On the other hand, if the count value of the counter n is not N + 1, the operation step returns to step S114. In this case, the search for the AF list is restarted without the counter n being initialized. On the other hand, if it is determined in step S136 that the frequency data is stored in the select memory 21, the AF lamp 8C is turned on in step S139. After step S139 In step S140, one frequency data is read from the select memory 21 in ascending order of frequency and sent to the local oscillation circuit of the second tuner circuit 3. As a result, the reception frequency of the second tuner circuit 3 is switched to that frequency. After step S140 In step S141, whether or not the PI code included in the RDS data of the reception output of the second tuner circuit 3 matches the PI code of the reception broadcast of the first tuner circuit 2 stored in the data memory 20 in advance. Is judged. That is, it is determined whether or not the second tuner circuit 3 receives the same program as the first tuner circuit 2. When both PI codes match, in step S142, the reception frequency of the second tuner circuit 3 is sent to the local oscillation circuit of the first tuner circuit 2, and the timer 22 is cleared. As a result, the first tuner circuit 2 is switched to the same reception frequency as the second tuner circuit 3. After step S142 In step S143, the reception frequency of the second tuner circuit 3 is deleted from the select memory 21. After step S143 In step S144, it is determined whether or not there is frequency data remaining in the select memory 21. If frequency data remains, the operation step proceeds to step S138. If no frequency data remains, the operation step proceeds to step S137, and the AF lamp 8C blinks. On the other hand, when the PI code mismatch is determined in step S141, the reception frequency of the second tuner circuit 3 is deleted from the select memory 21 in step S146. After step S146 In step S147, it is determined whether or not frequency data remains in the select memory 21. If frequency data remains, the operation step returns to step S140 and the next frequency data is read from the select memory 21 again. Will be done. On the other hand, if no frequency data remains in the select memory 21, the operation step proceeds to step S137. In the second embodiment of the present invention described above, it is determined whether or not there is a request to change the reception frequency even during the search for the AF list stored in the data memory 20 (step S126). Therefore, in the first embodiment described above, a delay of up to 8 seconds has occurred since the request for changing the reception frequency was made, but according to this second embodiment, such a delay time should not occur. It is possible to respond to a request to change the reception frequency. The flowchart of the second embodiment describes the main parts, and actually monitors the operations of the preset keys 12, 13, the memory key 14, the band key 15, and the AF key 16 at the same timing as the first embodiment. To do. This can be said in common with the third, fourth, fifth, and sixth embodiments described later. FIG. 6 is a block diagram showing a configuration of a radio receiver according to a third embodiment of the present invention. In the figure, a switch circuit SW is provided between the first and second tuner circuits 2 and 3 and the multiplexer 4 and the RDS decoder 7. This switch circuit SW performs a switching operation in response to a switching signal given from the CPU 18 via the I / O port 17 and the data bus. That is, in the first mode, as shown by the solid line in FIG. 6, the first tuner circuit 2 and the multiplexer 4 are connected, and the second tuner circuit 3 and the RDS decoder 7 are connected. In the second mode, as shown by the dotted line in FIG. 6, the first tuner circuit 2 and the RDS decoder 7 are connected, and the second tuner circuit 3 and the multiplexer 4 are connected. Other configurations are the same as those of the first embodiment shown in FIG. 2, and the same reference numbers are assigned to the corresponding parts, and the description thereof will be omitted. The third embodiment basically performs the same operation as the first embodiment described above, except for the following points. First, when the switch SW is connected like a solid line in the first mode, the first tuner circuit 2 receives a normal broadcast program, and the second tuner circuit 3 searches for frequency data. .. In this state, when the reception level of the first tuner circuit 2 drops below a predetermined level for 22 seconds, the frequency data read from the select memory 21 is given to the second tuner circuit 3. Then, when the PI code of the receiving station in the first tuner circuit 2 and the PI code of the receiving station in the second tuner circuit 3 match, the switch SW is switched to a state like a dotted line by the switching signal, and the second tuner circuit 3 is used. Move to mode. In this second mode, the first tuner circuit 2 searches for frequency data, and the second tuner circuit 3 receives a normal broadcast program. After that, each time the reception frequency of the tuner circuit on the side receiving the normal broadcast program is changed, the first mode and the second mode are alternately switched. In the first embodiment described above, after tuning the second tuner circuit 3 with the frequency data read from the select memory 21, if the PI codes match, the reception frequency data of the second tuner circuit 3 is first. It is sent to the tuner circuit 2 and the reception frequency of the first tuner circuit is changed. Therefore, the tuning time of the first tuner circuit 2 becomes the loss time when the frequency is changed. However, in the third embodiment, only the switching time of the switch circuit SW becomes the loss time, and the reception frequency can be changed more quickly than in the first embodiment. Of course, the third embodiment can be applied to the second embodiment described above. In the first to third embodiments described above, RDS data processing and normal broadcast program reception processing are performed by one CPU 18. Therefore, the CPU 18 requires an expensive microprocessor with high processing power. Therefore, it is desirable to use two microprocessors, share the processing for each, and transfer data between the respective microprocessors. Such an embodiment is shown in FIG. In the fourth embodiment shown in FIG. 7, a first microprocessor 18a and a second microprocessor 18b are provided. The first microprocessor 18a is provided for normal broadcast program reception processing, and performs the following processing according to a program written in the program memory 19a configured by ROM. That is, the first microprocessor 18a monitors the operation status of the preset keys 12 and 13, the memory key 14, the band key 15, and the AF key 16, exchanges data with the data memory 20a, and locally oscillates the first tuner circuit 2. It performs processing such as sending frequency data to and transferring data to and from the second microprocessor 18b. Further, the first microprocessor 18a detects the reception level of the first tuner circuit 2 based on the output of the A / D converter 10, and if this reception level drops to a predetermined level or more for 22 seconds or more, the first microprocessor 18a is used. 1 Outputs the change command signal of the reception frequency of the tuner circuit 2 to the second microprocessor 18b. On the other hand, the second microprocessor 18b is for processing RDS data, and performs the following processing according to the program written in the program memory 19b composed of ROM. That is, the second microprocessor 18b transfers data with the first microprocessor 18a, processes RDS data, exchanges data with the data memory 20b and the select memory 21b, and locally oscillates and drives the second tuner circuit 3. Sends frequency data to. The data memory 20b has an area for storing up to 25 frequency data included in the AF list and an area for storing the PS code and the PI code, similarly to the data memory 20 shown in FIG. Further, the select memory 21b stores frequency data whose reception level is equal to or higher than a predetermined value among the frequency data stored in the data memory 20b, similarly to the select memory 21 shown in FIG. The other configurations of the embodiment shown in FIG. 7 are the same as the configurations of the first embodiment shown in FIG. 2, and the same reference numbers are assigned to the corresponding parts, and the description thereof will be omitted. .. Next, the operation of the fourth embodiment will be described with reference to FIGS. 8A to 8C. The flowcharts of FIGS. 8A to 8C show the operation of the second microprocessor 18b, and are written in the program memory 19b as program information. First, when the preset key 12 or 13 is operated in the FM band after the power is turned on, the first microprocessor 18a reads the frequency data corresponding to the preset key from the data memory 20a, and the first tuner circuit 2 It is given to the local oscillation circuit and the second microprocessor 18b. When the second microprocessor 18b determines in step S201 that the frequency data has been transferred from the first microprocessor 18a, the second microprocessor 18b performs the following operations. First, in step S202, the frequency data received from the first microprocessor 18a is given to the local oscillation circuit and the drive circuit 9 of the second tuner circuit 3. As a result, the second tuner circuit 3 is tuned to the frequency, and the frequency is displayed on the frequency display 8A. Next, in step S203, it is determined whether or not the station is the receiving station or the RDS in the second tuner circuit 3. If the receiving station is an RDS station, the PI code extracted by the RDS decoder 7 at that time is stored in the data memory 20b in step S204. After step S204 In step S205, the RDS lamp lighting signal is output to the drive circuit 9, and the RDS lamp 8B is lit. Next, in step S206, it is determined whether or not the AF list is included in the RDS data output from the RDS decoder 7. If the RDS data does not include an AF list, it is determined in step S207 whether the RDS data contains a PS code. If the RDS data contains a PS code, in step S208, the PS code is read for 7 seconds and stored in the data memory 20b. After step S208 In step S209, the broadcasting station name is displayed on the frequency display 8A based on the PS code stored above. After that, the operation step returns to step S201. On the other hand, in step S206 described above, if it is determined that the RDS data includes the AF list, in step S210, the PS code and A for 7 seconds. The F list is read and stored in data memory 20b. When the AF list is included in the RDS data, the PS code is always included. After step S210 In step S211, the broadcasting station name is displayed on the frequency display 8A based on the PS code stored above. In step S212 after step S211, the total number of frequency data included in the AF list stored in the data memory 20b at that time is set as N. When the AF key 16 is operated in this state, the first microprocessor 18a outputs an AF command signal to the second microprocessor 18b. When the input of the AF command signal from the first microprocessor 18a is determined by the second microprocessor 18b (step S213), the AF lamp 8C blinks in step S214. After step S214, the select memory 21b is cleared and the counter n is set to 1 (steps S215, S216). After step S216 In step S217, it is determined whether or not the return data regarding the reception of frequency data has been transferred from the first microprocessor 18a. When there is no data transfer from the first microprocessor 18a, frequency data whose reception level is equal to or higher than a predetermined value is searched from the frequency data stored in the data memory 20b and stored in the select memory 21b (step S217 ~). S224). That is, the frequency data fn corresponding to the count value of the counter n is read from the data memory 20b, the second tuner circuit 3 is tuned with the read frequency data, and as a result, the reception level of the second tuner circuit is equal to or higher than the predetermined value. In the case of, the frequency data fn is stored in the select memory 21b. After that, the value of the counter n is updated by 1, and the above operation is repeated until the value becomes N. If the frequency data fn read from the data memory 20b and the reception frequency of the first tuner circuit 2 match, the reception level of the second tuner circuit 3 is not determined (step S219). When it is determined in step S223 that the value of the counter n has reached N, that is, when it is determined that the search for all frequency data stored in the data memory 20b has been completed, the select memory 21b is set in step S225. Whether or not the frequency data is stored is determined. If the frequency data is not stored in the select memory 21b, the operation step returns to step S214 again, and the search operation for frequency data whose reception level is equal to or higher than a predetermined value is repeated. On the other hand, when the frequency data is stored in the select memory 21b, the AF lamp 8C is turned on in step S226 to indicate that the frequency data that can be changed exists. After step S226 In step S227, it is determined whether or not there is a reception frequency change command from the first microprocessor 18a. If there is no command to change the reception frequency from the first microprocessor 18a, the second microprocessor 18b repeats the operations of steps S215 to S227 again. When the first microprocessor 18a detects that the reception level of the first tuner circuit 2 has dropped to a predetermined value or less for 22 seconds or more by the built-in timer, it outputs a reception frequency change command to the second microprocessor 18b. The second microprocessor 18b performs the following operations in response to the reception frequency change command from the first microprocessor 18a. That is, in step S228, one frequency data is read from the select memory 21b in ascending order of frequency and sent to the local oscillation circuit of the second tuner circuit 3. As a result, the second tuner circuit 3 is tuned to that frequency. After step S228 In step S229, the PI code extracted by the RDS decoder 7 at that time is compared with the PI code stored in advance in the data memory 20b (the PI code of the receiving station in the first tuner circuit 2). .. If both PI codes match (when the first tuner circuit 2 and the second tuner circuit 3 receive the same program), the data of the reception frequency of the second tuner circuit 3 in step S230. Is sent to the first microprocessor 18a. On the other hand, if both PI codes do not match, the frequency data given to the second tuner circuit 3 is deleted from the select memory 21b in step S231. After step S231 In step S232, it is determined whether or not frequency data is stored in the select memory 21b. If the frequency data is stored in the select memory 21b, the operation step returns to step S228 again, and the next frequency data is read from the select memory 21b. On the other hand, if the frequency data is not stored in the select memory 21b, the operation step returns to step S214 described above. Next, the second microprocessor 18b is the data from the first microprocessor 18a after the operation of step S230 (data indicating that the first tuner circuit 2 is tuned with the frequency data received from the second microprocessor 18b). While monitoring the return of the data in step S217, the frequency data whose reception level is equal to or higher than the predetermined value is searched until this data is returned (steps S214 to S227). Next, the first microprocessor 18a tunes the first tuner circuit 2 to that frequency based on the frequency data received from the second microprocessor 18b in step S230 described above. When the first tuner circuit 2 tunes to that frequency, the first microprocessor 18a sends data to the second microprocessor 18b that the first tuner circuit 2 has been tuned. When the second microprocessor 18b determines in step S217 that the return of the above data from the first microprocessor 18a is determined, the frequency data search is interrupted and the following operations are performed. That is, in step S233, the frequency data given to the first tuner circuit 2 is given to the local oscillation circuit and the drive circuit 9 of the second tuner circuit 3. As a result, the second tuner circuit 3 is tuned to that frequency, and the frequency indicator 8A displays the frequency. After step S233 In step S234, it is determined whether or not the RDS data extracted by the RDS decoder 7 contains the PS code. If the RDS data contains a PS code, in step S235, the PS code is read for 7 seconds and stored in the data memory 20b. After step S235 In step S236, the broadcasting station name is displayed on the frequency display 8A based on the PS code stored above. After that, the operation step returns to step S218, and the interrupted search for frequency data is resumed. As described above, in the fourth embodiment, after the frequency data for change is transferred from the second microprocessor 18b to the first microprocessor 18a, the data is transferred from the first microprocessor 18a to the second microprocessor 18b. The second microprocessor 18b searches for frequency data even until it is returned (data indicating that the first tuner circuit 2 is tuned with the frequency data). Therefore, the response time in the data transfer between the first microprocessor 18a and the second microprocessor 18b can be effectively used without waste. FIG. 9 is a block diagram showing a configuration of a fifth embodiment of the present invention. This fifth embodiment includes only one tuner circuit 2'as a receiving means. The receive output of the tuner circuit 2'is given to the multiplexer 4 and to the RDS decoder 7. In addition, the reception level of the tuner circuit 2'is detected by the A / D converter 11'. The tuner circuit 2'is alternately switched between a first mode for receiving a normal broadcast program and a second mode for searching frequency data in the AF list by the CPU 18. A first timer 22a is provided to measure the time when switching between the first and second modes. The first timer 22a is connected to the CPU 18 via the data bus. Similar to the timer 22 in FIG. 2, the second timer 22b is used for measuring the time when detecting that the reception level of the tuner circuit 2'has dropped to a predetermined value or less for 22 seconds or more. This second timer 22b is connected to the CPU 18 via the data bus. Further, the amplifier 5'is given a muting pulse from the CPU 18 via the I / O port 17. Other configurations are the same as those of the first embodiment shown in FIG. 2, and the same reference numbers are assigned to the corresponding parts, and the description thereof will be omitted. Before explaining the detailed operation of the fifth embodiment, the schematic operation will be described. In the fifth embodiment, the reception of a normal broadcast program in the tuner circuit 2'is interrupted at regular intervals, and the frequency data fn (n = 1, 2) from the AF list stored in the data memory 20 at the time of the interruption is interrupted. ...) is read and the tuner circuit 2'is tuned with the frequency data. Then, the reception level of the tuner circuit 2'is detected, and if it is equal to or higher than a predetermined level, the frequency data at that time is stored in the select memory 21. The switching timing of the reception mode in the tuner circuit 2'is shown in FIG. 10A. That is, every time a normal broadcast program is received (reception by the frequency data fp selected by the preset key 12 or 13) for 0.5 s, the program playback from the speaker 6 is interrupted by the muting pulse for 6 ms. As shown in FIG. 10B, in the first half (3ms) of the interruption period of 6ms, the frequency data fn (n = 1, 2 ...) read from the data memory 20 is given to the tuner circuit 2'. The tuner circuit 2'is tuned to that frequency. In the latter half of the interruption period (3ms), the original frequency data fp is given to the tuner circuit 2'again. The reason why muting is performed during the latter half of 3 ms is that noise is generated in the received output of the tuner circuit 2'when the reception frequency is switched, as shown in FIG. 10B. Next, the operation of the fifth embodiment will be described with reference to FIGS. 11A to 11C. First, when the power is turned on, it is determined in step S301 whether or not the preset keys 12 or 13 have been operated. When the preset key 12 or 13 is operated, in step S302, the frequency data fp corresponding to the preset key is read from the data memory 20 and given to the local oscillator circuit and the drive circuit 9 of the tuner circuit 2'. This tunes the tuner circuit 2'to that frequency and displays that frequency on the frequency indicator 8A. After that, in steps S303 to S315, the same operations as in steps S203 to 215 of FIGS. 8A and 8B in the above-described fourth embodiment are performed except for the processing of the PS code. That is, it is determined whether or not the receiving station in the tuner circuit 2'is an RDS station, and if it is an RDS station, the PI code and the AF list are stored in the data memory 20, and the AF key 16 is operated. , AF lamp 8C blinks and select memory 21 is cleared. After step S315 In step S316, the counter n is set to 1 and the flag register F is set to 0. After step S316, in step S317, the frequency data fn is read from the storage area of the data memory 20 corresponding to the counter n. After step S317 In step S318, it is determined whether or not the frequency data fp and the frequency data fn match. Here, the frequency data fp is the frequency data selected by the operation of the preset key 12 or 13. If the frequency data fp and fn do not match, the first timer 22a is started from the clear state in step S319. This initiates the 3ms timekeeping in the first half of the suspension period described above. In step S320 after step S319, a muting pulse is applied to the amplifier 5'. As a result, the amplifier 5'mute the input audio signal. After step S320 In step S321, the frequency data fn read from the data memory 20 is given to the local oscillator circuit of the tuner circuit 2'. This causes the tuner circuit 2'to tune to that frequency. After step S321 In step S322, it is determined whether or not the time counting time of the first timer 22a has reached 3 ms. When the time counting time of the first timer 22a reaches 3 ms, in step S323, it is determined whether or not the reception level of the tuner circuit 2'is equal to or higher than a predetermined value based on the output of the A / D converter 11'. When the reception level of the tuner circuit 2'is equal to or higher than a predetermined value, the frequency data fn is stored in the select memory 21 in step S324. After that, the operation step proceeds to step S325. On the other hand, when the reception level of the tuner circuit 2'is less than a predetermined value, the select memory 21 directly shifts to step S325 without storing several data fn. In step S325, it is determined whether or not the value of the counter n has become N. That is, it is determined whether or not the search for all frequency data of the AF list stored in the data memory 20 has been completed. If the value of the counter n is not N, that is, if the frequency data to be searched remains in the data memory 20, 1 is incremented by the counter n in step S326. After step S326 In step S327, the first timer 22a is started from the cleared state. This initiates the second half of the 3ms timekeeping during the aforementioned interruption period. After step S327 In step S328, the frequency data fp is read from the data memory 20 and given to the local oscillator circuit of the tuner circuit 2'. This causes the tuner circuit 2'to tune to that frequency. After step S328 In step S329, it is determined whether or not the first timer 22a clocks 3 ms. When the first timer 22a clocks 3 ms, the muting operation in the amplifier 5 is canceled in step S330. As a result, the broadcast program is played back from the speaker 6. After step S330 In step S331, the first timer 22a is restarted from the cleared state. As a result, the timing of 0.5 s of the reception period of the normal broadcast program is started. After step S331 In step S332, whether or not the reception level of the tuner circuit 2'is equal to or higher than a predetermined value is determined based on the output of the A / D converter 11'. If the reception level of the tuner circuit 2'is less than a predetermined value, the second timer 22b is started in step S333. On the other hand, when the reception level of the tuner circuit 2'is equal to or higher than a predetermined value, the second timer 22b is cleared in step S334. After the control operation of the second timer 22b in steps S333 and S334, it is determined in step S335 whether or not the first timer 22a clocks 0.5s. The first timer 22a is 0. When 5s is clocked, it is determined in step S336 whether or not 1 is set in the flag register F. Since 1 is not set in the flag register F until all frequency data of the AF list stored in the data memory 20 is searched, the operation step proceeds to step S317. Then, a search is performed for the remaining frequency data in the data memory 20. When the search for all frequency data included in the AF list stored in the data memory 20 is completed, the value of the counter n becomes N. Therefore, this is determined in step S325, and the operation step shifts to step S337. .. In step S337, the flag register F is set to 1. After step S337 In step S338, it is determined whether or not frequency data is stored in the select memory 21. If the frequency data is not stored in the select memory 21, the AF lamp 8C blinks in step S339. Then, the operation step shifts to step S327. In this case, after the operation of steps S327 to S335, it is determined that 1 is set in the flag register F in step S336, so the operation step shifts to step S315. Therefore, after the select memory 21 is cleared, the counter n is set to 1, and the flag register F is set to 0, the frequency data search is restarted from the initial state. On the other hand, if it is determined in step S338 that the frequency data is stored in the select memory 21, the AF lamp 8C is turned on in step S340. After step S340 In step S341, whether or not the second timer 22b is timing for 22 seconds or more, that is, whether or not the reception level of the normal broadcast program in the tuner circuit 2'has dropped to a predetermined level or more for 22 seconds or more. Judged. If the second timer 22b has not timed for 22 seconds or more, it is not necessary to change the reception frequency when receiving a normal broadcast program, so the operation step proceeds to step S327. On the other hand, when the second timer 22b is counting for 22 seconds or more, the reception state of the tuner circuit 2'when receiving a normal broadcast program has deteriorated. Therefore, the normal broadcast of the tuner circuit 2'is performed by the following operation. The reception frequency is changed when the program is received. That is, in step S342, the first timer 22a is started from the clear state. After step S342 In step S343, one frequency data is read from the select memory 21 in ascending order of frequency and given to the local oscillator circuit of the tuner circuit 2'. This causes the tuner circuit 2'to tune to that frequency. After step S343 In step S344, the PI code extracted by the RDS decoder 7 is read. This PI code reading continues until the first timer 22a clocks 0.2s (step S345). The reason why the reading time of the PI code is set to 0.2s is that the PI code is sent 11 times per second, so it is 0. It is based on the reason that 2s is enough to read. When the reading of the PI code is completed in step S345, the PI code is checked in step S346. That is, does the PI code (PI code at the time of receiving a normal broadcast program) previously stored in the data memory 20 in step S304 described above match the PI code obtained from the current reception output of the tuner circuit 2'? Whether or not it is judged. If both PI codes do not match, the data of the reception frequency at that time in the tuner circuit 2'is deleted from the select memory 21 in step S347. Then, in step S348, it is determined whether or not frequency data remains in the select memory 21, and if so, the next frequency data is read from the select memory 21 and the PI code is checked (step S342 ~). S346). If no PI code match is detected even if all the frequency data stored in the select memory 21 is read out and the tuner circuit 2'is tuned and controlled, it is determined in step S348 that there is no remaining frequency data in the select memory 21. , AF lamp 8C blinks in step S349. After that, the operation step shifts to step S327, the tuner circuit 2 is tuned again at fp, and the frequency data search is restarted from the initial state. On the other hand, if it is determined in step S346 that the PI codes match, the reception frequency data is changed in step S350. That is, the frequency data fp (frequency data based on the operations of the preset keys 12 and 13) up to that point is replaced by the frequency data f read from the select memory 21 at that time. Hereinafter, this frequency data f is treated as frequency data fp. Therefore, the reception frequency at the time of receiving a normal broadcast program is changed to this frequency data f. After step S350 In step S351, the AF lamp 8C blinks, the second timer 22b is cleared, and then the operation step moves to step S330. To do. Then, the frequency data search is restarted from the initial state. In the above configuration, the time required for the processing of steps S319 to 323 or the processing of steps S319 to 321, 333 to 337, and 323 during the time counting by the first timer 22a is very short as compared with 3 ms. In the fifth embodiment, similarly to the first embodiment described above, the time counting time of the second timer 22b is set each time the search for all frequency data of the AF list stored in the data memory 20 is completed. It is determined (step S341), and it is determined whether or not it is necessary to change the reception frequency at the time of receiving a normal broadcast program. Therefore, when it is determined that the reception frequency should be changed, there is a high possibility that frequency data having a reception level equal to or higher than a predetermined value exists in the select memory 21, and the changeability rate of the reception frequency is high. However, in this fifth embodiment as well as in the first embodiment described above, if the search for one cycle is completed immediately before the second timer 22b clocks 22 seconds, the frequency data search is again in the initial state. Will be repeated from. Therefore, the reception frequency change process is delayed by the time required for one cycle of search (in the fifth embodiment, if the AF list contains 25 frequency data, about 13 seconds). .. A sixth embodiment of the present invention capable of solving such a problem is shown in FIGS. 12A to 12D. 12A to 12D are flowcharts for explaining the operation of the sixth embodiment of the present invention. The hard circuit adopted in the sixth embodiment is the same as the hard circuit of the fifth embodiment described above (see FIG. 9). That is, the operation program written in the program memory 19 is only changed to that shown in FIGS. 12A to 12D. Hereinafter, the operation of the sixth embodiment of the present invention will be described with reference to FIGS. 12A to 12D. First, when the preset key 12 or 13 is operated after the power is turned on, the frequency data fp corresponding to the preset key is read from the data memory 20 and given to the local oscillator circuit and the drive circuit 9 of the tuner circuit 2'(). Steps S401, S402). As a result, the tuner circuit 2'is tuned to the frequency, and the frequency is displayed on the frequency display 8A. Next, when the receiving station of the tuner circuit 2'at that time is an RDS station, the PI code included in the RDS data is stored in the data memory 20 and the RDS lamp 8B is turned on (steps S403 to ~). S405). Subsequently, it is determined whether or not the RDS data extracted by the RDS decoder 7 includes the AF list, and if the AF list is included, the AF list is read for 7 seconds and stored in the data memory 20. (Steps S406, S407). Next, the total number of frequency data included in the AF list stored in the data memory 20 is set as N (step S408). Here, when the AF key 16 is operated, the AF lamp 8C blinks and the select memory 21 is cleared (steps S409 to S411). Subsequently, 0 is set in the flag register F1 (step S412). In addition, 0 is set in the flag register F2 and 1 is set in the counter n (step S413). Subsequently, the frequency data fn corresponding to the coefficient value of the counter n is read from the data memory 20, and whether this frequency data fn and the above-mentioned frequency data fp (frequency data based on the operations of the preset keys 12 and 13) match. Whether or not it is determined (steps S414, S415). If the frequency data fn and fp do not match, the first timer 22a is started from the clear state, and the muting of the amplifier 5 is started (steps S416 and S417). Subsequently, the frequency data fn is given to the local oscillator circuit of the tuner circuit 2'(step S418). This causes the tuner circuit 2'to tune to that frequency. In this state, when the first timer 22a clocks 3 ms, it is determined whether or not the reception level of the tuner circuit 2'is equal to or higher than a predetermined value based on the output of the A / D converter 11'(step S420). As a result of this determination, if the reception level of the tuner circuit 2'is equal to or higher than the predetermined value, the frequency data fn is stored in the select memory 21, and if it is less than the predetermined value, the frequency data fn is deleted from the select memory 21 (step S421). ~ S424). However, if the frequency data fn is already stored in the select memory 21, the frequency data fn is not stored, and if the frequency data fn is not stored in the select memory 21, the frequency data fn is not deleted. After the processing of steps S421 to S424, the operation step shifts to step S425. If it is determined in step S415 described above that the frequency data fp and fn match, the operation step directly shifts to this step S425. In step S425, the counter n is incremented by 1. Then, of the counter n Whether or not the value is N + 1 is determined (step S426). If the value of the counter n is not N + 1, one cycle of the search has not been completed, and the operation step proceeds to step S428. On the other hand, when the value of the counter n is N + 1, since one cycle of the search is completed, 1 is set in the flag registers F1 and F2, respectively (step S427). After that, the operation step shifts to step S428. In step S428, it is determined whether or not 1 is set in the flag register F1. When 1 is set in the flag register F1, the display control of the AF lamp 8C is performed according to whether or not the frequency data is already stored in the select memory 21 (steps S429 to S431). That is, the AF lamp 8C is lit when the frequency data is stored in the select memory 21, and the AF lamp 8C is blinked when the frequency data is not stored. On the other hand, if 0 is set in the flag register F1, the first search cycle has not ended, so even if frequency data is stored in the select memory 21, the AF lamp 8C is ready to blink. Maintained as a state. The maximum preparation state is about 13 seconds, and in this state, the reception frequency switching request in the first mode is not made (because the second timer 22b counts 22 seconds). The display control of the AF lamp 8C is performed according to whether or not the AF lamp is towed (steps S429 to S431). That is, the AF lamp 8C is lit when the frequency data is stored in the select memory 21, and the AF lamp 8C is blinked when the frequency data is not stored. On the other hand, if 0 is set in the flag register F1, the first search cycle has not ended, so even if frequency data is stored in the select memory 21, the AF lamp 8C is ready to blink. Maintained as a state. The maximum preparation state is about 13 seconds, and in this state, the reception frequency switching request in the first mode is not made (because the second timer 22b counts 22 seconds). The display control of the AF lamp 8C is performed according to whether or not the AF lamp is towed (steps S429 to S431). That is, the AF lamp 8C is lit when the frequency data is stored in the select memory 21, and the AF lamp 8C is blinked when the frequency data is not stored. On the other hand, if 0 is set in the flag register F1, the first search cycle has not ended, so even if frequency data is stored in the select memory 21, the AF lamp 8C is ready to blink. Maintained as a state. The maximum preparation state is about 13 seconds, and in this state, the reception frequency switching request in the first mode is not made (because the second timer 22b counts 22 seconds). Next, the first timer 22a is started from the cleared state, and the time counting of 3 ms in the latter half of the interruption period shown in FIG. 10B is started (step S432). Subsequently, the tuning control of the tuner circuit 2'is performed by the frequency data fp (step S433). After that, when the first timer 22a clocks 3 ms, the muting state is released (steps S434 and S435). After step S435, in step S436, the first timer 22a is started again from the cleared state, and the time counting operation of 0.5 s at the time of receiving a normal broadcast program is started. Next, it is determined whether or not the reception level of the tuner circuit 2'is equal to or higher than the predetermined value. If it is less than the predetermined value, the second timer 22b is counted, and if it is equal to or higher than the predetermined value, the second timer 22b is cleared. (Steps S437 to S439). After that, in step S440, it is determined whether or not the second timer 22b is timing for 22 seconds or more. If the second timer 22b has not clocked for 22 seconds or more, it is not necessary to change the reception frequency. Therefore, after the first timer 22a clocks for 0.5 seconds, it is determined whether or not 1 is set in the flag register F2. Is done (steps S441, S442). At this time, if 0 is set in the flag register F2, the operation step returns to step S414, and the search is performed for the remaining frequency data in the AF list stored in the data memory 20. On the other hand, if 1 is set in the flag register F2, the operation step returns to step S413. That is, in this case, since the search for all frequency data included in the AF list stored in the data memory 20 is completed, the search is restarted from the first frequency data again. On the other hand, in step S440, when it is determined that the second timer 22b has clocked for 22 seconds or more, the following reception frequency change processing is performed. First, in step S443, it is determined whether or not the frequency data is stored in the select memory 21. If the frequency data is not stored in the select memory 21, the frequency data with a good reception level does not exist, so the operation step returns to step S441, and the frequency data search is repeated again. If frequency data exists in the select memory 21, muting in the amplifier 5 is started, and the first timer 22a is started from the cleared state (steps S444 and S445). Next, one frequency data f is read from the select memory 21 in ascending order of frequency and given to the local oscillator circuit of the tuner circuit 2'(step S446). Therefore, the tuner circuit 2'is tuned to the frequency f. Next, the PI code is read until the first timer 22a clocks 0.2s (step S447, S448). Next, the PI code corresponding to the frequency data f (PI code read in step S447) and the PI code corresponding to the frequency data fp (PI code stored in the data memory 20 in step S404 described above) match. Whether or not it is judged. If both PI codes match, the frequency data f is deleted from the select memory 21 (step S450). Then, the frequency data f is set as the frequency data f, and the second timer 22b is cleared (step S451). As a result, the reception frequency of the tuner circuit 2'when receiving a normal broadcast program is changed. Next, it is determined whether or not the select memory 21 has the remaining frequency data (step S452). If there is frequency data remaining in the select memory 21, the operation step returns to step S453. In this case, the AF lamp 8C remains lit. On the other hand, if there is no remaining frequency data in the select memory 21, the AF lamp 8C is made to blink in step S453, and then the operation step returns to step S453. Next, in step S449 described above, the operation when a mismatch between both PI codes is determined will be described. In this case, since the received program of the tuner circuit 2'tuned and controlled by the frequency data f and the received program of the tuner circuit 2'tuned and controlled by the frequency data fp are different, the frequency data f is obtained from the select memory 21 in step S454. Will be deleted. Then, it is determined whether or not there is the remaining frequency data in the select memory 21 (step S455). If frequency data remains in the select memory 21, the operation step returns to step S445, and the next frequency data is read from the select memory 21 again. On the other hand, if no frequency data remains in the select memory 21, the AF lamp 8C is made to blink in step S456, and then the operation step returns to step S432. In the above configuration, the processing of steps S420 ~ S432 is performed during the counting by the first timer 22a time required for this process, the fifth real and very short compared to 3ms as withExample.. In the sixth embodiment described above, as in the second embodiment described above, the deterioration of the reception state of the tuner circuit 2'during the reception of a normal broadcast program is deteriorated in step S440 even during the frequency data search. Since the determination is made, the reception frequency can be changed immediately after the deterioration of the reception state is determined. In the first to sixth embodiments described above, a select memory is provided separately from the data memory, and the frequency data searched from the AF list stored in the data memory is stored in the select memory. There is. Instead, as shown in FIG. 13, a flag area 30 is provided corresponding to each frequency data storage area of the AF list table provided in the data memory, and the frequency data search result is stored in this flag area 30. You may let it. In this case, the select memory becomes unnecessary. (G) Effect of invention According to the present invention, frequency data having a good reception level among other broadcasting stations broadcasting the same program as the currently received broadcast program is searched in advance, so that the reception frequency is deteriorated due to the deterioration of the reception state. When a change request is issued, the reception frequency can be changed extremely quickly. As a result, the program interruption time is extremely short as compared with the conventional receiver, and the listener is not discomforted. Also, you will not miss important programs.

[Simple explanation of drawings]

FIG. 1 is a diagram showing a data format in one group of RDS data. FIG. 2 is a block diagram showing a configuration of a first embodiment of the present invention. FIG. 3 is a front view of the display according to the first embodiment of the present invention. 4A to 4D are flowcharts for explaining the operation of the first embodiment of the present invention. 5A to 5D are flowcharts for explaining the operation of the second embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a third embodiment of the present invention. FIG. 7 is a block diagram showing a configuration of a fourth embodiment of the present invention. 8A to 8C are flowcharts for explaining the operation of the fourth embodiment of the present invention. FIG. 9 is a block diagram showing a configuration of a fifth embodiment of the present invention. 10A and 10B are timing charts for explaining the operation of the fifth embodiment of the present invention. 11A to 11C are flowcharts for explaining the operation of the fifth embodiment of the present invention. 12A to 12D are flowcharts for explaining the operation of the sixth embodiment of the present invention. FIG. 13 is a diagram showing another example of the storage area of the data memory. (2) ...... 1st tuner circuit, (3) ...... 2nd tuner circuit, (2') ...... Tuner circuit, (7) ...... RDS decoder, (8) ...... display, (18) ...... CPU, (19) ...... program memory, (20) ...... data memory, (21) ...... Select memory, (22) ...... Timer, (22a) ...... 1st timer, (22b) ...... 2nd timer.