Method of making edge-aligned implants and electrodes therefor

Description: TECHNICAL FIELD [Detailed description of the invention]

[Technical field to which the invention belongs] The present invention generally relates to a method of manufacturing a semiconductor device having a doping agent ion-implanted in the form of a first set of strips under a first set of conductive strips that cooperate with each other. Such a method is useful for making charge coupling devices. [Conventional technology] A solid-state image sensor is characterized by a pixel, a semiconductor picture element that collects a small number of carriers in response to photons (photons) absorbed by the picture element. The charges generated in this way are accumulated by collecting them in an electric potential recess (potential well). The stored charge is, as is well known, transferred into the output circuit by row and column shift registers, which achieves charge transfer. Also, the charge binding device (hereinafter referred to as "CCD") is a solid-state imaging device in a preferred form, and the present invention particularly relates to the manufacture of this device. More specifically, the CCD features a MOS capacitor, preferably an embedded channel created by ion implantation. The high efficiency of a CCD imaging device is dominated by ion implantation and the formation of corresponding electrodes. More specifically, in the field of two-phase charge-shifting devices, the device can be manufactured so that the edges between the potential well formed by the ion-implanted strip and the electrodes present on it are aligned. Required. Failure to do this creates a barrier for stray potential wells and efficient charge delivery, and reduces the performance of the device. U.S. Pat. No. 4,035,906 describes how to form a CCD. Here, the mask used for ion implantation of the first set of injection strips is removed after its use and is not used to form the first set of polysilicon strips. Instead, the polysilicon strips are positioned by alignment marks (not shown) so that they are arranged in a staggered pattern with respect to the injection strip (see Figures 2C and 2D). To do this, the injected ions are coated with a polysilicon strip by diffusing into the underlying substrate during the separation oxidation step (between Figures 2C and 2D). It is necessary not to be included in the part of the substrate. This method, however, is not sufficient because it is difficult to control inward diffusion. Some n-type doping agents remain in oxides that do not require it. As described in more detail below, the tendency of doping agents to diffuse excessively, both downward and outward, to the very edge of the underlying electrode is a more serious drawback. .. This undesirably alters the potential wells of both the first set of electrodes and the second set of electrodes formed adjacent to it. This undesired potential change tends to make charge transfer inefficient. Therefore, in such a technique, it is difficult to accurately control the outside diffusion (out diffusion). These difficulties are exacerbated as the size of the CCD decreases, and the overall size of the integrated circuit decreases, requiring one step. That is, the thinner the separated oxide layer means that the oxidation time is shorter, and thus the sensitivity to stopping the external diffusion precisely as needed is increased. [Problems to be solved by the invention] The problem to be solved by the present invention is therefore that when manufacturing a semiconductor device such as a CCD, the edge of the injected barrier in the semiconductor substrate is precisely aligned with the edge of the electrode existing on the edge (edge). Alignment) is possible. This will become clearer by referring to Fig. 1. FIG. 1 shows the problems of the conventional technique. When the injected doping agent 5 diffuses out of the oxide layer 6, it diffuses excessively in the portion of the first polysilicon strip 8 adjacent to the edge portion 7, and the potential well illustrated in the substrate. Unwanted dents in D₁Tends to make. In addition, excessive diffusion occurs outwards, as indicated by reference number 9, and is an unwanted dent in the well of the second electrode strip formed adjacent to the first strip.₂To make. [Means to solve problems] According to the present invention, a method of forming a precisely aligned strip of injected doping agent inside a semiconductor substrate to manufacture a semiconductor device having a conductive strip on top of the resulting injection strip. There is the following process: a) A conductive material is adhered onto the semiconductor substrate (10) to form a conductive layer (14). b) A patterned mask (16,20,30) and a tail portion (34) of the mask (30) are formed on the conductive layer (14), at which time the mask (16,20,30) is formed. ) And the pattern of the tail portion (34), in the conductive layer (14), a plurality of first strip portions located at intervals from each other are exposed in the form of grooves (40). c) Ion-implant a strip of doping agent (52) into the substrate (10) through the groove (40) of the conductive layer (14) exposed by the mask (16, 20, 30) and tail (34). , d) Remove a portion (20,30) and tail portion (34) of the mask to the portion of the substrate (10) containing one of the injected doping agent strips (52). The conductive layer (14) including the correspondingly formed groove (40) and the portion (54,56) adjacent to the groove (40) is exposed. e) A second layer of material or film thickness effective to leave on the exposed conductive layer (14) between the remaining masks (16) when performing steps f) and g) below. Form a strip (60), f) The mask (16) is removed to expose the conductive layer (14) underneath. g) The portion of the underlying conductive layer (14) as described above that is not covered by the second strip (60) is removed by etching to form a groove (65), and then h) The conductive strip (70) formed from the conductive layer (14) between the grooves (65) on the substrate (10) is oxidized to form a separated oxide film around the strip (70). Forming (90), Provided is a method for manufacturing a semiconductor device, which comprises. [Embodiments of the Invention] Hereinafter, a two-phase or virtual phase type CCD configuration using an electrode strip made of polysilicon will be described with reference to. In addition, the present invention provides a conductive electrode strip of barrier injectate (or well injectate for p-type channel devices) regardless of whether the device is CCD or the electrodes are polysilicon. Applicable to any device that requires underneath, where the injectate and electrode strips are precisely aligned. For example, the present invention is useful in any case where, for example, when making a four-phase CCD or a CCD with a lateral overflow drain, the injecting doping agent must be self-aligned with the edge of the gate. Proper edge alignment between the implanted portion and the first phase conductive strip is partly the masking used for ion implantation as an effective masking edge for positioning the edge of the conductive strip. Achieved by using some of the materials. Each step of the method of the present invention is exemplified by preferred embodiments of FIGS. 2A-2K. The semiconductor substrate 10, most preferably the p-type single crystal silicon having an embedded n-type channel (not shown), has a layer 12 of gate oxide grown on it (see FIG. 2A). The entire surface conductive layer 14 made of silicon, eg, doped polysilicon, is then attached and then Si, as shown in FIG. 2B.₃N₄A first full mask layer 16 made of is adhered. Adhesion of the conductive layer 14 and the first mask layer 16 is carried out according to a conventional procedure, so that a more detailed explanation here may not be necessary. A second full mask layer 18 of oxides, eg, adhered oxides, is then adhered to a suitable ion masking depth, preferably up to about 5000 Å. The first mask layer 16 and the second mask layer 18 were patterned using conventional photoresist and etching techniques to form a mask strip 20, and the exposed conductive layer 14 present beneath it as a substrate. Leave the part. The mask strips 20 are preferably parallel and there is a predetermined spacing between them. Then, a third mask layer 30 made of a suitable substance is attached to the entire layer with a thickness that does not flatten the layer. That is, the portion 32 of the attached third mask layer 30 that is in contact with the mask strip 20 is preferably the same third mask layer 30 and is more than a portion existing between such mask strips 20. , As shown, it is raised by the distance y. The height of such a raised portion is due to the large thickness of the downward side of the mask strip 20 when the dotted line portion of the third mask layer 30 is removed by etching (see FIG. 2B). Tail) Selected so that part 34 remains. A typical example of the distance y is 5000 Å. For the formation of the third mask layer 30, any substance having such properties, for example, SiO by chemical vapor deposition₂Is useful, which produces a ridge (protrusion) at a distance y when covered with a nominal thickness of 5000 Å. In addition, the material forming the third mask layer 30 should have sufficient boron ion stopping power at the tail portion 34 formed by the material (see Figure 2C). Etching techniques for substances such as those described above are suitable for removing the dotted line in the figure (see Figure 2B). For example, reactive ion etching or plasma etching via an exposed and developed photoresist (not shown) can be used. One feature of such etching is that unless the polysilicon acts as a complete etching stop (etch stop) for such etching, the conductive layer 14 made of polysilicon will also have grooves (recesses). It means that 40 is formed. Such grooves are preferably about 100 Å or less. SiO for the third mask layer 30₂Instead of using and applying a photoresist on it, if the photoresist used does not allow the injected boron to reach the semiconductor substrate 10 with sufficient ion arrest, the third mask layer 30 will It can itself be its photoresist. At this point, the mask for the first ion implantation step is fully patterned. Ion implantation of the first set of barrier stops is performed by ion implantation of a suitable doping agent, eg boron, according to conventional methods, as shown by arrow 50 (see Figure 2C). The injection energy applied according to conventional methods is selected such that boron is injected below the interface between the semiconductor substrate 10 and the gate oxide layer 12, ie to form half of the desired barrier region. Usually, for example, energy of 200 KeV or less is sufficient. The strip after ion implantation is complete is indicated by the dashed line 52. However, the mask made of the third mask layer 30 made of oxide and the mask strip 20 prevents the doping agent from being injected into the semiconductor substrate 10 and into the conductive layer 14 made of polysilicon underneath it. It is effective in that. Thus, the ion-implanted strips match and align with the groove 40, and change the potential in those parts of the device. After that, Si of the above-mentioned mask₃N₄Remove all parts except (reference number 16). This is easily achieved, for example, by removing the adhering oxide with a buffered HF solution. This exposes not only the polysilicon groove 40, but also the adjacent portions 54 and 56 (see Figure 2D) that were previously in contact with the oxide of the third mask layer 30. Etching resistant material, eg thermally grown SiO₂Alternatively, metal siliconized strips 60 are formed on these exposed surface portions (reference numbers 40, 54 and 56) to act as a means of facing the etchant during polysilicon patterning. Strips such as oxides are formed where they are not covered by a portion of the large mask (first mask layer 16) previously used to pattern the location of the polysilicon-injected strip 52. To. Common methods are useful for forming strip 60. When the strip 60 is a metal siliconized material, this is achieved by adhering a layer of the metal siliconized material, eg, Ti, throughout. The device is then annealed at sufficient temperature to produce siliconized material only where the metal is in contact with the exposed polysilicon layer. Then, the unreacted metal is removed by etching to obtain a profile as shown in FIG. 2D. After that, the part where the above-mentioned mask was held (reference number 16) is, for example, heat H.₃PO₄Removed by etching or by etching highly anisotropic reactive ions. Due to this removal, SiO₂Etc. The polysilicon between the strips 60 is exposed to a suitable etchant, but the strips 60 are resistant to the etchant and protect the underlying polysilicon. Such suitable etching agents include plasma and reactive ion etching processes. Figures 2E and 2F show the results of etching and removing such exposed conductive polysilicon between the strips 60. The groove 65 formed may slightly undercut the strip 60. The conductive polysilicon strip 70 remains behind. FIG. 2F is intended to more clearly show the features and dimensions of such strips 60 and 70. The overall width of strip 60 is "x". Etching produces a surface 75 on one side of strip 70. Depending on the etchant used, the surface 75 is a protective SiO₂Etc., and the degree of undercut measured from the vertical portion of the surface 75 is "x'". The ion-implanted strip 52 has a width of "w". The edge 80 of strip 52 will be separated by a distance w'from the vertical alignment with the vertical portion of surface 75. Typical values for the above dimensions are: x = 2 ~ 20μm w = 1 ~ 7μm x = 0 ~ 3000Å w = 500 ~ 2000Å (If an etching method that does not form an undercut is used, x'is 0.) The strip 60 can then be removed using buffered HF as the etchant, for example when such strips are silicon dioxide. If the strips 60 are metallic siliconized products, they can be retained. The entire polysilicon strip 70 is then oxidized, for example by heating in a suitable atmosphere. A typical example is strip 70 H₂Heating to a temperature of about 950 ° C for about 20 minutes in an O-containing ambient atmosphere. As a result, a film 90 of the separated oxide is obtained (see Fig. 2G). Through such heating, it is possible to slightly diffuse the edge 80 of the strip 52 outwards depending on the severity of the heating, and to change the slope of the wall surface 75. In most cases where this type of heating process is employed, edge alignment still exists at the edge 80 after the diffusion is complete, comparing the edge 80 to the vertical portion of the surface 75 of the polysilicon strip 70 (Fig. 2G). reference). Groove 40 may extend towards surface 75 or may stop shortly, as shown in Figure 2G. In the former case, the difference in vertical alignment between the edge of the ion-implanted strip 52 after the oxidation step and the edge of the wall surface 75 can be ignored. Another modification can be used for the injection mask and / or for the etchant resistant material used to form the polysilicon strip 70. If the metal attached for the formation of the etching resistant strip 60 is tungsten and the second mask layer (strip) 18 is SiO as described first.₂When remaining as, tungsten is WF at 400-500 ° C₆From the vapor, it will only precipitate on exposed polysilicon surface portions (reference numbers 40, 54 and 56). SiO₂When the mask strip 20 and the first mask layer (strip) 16 are removed, tungsten in contact with polysilicon remains only on the surface portions 40, 54 and 56 as described above. Subsequent etching gives the results shown in Figure 2E. That is, here strip 60 is tungsten and is removed prior to the oxidation step which gives the results of FIG. 2G. At this point, only the first set of injection barrier strips is edge aligned with the corresponding electrodes on it. A two-phase CCD requires a second set. The second set of injections and the electrodes present on them are aligned as follows: Mask layer 100 is substantially aligned with third mask layer 30 in Figure 2B, as shown in Figure 2H. Adhered to the whole in the same way. The material of the mask layer 100 is patterned in the same manner as the third mask layer 30. Ion implantation is performed as indicated by arrow 110 (see FIG. 21) to form the ion implantation strip 120 only in the portion of the semiconductor substrate 10 that is not covered by the material of the mask layer 100. (The injection energy for the second injection is, for example, about 150 eV lower than that of the first injection, so no injection occurs under the exposed polysilicon strip 70.) Then the strip mask layer 100 is removed. (See Fig. 2J). A second set of polysilicon strips is then attached as a whole layer and then patterned to leave spaced strips 130 (see Figure 2K). The ion-implanted strips 120 are automatically edge-aligned with the outer surface of the polysilicon strip 70 due to their injection formation using the strip 70 as a mask, and therefore these ion-implanted strips 120 are them. At edge 122 of, is aligned perpendicular to each edge of strip 130 as an electrode. The first set of strips 70 is wired to the common terminal 270, while the second set of strips 130 is wired to the common terminal 330, thus completing a two-phase CCD. Once proper edge alignment is achieved for the first set of injection strips and the electrodes lying on each of them, the virtual phase electrode configuration is limited to the first set of thus formed electrodes. It can be provided in use and using routine self-alignment techniques. This is achieved by implementing the process in the direction of completion as shown in Figure 2J, and by performing additional steps such as: 1) Ion implantation is performed through the entire exposed groove 400 (see Fig. 2J), and a receptor doping agent extending over the entire length of the groove 400, for example, a boron strip 410 is implanted to form (see Fig. 3). 2) Next, an arbitrary heating step, for example, a heating step at 950 ° C for 30 minutes is carried out. This is to diffuse the strips 120 and 410 deeper into the substrate. As a result, a series of stepped potential wells indicated by line segment 510 is obtained. As will be readily appreciated by those skilled in the art from the above description, the methods of the present invention can be used to edge align the injected barrier in the context of a lateral overflow drain. The structure of the CCD device manufactured through such edge matching is shown in FIG. That is, the apparatus of FIG. 4 can be manufactured using the same technique as described above for forming electrodes from polysilicon strip 70 with reference to FIGS. 2A-2G. Further, therefore, the masking process used in manufacturing the illustrated apparatus is similar to that shown in FIGS. 2D to 2F, and the result is similar to that shown in FIG. 2G. More specifically, in order to form a polysilicon ridge 630 (as an electrode) as shown in Fig. 4, an etching resistant substance such as heat is used according to the process shown in Fig. 2D to Fig. 2E. Growing SiO₂Alternatively, a strip of metal siliconized material is formed in a predetermined region on polysilicon to act as a means against the polysilicon patterning agent for electrode formation. With reference to the CCD device in FIG. 4 again, portion 600 of the substrate 610 is an injected drain connected to a power source (not shown). Layer 620 is a separate oxide layer, and the raised ridges 630 found in the background are strips of oxide-coated polysilicon that make up one of the CCD electrodes. As described above, the above-mentioned method with reference to FIGS. 2A to 2K is effective for edge-aligning the edge 632 of the portion 600 as the injection drain with the edge 634 of the olisilicon strip. .. The portion 640 as an injection barrier acts to adjust the threshold for excess charge inflow into the drain 600 from the region below the ridge 630. The injection thus formed is indicated by a dashed line "inside" the substrate 610. The CCD device shown in Fig. 5 is a reference example. The illustrated manufacturing method is distinguished from the method of the present invention in that it does not use a tail portion. In the illustrated embodiment, however, subsequent heating that would cause lateral diffusion of the infused doping agent strip could be minimized. In addition, in FIG. 5, the first reference number is given to the part similar to the above-mentioned one, but the subscript "a" is added to those numbers for distinction. Thus, the polysilicon conductive layer 14a has a mask strip 20a, as in the case described above. Then a multilayer resist mask is used. This multilayer mask consists of a flattening layer 640, a barrier layer 650, such as spin-on-glass, and a relatively thin photoresist layer 660, as is commonly done in such masks. By exposing and developing the photoresist layer 660 as the first layer and etching the barrier layer 650, the flattening layer 640 can be anisotropically etched to obtain the configuration shown in FIG. it can. Subsequent remaining treatment steps can be performed using an etching agent suitable for strip removal, according to the procedure of the above-described embodiment. Yet another method can be utilized to form a polysilicon strip 70 whose edges are aligned with the lower injected doping strip. This method is shown in FIGS. 6-8. The same reference numbers are given to parts similar to those mentioned above, but the subscript "b" is added to those numbers for distinction. This method starts using the same steps as in FIGS. 2A-2C of the above-described embodiment, but the conductive layer 14b is made of silicon formed on the gate oxide layer 12b, such as amorphous silicon. Very thin layer (1000 Å or less), and mask strip 20b is preferably all Si₃N₄Is. At this point, a polysilicon or amorphous silicon strip 700 is attached onto the exposed gate oxide layer 12b and conductive layer 14b between the mask strips 20b. Most importantly, these strips 700 are thick enough to remain during the etching described below. Si₃N₄Priority adhesion of silicon at these positions rather than above is SiCl at a pressure of about 1/100 bar.₄+ H₂It can be obtained by depositing silicon from. The attached silicon may already be doped, or doping can be achieved by ion implantation. The mask strip 20b is then selectively etched off (see Figure 7). At this point, the portion of the conductive layer 14b exposed between the strips 700 is etched and removed by plasma or reactive ion etching. Since the strip 700 has a sufficient thickness as compared with the conductive layer 14b, as a result of this etching process, only the broken line portion of the strip 700 (see FIG. 8) is removed. The processing steps of the aforementioned embodiments are then useful for completing the CCD. According to another method, if the mask strip 20b is SiO₂Consists of, and if thick enough for the lift-off method, a silicon strip 700 can be attached both on and between the mask strip 20b (not shown), and the mask strip 20b. When removing by etching, the part on the mask strip 20b is removed. [Example] The present invention will be further described with reference to the following specific examples. Si with a film thickness of 500 Å according to the procedure shown in FIGS. 2A to 2D.₃N₄The first mask layer (strip) 16 of the above was formed on the conductive layer 14 of polysilicon of 3500 Å. Then SiO₂The second mask layer (strip) 18 of the above was attached to a thickness of 5000 Å. These are then etched through a mask using reactive ion etching to form mask strip 20, which is then adhered at a film thickness of 5000 Å.₂It was covered with a third mask layer 30 composed of. The third mask layer 30 was etched with reactive ions through a photoresist mask exposed and developed as described above, leaving the tail portion 34. Doping agents were injected with boron at an energy of 200 KeV and an exposure gap between 32 of 3 μm oxide strips (part of the third mask layer 30). Next, the adhered oxide layer is removed with a buffered HF etching agent, and a thin Si is used.₃N₄I left the strip. By oxidizing the polysilicon that remained after being exposed to the buffered HF etchant, strips 60 resistant to the etchant were formed. The first mask layer (strip) 16 of the nitride is then removed with phosphoric acid at 150 ° C for 30 minutes and the exposed polysilicon strip is SF.₆Etching was performed by the contained plasma etching method. For comparison purposes, the method shown in Figures 2A-2F of US Pat. No. 4,035,906 was carried out to produce a CCD similar to that produced as described above. That is, some 25 Ω-cm p-type wafers were processed by standard gettering and channel stop methods. After that, phosphorus is 1.2 × 10 by the blanket method.¹²cm²The implant was implanted by ion implantation at 150 KeV at the concentration of to form an embedded channel structure. A layer of silicon dioxide with a film thickness of 1000 Å was then grown at 950 ° C in a moist ambient atmosphere. A photoresist layer was attached onto this and patterned. Arsenic in this oxide through resist 1.3 × 10¹³cm^-2The conditions shown in Fig. 2B of US Pat. No. 4,035,906 were repeatedly injected at the concentration of. The photoresist strip was then removed. A layer of polysilicon was then applied throughout at 620 ° C and the phosphorus was doped at 900 ° C for 3 minutes. The polysilicon layer was then patterned to form a structure that essentially repeated that of US Pat. No. 4,035,906, FIG. 2C. The oxide layers between the polysilicon strips were then etched to remove the As injectate between the polysilicon strips. Following the etching process, a separate oxide was formed and the remaining As injectate was diffused into the substrate. This was achieved as follows. That is, the wafer was heated to 950 ° C for 20 minutes in a moist ambient atmosphere, repeating the conditions shown in Figure 2D of US Pat. No. 4,035,906. Finally, Phase 2 electrodes were made as described in US Pat. No. 4,035,906, and a final annealing at 1050 ° C was performed for 30 minutes to allow As to penetrate further into the substrate. The presence or absence of an undesired trapping wall was determined by the following procedure for both the above examples and comparative examples of the present invention. At a gate voltage of 0 volts, the storage area for Phase 1 of the comparative wafer was found to be 12.8 eV. In the phase 1 transfer area, the potential was 5.2 eV. At the boundary between the phase 1 storage area and the phase 2 transfer area, there was a well with a depth of approximately 3 eV and 1 μm. This latter produced inferior charge transfer rates. In contrast, the above embodiments of the present invention have such boundaries between the Phase 1 storage area and the Phase 2 storage area, or between the Phase 1 transfer area and the Phase 2 storage area. It turns out that it doesn't have a well. [Effect of the invention] The advantageous technical effect of the present invention is that more effective edge alignment between the injectable doping agent and the electrodes on top of it can be obtained than was possible using the prior art. .. A related advantageous technical effect of the present invention is that it provides a method of producing a CCD with increased efficiency by eliminating unwanted electron capture wells.

[Simple explanation of drawings]

FIG. 1 is a partial cross-sectional view showing the configuration of a semiconductor device according to the conventional technique. 2A to 2K are partial cross-sectional views showing the manufacture of the semiconductor device by the method of the present invention in order. FIG. 3 is a partial cross-sectional view of a virtual phase CCD, which is a semiconductor device manufactured by the method of the present invention, corresponding to the second K. FIG. 4 is a partial cross-sectional view of the CCD when observed at 90 ° with respect to the observation angles shown in FIGS. 2A to 2K. FIG. 5 is a partial cross-sectional view for reference, which is similar to FIG. 2B but shows a mode in which the tail portion is not used. 6 to 8 are partial cross-sectional views showing another embodiment similar to FIGS. 2A to 2C, respectively. In the drawings, the main reference numbers are: 10 ...... Semiconductor substrate, 14 ...... Conductive layer, 16 ...... Mask (1st mask layer), 18 ...... Mask (2nd mask layer) , 20 ...... Mask (mask strip), 30 ...... Mask (third mask layer), 34 ...... Tail part, 40 ...... Groove, 52. ..... Ion injection strip, 60 ...... Etching resistant material strip, 70 ...... Conductive strip.