Parallel scrambling system

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Industrial application field]

The present invention relates to a parallel scrambling system of signals in a system using an M-bit (M 1) interleaved multiplexer / demultiplexer.

【0002】

[Conventional technology]

A system using a conventional M-bit (M 1) interleaved multiplexer has an input signal A, as shown in FIG.₀ Or A_N-1 Is multiplexed by the M-bit interleaved multiplexer 11, and the multiplexed transmission signal is scrambled by the series scrambler 12. On the other hand, a system using an M-bit (M 1) interleaved demultiplexer receives the scrambled signal B, descrambles it with the serial descramble 15, and descrambles the signal, as shown in FIG. Is demultiplexed by the M-bit interleaved demultiplexer 16 and the original signal A₀ Or A_N-1 Is configured to restore. Here, the series scrambler 12 and the series descrambler 15 include series generators 13, 14 and exclusive OR (XOR) gate circuits 17, 18 of the same structure, respectively.

【0003】

In FIGS. 7 and 8, S indicates the sequence generated by the series generators 13 and 14, and B indicates the scrambled signal. The series generators 13 and 14 of the system shown in FIGS. 7 and 8 can be composed of a simple series generator and a modular series generator. FIG. 9 shows the configuration of a simple series generator, FIG. 10 shows the configuration of a modular series generator, and FIG. 11 shows another example of a simple series generator, which is an actual circuit diagram using a D flip-flop and an XOR gate. Is shown.

【0004】

In FIGS. 9 and 10, each block indicates a shift register (or flip-flop), and a number (1 or 0) in the block indicates the initial state of the shift register.

【0005】

Furthermore, as a typical example of a system using a conventional M-bit interleaved multiplexer, an SDH (Synchronous Digital Hierarchy Based System) transmission system recommended by CCITT can be mentioned, and in this system, the M-8 is used. It is adopted.

【0006】

[Problems to be Solved by the Invention]

However, in such a conventional scramble system, when the signal input to the multiplexer is, for example, a STM-1 (Synchronous Transport Module) signal of 155.520 Mbps, the high-speed transmission signal after multiplexing is scrambled, so that the speed is high. It had to be composed of processing elements, and therefore had many problems in terms of manufacturing cost and power consumption.

【0007】

Moreover, in the conventional scramble system, when the input signal is 16 STM-1 signals, the transmitted signal STM-16 after multiplexing is scrambled, so that it must be realized by a high-speed processing element of 2.48 GHz. However, this is practically almost impossible to achieve.

【0008】

An object of the present invention is to solve the above problems, to perform parallel scrambling and transmission of an input signal before multiplexing the input signal, and to perform parallel descramble after demultiplexing on the receiving side. The purpose is to provide a parallel scramble system that can restore the original signal.

【0009】

[Means for solving problems]

In order to achieve such an object, the present invention performs a first parallel signal generator that generates n (n> 1) parallel signals in order to perform M-bit (M 1) interleaved parallel scrambling. First exclusive with n (n> 1) exclusive OR gates that perform exclusive OR operations on n parallel signals from the first parallel signal generator and the n (n> 1) input signals. Receives a signal from an M-bit interleaved parallel scrambler including a target OR gate circuit and the M-bit interleaved parallel scrambler, multiplexes the received signal in M-bit units, and multiplexes the signal. An M-bit interleaved multiplexer that outputs the above, and an M for receiving the multiplexed signal, demultiplexing it in M-bit units, and outputting n (n> 1) demultiplexed signals. -A second parallel signal generator having the same structure as the first parallel signal generator in order to perform M-bit interleaved parallel descramble with a bit interleaved demultiplexer to restore the n input signals. , And n (n> 1) exclusive OR gates for performing exclusive OR operations on the n demultiplexed signals and n parallel signals from the second parallel signal generator. It is equipped with an M-bit interleaved parallel descriptor including a second exclusive OR gate circuit having the same.

【0010】

[Example]

Hereinafter, examples of the present invention will be described in detail with reference to the attached drawings.

【0011】

1 and 2 show the configuration of an embodiment of the present invention.

【0012】

As shown in FIG. 1, the parallel scramble system is input signal A before being multiplexed by the M-bit interleaved multiplexer 22.₀ Or A_N-1 Is scrambled by the M-bit (M 1) interleaved parallel scrambler 21, while the parallel scrambled signal B is received by the M-bit interleaved demultiplexer 24 as shown in FIG. The original signal A is multiplexed and demultiplexed by the M-bit interleaved parallel descrambler 26.₀ Or A_N-1 Is designed to be restored.

【0013】

Scramble in one embodiment of the invention comprising an M-bit interleaved multiplexer is an M-bit interleaved input signal before multiplexing, instead of scrambling the multiplexed signal (ie, conventional serial scrambling). Scramble in parallel. Further, the descramble in the first embodiment of the present invention provided with the M-bit interleaved demultiplexer performs M-bit interleaved parallel descramble of the demultiplexed signal. The M-bit interleaved parallel scrambler 21 and the M-bit interleaved parallel descrambler 26 are parallel series generators 23,25 and parallel series generators 23,25 with the same structure, respectively.₀ Or T_N-1 And includes an XOR gate circuit that performs an exclusive OR operation on the input signal.

【0014】

Here, the sequence T generated by the M-bit interleaved parallel scrambler 21_i (i = 0,1, ..., N-1) is called a parallel series, and B indicates a scrambled and multiplexed transmission signal. In this case, the M-bit interleaved parallel scrambler 21 (hereinafter referred to as MBIPS) to which the present invention is applied performs the following three steps.

【0015】

In the first step, the series S generated from the series generator 13 shown in FIG. 7 and the parallel series T generated from MBIPS._i Seeking a relationship with. In the second step, each parallel series T_i Find the shift register generator (hereinafter referred to as SRG) that generates. In the third step, parallel series T_i The sum of the SRGs corresponding to is taken and all parallel series are generated as one SRG.

【0016】

(1) Series S generated by the series generator and parallel series T generated by MBIPS_i Relationship with: Series S generated by the series series generator 13 shown in Fig. 7 is expressed as follows.

【0017】

[Number 1]

S = (S₀, S₁, ..., S_M-1: S_M, S_{M + 1}, ..., S_2M-1: : S_{(N-1) M}, S_{(N-1) M + 1}, ..., S_NM-1: ) Therefore, in order for MBIPS to become MBIPS for the scrambler shown in Fig. 7, the parallel series T_i Must be as follows.

【0018】

[Number 2]

T₀= (S₀, S₁, ..., S_M-1: S_NM, S_{NM + 1}: : S_{NM + M-1}: ) T_i= (S_M, S_{M + 1}, S_2M-1: S_{(N + 1) M}, S_{(N + 1) M + 1}, ..., S_{(N + 1) M + M-1}: ) T_N-1= (S_{(N-1) M}, S_{(N-1) M + 1}, ..., S_NM-1: S_{(2N-1) M}, S_{(2N-1) M + 1}, ..., S_2NM-1; ) That is, parallel series T_i Interleaving in M-bit units must be the sequence S generated by the series generator. In other words, parallel series T_iIs a series in which the series S is decimmed by MN and interleaved by M.

【0019】

(2) SRG to generate each parallel series: The series series generator 13 shown in Fig. 7 can be composed of a module composed of n shift registers (hereinafter referred to as MSRG), and its generation polynomial is G (hereinafter referred to as MSRG). x), initial state polynomial D₀ Let it be (x). Furthermore, the series S generated by these scramblers is described as follows.

【0020】

[Number 3]

S = S_MSRG[G (x), D₀(x)] Therefore, by the following decimation and interleaving theorem, the parallel series T_i MSRG can be obtained.

【0021】

Theorem 1 (Decimation): [0022]

[Outside 1]

<img file="JP2612397B2_D0001.tif" />【0023】

I-th L-decimated series of U_i And. Then [0024]

[Number 4]

<img file="JP2612397B2_D0002.tif" />【0025】

Is. Theorem 2 (Interleave): Series S_MSRG[G (x), D₀ⁱ(x)], i = 0,1, Let T be the sequence interleaving L-1. Then [0026]

[Number 5]

<img file="JP2612397B2_D0003.tif" />【0027】

Is.

【0028】

For example, consider a 4: 1 byte-interleaved parallel scrambler for the scrambler in Figure 9 used in SDH systems (ie M = 8, N = 4). The scrambler in Figure 9 has a simple SRG (SSRG) structure with characteristic polynomials C (x) = X.⁷ + X⁶ +1 and initial state polynomial D_0C(x) = X⁶ + X⁵ + X⁴ + X³ + X² + X¹ Has +1. The MSRG that produces the same series is shown in Figure 10, and its generation polynomial G (x) is X.⁷ + X + 1 and initial state polynomial D₀ (x) is X⁶ + X⁵ + X⁴ + X³ + X² + X [Specifically, the series generated from MSRG is always generated from SSRG, and the characteristic polynomial C (x) of SSRG is X.ⁿ G (x^-1) (Where n indicates the degree of the characteristic polynomial (or generation polynomial)), the initial state polynomial D_0C(x) is Xⁿ D₀ Must be the same as (x) divided by G (x)]. Therefore, the sequence 32 (= MN) -decimated by Theorem 1 is expressed as follows.

【0029】

[Number 6]

V₀= S_MSRG[G'(x), X⁶+ X⁵+ X³+ X²+ X +1], V₁= S_MSRG[G'(x), X⁶+ X⁵+ X²+ X +1], V₂= S_MSRG[G'(x), X⁶+ X⁵+ X²], V₃= S_MSRG[G'(x), X⁶+ X⁴+ X²], V₄= S_MSRG[G'(x), X⁶+ X⁴+ X³+ X²+ X], V₅= S_MSRG[G'(x), X⁶+ X⁵+ X⁴+ X³+ X²+1], V₆= S_MSRG[G'(x), X⁶+1], V₇= S_MSRG[G'(x), X³], However, G'(x) is X⁷+ X +1.

【0030】

Using Theorem 2 and the relationship between the parallel series and the series generated by the scrambler in FIG. 7, the parallel series is expressed as follows.

【0031】

[Number 7]

T₀= S_MSRG[G (x⁸), X⁵⁵ + X⁵⁴ + X⁵³ + X⁵² + X⁵¹ + X⁵⁰ + X⁴⁹ + X⁴⁷ + X⁴⁶ + X⁴⁵ + X⁴² + X³⁶ + X³⁵ + X³⁴ + X³¹ + X²⁷ + X²⁶ + X²⁴ + X²³ + X²² + X²¹ + X²⁰ + X¹⁹ + X¹⁸ + X¹⁵ + X¹⁴ + X ¹¹ + X⁷+ X⁶+ X²+ X] ... (1) In the same way, T₁ , T₂ , T₃ Can be sought.

【0032】

(3) Sum SRG: The method of generating one MSRG or all parallel series as SSRG from the SRG that generates each parallel relation is made possible by the following theorem.

【0033】

Theorem 3 (Specific example of sum SSSRG): Parallel series T₀ The sequence generated from the i-th shift register of SSRG that generates W_j, i = 0,1, ..., M_n-1 And. In addition, a_jⁱ, i = 0,1, ..., N-1, j = 0,1, ..., n-1 [0034]

[Outside 2]

<img file="JP2612397B2_D0004.tif" />【0035】

Have a value of 0 or 1 that satisfies. However, m is the smallest integer that satisfies mMN = 1 modulo (period of series S), and G'(x) is the generation polynomial of the MN-decimated series of series S. Then, the parallel series can be expressed as follows.

【0036】

[Number 8]

<img file="JP2612397B2_D0005.tif" />【0037】

Theorem 4 (Specific example of sum MSRG): Parallel sequence sequence T₀ The sequence generated from the i-th shift register of MSRG that generates W'_i , i = 0,1, ..., M_n-1 And. In addition, b_jⁱ, i = 0,1, ..., N-1, j = 0,1, ..., n-1 [0038]

[Outside 3]

<img file="JP2612397B2_D0006.tif" />【0039】

Have a value of 0 or 1 that satisfies. Therefore, the parallel series can be expressed as follows.

【0040】

[Number 9]

<img file="JP2612397B2_D0007.tif" />【0041】

For example, consider a 4: 1 byte-interleaved parallel scrambler for the scrambler shown in Figure 9. Then, since the period of the sequence generated from the scrambler is 127, m of Theorem 3 becomes 4 (because MN = 32). Therefore, the parallel relation can be expressed by Theorem 3 as follows.

【0042】

[Number 10]

T₀= W₀, T₁= W₈+ W₁₆ + W₃₂ , T₂= W₈+ W₃₂ , T₃= W₈+ W₂₄ + W₄₈This equation and the 0th parallel series T from equation (1)₀ After finding the SSRG that generates, theorem 3 can be used to find the MBIPS based on the SSRG structure as shown in Fig. 3. By the same method, theorem 4 can be used to obtain MBIPS based on MSRG as shown in Fig. 4.

【0043】

FIG. 3 shows an example of an M-bit interleaved parallel scrambler configured by the method described above, and FIG. 4 shows another example of an M-bit interleaved parallel scrambler.

【0044】

In FIG. 3, the M-bit parallel scrambler (MBIPS) includes a group of seven shift registers configured by sequentially concatenating eight shift registers. In this case, the number of shift register groups is seven, which is the seventh-order generation polynomial (C (x) = X) in this embodiment.⁷ + X⁶ This is because +1) is used. These seven shift register groups are also sequentially concatenated. However, after performing an exclusive OR operation on the output of the final shift register (leftmost shift register) of the 7th shift register group (leftmost shift register group) and the output of the final shift register of the 6th shift register group, the first The result is output to the first shift register (rightmost shift register) of the shift register group (rightmost shift register group).

【0045】

In this embodiment, four parallel scramble signals T from the seven shift register groups described above.₀ Or T₃ Is configured to generate. However, the 0th scramble signal T₀ Is generated from the last shift register of the 7th shift register group, and the remaining scramble signal T₁ Or T₃ Is generated by using the shift register and XOR gate mentioned above.

【0046】

In FIG. 4, the M-bit interleaved parallel scrambler MBIPS is composed of seven shift register groups each consisting of eight shift registers connected in sequence. These seven shift register groups are also sequentially concatenated. However, the output of the final shift register group of the 7th shift register group is output to the 1st shift register of the 1st shift register group, and at the same time, the output of the final shift register of the 1st shift register group is subjected to an exclusive OR operation. After that, the result is output to the first shift register of the second shift register.

【0047】

In this embodiment, as in FIG. 3, four parallel scramble signals T from the above-mentioned seven shift register groups.₀ Or T₃ Is configured to generate. However, the 0th scramble signal T₀ Is generated from the last shift register of the 7th shift register group, and the remaining scramble signal T₁ Or T₃ Was generated using the shift register and exclusive OR gate described above.

【0048】

FIG. 5 shows an example of MBIPS based on the SSRG structure, which generates 16 parallel scrambled signals. MBIPS is configured by the same method as in Fig. 3. FIG. 6 shows an example of MBIPS based on the MSRG structure, and shows another example of generating 16 parallel scrambled signals. MBIPS is configured by the same method as in Fig. 4.

【0049】

In FIGS. 3 to 6, the number 1 or 0 in each shift register indicates the initial state of the shift register, respectively.

【0050】

[Effect of the invention]

As described above, the present invention can perform parallel scrambling before multiplexing and can operate the scrambler at the same speed as the transmission speed of the input signal, thus reducing production costs and power consumption. It has the effect of being able to.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the scrambler of one Example of this invention.

[Figure 2]

It is a block diagram which shows the descrambler of one Example of this invention.

[Fig. 3]

It is a block diagram which shows an example of the M-bit interleaved parallel scrambler.

[Fig. 4]

It is a block diagram which shows another example of M-bit interleaved parallel scrambler.

[Fig. 5]

It is a block diagram which shows an example of MBIPS based on SSRG structure.

[Fig. 6]

It is a block diagram which shows an example of MBIPS based on MSRG structure.

[Fig. 7]

It is a block diagram which shows the conventional example of the system using the M-bit interleaved multiplexer.

[Fig. 8]

It is a block diagram which shows the conventional example of the system using the M-bit interleaved demultiplexer.

[Fig. 9]

It is a block diagram which shows the structure of a simple series generator.

[Fig. 10]

It is a block diagram which shows the structure of a modular series generator.

[Fig. 11]

It is a block diagram which shows the structure of another example of a simple series generator.

[Explanation of symbols]

21 M-bit interleaved parallel scrambler 26 M-bit interleaved parallel desk rambler 22 M-bit interleaved multiplexer 24 M-bit interleaved demultiplexer 23,25 Parallel series generator