Access control system for address converting table

Description: TECHNICAL FIELD [Detailed description of the invention]

[Overview] Regarding access control to the address translation table that shows the correspondence between the logical address and the physical address in the data processing device. The purpose is to enable sharing of address translation tables by multiple central processing units. A system in which a plurality of central processing units each having a memory management unit share a memory for storing an address translation table in which each entry contains information indicating that a reference and a write have been made to the memory area managed by the entry. In the memory management unit, a conversion index buffer consisting of a small amount of high-speed memory that performs high-speed address conversion, and an operation that operates when the requested logical address is not in the conversion index buffer and registers it in the conversion index buffer. A target address conversion mechanism, a lock instruction means for instructing the lock of the common bus during this series of processes of reading, changing, and writing to the address conversion table as inseparable processes, and a notification of prohibition of access to the common bus in response to the lock instruction. It is equipped with a lock control mechanism that sends out a lock signal to be used, and is configured to prohibit access by other memory management units during a series of processes of reading, changing, and writing from one memory management unit to the address conversion table as inseparable processes. To do. [Industrial application field] The present invention relates to address translation in a data processing system using virtual memory, and more particularly to an access control method that enables sharing of an address translation table by a plurality of central processing units. [Conventional technology] Many data processing devices that use virtual memory are equipped with a memory management unit in order to manage the conversion between a logical address and a physical address. The memory management unit is required by the TLB to have a translation index buffer (usually called a TLB: Table Lookaside Buffur) that manages the parts required for high-speed memory in units (pages) of an appropriate size and performs high-speed conversion. It is equipped with a dynamic address translation mechanism (usually called DAT: Dynamic Address Translation) that automatically searches the address translation table in main memory and replaces TLB entries when there is no translation information on the page. As shown in Fig. 4, in the memory management unit of the data processing device, when dynamically converting from a logical address to a physical address, the page, which is the minimum unit of address conversion, was accessed for virtual memory management. You must remember if something has happened and if the content of the page has changed. Hereinafter, the information indicating that the access has been made is referred to as an R bit, and the information indicating that the information has been changed is referred to as an M bit. The R bit is used to find out if it was recently referenced when deciding which page to evict to put a new page in TLB, and the M bit is used to determine if the page to evict from main memory needs to be written to secondary memory. use. Large computers often have R-bits and M-bits attached to the physical memory page, and R-bits and M-bits are managed by dedicated hardware attached to the memory. In such a case, the problem described below can be easily solved by processing the dedicated hardware. However, in a microprocessor-related memory management unit, as shown in Fig. 5, it is common to store R bits and M bits in an address translation table entry. In the example of FIG. 5, the address translation table entry has a physical page number, R bit, M bit, V bit indicating the validity of the entry, and access protection information. This type of memory management unit reads an address translation table entry containing R and M bits once, and then writes to the address translation table entry when it is necessary to change the R bit or M bit. [Problems to be solved by the invention] As shown in Fig. 6, when multiple central processing units with the above memory management units are connected and the address translation table is shared, the M bit is guaranteed when the following operations are performed. become unable. It is assumed that both the R bit and the M bit of a certain address translation table entry (hereinafter abbreviated as ATE) are '0'. The central processing unit 1 read the ATE from the memory because it tried to write to the data in the page specified by the ATE. ATE value in memory: R = 0, M = 0 The central processing unit 2 tried to read the data in the page specified by the same ATE, so the ATE was read from the memory. ATE value in memory: R = 0, M = 0 Since the central processing unit 1 performs write access, R = 1 and M = 1 were set and ATE was rewritten. ATE value in memory: R = 1, M = 1 Since the central processing unit 2 makes read access, I set R = 1 (M is 0 as it was read in) and rewrote ATE. ATE value in memory: R = 1, M = 0 At this point, it is forgotten that the central processing unit 1 has written to the page specified by the ATE. If the M bit of an address translation table entry is 0 when it should be 1, changes in that page are not reflected in secondary memory and the page is paged back into physical page memory. It malfunctions. Therefore, in the conventional method, there is a problem that the address translation table cannot be shared by a plurality of central processing units at the same time. An object to be solved by the present invention is to provide an address translation table access method that solves such a conventional problem. [Means to solve problems] FIG. 1 is a block diagram showing the principle of means for solving the above-mentioned problems. In the figure, 1 is the central processing unit and 2 is the memory. 11 is a memory management unit that performs conversion from a logical address to a physical address during instruction execution. 21 is an address translation table, which stores the physical address corresponding to the logical address. Reference numeral 111 is a translation lookaside buffer (TLB), which consists of a small-capacity high-speed memory that performs high-speed address translation. 112 is a dynamic address translation mechanism, which operates when the requested logical address is not in the translation index buffer 111 and replaces the contents of the TLB. Reference numeral 113 denotes a lock instruction means, which instructs the lock of the common bus during this period as a series of processes of reading, changing, and writing to the address translation table 21 as inseparable processes. Reference numeral 114 denotes a lock control mechanism, which sends a lock signal notifying that access to the common bus is prohibited in response to a lock instruction. Reference numeral 30 denotes a common bus, which includes a physical address bus 31, a data bus 32, and a lock signal line 40 for notifying access prohibition to the physical address bus 31. [Activity] The problem with the conventional method is that another central processing unit reads the same entry while performing the operations of reading, changing, and writing the address translation table entry. Therefore, in the present invention, the operation of reading, changing, and writing the address translation table entry (usually called read-modify-write) is an atomic operation, and another central processing unit reads the entry during that operation. It is forbidden to do. Therefore, the lock instruction means 113 makes a series of processes of reading / changing / writing (reading the contents of the entry, changing the contents and writing to the entry) to the access conversion table 21 as inseparable processes, and a dynamic address translation mechanism during this period. Instruct 112 to lock. The dynamic address conversion mechanism 112 gives a lock instruction to the lock control mechanism 114 together with a lock instruction from the lock instruction means 113 and a lock instruction due to other factors, and the lock control mechanism 114 issues a lock signal in response to these lock instructions. Send out. Indiscriminate lock instruction for reading / changing / writing processing to the address translation table 21 by the lock instruction means 113 does not require bus lock when the central processing unit is operating independently, and other devices during bus lock. Since the use of the bus will be delayed, it is possible to make the lock inseparable only when the information instructing the lock instruction means to be indivisible is set by the software. As a result, other memory management units do not read the same ATE between ATE reading and writing by one memory management mechanism as described above. [Example] Hereinafter, the present invention will be described in more detail with reference to the examples shown in FIGS. 2 and 3. FIG. 2 is a diagram showing a configuration of a lock instruction means and a lock control mechanism according to an embodiment of the present invention. In the figure, circuit elements 1131 to 1136 form a lock indicating means, and circuit elements 1141 to 1149 form a lock control mechanism. Inverters 1131,1132 form a switch, and inverters 1133,1134 form a latch. Inverter 1134, marked R, makes a weak feedback to inverter 1133 and constitutes a latch, but is dominated by the input. One bit of the control data bus (a bit that indicates the indivisible access to the address conversion table) is input to the inverter 1132, an input instruction determined by a specific instruction or a specific operand is input to the inverter 1131, and the input instruction is ". When it is 1 ", the switch is opened and the 1-bit (negative logic) value of the control data bus is latched. The state of this latch is input to the AND circuit 1141 and input to the AND circuit 1135, and if there is an output instruction, the value is returned to 1 bit of the control data bus via the driver 1136 and can be read. .. The processing device of this embodiment includes an instruction with an interlock. For example, BSETI (set a bit with interlocked) locks the bus, inverts the value of the specified bit, and stores it in a specific location. Furthermore, it is an instruction to set the specified bit "1", and is CSI (compare and). store (interlocked)) is an instruction that locks the bus, compares the destination operand with the comparison operand, determines the result, and updates the contents. The bus lock access signal at the lower side of FIG. 2 is a signal indicating that it is an operand access that locks these interlocked instructions based on the result of instruction decoding. The address translation table access signal is instructed by the dynamic address translation mechanism. The address translation table access signal and latch (1133,1134) values are input to the AND circuit 1141, and the output is "1" when the latch value is "0" and the address translation table access signal is "1". .. The output of the AND circuit 1141 and the bus lock access signal are input to the NOR circuit 1142, and the output is 0 when the bus lock access is performed or when the address translation table access is performed and the latch is latched to 0. ". The inverters 1144 and 1145 form a switch, and the AND circuit 1146 and the inverter 1147 form a latch circuit. The gate is opened by the bus cycle start signal, the output value of the NOR circuit 1142 is "0", and the AND circuit. When the output of 1143 is "0", it is latched and the output becomes "1", and the * lock signal (* indicates inverse logic) is latched to "1" via the inverters 1148 and 1149 and locked. Be done. When the bus lock cycle end signal no longer needs to be bus-locked, its output becomes "1", the latch (1146,1147) is released, * the lock signal becomes "0", and the lock is released. As a result, when the lock is instructed by the input instruction, the bus is locked during the bus cycle if there is access conversion table access. In the case of an instruction with an interlock, the bus is locked while the bus lock access signal is turned on. FIG. 3 is a time chart showing the bus lock operation of the read / modify / write in this embodiment. The uppermost row shows the bus lock signal, the next row shows the address (A) signal, and the next row shows the read or write (R / W) signal. The shaded area in the address signal is the part where nothing is done, that is, the read-modify-write modification part. The next stage is the address strobe (AS), which indicates that the address signal is valid when it is on the lower side (low), and the next stage is the data strobe (DS), which is on the lower side (low). When it is, it indicates that the data (D) in the next stage is valid. The SDC in the next stage is synchronous data complete, which indicates that data has been placed on the data bus from the memory side at the time of reading, indicates that writing to the memory has been completed at the time of writing, and ends the memory cycle. Indicates that it may be done. The bottom row shows the lock signal (LOC), which indicates that when read access is made, it will be on (low side) until the end of the write. [Effect of the invention] As described above, according to the present invention, the access conversion table including the R bit and the M bit can be shared by a plurality of central processing units, thereby facilitating the construction of a tightly coupled multiprocessor system. effective.

[Simple explanation of drawings]

FIG. 1 is a block diagram showing the principle of the present invention. FIG. 2 is a diagram showing a configuration of a lock instruction and a lock control circuit according to an embodiment of the present invention. FIG. 3 is a time chart showing the operation of an embodiment of the present invention. Figure 4 shows a data processing device with a memory management unit. Figure 5 shows an example of an address translation table entry. FIG. 6 is a diagram showing an example in which a plurality of central processing units share an address translation table. In the drawing 1 is the central processing unit, 2 is the memory, 11 is the memory management unit, 21 is the address translation table, 111 is the translation lookaside buffer (TLB), 112 is a dynamic address translation mechanism, 113 is the lock indicator, 114 is the lock control mechanism, 1131 ~ 1134,1144,1145,1147 ~ 1149 are inverters, 1135,1141,1146 are AND circuits, 1142 is a NOR circuit, 1136 is a driver, Are shown respectively.