Methods of and apparatuses for recording and/or reproducing digital data

Description: TECHNICAL FIELD [Detailed description of the invention]

[Industrial application field] The present invention relates to a data recorder that records a data signal or the like from a computer using a rotating head type digital audio tape recorder (DAT). [Outline of Invention] The present invention relates to a data recorder by diverting a so-called DAT recording device and providing a means for determining the continuity of these tracks in the data signals of two tracks forming one frame in the DAT format. , The head clog or the like makes it possible to easily detect the unerased data signal. [Conventional technology] For example, in a computer, in order to store data written in a hard disk or the like, these data are transferred to a so-called data recorder and recorded. In that case, as the above-mentioned data recorder, so-called analog audio tape recorders have been often used in the past. However, in such an analog tape recorder, the consumption of the recording medium is extremely large, and since the data record at the time of recording is low, it takes an extremely long time to transfer and record. Further, there is a problem that it is not possible to easily find the desired recording portion. By the way, DAT (Digital Audio Tape Recorder) has been developed (see "ES Review", published by Sony Corporation Shibaura Factory: ISSN 0389-7737: December 1985, pp. 11-17). According to this DAT, since it is originally designed to record / reproduce a digital signal, it is suitable for recording the above-mentioned data. However, in such a DAT, when another signal is recorded on the medium on which the signal is once recorded, the previous signal is generally erased by recording a new signal by so-called overwrite without using an erase head. I try to do it. Therefore, for example, if the overwriting is not performed normally by the head clog, the previous signal may be left unerased. Therefore, in the DAT format, an error detection code is added to each recorded track so that when a part of the track is unerased, it is detected as an error. However, even if such a code is added, if the entire track is left unerased, the error detection code in this track is normal and cannot be detected. It ends up. When the signal recorded here is an audio signal, the signal from the unerased track can be excluded due to the compatibility of the front and rear. However, when DAT is used as a data recorder, data compatibility cannot generally be used. By the way, when the DAT is used as a data recorder, an error correction code is generated for the data signals of a plurality of frames supplied to the DAT, and the generated code is supplied to the DAT and recorded in the same manner as the data signal. Can be considered. According to this, since the error correction is performed outside the DAT, it is possible to have a strong error correction capability. However, in this case, a frame in which an error has occurred is detected in advance in order to perform error correction. There is a need. However, if the entire track is left unerased as described above, this error cannot be detected, and therefore the error correction code is corrected even if the error correction code is generated outside the DAT described above. I couldn't do it. [Problems to be solved by the invention] As described above, the conventional technique has a problem that when DAT is used as a data recorder, it becomes impossible to perform error correction in which unerased tracks occur. [Means to solve problems] The present invention has a rotating head, and one rotation of the rotating head forms two inclined tracks, and the two inclined tracks are regarded as one frame, and a data signal or a code signal is generated for each frame. A device (DAT (1)) that is formatted for recording and playback is provided, a predetermined header portion is provided in the formatted data signal, and the contents of the header portion form the above one frame. It is a data recorder characterized by making it equal for two tracks (controller (2)). [Action] According to this, by providing a means for determining the continuity of these tracks in the data signals of two tracks forming one frame of the DAT format, the unerased residue of the data signal by the head clog or the like is detected. This makes it possible to form a good data recorder using this DAT. [Example] In FIG. 1, (1) shows the configuration of a DAT, the DAT (1) is provided with a rotating head drum (11), and the magnetic tape (12) is about 90 degrees around the drum (11). It is wrapped around a range and transferred. Two recording / playback heads A and B are provided on this drum (11) with an angle interval of 180 degrees, and two inclined tracks are recorded / played back by one rotation of this drum (11). It has become so. On the other hand, digital data from the outside is input to the IO circuit (13), supplied from the IO circuit (13) to the digital signal processing circuit (14), and converted to the above-mentioned DAT format. This formatted signal is supplied to the heads A and B through the recording side contacts of the recording amplifier (15) and the recording / playback selector switch (16), and is recorded in the data (12). When the signal recorded on the tape (12) is reproduced by the heads A and B, this reproduction signal is supplied to the processing circuit (14) through the reproduction side contact of the recording / reproduction selector switch (16) and the reproduction amplifier (17). Then, the digital data obtained by reverse conversion is output to the outside through the IO circuit (13). Further, an external control signal is supplied to the system control circuit (18), and the signal from this control circuit (18) controls the rotation of the head drum (11), transfers the tape (12), and switches the switch (16). Along with the control and the like, the signal from the control circuit (18) at the time of recording is supplied to the processing circuit (14) to form a predetermined subcode signal and the like. Further, at the time of reproduction, the signal extracted by the processing circuit (14) is supplied to the control circuit (19), control such as totacking is performed, and a part of this signal is taken out to the outside. DAT (1) is formed by the above configuration. Then, in this device, for example, audio (analog) signals are recorded / reproduced by providing a DA / AD conversion circuit outside the IO circuit (13) and providing a predetermined control device outside the control circuit (18). be able to. On the other hand, in the above-mentioned device, an arbitrary interface bus (3) is connected via the controller (2) as the outside of the DAT (1). Here, as the interface bus (3), for example, the SCSI standard ("NIKKEI") "ELECTRONICS" published by Nihon Keizai Shimbun Inc .: October 6, 1986, pp. 102-107) can be used. Further, the host computer (5), the hard disk device (6), and the like are connected to this bus (3) via the adapter (4). Then, in the above-mentioned controller (2), a protocol control circuit (21) is provided between the controller (2) and the bus (3), and a microcomputer (22) that controls the operation of the controller (2) via the control circuit (21). ) And the memory control (DMA) circuit (23) and the bus (3) exchange data and control signals. Furthermore, state detection and operation control are performed between the microcomputer (22) and the DMA circuit (23), and data is generated between the buffer memory (24) and the bus (3) through this DAM circuit (23). Input / output is performed. Further, the memory (24) is provided with an error correction code (ECC) generation circuit (25) for the data written in the memory (24), and the error correction code generated by this circuit (25) is provided. Is written to a predetermined part of the memory (24). Then, data is input / output between the memory (24) and the processing circuit (14) of the DAT (1) via the IO circuits (26) and (13). In addition, control signals are exchanged between the microcomputer (22) and the system control circuit (18). Therefore, in this device, the data written in the hard disk device (6) is input to the controller (2) through the bus (3) in response to the transfer request from the controller (2) at the time of recording, and the DMA circuit Written to memory (24) via (23). Then, an error correction code is generated by the generation circuit (25) for the data written in the memory (24), and the data including this error correction code is read out via the IO circuit (26) and DAT (1). ) Is entered. Then, in this DAT (1), the data input to the IO circuit (13) is regarded as equivalent to the data from the AD conversion circuit at the time of audio recording, and the digital signal processing circuit (14) formats the predetermined DAT. It is converted to and recorded on the tape (12) by the heads A and B. Then, at the time of this recording, the error correction code is generated as follows. That is, for an arbitrary data string supplied to DAT (1), the error correction code generation matrix is set as follows, for example.<img file="JP2576512B2_D0001.tif" /> Further, for this generation matrix, a syndrome generation circuit can be formed, for example, as shown in FIG. That is, in the figure, the data signals supplied to the terminals (31) on the left side are supplied to the adder circuits (32a) to (32d), respectively, and the signals from the adder circuits (32a) to (32d) are directly or α, respectively. α², α₃It is supplied to the syndrome registers (34a) / (34d) through the coefficient circuits (33b) to (33d) of. Then, the signals from the registers (34a) to (34d) are fed back to the adder circuits (32a) to (32d), and this feedback is performed for each supply of the data signal to the registers (34a) to (34d). A syndrome is generated. Therefore, in this circuit, the calculation proceeds from the right side of the data unit of the above-mentioned matrix each time a data signal is supplied. Normally, for example, when the data of 251 symbols is supplied, a syndrome is generated in the registers (34a) to (34a), and this syndrome is supplied to the arithmetic circuit (35) corresponding to the marilix of the above-mentioned parity part 4 A symbol error correction code is generated. On the other hand, if the data string ends while the above operation is in progress, a syndrome equivalent to the supply of all 0s to the left of the point where the operation on the matrix proceeded at that time is registered. It means that it is generated in (34a) to (34d), and at this point, by fixing the registers (34a) to (34d) and supplying the contents to the arithmetic circuit (35), it is supplied by then. An error correction code is generated for the data. As a result, an error correction code can be smoothly added to an arbitrary variable length data string. In this case, the above-mentioned syndrome generation circuit is actually formed by software such as a microcomputer, but the specific configuration required here is only the memory area corresponding to the syndrome registers (34a) to (34d). It can be realized with an extremely simple configuration. In addition, the memory capacity of the registers (34a) to (34d) is only the amount of data for one track x 4, and the required memory capacity can be extremely small. Then, by supplying the generated error correction code to the DAT (1) continuously to the data signal, it is possible to smoothly record an arbitrary variable length data signal, and a good data recorder using the DAT. Can be formed. In this case, since the data string for generating the error correction code in the above example is extracted from 1 frame by 2 symbols, the recording is 2 frames (4) for the error correction code of 4 symbols to be generated. It can be done by track). Also, as a special case, when the error correction code is set to 2 symbols, for example<img file="JP2576512B2_D0002.tif" />Matrix can be used, which eliminates the need for the arithmetic circuit (25). Further, in the above-mentioned device, the error correction processing at the time of reproduction can be performed as follows. That is, in Fig. 3, the data signal and error correction code (ECC) are reproduced as shown in Fig. A, and error correction is not possible for this signal, for example, with DAT (1) as shown in Fig. B. When a frame is detected, the state in which the first data signal was directly output is stopped as shown in Fig. C. However, at this time, the supply of data to the syndrome generation circuit described above is continued, and when the reproduction of the error correction code is completed, the data for error correction for the error frame from the DAT (1) described above is transmitted to the syndrome generation circuit. Is generated. Therefore, from this state, rewinding is instructed to DAT (1) as shown in the figure DNJ, and the data is replayed from the beginning as shown in the figure E, and at this time, the detected error frame is The correction data from the syndrome generation circuit is inserted, and the entire data signal is reproduced. Therefore, when there is no normal error frame, the data signal is reproduced as it is and output to the interface bus (3), and the above processing is performed only when there is an error frame. Therefore, the data signal as a whole is extremely quick. Is played back. Further, when performing the above-mentioned error correction, by using the data signal regenerated from the DAT (1), it is not necessary to provide a large-capacity buffer memory or the like corresponding to the entire data portion described above, and the above-mentioned Error correction can be performed only in a small memory area corresponding to the syndrome register. Then, in the above-mentioned device, the format of the DAT recorded on the tape (12) is as follows. That is, in FIG. 4, one frame is composed of two tracks Ta and Tb recorded by the heads A and B, each of these tracks is formed from the lower side of the drawing, and the recorded signal is Gap part of 5.051 degrees from the lower end side with respect to the total length of 90 degrees Preamble part for PLL of 0.918 degrees subcode First subcode part of 3.673 degrees Postable part of 0.459 degrees Between blocks of 1.378 degrees Gap part 2.296 degree tracking (ATF) signal part 1.378 degree block gap part 0.918 degree data PLL preamble part 58.776 part data part 1.378 degree block gap part 2.296 degrees AFT signal part 1.378 degree inter-block gap part 0.918 degree subcode PLL preamble part 3.673 second subcode part 0.459 degree post amble part 5.050 degree margin part There is. The scale of the figure is not accurate. Then, in the above-mentioned device, the data input from the IO circuit (13) is added with a predetermined error detection / correction code or the like by the processing circuit (14), and is added to the data section of the tracks Ta and Tb in a predetermined interleave relationship. It is sorted and inserted. First, in this data unit, an 8-bit synchronization unit is provided at the beginning of the data unit, followed by a total of 16-bit ID units called W1 and W2. Therefore, this ID part is divided into eight ID areas of 2 bits each, and the first ID area (ID-0) is set as a format ID, for example, "01" is provided in the case of data specifications. In the next ID area (ID-1), "00" is provided as a subcategory ID for, for example, a computer peripheral device. Further, ID-2 is provided with, for example, "00" when the recording capacity of one frame is 5760 bytes and "01" when the recording capacity of one frame is 5292 bytes as the frame size ID. For the next ID-5, for example, "00" is provided when the track pitch is 13.6 μm, and "01" is provided when the track pitch is 20.4 μm. Similarly, the subcode part is also provided with the ID part of W1 and W2. In this ID part, the area where the frame is included in the first 3 bits of W1 is the read-in area (000) at the beginning of the tape and the data area. (001), a readout area (010) at the end of data recording, and an area ID indicating the end of media (011) at the end of the tape are provided, and the next 1 bit is valid (1) and invalid (0) of the data. A code (VF) indicating the above is provided, and the content of the frame is a normal frame (0 ** 0), an amble frame (0 ** 1) used for synchronization, etc., a frame other than the file mark (000 *), in the following 4 bits. A frame ID indicating a first file mark (001 *), a second file mark (010 *), and a third file mark (011 *) is provided. In addition, the first bit of W2 is set to "1", the next 3 bits are provided with a format ID of "000" indicating that the subcode is in the Pax format described later, and the block address is set to 4 bits at the end. The indicated numerical value is provided. The LSB of the block address is set to "0" in the first subcode and "1" in the second subcoat. As described above, various identifications and the like when the DAT (1) is used as a data recorder are performed. Further, in the above-mentioned device, the data unit is provided with, for example, a recording capacity of 5760 bytes per frame, and the data of this one frame is formatted as follows, for example. That is, in FIG. 5, the above-mentioned 5760 bytes are configured into words (0 to 1439) of 4 bytes (32 bits) each, and each of these words is a 16-bit (2 bytes) L according to the audio signal. It is divided into a channel and an R channel. And in this format, a 3-word (12-byte) sync section is provided first, the first 1 byte is all "0", the next 10 bytes are all "1", and the last 1 byte is all. It is set to "0". Next, an 8-word (32-byte) header is provided. The header part here is the same for the L channel and the R channel, and is double-written. First, the first half byte of word 3 is used as an area for displaying the frame status, and the same frame ID, VF, and format ID as W1 and W2 of the above-mentioned subcode part are provided. The latter byte is a mode area, for example, "0000" to "0011" are assigned for CD-ROM, and "1000" is provided for DAT. Furthermore, the first-half bytes of word 4 and word 5 are defined as the logical frame number (LFNO) area, and a total of 24 bits is provided with a binary value indicating the serial number of the effective frame from the tip of each save set. All invalid frames are set to "0". The second half of the word 5 is an area for displaying the data status, and the recording format is streaming type 1 (0000), type 2 (0001), and start / stop type with 4 bits on the MSB side of this byte. A code indicating that it is 1 (0010) is provided, and whether or not the data of these header parts is further provided in the data signal supplied from the bus (3) in the next 1 bit (1). A flag (DH) indicating whether it is (0) is provided, and the number of frames (PFL) of the error correction code is provided as a binary value in the 3 bits on the LSB side. Furthermore, the first half of word 6 is the area of the total number of frames (ECFL) of the data signal and error correction code, and this value is set as a binary value, and when this number of frames is indefinite, it is all "0". Be made. The second half of the byte is the number of overwrites (OWNO) area, and the number of times is set as a binary value. Furthermore, the first half byte of word 7 is the frame number (EFNO) area to which the error correction code is added. When the first bit on the MSB side is "0", it is the frame of the data signal, and when it is "1", the error correction code. The first frame of the serial number of the frame of the data signal and the serial number of the frame of the error correction code within the range where the error correction code is generated once every 7 bits is set to "1". It is provided as a binary value. If no error correction code is added, all are set to "0". The second half of word 7 and the first half of word 8 are used as the number of bytes (EBL) area of valid data in the frame, and a binary value indicating the number of bytes is provided. Furthermore, the bytes in the latter half of word 8 and words 9 and 10 are all "0" for the time being as extension bits. A total of 5712 bytes of data is provided in the subsequent words 11 to 1438, and a data signal from the bus (3) is sequentially provided in each word by 4 bytes. Further, the word 1439 is a CRC unit, and an error detection code (CRC) is generated and provided for each data signal of the header unit and the data unit described above for each signal recorded on each track. That is, in the DAT format, the data of the L channel and the data of the R channel are alternately divided into two tracks by 2 bytes and recorded. For example, a head forming tracks on both sides of the figure. It is indicated by the azimuth (±) of. So, for example, in the (-) Ajimas CRC, the L channel word 3 (L)₃), R channel word 4 (R₄), Below L₅, R₆, L₇CRC is generated for the data string of ..., and (+) is R in CRC of Azimas₃, L₄, R₅, L₆, R₇CRC is generated for the data string of .... Therefore, according to this format, since the header part is double-written in the L and R channels, it is possible to determine the unerased portion by comparing the contents. That is, in the above format, the value of the number of overwrites (OWNO) area is changed for each overwrite, and if one of the tracks is left unerased, this will be inconsistent. Also, the values in the logical frame number (LFNO) area will be inconsistent if they are left unerased. Therefore, by comparing these values, it is possible to determine the unerased residue, and by making this frame an error, it is possible to reliably perform error correction outside the above-mentioned DAT (1). According to the above format, since the synchronization unit is provided, the synchronization between the controller (2) and the DAT (1) can be freed, which is particularly good when the amount of data in one frame fluctuates. Can be supported. However, since the above-mentioned synchronization pattern may appear in the data signal, it is necessary to scramble the data in the header part, the data part, and the CRC part by adding an arbitrary M sequence or the like. That is, in the control (2), the data of the header part is formed with respect to the data signal from the bus (3), the CRC is generated from this, then scrambled, and the synchronization part is added to DAT (1). Will be supplied to. Furthermore, in the above format, since the CRC of the data for each track is added, it is possible to detect an error in the data in the track outside the DAT (1). The data signal is formatted by the above. Further, in the above-mentioned device, 2048-bit data can be recorded in each of the first subcode section and the second subcode section. Here, in the audio signal recording format, the 2048 bits are divided into packs of 64 bits each, and information such as the time code and recording date and time of the signal recorded for each pack is recorded. Therefore, a data recorder can be assigned to this pack so that various controls can be performed using the two packs. That is, Fig. 6 shows the structure of the pack for that purpose. In the figure, 64 bits of each pack is divided into 8 words of 8 bits each. The 4 bits on the first (1st) wardno MSB side in each pack are designated as the ITEM area, and this area is the same as the audio signal recording format, and the contents of the pack are displayed in this 4-bit binary code. Will be done. It should be noted that 9 out of 16 codes with 4 bits have already been defined for recording audio signals, and any of the remaining 7 codes is defined for the data recorder and is used, for example. The first of the two packs is "0001" and the second is "0010". In addition, the 4 bits on the LSB side of the first word and the second word are areas for displaying the frame status, and the format ID, area ID, VF, and frame ID are provided in the same manner as W1 and W2 described above. In addition, the 3rd to 5th words of the 1st pack are aread in the file number (FNO) area, and a binary value indicating the serial number of the file in the data (save set) backed up at one time is provided. In addition, the 6th and 7th words are set as the save set number (SSNO) area, and a total of 16 bits is provided with a second trial value indicating, for example, the number of backups from the start of use of the device. The 8th word is the parity for the 1st to 7th words above each. The 3rd to 5th words of the 2nd pack are the absolute frame number (AFNO) area, and these 48 bits provide binary values indicating the serial number of the frame from the tip of the tape, and the 6th and 7th words. Is set to all "0" as an extension bit for the time being, and the 8th word is the parity for the 1st to 7th words. Therefore, by identifying these ID codes and the like and performing the reproduction, extremely smooth reproduction can be performed. In the above-mentioned device, information that can be formed on the controller (2) side is provided in the header portion of the data unit, and information that can be formed on the DAT (1) side is provided in the subcode portion. Further, in the generation of the error correction code by the controller (2) described above, in the DAT format, as shown in Fig. 7, two inclined tracks formed by one rotation of the drum (11) are regarded as one frame, and this one frame. One (+ azimus) track has even-numbered data on the left channel in the first half, odd-numbered data on the right channel in the second half, even-numbered data on the right channel in the first half of the other (-azimus) track, and left channel in the second half. The data is interleaved and recorded, such as the odd-numbered data in. The C in the center indicates the error correction code added by DAT (1). Therefore, in generating the above-mentioned error correction code, the tape (12) is formed by extracting the 2n (even number) data and the 2n + 1 (odd number) data of each frame to form a data string. It is possible to generate an error correction code for the data string interleaved above. This makes it possible to divide the error correction capability when the tape (12) has a lateral scratch or the like. As a result, it is possible to improve the error correction capability when the tape (12) has a lateral scratch or the like. Thus, according to the above-mentioned device, the DAT can be used as a data recorder. In this case, according to the above-mentioned configuration, the rotating head drum (11) is rotated at, for example, 2000 rpm, and the data is recorded at an extremely high speed of 192,000 bytes per second. At the same time, the recording medium consumed by the recording medium can be extremely reduced. Further, according to the above-described configuration in this case, smooth recording with an error correction code added can be performed, so that good data can be recorded using this. [Effect of the invention] According to the present invention, by providing a means for determining the continuity of these tracks in the data signals of two tracks forming one frame of the DAT format, the data signal remains unerased by a head clog or the like. The detection has become easier, which has made it possible to form a good data recorder using this DAT.

[Simple explanation of drawings]

FIG. 1 is a block diagram of an example of the present invention, and FIGS. 2 to 7 are diagrams for explaining the same. (1) is DAT, (2) is controller, (3) is bus, (4) is adapter, (5) is host computer, (6) is hard disk device, (11) is rotating head drum, (12) is Tape, (14) is a digital signal processing circuit, (16) is a switch, (18) is a system control circuit, (22) is a microcomputer, (23) is a DMA, (24) is a memory, and (25) is an error correction. The code generation circuits, A and B, are recording / playback heads.