Display device.
8 claims: 2 independent, 6 dependent
- 1(57)【特許請求の範囲】 【請求項1】強誘電体液晶層を具備しており、この液晶層はそれの一側における第1の組の電極の部材と前記液相層の他の側における第2の組の電極の部材との間の重複領域によって画定された複数のピクセルを有しており、前記ピクセルのそれぞれが第1および第2の光学的に識別しうる状態を有し、かつ前記液晶層間の電位差に依存する前記第1および第2の状態間の切換えのためのレスポンス時間を有するマトリクス・アレイ型液晶セルをアドレスする方法であって、選択されたピクセルに切換えピクセル波形を与えて前記選択されたピクセルの前記第1および第2の状態間で切換える工程を含んでおり、前記切換えピクセル波形はチャージ・バランスされかつ前記選択されたピクセルを切換えるのに十分なパルス幅とパルス高さを有する第1のパルスとこの第1のパルスの十分なパルス高さよりも大きいパルス高さと前記選択されたピクセルを切換えるのには不十分なパルス幅を有する第2のパルスよりなる液晶セルのアドレス方法。
- 2【請求項2】前記切換えピクセル波形は前記第1のパルス、前記第2のパルス、および必要に応じて1つ以上のゼロ電圧信号よりなり、前記第2のパルスが前記第1のパルスチャージ・バランスする請求項1記載の方法。
- 3【請求項3】前記セルが前記第1の組の電極の部材にストローブ波形を直列に印加し、前記第2の組の電極の部材にデータ波形を並列に印加することによってライン・バイ・ライン形式でアドレスされる請求項1または2記載の方法。
- 4【請求項4】前記ストローブ波形がバランスした両極性パルスよりなる請求項3記載の方法。
- 5【請求項5】前記液晶層のレスポンス時間が特定の電位差で最小値を示しかつ前記第2のパルスのパルス幅がこの第2のパルスのパルス高さに関係なく前記選択されたピクセルを切換えるのには不十分である請求項1~4のうちの1つに記載の方法。
- 6【請求項6】前記第2のパルスの幅が前記選択されたピクセルを切換えるのにはその第2のパルスのパルス高さに関連して不十分である請求項1~4のうちの1つに記載の方法。
- 7【請求項7】請求項1~6項のうちの1つに記載された方法によってマトリクス・アレイ型液晶セルをアドレスするための駆動回路。
- 8【請求項8】強誘電体液晶層と、第1の組の電極と、第2の組の電極を有するマトリクス・アレイ型液晶セルを具備しており、前記第1の組の電極の部材と前記第2の組の電極の部材の間の重複領域が前記液晶層に複数の層を形成し、前記ピクセルはそれぞれ第1および第2の光学的に識別可能な状態を有しかつ前記液晶層間の電位差に依存する前記第1および第2の状態間の切換えに対するレスポンス時間を有しており、さらに請求項7による駆動回路を具備している表示装置。
Independent claims8
4 paragraphs, as filed
Description: TECHNICAL FIELD [Detailed description of the invention]
The present invention relates to a liquid crystal display device. The present invention relates to a display device comprising a matrix of ferroelectric liquid crystal elements that can be selectively set, and in particular a method of addressing such a display device. In the present invention, the width and / or height of the pulse is used to multiplex the matrix. Since the liquid crystal material is composed of long and thin polar molecules, it is possible to maintain a high degree of long-distance orientation order of the molecules in the liquid state. This type of material has anisotropy for properties such as dielectric constants and is characterized by two constants, one in the direction of the long molecular axis and one in the direction orthogonal to it. The anisotropy of the dielectric constant allows the molecules to align in the direction of the electric field, and the molecules are oriented in that direction to generate minimal electrostatic free energy. Certain liquid crystal materials exhibit ferroelectric properties. That is, they have a permanent dipole moment orthogonal to the long molecular axis. When the liquid crystal material is placed between two glass plates whose surfaces have been treated to align the molecules, the molecules will have two possible states depending on the direction of the permanent dipole moment. By applying an electric field of the correct amplitude and polarity, the molecule can be switched between those two states . In a matrix-type display device provided with a ferroelectric liquid crystal layer, the pixels of the matrix are a member of a first set of electrodes on one side of the liquid crystal layer and a member of a second set of electrodes on the other side of the liquid crystal layer. It is defined by overlapping areas between. An electric field is applied to the molecules of a pixel by generating a voltage on the members of the first set of electrodes and the members of the second set of electrodes that define one pixel. The individual electrodes may be in electrical contact with or isolated from the liquid crystal layer. In the former case, the presence of a direct current flow through the layer may cause deterioration of the electric field quality of the liquid crystal. In the latter case, charge accumulation may occur between the liquid crystal and the insulation. These risks can be mitigated by allowing the voltage waveforms applied to these electrodes to be charge-balanced over time, i.e. the DC component of the waveform to be zero for a long period of time. GB2173335A (STC) has a height (V)<sub>s</sub>+ V<sub>d</sub>) And width t<sub>s</sub>The switching pulses of are three pulses of opposite polarity, namely height-(V)<sub>s</sub>-V<sub>d</sub>), Width t<sub>s</sub>One pulse and height mV<sub>d</sub>, A method of addressing a matrix-addressed ferroelectric liquid crystal cell that is charge-balanced by two pulses of width t / m (where m is a coefficient greater than 1) is disclosed. The document suggests that this method can be used for display devices that can withstand reverse polarity of only 75% of the pulse amplitude sufficient for the liquid crystal material to make a switch with the same lifetime. .. However, the minimum line address time for this method (ie the minimum time required to generate a voltage waveform containing switching and charge balance pulses) is 2t.<sub>s</sub>(1 + 1 / m). We have acknowledged that the width of the pulse has a greater effect on the tendency of pixels to switch than the height of the pulse. The present invention utilizes this invention. The reason for this is that, as described above, the electric field has two actions on the ferroelectric liquid crystal molecules. One is to stabilize those molecules in a nearly favorable state by acting on dielectric anisotropy. The other action of the electric field is to act on the permanent dipole. The net effect is the parabolic voltage on the "switching force" characteristic. Therefore, long low-voltage pulses can have a much greater effect than short high-voltage pulses, even if they have the same area. According to the present invention, a strong dielectric pair liquid crystal layer is provided, and the liquid crystal layer includes a member of a first set of electrodes on one side thereof and a second set of electrodes on the other side of the liquid phase layer. It has a plurality of pixels defined by an overlapping region between the members, each of the pixels has a first and second optically distinguishable state, and the potential difference between the liquid crystal layers is large. A method of addressing a matrix array type liquid crystal cell having a response time for switching between the first and second states depending on the selected pixel by giving a switching pixel waveform to the selected pixel. Includes the step of switching between the first and second states, the switching pixel waveform being charge-balanced and having sufficient pulse width and pulse height to switch the selected pixel. A method of addressing a liquid crystal cell is provided consisting of a pulse and a second pulse having a pulse height greater than the sufficient pulse height of this first pulse and a pulse width insufficient to switch between the selected pixels. .. The first pulse, the switching pulse, is charge-balanced. This charge balance is partly due to the second pulse, which has a higher pulse height than the first pulse. Therefore, the pulse width of the second pulse may be smaller than the pulse width of the first pulse, and the minimum address time of the method of the present invention may be smaller than twice the pulse width of the first pulse. This reduces the minimum line address time compared to traditional charge-balanced switching waveforms. In the present invention, whether or not a pulse is a switching pulse is determined by its pulse. With respect to the terms herein, the term "slot" refers to (1) the minimum time required for a liquid crystal material to switch from a first state to a second state for a given pulse height, and (2). It should be noted that a waveform can have one of two meanings: a (predetermined) constant voltage, i.e., a time having a pulse width of a pulse of a predetermined pulse height. Since the meaning of (2) above is more general, it is interpreted in this specification unless otherwise specified. Unless otherwise specified, the term used in the meaning of (1) above in this specification is "response time t".<sub>s</sub>". Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a part of a matrix array type liquid crystal cell 2, which is made of a ferroelectric liquid crystal material such as a biphenyl ester marketed under the trade name BDH SCE3. Therefore, a layer having a thickness in the range of 1.4 μm to 2.0 μm is provided. Pixels 4 of the matrix are defined by overlapping regions between the members of the first set of row electrodes 6 on one side of the liquid crystal layer and the members of the second set of column electrodes 8 on the other side of the liquid crystal layer. There is. For each pixel, the electric field between them determines the state of the liquid crystal molecules, and thus their alignment. Parallel polarizers (not shown) are provided on both sides of cell 2. The relative orientation of those polarizers determines whether light can pass through the pixels in a given state. Thus, for a given orientation of the polarizer, each pixel has a first and second optically distinguishable state provided by the two bistable states of the liquid crystal molecule at that pixel. A voltage waveform is applied to the row electrode 6 and the column electrode 8 by the row driver 10 and the column driver 12, respectively. The matrix of pixels 4 is addressed in a line-by-line format by applying a voltage waveform called a strobe waveform in series with the row electrode 6, and a voltage waveform called a data waveform is applied in parallel to the column electrode 8. .. The waveform generated between one pixel defined by one row electrode and one column electrode is given by the potential difference between the waveform applied to that row electrode and the waveform applied to that column electrode. FIG. 2 shows the configuration according to the present invention. This configuration is 1.5 slots, or 1.5t, in the sense that one slot is the time it takes for the material to switch.<sub>s</sub>To use. The driver output voltage must change 6 times and 5 output states are required. The top strobe on the left appears in the selected row. A constant 0 volt voltage is applied to the unselected or unstrobed rows. The second row on the figure shows the columns or data waveforms. These waveforms are made up of bipolar pulses to minimize the switching effect on those unselected rows. The pixel waveforms obtained for the selected rows are shown above each column waveform. Pixels that are switched off receive a long low-voltage negative pulse followed by a short high-voltage positive pulse of equal area, maintaining a zero DC component. A related configuration is shown in Figures 3, 4 and 5 showing alternative equalized pulse shapes. Each of the configurations shown in FIGS. 2 to 5 has a switching pulse having a pulse width and a pulse height sufficient to switch pixels, but the width is smaller, that is, it is not possible to switch the pixel. Sufficient but uses the fact that the pulse height can be charge balanced by a larger non-switching pulse to that pulse. In each configuration, one of the two waveforms, namely a bipolar strobe waveform or a constant zero voltage waveform, is applied to each row electrode, and the row electrode to which this strobe waveform is applied is the selected row. One of the two data waveforms, namely the column "off" waveform or the column "on" waveform, can be applied to each column electrode. Since both data waveforms are bipolar waveforms, the resulting pixels in the unstripped rows do not affect the pixels in those rows, so they do not switch states. In the selected row, the combination of either the bipolar strobe waveform or the data waveform yields a pixel waveform that is a switching pulse waveform. Such a waveform is shown in Figures 2-5, which is the first pulse, a switching pulse with sufficient pulse width and pulse height to switch selected pixels. A second pulse that charges and balances the first pulse with a pulse height greater than the sufficient pulse height of this switching pulse and a pulse width insufficient to switch back the selected pixels. And, if necessary, it consists of a zero voltage signal that does not affect its charge balance. In the configuration of FIG. 5, the switching pulse itself is identified as two pulses, one of the two pulses has a smaller pulse height than the other, and the overall pulse width is the smaller pulse height. It differs from the configurations shown in FIGS. 2 to 4 in that it is sufficient to switch the selected pixels. As can be seen from FIGS. 2 to 5, the response time of the liquid crystal material at the pulse height of the switching pulse at the minimum line address of each configuration is t.<sub>s</sub>Less than twice. In Fig. 2, Fig. 3 and Fig. 5, the line address time is 1.5t.<sub>s</sub>And in Fig. 4, the line address time is 1.3t.<sub>s</sub>Is. The configuration line address time in Figure 4 is smaller than that in the configurations in Figures 2, 3 and 5, but requires more output states. FIG. 6 shows the electro-optic properties of a ferroelectric liquid crystal material such as the biphenyl ester described above, which is suitable for use in a matrix array type liquid crystal cell addressed by the method of the present invention. The electro-optical characteristic is a graph showing the response time of the liquid crystal material with respect to the potential difference of the material. Since there is a minimum value for that characteristic, t<sub>m</sub>Pulses of smaller width do not switch pixels regardless of the height of the pulse. Therefore, as can be seen from Fig. 5, the height V<sub>1</sub>And width t<sub>1</sub>Switching pulse is V<sub>1</sub>Greater height V<sub>2</sub>And width t<sub>2</sub>It can be charge-balanced by a pulse with, and its width t<sub>2</sub>Is t<sub>m</sub>It is smaller and is not wide enough to switch pixels regardless of pulse height. The method of the present invention has a response time t<sub>s</sub>Can be used to address a matrix array type liquid crystal cell provided with a liquid crystal material such as fluoroterphenyl having electro-optical properties as shown in FIG. 7, which gradually changes with a potential difference. In this case, height V<sub>3</sub>And width t<sub>3</sub>Switching pulse is V<sub>3</sub>Greater height V<sub>4</sub>And height V to switch selected pixels<sub>4</sub>Insufficient width t compared to<sub>4</sub>It is charged and balanced by the pulse of. Therefore, there is an element of switching depending on the pulse height and the pulse width. The electro-optic characteristics have the minimum value, but the pulse height and width of the switching pulse are t.<sub>3</sub>Both pulse width and pulse height must be considered if the charge balance is to be provided by a larger width pulse. The relatively complex waveforms in Figures 2-5 need not be generated independently by each row or column driver. In each case, the row or column output stage only needs to be switched between one of the two waveforms. Figures 8 and 9 show the switching voltage or pixel waveform and the oscilloscope waveform of the optical response obtained from the simulation of the proposed configuration. Figure 8 shows that when no row is selected, the liquid crystal switches between optically identifiable states and is in a stable state, with the switching waveform being too fast for oscilloscope sampling. Figure 9 shows the switching point S in more detail. Switching occurs when a wide pulse is applied. Narrower equalization and crosstalk pulses act to stabilize the pixel state. Effectively for two-level representations, especially for the relatively complex waveforms used in the methods of the invention, as disclosed in the European patent applications corresponding to UK patent applications 8717172 and 8718351. Readily available integrated circuits can be used to implement complex XY matrix display drive schemes. Display driver chips in the form of n-stage shift registers with multiple high voltage CMOS outputs and latched outputs are available. The obvious limitation of these devices is that they have two power states. The output voltage is the high voltage or the ground voltage. This limitation is removed by using the configurations and methods according to the invention. FIG. 10 is a block diagram showing the configuration and method of the present invention. This circuit generates a second waveform B on the second supply rail 23, which acts as a ground potential for this circuit, and a means 20 for generating the first waveform A on the first supply rail 21. Means 22 are provided. The display driver chip 24 has a plurality of outputs, each of which has a switch for switching the output to waveform A on the first supply rail 21 or waveform B on the second supply rail 23. There is. Therefore, each output waveform is generated for each of the plurality of outputs. The selective switching of each output to waveform A or B is controlled by control from a control circuit (not shown) and output latch data. Since the ground potential of the drive circuit changes with the voltage of waveform B as a whole, the data is fed to the driver chip 24 via means for separating the data waveform, so that the data is like the Ooft isolator 26. It relates to the supply rail 23. If the logical value of one output is "1", the output is switched to waveform A on supply rail 21, and if that logical value is "0", the output is switched to waveform B on supply rail 23. .. The power supply to the driver chip 24 consists of a separate power supply 28 for providing a constant 12V potential difference with respect to the potential of the ground supply rail 23. One embodiment of the drive circuit is shown in FIG. Waveforms X and Y on supply rails 30 and 32 are generated by first and second 4-way high voltage multiplexers 34, 36. Each multiplexer 34, 36 has four voltages to generate each waveform, for example, 2Ve, Ve, 0 and -Ve for the multiplexer 34, and Ve, 0, -Ve and -2Ve for the multiplexer 36. A state can be generated, and the voltage state generated at any time is one of those four states and the logical input S to the multiplexer 34 as shown below.<sub>1</sub>, S<sub>2</sub>And the logical input S for the multiplexer 36<sub>3</sub>, S<sub>4</sub>Determined by.<img file="JP2558331B2_D0001.tif" /> For the biphenyl ester mentioned above, Ve = 35V can be used. The display driver chip 38 for this circuit is a Si 9555 (manufactured under the Siliconix trademark) with 32 channels, namely a 32-bit stage shift register, 32 latches and 32 outputs. Each one of those outputs is switched to the voltage of supply rail 30 (ie waveform X) by the logical input of "1" or to the voltage of supply rail 32 (ie waveform Y) by the logical input of "0". The logic for controlling the multiplexers 34 and 36 and the driver chip 38 is generated and synchronized by the gate array 40. FIG. 11 shows three outputs from the gate array 40 connected via three optoisolators (indicated by the number 42 as a whole) by each of the three inputs of the driver chip 38. These three illustrated inputs consist of a clock input and a data input that loads logic in series with a 32-bit stage shift register, and when high the contacts of the 32-bit stage shift register are known in a known manner. A latch that is shifted into the output register acts. Two supply rails, -2Ve and -2Ve + 5V, power the gate array 40 itself. The driver chip 38 is powered by a 12V constant DC power source generated by a separate power supply 44 connected between the positive power supply rail 45 and the grounded supply rail 32. Inputs 46 and 48 to the power supply 44 are connected to the 240V AC main power supply. The voltage is transformed by the transformer 50 and rectified by the full-wave rectifier 52. Power supply 44 is further 10000 μF electrolytic capacitor C<sub>1</sub>, 7812 Voltage Regulator 54 and 100nF Capacitor C<sub>2</sub>Is equipped with. The generated 12V constant DC power supply is constant with respect to the grounded supply rail 32, so that the positive power supply rail 45 has the voltage of waveform Y superimposed on it. A typical display device has hundreds of row and column electrodes and therefore requires a large number of driver chips. However, a single multiplexer 34, multiplexer 36, separate power supply 44 and gate array 40 may be provided for a set of row or column electrodes and the corresponding driver chip. Therefore, the chip is effectively used as a set of analog switches rather than being used as a two-state driver. The latches and shift registers are powered separately to form a high voltage output stage, so their operation is unaffected as long as that power is maintained with respect to ground (waveform B). Any of those outputs can be switched to waveform A or waveform B. The only limitation is that the instantaneous voltage of waveform A must not be less than the voltage of waveform B more than the forward voltage drop of the two diodes. If two alternative row or column drive waveforms intersect, the contents of the output latch can be inverted and the waveforms exchanged. FIG. 12 shows how this method and configuration can be used to implement the configuration of FIG. The left column shows the waveform for the drive circuit for the row electrodes and the right column shows the waveform for the drive circuit for the column electrodes. Figures 12a and 12b show waveforms A and B supplied to the row drive circuit supply rails. The strobe waveform (Fig. 12c) is generated by the data sequence of 000111, and the non-strobe waveform (Fig. 12d) is generated by the data sequence of 111000. Figures 12e and 12f show waveforms A and B applied to the supply rails of the row drive circuit. The column "on" waveform (Fig. 12g) is generated by the data sequence of 110011, and the column "off" waveform (Fig. 12h) is generated by the data sequence of 001100. Similar waveforms A and B can be devised for the configurations of FIGS. 2, 4 and 5.
[Simple explanation of drawings]
FIG. 1 is a schematic view of a liquid crystal display device that can be driven by the method of the present invention, FIGS. 2 to 5 are diagrams showing a waveform configuration by the method of the present invention, and FIGS. 6 and 7 are the first display. Figures 8 and 9 show the electro-optical properties of liquid crystal materials that can be used in the device, Figures 8 and 9 show the switching voltage and pixel optical response in the display device of Figure 1 on different time scales, Figure 10 shows. The schematic diagram of the drive circuit for the display device of FIG. 1, the figure 11 shows the drive circuit for the display device of FIG. 1, and FIG. 12 is the drive circuit for carrying out the waveform configuration of FIG. It is a figure which shows the waveform used. In the drawings, 2 is a liquid crystal cell, 4 is a pixel, 6 is a row electrode, and 8 is a column electrode.
13 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13
Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| JP63193131A | Cites | Japan |
| JP61230197A | Cites | Japan |
| JP62205322A | Cites | Japan |
| JP60154996U | Cites | Japan |
26 members in 8 offices
Priority claims10
| Document | Office | Kind | Date |
|---|---|---|---|
| 8717172 | United Kingdom | A | |
| 8717172 | United Kingdom | A | |
| 8718351 | United Kingdom | A | |
| 8718351 | United Kingdom | A | |
| 8717172 | – | – | – |
| 8718351 | – | – | – |
| 8717172 | United Kingdom | – | – |
| 8718351 | United Kingdom | – | – |
| GB19870017172 | – | – | – |
| GB19870018351 | – | – | – |
Members26
| Document | Office | Kind | |
|---|---|---|---|
| GB8717172D0 | United Kingdom | D0 | |
| GB8718351D0 | United Kingdom | D0 | |
| EP0300754A2 | European Patent Office (EPO) | A2 | |
| EP0300755A2 | European Patent Office (EPO) | A2 | |
| JPS6448042A | Japan | A | |
| JPS6454421A | Japan | A | |
| EP0300754A3 | European Patent Office (EPO) | A3 | |
| EP0300755A3 | European Patent Office (EPO) | A3 | |
| US5010328A | United States of America | A | |
| US5111319A | United States of America | A | |
| CA1311318C | Canada | C | |
| CA1311319C | Canada | C | |
| EP0300755B1 | European Patent Office (EPO) | B1 | |
| AT96240T | Austria | T | |
| ATE96240T1 | Austria | T1 | |
| DE3885026D1 | Germany | D1 | |
| EP0300754B1 | European Patent Office (EPO) | B1 | |
| AT98801T | Austria | T | |
| ATE98801T1 | Austria | T1 | |
| DE3886290D1 | Germany | D1 | |
| ES2046302T3 | Spain | T3 | |
| ES2047551T3 | Spain | T3 | |
| DE3885026T2 | Germany | T2 | |
| DE3886290T2 | Germany | T2 | |
| JP2558331B2This record | Japan | B2 | |
| JP2609690B2 | Japan | B2 |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Cancellation because of no payment of annual feesLAPS | LAPS |
Numbers
- Publication
- 2558331
- Publication, DOCDB
- 2558331
- Publication, EPODOC
- JP2558331B
- Application
- 63179275
- Application, DOCDB
- 17927588
- Application, EPODOC
- JP19880179275
Titles2
- Japanese
- 液晶セルのアドレス方法及び液晶表示装置
- English
- INDUSTRIAL APPLICABILITY: Liquid crystal cell addressing method and liquid crystal display device
Classification
- CPC, 5
- G09G3/3692
- G09G3/3629
- G09G3/3681
- G09G2310/06
- G09G2330/02
- IPC, 2
- G02F1 133
- G09G3 36
