Vector processor using buffer for preparing vector data.

Description: TECHNICAL FIELD [Detailed description of the invention]

[Industrial application field] The present invention relates to a vector processing apparatus, and more particularly to an improvement of a vector data loading method. [Conventional technology] In general, a vector processing device is a storage unit (main memory) that stores instructions and data, an operation execution unit that performs vector operations, and a storage control that supplies instructions from the storage unit to an execution instruction control unit or supplies data to an operation execution unit. It includes a unit and an execution instruction control unit that controls each unit by decoding instructions, managing resources, etc., and can process vector data at high speed by a so-called pipeline method. Now, the configuration and operation of the conventional vector processing apparatus will be described by taking the following vector processing instruction sequence as an example. VLD V1 ... (1) VADD V2 S + V1 ... (2) VLD V3 ... (3) VMPY V4 V2 × V3 ... (4) Here, instruction (1) is a vector load instruction that loads vector data from the storage unit into vector register V1, and instruction (2) adds scalar data S to the vector data loaded into vector register V1 by instruction (1). The vector addition instruction that stores the result in the vector register V2, the instruction (3) is the vector load instruction that loads the vector data from the storage into the vector register V3, and the instruction (4) is stored in the vector register V2 by the instruction (2). This is a vector multiplication instruction that multiplies the vector data and the vector data loaded in the vector register V3 by the instruction (3) and stores the result in the vector register V4. FIG. 6 is a time chart when the above-mentioned vector processing instruction sequence is executed by a conventional vector processing device. When the instruction (1) is stored in the instruction register, the execution instruction control unit decodes the instruction (1) and sends this vector load instruction to the storage control unit because it is a vector load instruction. When the storage control unit receives the vector load instruction, it accesses the storage unit and loads the vector data into the vector register V1. On the other hand, when the instruction control unit finishes decoding the instruction (1), the instruction (2) is decoded in parallel with the activation of the instruction (1). Since this instruction (2) is an instruction that uses the vector data loaded by the instruction (1), the execution instruction control unit waits for the vector data to be loaded in the vector register V1 and loads the vector data in the vector register V1. When it starts, the instruction (2) is activated in the calculation execution unit. The activated arithmetic execution unit adds the scalar data S to the vector data of the vector register V1 and stores the result in the vector register V2. When the execution instruction control unit activates the instruction (2), it recognizes that the instruction (3) is an instruction that can be activated immediately from the decoding result of the next instruction (3), and gives the memory control unit a vector load instruction ( 3) is sent. In response to this, the storage control unit accesses the storage unit and performs a process of loading the vector data into the vector register V3. Next, the execution instruction control unit determines the decoding result of the instruction (4), but since this instruction (4) is an instruction that uses the results of the preceding instructions (2) and (3), the instruction is given to the vector register V2. The addition result by (2) is prepared, the load data is prepared in the vector register V3, and when they are prepared, the instruction (4) is activated to the operation execution unit. [Problems to be solved by the invention] As described above, in the conventional vector processing device, when the instruction to be executed next is the vector load instruction (1), (3), the vector load instruction (1), (3) is sent to the storage control unit. The storage control unit is configured to access the storage unit for the first time at that time and supply the read data to the calculation execution unit. Therefore, if the absolute time required to access the vector data of the storage unit from the storage control unit is long, there is a drawback that the performance of the vector processing device deteriorates. An object of the present invention is to prevent the performance of the vector processing apparatus from being deteriorated due to the time required for the storage control unit to access the vector data of the storage unit. [Means to solve problems] In order to achieve the above object, the present invention A storage unit that stores data, a calculation execution unit that performs vector operations, a storage control unit that supplies data from the storage unit to the calculation execution unit, and the storage control that performs instruction decoding, resource management of the calculation execution unit, and the like. In a vector processing device including an execution instruction control unit that sends control information to the unit and the calculation execution unit. The execution instruction control unit stores the instruction stored in the instruction register in the instruction storage unit, and when the instruction is a vector load instruction, the execution instruction control unit issues a load request to the storage control unit, and the first control means. The instruction stored in the instruction storage unit is decoded, and when the instruction is a vector load instruction, a data transfer enable signal is sent to the storage control unit on condition that resource conflict does not occur in the operation execution unit. Has a second control means The storage control unit has a buffer for temporarily storing data from the storage unit, starts reading data from the storage unit to the buffer in response to the load request, and at least a part of the data is read into the buffer. It has a configuration in which data transmission from the buffer to the calculation execution unit is started in response to the data transfer enable signal on condition that data has begun to be input. [Action] If the instruction stored in the instruction register is a vector load instruction, the first control means in the execution instruction control unit issues a load request corresponding to the vector load instruction to the storage control unit. The storage control unit accesses the storage unit in response to the load request and stores the vector data in the buffer. The instruction stored in the instruction register is transferred to the instruction storage unit, and then decoded by the second control means. When the instruction to be executed is a vector load instruction, the second control means performs a resource check to check whether resources such as the vector register of the load destination can be used, and transfers data to the storage control unit if possible. Send a signal. In response to this data transfer signal, the storage control unit sends the vector data stored in the buffer to the operation execution unit. [Example] Next, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a vector processing apparatus to which the present invention is applied. This vector processing device has an execution instruction control unit 1, a storage control unit 2 having a buffer 2a for temporarily storing data, a storage unit 3 for storing data and instructions, and an operation execution for executing a vector operation. Includes part 4 and. Further, the execution instruction control unit 1 includes an instruction register 11, an instruction stack 12, a decoding / conflict checking unit 13, a resource state management unit 14, and a decoding device 15. The instruction register 11 is a register that holds an instruction to be executed fetched from the storage unit 3 by a path (not shown), and the decoder 15 decodes the contents of the instruction register 11, and if it is not a vector load instruction, that instruction. Is stored in the instruction stack 12, and if it is a vector load instruction, the instruction is stored in the instruction stack 12 and a load request is sent to the storage control unit 2. When the storage control unit 2 receives the load request, the storage control unit 2 accesses the storage unit 3 and starts the process of storing the vector data in the buffer 2a. The resource state management unit 14 executes an operation based on a transfer enable signal issued from the decoding / conflict check unit 13, an execution instruction, an instruction added from the instruction stack 12, a transfer start signal sent from the storage control unit 2, and a transfer end signal. It manages the status of resources such as vector registers and arithmetic units in the unit, and sends the management information to the decoding / conflict check unit 13. The first instruction of the instruction stack 12 is decoded by the decoding / contention check unit 13, and the resource contention check is performed based on the resource management information added from the resource state management unit 14. If the first instruction of the instruction stack 12 is a vector load instruction, data is transferred to the storage control unit 2 and the resource state management unit 14 unless the vector register in the operation execution unit 4 to be loaded is a preceding instruction and is being written. Send a possible signal. When the storage control unit 2 receives the data transfer enable signal, it starts sending the data to the corresponding vector register of the arithmetic execution unit 4 when the corresponding data starts to enter the buffer 2a or if it is already stored in the buffer 2a. At the same time, the resource status management unit 14 is notified to that effect. Further, when the data transfer to the vector register is completed, the resource state management unit 14 is notified to that effect. When the first instruction of the instruction stack 12 is an arithmetic instruction, the decoding / conflict check unit 13 checks for conflicts such as whether or not the arithmetic unit that executes the arithmetic instruction is free, and whether or not arithmetic data is prepared. If there is no problem, an execution instruction is sent to the calculation execution unit 4 and the resource status management unit 14. In response to this, the calculation execution unit 4 performs a vector operation on the data held in the vector register. Fig. 2 shows the following instruction sequence used in the explanation of the conventional example. VLD V1 ... (1) VADD V2 S + V1 ... (2) VLD V3 ... (3) VMPY V4 V2 × V3 ... (4) Is a time chart when processed by the vector processing apparatus shown in FIG. Hereinafter, the operation of this embodiment will be further described with reference to the time chart of FIG. When the instruction (1) is stored in the instruction register 11, the decoder 15 issues a load request a to the storage control unit 2, and the storage control unit 2 performs a process of reading data from the storage unit 3 into the buffer 2a. Start. When the instruction (1) is stored on the instruction stack 12 and then the instruction (2) is decoded by the decoder 15, it is simply stored on the instruction stack 12 because it is an arithmetic instruction. Next, when the instruction (3) is decoded, since it is a vector load instruction, a load request b is issued from the decoder 15 to the memory control unit 2, and the memory control unit 2 reads the data from the storage unit 3 and reads it into the buffer 2a. Start the process of inserting. Since the next instruction (4) is an operation instruction, it is simply stored on the instruction stack 12. Instructions are stored in the instruction stack 12 in the order of instruction (1), instruction (2), instruction (3), instruction (4), and are processed by the decoding / conflict check unit 13 in order from the first instruction (1). To. When the decryption / conflict check unit 13 decodes the instruction (1) and recognizes that the instruction (1) is a vector load instruction, the resource state management unit 14 determines whether or not the load destination vector register V1 can be used. By checking according to the information and being available, a data transfer enable signal c is sent to the storage control unit 2 to instruct the data transfer, and the data transfer is also performed to change the management state of the vector register V1. The possible signal c is sent to the resource status management unit 14. When the decoding / conflict check unit 13 finishes decoding the instruction (1), the next instruction (2) is decoded, and the instruction (2) uses the data of the vector register V1 loaded by the instruction (1). Since it is found from the information from the resource state management unit 14 that the data is not stored in the vector register V1 yet, the instruction (2) is waited for activation. The storage control unit 2 that receives the data transfer enable signal c issued from the decoding / conflict check unit 13 transfers the data to the vector register V1 in the arithmetic execution unit 4 when the corresponding data is prepared in the buffer 2a. .. At the same time, the transfer start signal d is sent to the resource state management unit 14 in order to update the management state of the vector register V1. Further, at the end of the transfer, the resource status management unit 14 is notified to that effect in order to update the management status of the vector register V1. When the decoding / conflict checking unit 13 identifies that the corresponding data has been prepared in the vector register V1 from the information from the resource state management unit 14, the decoding / conflict checking unit 13 executes the arithmetic execution unit 4 in order to activate the waiting instruction (2). Send instructions. As a result, the operation execution unit 4 starts the vector addition operation of the instruction (2) and stores the result in the vector register V2. The above execution instruction is also sent to the resource state management unit 14 in order to update the management information of the vector register V1. When the decoding / conflict check unit 13 activates the instruction (2), the resource state management unit 14 determines whether or not the load destination vector register V3 can be used because the next instruction (3) is a vector load instruction. It checks based on the information, and if it is available, sends a data transfer enable signal e to the storage control unit 2 and the resource status management unit 14. Upon receiving the above data transfer enable signal e, the storage control unit 2 starts the process of transferring the data to the vector register V3 of the arithmetic execution unit 4, but as is clear from the time chart of FIG. 2, it precedes. Since most of the data to be transferred by the load request b is already stored in the buffer 2a, the data transfer actually starts to the arithmetic execution unit 4 after the data transfer enable signal e is added from the execution instruction control unit 1. The time required for this is short, and the necessary data is quickly stored in the vector register V3. In FIG. 2, f is a transfer start signal. When the decoding / conflict check unit 13 finishes invoking the instruction (3), the next instruction (4) is an instruction that uses the vector registers V2 and V3 processed by the preceding instructions (2) and (3). Then, the instruction (4) is waited to be activated until they are prepared, and when the instruction (4) is prepared, the instruction (4) is activated to the operation execution unit 4. As a result, the arithmetic execution unit 4 multiplies the data of the vector register V2 and the data of the vector register V3, and stores the result in the vector register V4. FIG. 3 is a block diagram of a main part of an embodiment of the memory control unit 2. When the main memory request control circuit 200 receives a load request from the decoder 15 in FIG. 1, the main memory request control circuit 200 finishes the processing if there is a load request being processed, and if not, promptly processes the received load request. Access information such as a main memory request and an address is sent to the storage unit 3, and the write / read control circuit 201 is activated. Upon receiving the main memory request, the storage unit 3 sends information including the data of the corresponding address to the storage control unit 2. The data sent from the storage unit 3 is stored in the buffer 2a according to the address generated by the write / read control circuit 201. On the other hand, the main memory request issued from the main memory request control circuit 200 becomes a count-up signal of the counter 203 via the time adjustment circuit 202. The time adjustment circuit 202 is for increasing the counter 203 by +1 after the lapse of time after the main storage request is issued and the corresponding data will start to be stored in the buffer 2a. Therefore, the counter 203 indicates the number of processed load requests for which the corresponding data is prepared in the buffer 2a. The zero check circuit 204 checks whether the content of the counter 203 is "0", and if it is not "0", the output to the gate 205 is set to logic "1", and if it is "0", it is set to logic "0". To do. The gate 205 is a gate that opens when the output of the zero check circuit 204 is 1 and the timing signal 208 is 1. The data transfer enable signal from the decoding / conflict check unit 13 of FIG. 1 is received by the stack 206. When the data transfer enable signal is stored in the stack 206, the read circuit 207 extracts one data transfer enable signal from the stack 206 and adds it to the gate 205. Therefore, if the content of the counter 203 is not "0", the data transfer enable signal passes through the gate 205 at the timing of the timing signal 208 and is output as the transfer start signal. Since the data transferable signal naturally includes information about which vector register can be transferred, the transfer start signal also includes information about which vector register can start transfer, and write / read control. It is sent to the circuit 201, the counter 203, and the resource status management unit 14 of FIG. The write / read control circuit 201 sequentially generates an address for reading the corresponding data stored in the buffer 2a by the data transfer enable signal, and transfers the data to the corresponding vector register of the calculation execution unit 4 of FIG. Further, the counter 203 decrements the content by the above data transfer enable signal. The transfer start signal output from the gate 205 is also added to the time adjustment circuit 209, and the time adjustment circuit 209 completes the transfer of the corresponding data to the corresponding vector register after the transfer start signal is added to the write / read control circuit 201. A transfer start signal is sent to the gate 210 after the lapse of time. The gate 210 is a gate that opens at the timing of the timing signal 211 that is periodically generated, and the transfer start signal is sent to the resource state management unit 14 of FIG. 1 as a transfer end signal through the gate 210. FIG. 4 is a block diagram of a main part of an embodiment of the resource state management unit 14. In the resource state management unit 14 of this embodiment, each arithmetic unit is connected to a plurality of dedicated vector registers, and the resource management of the vector registers is performed so that the resource management of the arithmetic units is also performed at the same time. Of course, the form of resource management is not limited to this. In FIG. 4, the load weight management flag group 300, the load busy management flag group 301, the read busy management flag group 302, and the write busy management flag group 303 each have a flag corresponding to a vector register. Which flag in each flag group 300, 301, 302, 303 is to be updated depends on the data transfer enable signal sent from the decoding / conflict check unit 13, the resource information included in the execution instruction, and the transfer start sent from the storage control unit 2. It is determined according to the resource information included in the signal and transfer end signal. The load weight management flag group 300 is set by the data transfer enable signal and reset by the transfer start signal. The load busy management flag group 301 is set by the data transfer enable signal and reset by the transfer end signal. The read busy management flag group 302 is set by the execution instruction of the vector operation and is reset by the read end signal. The write busy management flag group 303 is set by the execution instruction of the vector operation, and is reset by the write end signal. The time management circuit 304 is based on the number of vector elements of each instruction from the instruction stack 12, the time from the reception of the vector operation execution instruction to the end of reading the vector register, and the time of receiving the vector operation execution instruction. The time from to the end of writing to the vector register is measured, a read end signal is generated at the end of reading, and a write end signal is generated at the end of writing. Information indicating the set and reset status of each of the above flag groups (LDW, LDBSY, RBSY, WBSY) is sent to the decoding / conflict check unit 13 as resource management information. FIG. 5 is a block diagram showing a configuration example of the decoding / conflict check unit 13, and shows only a partial configuration. When the stack head instruction is, for example, a vector load instruction for loading vector data into the vector register VRi, the decoder 400 outputs a signal VLDi corresponding to the vector register VLi and adds it to the gates 401 and 402. A signal LDBSYi indicating whether the vector register VRi is busy is added to the gate 401 from the resource state management unit 14, and a signal WBSYi indicating whether the vector register VRi is light busy is added to the gate 402. When the vector register VRi is neither load busy nor write busy, the signal VLDi is transmitted via the gate 403 as a data transferable signal. If the stack head instruction is, for example, an operation instruction that reads the contents of the vector register VRj, performs an operation, and writes the result to the vector register VRk, the decoder 400 outputs a signal VRrj for reading the vector register VRj to the gates 404 and 405. At the same time, the signal VRwk for writing the vector register VRk is output and added to the gates 406 and 407. From the resource state management unit 14, the gate 404 has a signal RBSYj indicating whether the vector register VRj is read busy, the gate 405 has a signal LDWj indicating whether the vector register VRj is in load weight, and the gate 406 has a vector. A signal WBSYk indicating whether the register VRk is busy or not is added to the signal WBSYk, and a signal LDBSYk indicating whether the vector register VRk is busy load is added to the gate 407. An instruction to execute the vector operation is issued. Although the examples of the present invention have been described above, the present invention is not limited to the above examples, and various other additions and changes are possible. For example, in the above embodiment, each instruction in the decoding / conflict check unit 13 is activated in the order of instructions instructed by the software, but if there is an instruction waiting to be activated, if there is a subsequent instruction that can be executed independently, it precedes. The present invention is also applicable to the activation method. Since the instruction (3) can be executed independently of the instructions (1) and (2) in the instruction sequences (1) to (4), the processing speed is improved by activating the instruction (2) in advance. However, if the instruction (3) is an instruction that loads data into the vector register V1 instead of the vector register V3, the instruction (3) cannot be activated until the instruction (2) is completed, so it is necessary for the instruction (3). The processing speed can be improved by applying the present invention in which various vector data are loaded into the buffer of the storage control unit 2 in advance. [Effect of the invention] As described above, the present invention is a storage that accesses a storage unit by receiving a load request, stores vector data in a buffer, and sends data from the buffer to an arithmetic execution unit by receiving a data transfer enable signal. A control unit is provided, and in the case of a vector load instruction, the execution instruction control unit issues a load request to the storage control unit at an early stage, so that the time required for the storage control unit to access the vector data of the storage unit. It is possible to prevent the performance of the vector processing apparatus from being deteriorated. Further, since the storage control unit starts sending data from the buffer to the arithmetic execution unit if at least a part of the data has begun to enter the buffer, the storage unit loads the data into the buffer prior to the execution of the vector load instruction. When the execution of the vector load instruction is started and a data transfer enable signal is generated during the process, the transfer time is compared with the case where all the data is temporarily stored in the buffer and then read out and supplied to the calculation execution unit. Can be shortened.

[Simple explanation of drawings]

FIG. 1 is a block diagram showing an example of a vector processing apparatus to which the present invention is applied. FIG. 2 is a time chart of an embodiment of the present invention. FIG. 3 is a block diagram of a main part of an embodiment of the memory control unit 2, Fig. 4 is a block diagram of the main parts of the example of the resource status management unit 14. FIG. 5 is a block diagram of the main parts of the embodiment of the decoding / competition check unit 13 and FIG. 6 is a conventional time chart. In the figure 1 ...... Execution instruction control unit, 12 ...... Instruction stack 2 ...... Memory control unit, 13 ...... Decoding / conflict check unit 2a ...... buffer 3 ...... Memory unit, 14 ...... Resource status management unit 4 ...... Arithmetic execution unit, 15 ...... Decoder 11 ...... Instruction register