Interface device

Description: TECHNICAL FIELD [Detailed description of the invention]

[Industrial application field] The present invention relates to an image processing apparatus having a storage means capable of storing a plurality of types of image data.

[Conventional technology] Images are generally divided into binary images such as characters and line arts and multi-valued images having halftones such as photographs. Of these images, binary images are required to have high resolution, whereas multivalued images emphasize gradation expression and generally do not require the same resolution as binary images. However, if a system that handles such images tries to satisfy both resolution and gradation, the amount of image information will be enormous. It is divided into a system that emphasizes gradation for toned images, and there is no system that can efficiently process both images. However, in reality, there are very large demands for devices that can process binary images and multi-value images, such as mixed images of characters and photographs.

[Problems that the invention tries to solve] The present invention has been made in view of the above conventional example, and in a device that handles a plurality of types of image data different from each other, when displaying an image, the quality of the image is good and the data processing for the display can be efficiently performed. It is an object of the present invention to provide an image processing apparatus capable of providing an image processing apparatus.

[Means to solve the problem] In order to achieve the above object, the image processing apparatus of the present invention has the following configuration. That is, Input means for inputting multi-valued image data and A first data compression means that compresses the amount of data by lowering the resolution of the multi-valued image data input by the input means, and A first storage means for storing multi-valued image data compressed by the first data compression means, and a first storage means. A second data compression means that compresses the amount of data by reducing the gradation of the multi-valued image data input by the input means, and A second storage means for storing multi-valued image data compressed by the second data compression means, and a second storage means. It has a display means for displaying according to the multi-valued image data input by the input means.

[Action] In the above configuration, the first data compression means reduces the resolution of the multi-valued image data input by the input means to compress the amount of data and store it in the first storage means, and the second data compression. By means, the amount of data is compressed and stored in the second storage means by lowering the gradation property of the multi-valued image data input by the input means. Then, it operates so as to display on the display device using the multi-valued image data stored in the first storage means.

[Example] Hereinafter, examples of the present invention will be described in detail with reference to the accompanying drawings.

[Explanation of image processing system (Fig. 1)] FIG. 1 is a configuration diagram of an image processing system using an interface circuit according to an embodiment of the present invention. In the figure, 1 is a CPU, which is a host computer, and has a main memory used as a work area as well as a control program. 2 is a frame buffer, which stores image data for at least one screen. 3 is a CRT that displays the image data of the frame buffer 2 and displays instructions from the keyboard 4 and the pointing device 5, and 4 is a keyboard that inputs various commands and control information. Reference numeral 5 denotes a pointing device (PD), which gives an area instruction or the like on the image displayed on the CRT3 as described later. Reference numeral 6 denotes a disk device, which stores image data and the like input from the image skiyana 7 and the like, which will be described later. 7 is a system bus that connects CPU 1 and various buffers, etc., and CPU 1 is configured so that each buffer can be accessed via system bus 7. The above is the system configuration on the host computer side. 8 is an image printer that reads image information by photoelectric conversion and inputs it as multi-valued image data, and 9 is a printer that prints with multi-valued data. Reference numeral 10 denotes an interface circuit of this embodiment, which is controlled by the controller 11. The multi-value image data from the image skiana 8 is simultaneously input to the multi-value binary conversion circuit 13 and the resolution conversion circuit 14 via the video bus 12. In the multi-value binary conversion circuit 13, the input multi-value data is binarized by threshold processing and stored in the binary buffer 15. On the other hand, the resolution conversion circuit 14 converts the input multi-value data to low resolution by thinning or the like and stores the multi-value buffer 16. When the image data is output to the printer 9, the binary data of the binary buffer 15 is converted in min / max density by the multi-value binary conversion circuit 13 and output as multi-value. Further, the multi-value data of the multi-value buffer 16 is interpolated by the resolution conversion circuit 14, and the low-resolution data is expanded from the multi-value binary conversion circuit 13 according to the dot density of the multi-value data. .. 17 is an address counter that indicates read / write to the binary value 15 and the multi-valued image 16 and the area control image 18, and 19 is an address counter that indicates read / write to the area control image 18 according to the area information 20 from the area control image 18 when the image data is output. This is a switching circuit that switches and outputs image data from the multi-value binary conversion circuit 13 and the resolution conversion circuit 14. As will be described later, when the pointing device 5 indicates a binary or multi-valued image area on the image displayed on the CRT3, the area control buffer 18 sets the data of the area control buffer 18 to, for example, 2. The value area is stored as "1" and the multi-value area is stored as "0". Then, when the image data is output, the area information 20 of "1" or "0" is output in synchronization with the reading of the binary and multi-value buffers 15 and 16.

[Explanation of image editing examples (Figs. 2 and 3)] FIG. 2 (A) shows the image data input from the image skiyana 8, where 200 is a photographic part and 201 is a character part. FIG. 2B shows image data for print output in which the photograph portion 200 is moved. Hereinafter, the state of each buffer at the time of image input and at the time of image output, and the operation at the time of image movement will be described with reference to FIG. First, when multi-valued image data is input from the image skiyana 8, the binary-valued image data binarized by the multi-valued binary conversion circuit 13 is stored in the binary-value buffer 15. At the same time, the multi-valued image reduced in resolution by the resolution conversion circuit 14 is stored in the multi-valued buffer 16. This is shown in Fig. 3 (a). Here, 30 is the photo part and 31 is the character part. Next, in Fig. 3 (b), CPU1 reads the multi-value data of the multi-value buffer 16 via the system bus 7, stores it in the frame buffer 2, and monitors it on the CRT3. Here, the operator points to the photo portion 30 by PD5 while looking at CRT3. As a result, the bits of the area 32 corresponding to the photographic area 30 in the area control buffer 18 are inverted, and the area information is stored. ((C) in Fig. 3). Next, in (d) of FIG. 3, when the operator instructs the movement of the photographic portion 30 on the CRT3 by the PD5, the photographic area 30 is moved as shown in the figure in the frame buffer 2, and the photographic portion on the CRT3 is moved. The display moves accordingly. When the above editing work is completed, the photo area 30 is moved in the same manner on the binary value buffer 15, the multivalued battery 16 and the area control panel 18 according to the operator's editing end instruction (Fig. 3 (e)). .. This movement is performed, for example, as follows. First, CPU1 reads the binary image data of one pixel in the photo area 30 of the binary buffer 15 and the binary image data of the pixel to which the pixel is moved via the system bus 7, and replaces both to make the binary buffer again. Store in 15. By performing this means on all the pixels in the photographic area 30, the binary image in the binary buffer 15 is in the state shown in FIG. 3 (e). The multi-value buffer 16 and the area buffer 18 can also be moved as shown in FIG. 3 (e) by moving in the same manner as in the binary buffer 15. Finally, according to a print instruction from the keyboard 4 or the like, each image data and area information 20 are read out in synchronization from the three buffers 15 to 18. The binary image data of the binary buffer 15 is converted into the multi-value image data by the multi-value binary conversion circuit 13, and the low-resolution multi-value data on the multi-value buffer 16 is converted into the multi-value image data by the resolution conversion circuit 14. The value is stretched to match the resolution (dot density) on the image data side. One of these two image data is selected for output according to the area information 20 read from the area control buffer 18 by the switching circuit 19, and is output to the printer 9. As a result, it is possible to obtain an image represented by high-resolution binary data in the character portion and multi-valued data having low resolution and gradation in the photo portion. Further, when this image data is stored in the disk device 6, each of the binary / multi-value image data cut out according to the area information 20 is stored after performing data compression suitable for each. Data can be compressed significantly. In this embodiment, the case of image editing has been described, but the present invention is not limited to this and can be applied to a wide range. As described above, according to the present embodiment, a high-resolution binary image and a low-resolution multi-value image created based on the same high-resolution multi-value data are provided on an independent binary or multi-value interface. By being able to input and output at the same time and making each battery randomly accessible from the system bus on the host computer side, the host computer has the effect of being able to handle high-quality images with a small amount of data by freely using each battery. ..

[Effect of the invention] As described above, according to the present invention, there is a first storage means for storing image data with reduced resolution and a second storage means for storing image data with reduced gradation. In the image processing device, when displaying by the display means, by using the multi-valued image data stored in the first storage means, an image having good gradation can be displayed by a simple process. There is an effect.

[Simple explanation of drawings]

FIG. 1 is a configuration diagram of an image processing system using the interface circuit of this embodiment. Fig. 2 (A) shows an example of image data input from Image Skiana. FIG. 2 (B) is a diagram showing an example of image data for print output in which the photographic portion of the image data of FIG. 2 (A) is moved. FIG. 3 is a transition diagram showing the procedure of image editing and the state of each buffer accompanied by editing. In the figure, 1 ...... CPU, 2 ...... frame circuit, 3 ...... CRT, 4 ...... keyboard, 5 ...... pointing Device (PD), 6 ... disk device, 7 ... system bus, 8 ... image keyboard, 9 ... printer, 10 .... .. interface circuit, 11 ...... controller, 12 ...... video bus, 13 ...... multi-value binary conversion circuit, 14 ...... resolution conversion circuit, 15 ...... Binary value, 16 ... Multi-valued, 17 ... Address counter, 18 ... Area control, 19 ... Switching circuit, 20 ... area information, 30, 200 ... photo part, 31,201 ... character part.