Semiconductor device and electronic appliance

The present invention relates to semiconductor devices and methods for driving them. More particularly, to semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, or methods for driving them, having a drive circuit formed on the same substrate as the pixel portion. Alternatively, it relates to electronic equipment having said semiconductor device, said display device, said liquid crystal display device, or said light-emitting device.

In recent years, the development of large-screen display devices such as LCD televisions has been actively pursued. In particular, the technology of forming drive circuits, such as gate driver circuits, on the same substrate as the pixel portion using transistors with non-single-crystal semiconductors is being actively developed because it greatly contributes to reducing manufacturing costs and improving reliability (for example, Patent Document 1).

<p><patcit num="1"><text>Japanese Patent Publication No. 2004-78172</text></patcit></p>

<p>However, as described in Patent Document 1, the amplitude voltage of the clock signal input to the shift register circuit will operate with the same amplitude as the gate signal (also called the scan signal or selection signal) output to the scan line in a scan line drive circuit. In order to reduce the power consumption of the drive circuit, it is necessary to keep the amplitude voltage of the clock signal low.</p><p>In view of the above issues, one aspect of the present invention aims to reduce the drive voltage of the drive circuit and thereby reduce the power consumption of the drive circuit.</p>

<p>One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first terminal of the first transistor is electrically connected to a first wire, the second terminal of the first transistor is electrically connected to a second wire, and the first terminal of the second transistor is electrically connected to a third wire. The second terminal of the second transistor is electrically connected to a second wire. The first terminal of the third transistor is electrically connected to a first wire, the second terminal of the third transistor is electrically connected to the gate of the first transistor, and the gate of the third transistor is electrically connected to a fourth wire. The first terminal of the fourth transistor is electrically connected to a third wire, the second terminal of the fourth transistor is electrically connected to the gate of the first transistor, and the gate of the fourth transistor is electrically connected to the gate of the second transistor. The first terminal of the fifth transistor is electrically connected to the fifth wire, the second terminal of the fifth transistor is electrically connected to the gate of the second transistor, and the gate of the fifth transistor is electrically connected to the sixth wire. The first terminal of the sixth transistor is electrically connected to the third wire, the second terminal of the sixth transistor is electrically connected to the gate of the second transistor, and the gate of the sixth transistor is electrically connected to the fourth wire.</p><p>In one embodiment of the present invention, a semiconductor device may be configured such that a first signal is input to a fourth wire, a second signal is output from a second wire, and the amplitude voltage of the second signal is greater than the amplitude voltage of the first signal.</p><p>In one embodiment of the present invention, the semiconductor device may be such that the first signal is a digital signal, the second signal is a digital signal, and when the first signal is at an H level, the second signal is at an H level, and when the first signal is at an L level, the second signal is at an L level.</p><p>In one embodiment of the present invention, the fourth wiring may be a semiconductor device electrically connected to the shift register circuit.</p><p>Note that in the figures, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown.</p><p>The diagram is a schematic representation of an ideal example and is not limited to the shapes or values shown in the diagram. For example, it may include variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.</p><p>Technical terms are often used to describe specific embodiments, etc. However, one aspect of the present invention is not intended to be interpreted as being limited by technical terms.</p><p>Furthermore, undefined terms (including scientific and technical terms such as specialized or academic terms) may be used with meaning equivalent to that of a person skilled in the art. Terms defined in dictionaries, etc., should preferably be interpreted in a way that is consistent with the background of the related technology.</p>

<p>One aspect of the present invention makes it possible to reduce the drive voltage of the drive circuit and thereby reduce power consumption.</p>

<figref num="1">An example of a circuit diagram of the semiconductor device in Embodiment 1.</figref><figref num="2">An example of a diagram illustrating the operation of the semiconductor device in Embodiment 1.</figref><figref num="3">An example of a schematic diagram illustrating the operation of the semiconductor device in Embodiment 1.</figref><figref num="4">An example of a schematic diagram illustrating the operation of the semiconductor device in Embodiment 1.</figref><figref num="5">An example of a circuit diagram of the semiconductor device in Embodiment 1.</figref><figref num="6">An example of a circuit diagram of the semiconductor device in Embodiment 1.</figref><figref num="7">An example of a circuit diagram of the semiconductor device in Embodiment 1.</figref><figref num="8">An example of a circuit diagram of the semiconductor device in Embodiment 1.</figref><figref num="9">An example of a circuit diagram of the semiconductor device in Embodiment 1.</figref><figref num="10">An example of a circuit diagram of the semiconductor device in Embodiment 1.</figref><figref num="11">An example of a circuit diagram of a semiconductor device in Embodiment 2.</figref><figref num="12">An example of a timing chart for illustrating the operation of the semiconductor device in Embodiment 2.</figref><figref num="13">An example of a timing chart for illustrating the operation of the semiconductor device in Embodiment 2.</figref><figref num="14">An example of a timing chart for illustrating the operation of the semiconductor device in Embodiment 2.</figref><figref num="15">An example of a circuit diagram of a semiconductor device in Embodiment 2.</figref><figref num="16">An example of a timing chart for illustrating the operation of the semiconductor device in Embodiment 2.</figref><figref num="17">An example of a block diagram of the display device in Embodiment 3 and an example of a pixel circuit diagram.</figref><figref num="18">An example of a circuit diagram of a semiconductor device in Embodiment 4, an example of a timing chart for explaining the operation of the semiconductor device, and an example of a block diagram of a display device.</figref><figref num="19">An example of a cross-sectional view of a semiconductor device in Embodiment 5.</figref><figref num="20">An example of a top view and an example of a cross-sectional view of the display device in Embodiment 6.</figref><figref num="21">An example of a diagram showing the manufacturing process of the semiconductor device in Embodiment 7.</figref><figref num="22">An example of a diagram illustrating the electronic device in Embodiment 8.</figref><figref num="23">An example of a diagram illustrating the electronic device in Embodiment 8.</figref>

The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the invention should not be interpreted as being limited to the descriptions of the embodiments. In the configurations described below, parts that are the same or have similar functions are indicated by common reference numerals between different drawings, and detailed descriptions of the same or similar functions are omitted.

Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and/or content described in one or more other embodiments (even if only a part of it).

The terms "first," "second," "third," etc., are used to distinguish various elements, components, areas, layers, and zones from each other. Therefore, the terms "first," "second," "third," etc., do not limit the number of elements, components, areas, layers, zones, etc. Furthermore, it is possible to replace, for example, "first" with "second" or "third."

(Embodiment 1) This embodiment describes an example of a semiconductor device and an example of a method for driving the semiconductor device. In particular, it describes an example of a level shifter circuit and an example of a method for driving the level shifter circuit.

First, an example of a semiconductor device according to this embodiment will be described.

Figure 1 shows an example of a semiconductor device. Circuit 100 includes circuits 110 and 120. Circuit 110 is connected to wiring 11, 13, 14, 16 and circuit 120. Circuit 120 is connected to wiring 11, 12, 15, 16 and circuit 110. However, this example of the embodiment is not limited to this. For example, circuits 100, 110, and 120 can be connected to various wirings depending on their configuration.

Circuit 110 has transistors 111 and 112. Circuit 120 has transistors 121, 122, 123 and 124. The first terminal of transistor 121 is connected to wiring 15, and the second terminal of transistor 121 is connected to wiring 12. The first terminal of transistor 122 is connected to wiring 16, and the second terminal of transistor 122 is connected to wiring 12. The first terminal of transistor 123 is connected to wiring 15, the second terminal of transistor 123 is connected to the gate of transistor 121, and the gate of transistor 123 is connected to wiring 11. The first terminal of transistor 124 is connected to wiring 16, the second terminal of transistor 124 is connected to the gate of transistor 121, and the gate of transistor 124 is connected to the gate of transistor 122. The first terminal of transistor 111 is connected to wire 14, the second terminal of transistor 111 is connected to the gate of transistor 122, and the gate of transistor 111 is connected to wire 13.

The first terminal of transistor 112 is connected to wiring 16, the second terminal of transistor 112 is connected to the gate of transistor 122, and the gate of transistor 112 is connected to wiring 11.

Note that the connection point between the second terminal of transistor 111, the second terminal of transistor 112, the gate of transistor 122, and the gate of transistor 124 will be indicated as node A. The connection point between the gate of transistor 121, the second terminal of transistor 123, and the second terminal of transistor 124 will be indicated as node B.

Transistors 111, 112, and 121-124 are all N-channel type. An N-channel transistor turns on when the potential difference between the gate and source becomes greater than the threshold voltage. Therefore, the semiconductor device of this embodiment can be constructed using transistors made of amorphous semiconductors, microcrystalline semiconductors, oxide semiconductors, or organic semiconductors. In particular, it is preferable to construct the semiconductor device of this embodiment using transistors made of oxide semiconductors. This is because using an oxide semiconductor as the semiconductor layer allows for higher transistor mobility. Therefore, it becomes easier to use the semiconductor device of this embodiment in high-resolution display devices or large-screen display devices. However, this is not the only example of this embodiment. For example, all of transistors 111, 112, and 121-124 can be P-channel type. A P-channel transistor turns on when the potential difference between the gate and source falls below the threshold voltage.

A transistor is a device having at least three terminals, including a gate, a drain, and a source. It also has a channel region between the drain (drain region or drain electrode) and the source (source region or source electrode), allowing current to flow through the drain, channel region, and source. Here, the source and drain vary depending on the structure and operating conditions of the transistor, making it difficult to definitively determine which is the source and which is the drain. Therefore, the parts that function as the source and the parts that function as the drain are sometimes not referred to as the source or drain. In such cases, for example, one of the source and drain may be referred to as the first terminal, first electrode, or first region, and the other of the source and drain may be referred to as the second terminal, second electrode, or second region.

Furthermore, when it is explicitly stated that X and Y are connected, this includes cases where X and Y are electrically connected, functionally connected, and directly connected. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to predetermined connection relationships, such as those shown in diagrams or text, but also includes connection relationships other than those shown in diagrams or text.

The voltage VDD1 is input to wire 14. The voltage VDD1 is a constant voltage and is greater than the ground voltage. Therefore, wire 14 functions as a power line or a positive power line. The voltage VDD2 is input to wire 15. The voltage VDD2 is a constant voltage and is greater than the voltage VDD1. Therefore, wire 15 functions as a power line or a positive power line. The voltage VSS is supplied to wire 16. The voltage VSS is a constant voltage and is less than the voltage VDD1. Therefore, wire 16 functions as a power line or a negative power line.

However, this embodiment is not limited to this example. For example, signals can be input to wiring 14, wiring 15 and/or wiring 16. In such a case, wiring 14, wiring 15 and/or wiring 16 can function as signal lines. As another example, the voltage VSS can be approximately equal to the ground voltage. Therefore, wiring 16 can function as a ground line or earth, etc.

Signal IN1 is input to wiring 11. Signal IN1 is a digital signal. The potential of the H level of signal IN1 is approximately VDD1, and the potential of the L level of signal IN1 is approximately VSS. Therefore, wiring 11 functions as a signal line. Signal IN2 is input to wiring 13. Signal IN2 is a digital signal. The potential of the H level of signal IN2 is approximately VDD1, and the potential of the L level of signal IN2 is approximately VSS. Therefore, wiring 13 functions as a signal line. However, this embodiment is not limited to this example. For example, a voltage (e.g., voltage VDD1 or voltage VDD2) can be input to wiring 13. This allows signal IN2 to be omitted, thus reducing the number of signals and wires. Furthermore, power consumption can be reduced.

Wiring 12 is assumed to output a signal OUT. Signal OUT is a digital signal and is the output signal of circuit 100. The potential of the high level of signal OUT is approximately VDD2, and the potential of the low level of signal OUT is approximately VSS. In other words, the amplitude voltage of signal OUT is assumed to be greater than the amplitude voltage of signal IN1. Therefore, wiring 12 is assumed to function as a signal line.

Next, an example of the operation of the semiconductor device of this embodiment will be described.

Figure 2 is an example diagram illustrating the operation of the semiconductor device of this embodiment. The semiconductor device of this embodiment can perform the first to fourth operations by combining the high and low levels of signals IN1 and IN2. The first to fourth operations will be described below. However, this example of the embodiment is not limited to this. For example, by changing the potential of wiring 14, wiring 15 and/or wiring 16, the semiconductor device of this embodiment can perform even more operations.

First, let's explain the first operation (see Figure 3(A)). In the first operation, signal IN1 becomes high level and signal IN2 becomes low level. As a result, transistor 111 turns off and transistor 112 turns on, so node A becomes conductive with wiring 16.

Then, node A is supplied with the potential (voltage VSS) of wire 16, so the potential of node A (indicated as potential Va) is approximately VSS. As a result, transistor 124 turns off. At this time, transistor 123 turns on, so node B becomes conductive with wire 15. Then, node B is supplied with the potential of wire 15 (e.g., voltage VDD2), so the potential of node B (indicated as potential Vb) begins to rise. Subsequently, when the potential of node B reaches VSS + Vth121 (Vth121: threshold voltage of transistor 121), transistor 121 turns on. At this time, transistor 122 turns off, so wire 12 becomes conductive with wire 15. Then, wire 12 is supplied with the potential of wire 15 (e.g., voltage VDD2), so the potential of wire 12 (signal OUT) begins to rise. Subsequently, the potential of node B and the potential of wire 12 continue to rise further. Eventually, the potential of node B becomes the value obtained by subtracting the threshold voltage of transistor 123 (Vth123) from the gate potential (voltage VDD1) of transistor 123. As a result, transistor 123 turns off, and wiring 15 and node B become non-conductive. Therefore, node B becomes floating. At this time, the potential of wiring 12 continues to rise. Therefore, the potential of node B rises further from VDD1-Vth123 due to the parasitic capacitance between the gate and the second terminal of transistor 121. Eventually, the potential of node B becomes VDD2+Vth121+V1 (V1: a positive number). This is what is known as bootstrap operation. Therefore, the potential of wiring 12 can rise to VDD2. In this way, signal OUT becomes high level.

Next, the second operation will be explained (see Figure 3(B)). In the second operation, signal IN1 becomes low and signal IN2 becomes high. As a result, transistor 111 turns on and transistor 112 turns off, so node A becomes conductive with wiring 14.

Then, the potential of wire 14 (voltage VDD1) is supplied to node A, so the potential of node A rises. Subsequently, the potential of node A becomes the value obtained by subtracting the threshold voltage of transistor 111 (Vth111) from the gate potential of transistor 111 (high-level signal IN2) (VDD1-Vth111). Then, transistor 111 turns off, and wire 14 and node A become non-conductive. Therefore, node A becomes floating, and the potential of node A is maintained at approximately VDD1-Vth111. As a result, transistor 124 turns on. At this time, transistor 123 turns off, so node B becomes conductive with wire 16. Then, the potential of wire 16 (voltage VSS) is supplied to node B, so the potential of node B is approximately VSS. Therefore, transistor 121 turns off. At this time, transistor 122 turns on, so wire 12 becomes conductive with wire 16. As a result, the potential (voltage VSS) of wire 16 is supplied to wire 12, so the potential (signal OUT) of wire 12 becomes approximately VSS. In this way, signal OUT becomes low level.

Next, the third operation will be explained (see Figure 4(A)). In the third operation, signal IN1 becomes high level and signal IN2 becomes high level. As a result, transistor 111 turns on and transistor 112 turns on, so node A becomes conductive with wiring 14 and wiring 16. Then, node A is supplied with the potential of wiring 14 (voltage VDD1) and the potential of wiring 16 (voltage VSS), so the potential of node A is a value between VSS and VDD1. This potential of node A is determined by the current supply capability of transistor 111 and the current supply capability of transistor 112. Here, we assume that the current supply capability of transistor 112 is greater than that of transistor 111. Therefore, preferably, the potential of node A is a value closer to VSS than to VDD1. More preferably, the potential of node A is set to a value lower than VSS+Vth124 (Vth124: threshold voltage of transistor 124) or VSS+Vth122 (Vth122: threshold voltage of transistor 122). As a result, transistor 124 turns off. At this time, transistor 123 turns on, so node B becomes conductive with wiring 15. Then, the potential of wiring 15 (e.g., voltage VDD2) is supplied to node B, so the potential of node B (indicated as potential Vb) begins to rise. Subsequently, when the potential of node B reaches VSS+Vth121 (Vth121: threshold voltage of transistor 121), transistor 121 turns on. At this time, transistor 122 turns off, so wiring 12 becomes conductive with wiring 15. Then, the potential of wiring 15 (e.g., voltage VDD2) is supplied to wiring 12, so the potential of wiring 12 (signal OUT) begins to rise. Subsequently, the potential of node B and the potential of wiring 12 continue to rise. Eventually, the potential of node B becomes the value obtained by subtracting the threshold voltage (Vth123) of transistor 123 from the gate potential (voltage VDD1) of transistor 123. At this point, transistor 123 turns off, and wiring 15 and node B become non-conductive. Therefore, node B becomes floating. At this time, the potential of wiring 12 continues to rise. Therefore, the potential of node B rises further from VDD1-Vth123 due to the parasitic capacitance between the gate and the second terminal of transistor 121. Eventually, the potential of node B becomes VDD2+Vth121+V1 (V1: a positive number). This is what is known as bootstrap operation. Therefore, the potential of wiring 12 can rise to VDD2. In this way, signal OUT becomes high level.

Next, the fourth operation will be explained (see Figure 4(B)). In the fourth operation, signal IN1 becomes low and signal IN2 becomes low. As a result, transistor 111 turns off and transistor 112 turns off, so node A becomes floating. Then the potential of node A remains the same as it was before the fourth operation. For example, suppose the first or third operation is performed before the fourth operation. In this case, the potential of node A will be approximately VSS. On the other hand, suppose the second operation is performed before the fourth operation. In this case, the potential of node A will be approximately VDD1-Vth111. Here, we assume that the second operation is performed before the fourth operation. Therefore, the potential of node A will be maintained at approximately VDD1-Vth111. As a result, transistor 124 turns on. At this time, transistor 123 turns off, so node B becomes conductive with wiring 16. As a result, node B receives the potential (voltage VSS) of wire 16, so the potential of node B is approximately VSS. Therefore, transistor 121 turns off. At this time, transistor 122 turns on, so wire 12 becomes conductive with wire 16. As a result, wire 12 receives the potential (voltage VSS) of wire 16, so the potential of wire 12 (signal OUT) is approximately VSS. In this way, signal OUT becomes low.

As described above, the semiconductor device of this embodiment can output a signal IN1 with a large amplitude voltage. Specifically, it can output a signal IN1 with a high amplitude voltage. This makes it possible to reduce the amplitude voltage of the circuit (shift register circuit, decoder circuit, etc.) that outputs the signal IN1 to the semiconductor device of this embodiment. Therefore, the power consumption of the circuit can be reduced. Alternatively, the voltage applied to the transistor constituting the circuit can be reduced. Therefore, the degradation or destruction of the transistor can be suppressed.

Alternatively, the inversion timing of signal OUT can be made approximately equal to the inversion timing of signal IN1. This eliminates the need to provide an inverter circuit or similar in wiring 12. As a result, power consumption can be reduced, the circuit size can be reduced, or the layout area can be reduced.

Alternatively, in the first operation, when signal IN1 is at a high level, signal IN2 becomes low, which prevents through-current between wiring 14 and wiring 16. This reduces power consumption.

Although the first to fourth operations have been described, it should be noted that the semiconductor device of this embodiment does not need to perform all of these operations. The semiconductor device of this embodiment can select only the necessary operations from among these multiple operations and perform only those selected operations.

Next, a configuration of the semiconductor device of this embodiment that differs from that shown in Figure 1 will be described.

First, as shown in Figures 5(A) and 5(B), in the semiconductor device shown in Figure 1, the first terminal of transistor 111 can be connected to a wiring other than wiring 14. Figure 5(A) shows an example of a semiconductor device when the first terminal of transistor 111 is connected to wiring 15. This allows the voltage VDD1 to be omitted. Alternatively, the potential difference (Vds) between the source and drain of transistor 111 can be increased, thus shortening the rise time of the potential at node A. Figure 5(B) shows an example of a semiconductor device when the first terminal of transistor 111 is connected to wiring 13. Therefore, the voltage VDD1 can be omitted. Alternatively, a reverse bias can be applied to transistor 111, thus suppressing the degradation of transistor 111. However, this embodiment is not limited to these examples. For example, the first terminal of transistor 111 can be connected to a wiring to which the inverted signal of signal IN1 is input.

Next, as shown in Figures 6(A) and 6(B), in the semiconductor device shown in Figures 1 and 5(A) to (B), the gate of transistor 111 can be connected to a wiring other than wiring 13. Figure 6(A) shows an example of a semiconductor device when the gate of transistor 111 is connected to wiring 15. This allows the signal IN2 to be omitted, thus reducing power consumption. Figure 6(B) shows an example of a semiconductor device when the gate of transistor 111 is connected to wiring 14. This allows the signal IN2 to be omitted, thus reducing power consumption. However, the examples of this embodiment are not limited to these. For example, the gate of transistor 111 can be connected to a wiring to which the inverted signal of signal IN1 is input.

Next, as shown in Figure 7(A), in the semiconductor device shown in Figures 1, 5(A)-(B), and 6(A)-(B), the first terminal of transistor 111 can be connected to a different wire than the wire 14, and the gate of transistor 111 can be connected to a different wire than the wire 13. Figure 7(A) shows an example of a semiconductor device in which the first terminal of transistor 111 is connected to the wire 13 and the gate of transistor 111 is connected to the wire 14. This allows the potential of node A to be increased in the second operation and decreased in the fourth operation. As a result, transistors 122 and 124 are turned on in the second operation and turned off in the fourth operation. In this way, the time that transistors 122 and 124 are on can be shortened. As a result, the degradation of transistors 122 and 124 can be suppressed.

Next, as shown in Figures 7(B) and 8(A), in the semiconductor devices shown in Figures 1, 5(A)-(B), 6(A)-(B), and 7(A), the first terminal of transistor 123 can be connected to a wiring other than wiring 15. Figure 7(B) shows an example of a semiconductor device when the first terminal of transistor 123 is connected to wiring 13B. The signal IN2B is input to wiring 13B. Signal IN2B is the inverted signal of signal IN2. This allows a reverse bias to be applied to transistor 123, thereby suppressing transistor degradation. Figure 8(A) shows an example of a semiconductor device when the first terminal of transistor 123 is connected to wiring 11. This allows the potential difference (Vds) between the source and drain applied to transistor 123 during the second and fourth operations to be reduced. Therefore, degradation of transistor 123 can be suppressed. Alternatively, the off-current of transistor 123 can be reduced, thereby reducing power consumption. However, this embodiment is not limited to this example. For example, the first terminal of transistor 123 can be connected to wiring 14.

As shown in Figure 8(B), when the first terminal of transistor 123 is connected to wiring 11, the gate of transistor 123 can be connected to wiring other than wiring 11. Figure 8(B) shows an example of a semiconductor device when the gate of transistor 123 is connected to wiring 14. However, this example is not limited to this embodiment. The gate of transistor 123 can be connected to wiring 15, wiring to which the inverted signal of signal IN2 is input, or wiring to which a signal with a different phase from signal IN2 is input.

Next, as shown in Figure 9(A), in the semiconductor devices shown in Figures 1, 5(A)-(B), 6(A)-(B), 7(A)-(B), and 8(A)-(B), it is possible to provide a capacitive element 125 between the gate and the second terminal of transistor 121. This allows the potential of node B to be further increased during the first and second operations. As a result, the potential difference (Vgs) between the gate and source of transistor 121 can be increased, thus shortening the rise time of signal OUT.

Next, as shown in Figure 9(B), in the semiconductor device shown in Figures 1, 5(A)-(B), 6(A)-(B), 7(A)-(B), 8(A)-(B), and 9(A), it is possible to provide a capacitive element 126 between node A and wiring 16. This makes it possible to suppress fluctuations in the potential of node A and noise in node A during the fourth operation, making it easier to maintain the potential of node A. However, this embodiment is not limited to this example. For example, the capacitive element 126 can be connected between node A and wiring other than wiring 16 (for example, wiring 13, wiring 14, or wiring 15). In particular, by connecting the capacitive element 126 between node A and wiring 13, the potential of node A can be varied in synchronization with the signal IN2. Therefore, the time during which transistors 122 and 124 are ON can be shortened.

Next, as shown in Figure 10(A), in the semiconductor devices shown in Figures 1, 5(A)-(B), 6(A)-(B), 7(A)-(B), 8(A)-(B), and 9(A)-(B), each transistor can be connected to separate wiring. Figure 10(A) shows an example of a semiconductor device in which the first terminal of transistor 112, the second terminal of transistor 124, and the second terminal of transistor 122 are connected to separate wiring. Wiring 16 is divided into multiple wires, 16A to 16C. The first terminal of transistor 112, the second terminal of transistor 124, and the second terminal of transistor 122 are connected to wiring 16A, wiring 16B, and wiring 16C, respectively. However, this example of the embodiment is not limited to this. For example, the first terminal of transistor 121 and the first terminal of transistor 123 can also be connected to separate wiring. In this case, it is possible to split wiring 15 into two separate wires.

Next, as shown in Figure 10(B), in the semiconductor devices shown in Figures 1, 5(A)-(B), 6(A)-(B), 7(A)-(B), 8(A)-(B), 9(A)-(B), and 10(A), transistors can be replaced with resistive elements, diodes, capacitive elements, etc. Figure 10(B) shows a semiconductor device in which transistor 111 is replaced with diode 111d. One electrode (e.g., anode) of diode 111d is connected to wiring 13, and the other electrode (e.g., cathode) is connected to node A. However, this embodiment is not limited to this example. For example, transistor 111 can be replaced with a resistive element. The resistive element can be connected between any one of the wirings 13-15 and node A. As another example, transistor 123 can be replaced with a diode in which one electrode (e.g., anode) is connected to wiring 11 and the other electrode (e.g., cathode) is connected to node B. As yet another example, a diode can be a diode-connected transistor.

Next, we will explain an example of the function of each circuit and an example of the function of each transistor.

First, circuit 100 has the function of increasing the amplitude voltage of signal IN1. Alternatively, it has the function of raising the potential of signal IN1 to a high level. Alternatively, circuit 100 has the function of inverting signal OUT when signal IN1 is inverted. Alternatively, circuit 100 has the function of setting signal OUT to a high level when signal IN1 is at a high level.

Alternatively, circuit 100 has the function of setting signal OUT to a low level when signal IN1 becomes a low level. In this way, circuit 100 functions as a level shifter circuit.

Furthermore, by making voltage VDD2 smaller than voltage VDD1, the potential of the high level of signal OUT can be made lower than the potential of the high level of signal IN1 or signal IN2. In this case, circuit 100 has the function of reducing the amplitude voltage of signal IN1.

Next, circuit 110 has the function of inverting signal IN1. Alternatively, circuit 110 has the function of decreasing the potential of node A when signal IN1 is at a high level. Alternatively, circuit 110 has the function of increasing the potential of node A when signal IN1 is at a low level. Alternatively, circuit 110 has the function of putting node A into a floating state. In this way, circuit 110 functions as an inverter circuit.

Next, circuit 120 has the function of increasing the amplitude voltage of signal IN1. Alternatively, circuit 120 has the function of raising the potential of signal IN1 to a high level. Alternatively, circuit 120 has the function of inverting signal OUT when signal IN1 is inverted. Alternatively, circuit 120 has the function of setting signal OUT to a high level when signal IN1 is at a high level. Alternatively, circuit 120 has the function of setting signal OUT to a low level when signal IN1 is at a low level. In this way, circuit 120 functions as a level shifter circuit.

Next, transistor 111 has the function of controlling the conduction state between wiring 14 and node A. Alternatively, transistor 111 has the function of controlling the timing of supplying the potential of wiring 14 to node A. Alternatively, transistor 111 has the function of controlling the timing of raising the potential of node A. Alternatively, transistor 111 has the function of controlling the timing of putting node A into a floating state. In this way, transistor 111 functions as a switch.

Next, transistor 112 has the function of controlling the conduction state between wiring 16 and node A. Alternatively, transistor 112 has the function of controlling the timing of supplying the potential of wiring 16 to node A. Alternatively, transistor 112 has the function of controlling the timing of decreasing the potential of node A. In this way, transistor 112 functions as a switch.

Next, transistor 121 has the function of controlling the conductivity between wiring 15 and wiring 12. Alternatively, transistor 121 has the function of controlling the timing of supplying the potential of wiring 15 to wiring 12. Alternatively, transistor 121 has the function of controlling the timing of raising the potential of wiring 12. Alternatively, transistor 121 has the function of controlling the timing of performing a bootstrap operation. Alternatively, transistor 121 has the function of controlling the timing of raising the potential of node B. In this way, transistor 121 functions as a switch.

Next, transistor 122 has the function of controlling the conductivity between wiring 16 and wiring 12. Alternatively, transistor 122 has the function of controlling the timing of supplying the potential of wiring 16 to wiring 12. Alternatively, transistor 122 has the function of controlling the timing of decreasing the potential of wiring 12. In this way, transistor 122 functions as a switch.

Next, transistor 123 has the function of controlling the conduction state between wiring 15 and node B. Alternatively, transistor 123 has the function of controlling the timing of supplying the potential of wiring 14 to node B. Alternatively, transistor 123 has the function of controlling the timing of raising the potential of node B. Alternatively, transistor 123 has the function of controlling the timing of putting node B into a floating state. In this way, transistor 123 functions as a switch.

Next, transistor 124 has the function of controlling the conduction state between wiring 16 and node B. Alternatively, transistor 124 has the function of controlling the timing of supplying the potential of wiring 16 to node B. Alternatively, transistor 124 has the function of controlling the timing of decreasing the potential of node B. In this way, transistor 124 functions as a switch.

Next, we will describe an example of the channel width of each transistor.

First, it is preferable that the channel width of transistor 121 is larger than the channel widths of transistors 111, 112, and 122-124. In other words, it is preferable that it be the largest among the transistors in circuit 100. This is because transistor 121 has the role of driving the wiring 12 and therefore requires a large driving capacity. Furthermore, it is preferable that the channel width of transistor 121 is 2 to 10 times that of transistor 123. More preferably, it is 3 to 8 times. Even more preferably, it is 4 to 6 times.

Next, it is preferable that the channel width of transistor 122 is larger than the channel widths of transistors 111, 112, 123, and 124.

This is because transistor 122 has the role of driving the wiring 12, and therefore requires a large driving capacity. The channel width of transistor 122 is preferably 2 to 30 times the channel width of transistor 124. More preferably 4 to 15 times, and even more preferably 6 to 10 times.

Furthermore, the channel width of transistor 122 can be larger than the channel width of transistor 121.

The channel width of transistor 123 is preferably larger than that of transistor 124. This is because, in the first and third operations, even if transistors 123 and 124 are turned on simultaneously due to a timing difference, the potential of node B can still be increased. The channel width of transistor 123 is preferably 1.5 times or more and 10 times or less than the channel width of transistor 124.

More preferably, it is between 2 and 8 times. Even more preferably, it is between 2.5 and 5 times.

Furthermore, the current supply capability of a transistor can be controlled by its channel width. Specifically, the larger the channel width of the transistor, the better its current supply capability. However, the factors that control the current supply capability of a transistor are not limited to the channel width. For example, the current supply capability can be controlled by the channel length of the transistor or the potential difference (Vgs) between the gate and source of the transistor. Specifically, the smaller the channel length of the transistor, the better its current supply capability. Also, the larger the potential difference (Vgs) between the gate and source of the transistor, the better its current supply capability. In addition, the current supply capability can be reduced by making the transistor a multi-gate structure.

As described above, there are multiple ways to control the current supply capability of a transistor. Therefore, in the following examples, when controlling the channel width is given as a method for controlling the current supply capability of a transistor, the channel width can be replaced with the channel length or the potential difference (Vgs) between the gate and source of the transistor.

(Embodiment 2) This embodiment describes an example of a semiconductor device and an example of a method for driving the semiconductor device. The semiconductor device in this embodiment is assumed to have the semiconductor device of Embodiment 1.

First, an example of a semiconductor device according to this embodiment will be described.

Figure 11 shows an example of a semiconductor device according to this embodiment. The semiconductor device shown in Figure 11 has circuits 300, 400, and 500. Circuit 400 has circuits 401_1 to 401_m (where m is a natural number). Circuits 401_1 to 401_m can each be the semiconductor device described in Embodiment 1. In Figure 11, circuits 401_1 to 401_m are each the semiconductor device shown in Figure 1.

Circuit 500 shall have circuits 501 and 502.

Circuit 300 is connected to wirings 21_1 to 21_m, wiring 23, wirings 24_1 to 24_4, wiring 25, and wiring 27. Circuit 400 is connected to wirings 21_1 to 21_m, wirings 22_1 to 22_m, wirings 24_1 to 24_4, wiring 25, wiring 26, and wiring 27. Circuit 401_i (where i is one of 1 to m) is connected to wiring 21_i, wiring 22_i, one of wirings 24_1 to 24_4, wiring 25, wiring 26, and wiring 27. In circuit 401_i, wirings 11, 12, 13, 14, 15, and 16 are each connected to wiring 21_i, wiring 22_i, one of wirings 24_1 to 24_4, wiring 25, wiring 26, and wiring 27. Circuit 500 is connected to wiring 23, wirings 24_1 to 24_4, wiring 25, wiring 26, and wiring 27. Circuit 501 is connected to wiring 23 and wirings 24_1 to 24_4, and circuit 502 is connected to wiring 25, wiring 26, and wiring 27.

Let's assume that circuit 401_i is connected to wiring 24_1. In this case, circuits 401_i+1, 401_i+2, and 401_i+3 are often connected to wirings 24_2, 24_3, and 24_4, respectively. Alternatively, circuits 401_i-3, 401_i-2, and 401_i-1 are often connected to wirings 24_2, 24_3, and 24_4, respectively.

Furthermore, it is preferable that circuit 401_i is connected to the wiring among wirings 24_1 to 24_4 whose potential is at a low level during the period when signal SOUTi is at a high level. This eliminates the period during which transistors 111 and 112 are simultaneously turned on. As a result, power consumption can be reduced.

Circuit 500 has the function of controlling the timing of supplying signals or voltages to circuits 300 and 400. Furthermore, circuit 500 has the function of controlling the timing of the operation of circuits 300 and 400. In other words, circuit 500 functions as a controller.

Circuit 501 has the function of controlling the timing of outputting signals SP, CK1, CK2, CK3, and CK4 to wirings 23, 24_1, 24_2, 24_3, and 24_4, respectively. In other words, circuit 501 functions as a signal generation circuit (also called a timing generator). Therefore, circuit 501 may include switches, diodes, transistors, oscillator circuits, clocked generators, PLL circuits, and/or frequency divider circuits.

As shown in Figure 12, signals SP, CK1, CK2, CK3, and CK4 are often digital signals. The potential of the high level of these signals is generally VDD1, and the potential of the low level is generally VSS. Signal SP is assumed to function as a start pulse (also called a horizontal synchronization signal or vertical synchronization signal). Therefore, wiring 23 is assumed to function as a signal line (also called a start signal line). Signals CK1 to CK4 are assumed to each function as a clock signal. Signals CK1 to CK4 are assumed to have a phase difference of 1/4 period (90°) each. Therefore, wirings 24_1 to 24_4 are assumed to function as clock signal lines (also called signal lines).

As shown in Figure 12, signals CK1 to CK4 are assumed to be balanced. Balance means that the period of time when the signal is at a high level and the period when it is at a low level are approximately equal within one cycle. However, this example is not limited to this. For example, as shown in Figure 13(A), signals CK1 to CK4 can be unbalanced. Unbalanced means that the period of time when the signal is at a high level and the period when it is at a low level are different. Here, "different" means anything other than the case where the signals are approximately equal.

As shown in Figures 13(B) and 13(C), the semiconductor device of this embodiment can use a single-phase clock signal. In this case, the clock signal can be balanced, as shown in Figure 13(B), or unbalanced, as shown in Figure 13(C). However, this embodiment is not limited to this example. For example, the semiconductor device of this embodiment can use a three-phase clock signal or a clock signal with five or more phases.

Circuit 502 shall have the function of outputting voltages VDD1, VDD2, and VSS to wirings 25, 26, and 27, respectively. In other words, circuit 502 shall function as a power supply circuit (also called a regulator). Therefore, wiring 25 shall function as a power line or positive power line. Wiring 27 shall function as a power line, negative power line, ground line, or earth, etc. Therefore, circuit 502 may have switches, transistors, capacitive elements, coils, diodes, regulators, DC-DC converters and/or boost circuits, etc.

Furthermore, circuits 500, 501, and 502 can supply various signals or voltages to circuits 300 and 400, depending on the configuration of circuits 300 and 400.

Circuit 300 has the function of controlling the timing of outputting signals SOUT1 to SOUTm according to the signals and voltages supplied from circuit 500 (for example, signal SP, signals CK1 to CK4, voltage VDD1, and voltage VSS). Signals SOUT1 to SOUTm are often digital signals, with their high level potential generally being VDD1 and their low level potential generally being VSS. Circuit 300 has the function of sequentially setting signals SOUT1 to SOUTm to high level. In other words, circuit 300 functions as a shift register circuit. However, this embodiment is not limited to this example. For example, circuit 300 can have the function of setting signals SOUT1 to SOUTm to high level in any order. Therefore, circuit 300 can function as a decoder circuit.

Signals SOUT1 to SOUTm are input to circuit 400 via wiring 21_1 to 21_m, respectively. For example, signal SOUTi is input to circuit 401_i via wiring 21_i. Therefore, wiring 21_1 to 21_m each function as a signal line.

In the timing chart shown in Figure 12, a portion of the period during which signal SOUTi is at a high level overlaps with a portion of the period during which signal SOUTi-1 is at a high level. Furthermore, a portion of the period during which signal SOUTi is at a high level overlaps with a portion of the period during which signal SOUTi+1 is at a high level. This allows for a longer period during which signals SOUT1 to SOUTm are at a high level. As a result, the drive frequency of circuit 300 can be slowed down, thereby reducing power consumption. However, this embodiment is not limited to this example. For example, as shown in Figures 13(A) to (C), the periods during which signals SOUT1 to SOUTm are at a high level do not overlap.

Circuit 400 has the function of controlling the timing of outputting signals BOUT1 to BOUTm in accordance with the signals supplied from circuit 300 (e.g., signals SOUT1 to SOUTm) and the signals and voltages supplied from circuit 500 (e.g., signals CK1 to CK4, voltages VDD1, VDD2, and VSS). Signals BOUT1 to BOUTm are often digital signals, with their high-level potential approximately equal to VDD2 and their low-level potential approximately equal to VSS. The timing of the inversion of signals BOUT1 to BOUTm is approximately equal to the timing of the inversion of signals SOUT1 to SOUTm. In other words, circuit 400 has the function of increasing the amplitude voltage of signals SOUT1 to SOUTm.

Next, an example of the operation of the semiconductor device of this embodiment will be described.

Figure 14 is an example of a timing chart for circuit 401_i. Figure 14 shows signal SOUTi, signal CK, the potential of node A of circuit 401_i, the potential of node B of circuit 401_i, and signal BOUTi. Signal CK is one of signals CK1 to CK4. Signal CK is the signal that becomes low when signal SOUTi becomes high. The timing chart shown in Figure 14 has periods Ta, Tb, and Tc. In the timing chart shown in Figure 14, periods Tb and Tc are arranged in order, except for period Ta.

Note that signal SOUTi corresponds to signal IN1 shown in Figure 2. Signal CK corresponds to signal IN2 shown in Figure 2. Signal BOUTi corresponds to signal OUT shown in Figure 2.

First, during period Ta, signal SOUTi becomes high and signal CK becomes low. Then, circuit 400_i performs its first operation. As a result, signal BOUTi becomes high. In this way, the potential of the high-level signal SOUTi can be raised from VDD1 to VDD2.

Next, during period Tb, signal SOUTi becomes low and signal CK becomes high. Then, circuit 400_i performs its second operation. As a result, signal BOUTi becomes low.

Next, during period Tc, the signal SOUTi remains at a low level, and the signal CK becomes low. Then, circuit 400_i performs a fourth operation.

Furthermore, since period Tb precedes period Tc, the potential Va remains VDD1-Vth111. Therefore, the signal BOUTi remains at a low level.

As described above, the semiconductor device of this embodiment can output the output signal of circuit 300 after increasing its amplitude voltage. This makes it possible to reduce the amplitude voltage of circuit 300. Therefore, the power consumption of circuit 300 can be reduced.

Alternatively, circuits 401_1 to 401_m often perform one of the first, second, or fourth operations, respectively. Therefore, since there is no period during which transistors 111 and 112 are turned on simultaneously, power consumption can be reduced.

Next, an example of circuit 300 will be described.

Figure 15 shows an example of circuit 300. Circuit 300 is assumed to have circuits 310_1 to 310_m. Circuit 310_i is connected to any three of the following: wiring 21_i, wiring 21_i-1, wiring 21_i+2, wiring 24_1 to 24_4, wiring 25, and wiring 27. However, circuit 310_1 is often connected to wiring 23 instead of wiring 21_i-1.

Circuits 310_1 to 310_m each have transistors 311, 312, 313, 314, 315, 316, 317, 318, and 319, respectively. The first terminal of transistor 311 is connected to wire 33, and the second terminal of transistor 311 is connected to wire 32. The first terminal of transistor 312 is connected to wire 37, the second terminal of transistor 312 is connected to wire 32, and the gate of transistor 312 is connected to wire 35. The first terminal of transistor 313 is connected to wire 37, and the second terminal of transistor 313 is connected to wire 32. The first terminal of transistor 314 is connected to wire 37, the second terminal of transistor 314 is connected to the gate of transistor 311, and the gate of transistor 314 is connected to the gate of transistor 313. The first terminal of transistor 315 is connected to wire 36, the second terminal of transistor 315 is connected to the gate of transistor 311, and the gate of transistor 315 is connected to wire 31. The first terminal of transistor 316 is connected to wire 36, the second terminal of transistor 316 is connected to the gate of transistor 313, and the gate of transistor 316 is connected to wire 38. The first terminal of transistor 317 is connected to wire 36, and the gate of transistor 317 is connected to wire 35. The first terminal of transistor 318 is connected to the second terminal of transistor 317, the second terminal of transistor 318 is connected to the gate of transistor 313, and the gate of transistor 318 is connected to wire 34. The first terminal of transistor 319 is connected to wire 37, the second terminal of transistor 319 is connected to the gate of transistor 313, and the gate of transistor 319 is connected to wire 31.

Note that the connection point between the gate of transistor 311, the second terminal of transistor 314, and the second terminal of transistor 315 is indicated as node C. The connection point between the gate of transistor 313, the gate of transistor 314, the second terminal of transistor 316, the second terminal of transistor 318, and the second terminal of transistor 319 is indicated as node D.

Transistors 311 to 319 are assumed to be N-channel type. Therefore, the semiconductor device of this embodiment can be constructed entirely of N-channel transistors.

However, this embodiment is not limited to this example. For example, all of transistors 311 to 319 can be P-channel type.

In circuit 310_i, wire 31 is connected to wire 21_i-1. Wire 32 is connected to wire 21_i. Wires 33-35 are connected to three selected wires from wires 24_1-24_4. For example, if wire 33 is connected to wire 24_1, then wire 34 is connected to wire 24_2, and wire 35 is connected to wire 24_3. Wire 36 is connected to wire 25. Wire 37 is connected to wire 27. Wire 38 is connected to wire 21_i+2. However, in circuit 310_1, wire 31 is connected to wire 23.

Next, an example of the operation of circuit 300 will be described.

Figure 16 shows an example of a timing chart that can be used in circuit 310_i. The timing chart shown in Figure 16 shows signals IN33, IN34, IN35, SOUTi-1, SOUTi+1, the potential at node C (potential Vc), the potential at node D (potential Vd), and signal SOUTi. The timing chart shown in Figure 16 has periods T1 to T9. Periods T5 to T9 are arranged in order, and periods T1 to T4 are arranged in order and repeated in the remaining periods.

First, during period T1, signal SOUTi becomes low, signal SOUTi+2 becomes low, signal IN33 becomes low, signal IN34 becomes high, and signal IN35 becomes high. As a result, transistor 316 turns off, transistor 317 turns on, transistor 318 turns on, and transistor 319 turns off, so node D becomes conductive with wiring 36. Then, the potential of wiring 36 (for example, voltage VDD) is supplied to node D, so the potential of node D rises. As a result, transistor 314 turns on. At this time, transistor 315 turns off, so node C becomes conductive with wiring 37. Then, the potential of wiring 37 (voltage VSS) is supplied to node C, so the potential of node C is approximately VSS. As a result, transistor 311 turns off. At this time, transistors 312 and 313 turn on, so wiring 32 becomes conductive with wiring 37. As a result, the potential (voltage VSS) of wiring 37 is supplied to wiring 32, so the potential of wiring 32 is approximately VSS. In this way, the signal SOUTi becomes low.

Next, in period T2, the difference from period T1 is that the signal IN34 becomes low. As a result, transistor 318 turns off, and wiring 36 and node D become non-conductive. Consequently, node D becomes floating, and the potential of node D remains the same as it was in period T1.

Next, in period T3, the difference compared to period T2 is that signal IN33 becomes high level and signal IN35 becomes low level. Therefore, transistors 317 and 312 are turned off.

Next, in period T4, the difference compared to period T3 is that the signal IN34 becomes high level. Therefore, transistor 318 turns on.

Next, during period T5, signal SOUTi becomes high, signal SOUTi+2 becomes low, signal IN33 becomes low, signal IN34 becomes low, and signal IN35 becomes high. As a result, transistor 316 turns off, transistor 317 turns on, transistor 318 turns off, and transistor 319 turns on, so wiring 37 and node D become conductive. Then, the potential of wiring 37 (voltage VSS) is supplied to node D, so the potential of node D is approximately VSS. As a result, transistor 314 turns off. At this time, transistor 315 turns on, so node C becomes conductive with wiring 36. Then, the potential of wiring 36 is supplied to node C, so the potential of node C begins to rise. Eventually, the potential of node C becomes the sum of the potential of wiring 32 (VSS) and the threshold voltage of transistor 311 (Vth311) (VSS+Vth311). Then, transistor 311 turns on. At this time, transistor 312 turns on and transistor 313 turns off, so wire 32 becomes conductive with wires 37 and 33. Then, the potential of wire 37 (voltage VSS) and the potential of wire 33 (L-level signal IN33) are supplied to wire 32, so the potential of wire 37 is approximately VSS. Thus, the signal SOUTi becomes L level. After that, the potential of node C continues to rise. Eventually, the potential of node C becomes VDD1-Vth315 (Vth315 is the threshold voltage of transistor 315). Then, transistor 315 turns off and node C becomes floating. Therefore, the potential of node C is maintained at VDD1-Vth315.

Next, during period T6, signal SOUTi-1 remains at a high level, signal SOUTi+2 remains at a low level, signal IN33 is at a high level, signal IN34 remains at a low level, and signal IN35 is at a low level. As a result, transistor 316 remains off, transistor 317 remains off, transistor 318 remains off, and transistor 319 remains on, so node D remains in a conductive state with wiring 37. Consequently, node D continues to receive the potential (voltage VSS) of wiring 37, so the potential of node D remains approximately VSS. Therefore, transistor 314 remains off. At this time, transistor 315 also remains off. Consequently, node C becomes floating, so the potential of node C remains VDD1-Vth315. Therefore, transistor 311 remains on. And, since transistors 312 and 313 are off, wiring 32 becomes in a conductive state with wiring 33. At this point, signal IN33 becomes high, causing the potential of wiring 32 to begin rising. Simultaneously, the potential of node C also rises due to the bootstrap operation. As a result, the potential of node C rises to VDD1 + Vth311 (where Vth311 is the threshold voltage of transistor 311) + V1. Therefore, the potential of wiring 32 rises to approximately VDD1. Thus, signal SOUTi becomes high.

Next, in period T7, the signal SOUTi-1 becomes low and the signal IN34 becomes high, which is different from period T6. As a result, transistor 318 turns on and transistor 319 turns off. Then node D becomes floating, and the potential of node D is maintained at approximately VSS.

Next, during period T8, signal SOUTi-1 remains at a low level, signal SOUTi+2 becomes high, signal IN33 becomes low, signal IN34 remains high, and signal IN35 becomes high. As a result, transistor 316 turns on, transistor 317 turns on, transistor 318 turns on, and transistor 319 remains off. Therefore, node D becomes conductive with wiring 36. Consequently, node D is supplied with the potential of wiring 36 (voltage VDD1), causing the potential of node D to rise. Therefore, transistor 314 turns on. At this time, transistor 315 remains off, so node C becomes conductive with wiring 37. Consequently, node C is supplied with the potential of wiring 37 (voltage VSS), causing the potential of node C to be approximately VSS. Therefore, transistor 311 turns off. At this time, transistors 312 and 313 turn on, so wire 32 becomes conductive with wires 33 and 37. As a result, the potential (voltage VSS) of wire 37 is supplied to wire 32, so the potential of wire 32 is approximately VSS. Thus, the signal SOUTi becomes low.

Next, in period T9, the difference compared to period T8 is that the signal IN34 becomes low. Therefore, transistor 318 turns off.

The above describes an example of circuit 300.

Furthermore, the gate of transistor 317 can be connected to wiring 34, and the gate of transistor 318 can be connected to wiring 35.

Note that transistor 319 can be omitted.

Note that transistor 312 can be omitted.

(Embodiment 3) In this embodiment, an example of a display device and an example of pixels that the display device has will be described.

In particular, an example of a liquid crystal display device and a pixel having a liquid crystal display device will be described. Note that the drive circuit of the display device in this embodiment can have the semiconductor device described in Embodiments 1 and 2.

First, an example of the display device of this embodiment will be described.

Figure 17(A) shows an example of a display device according to this embodiment. The display device shown in Figure 17(A) has a circuit 1001, a circuit 1002, a circuit 1003_1, a pixel unit 1004, and a terminal 1005. Multiple wires extend from circuit 1003_1 to the pixel unit 1004. These multiple wires function as gate signal lines (also called scan lines). Alternatively, multiple wires extend from circuit 1002 to the pixel unit 1004. These multiple wires function as video signal lines (also called data lines). Multiple pixels are arranged corresponding to the multiple wires extending from circuit 1003_1 and the multiple wires extending from circuit 1002. However, this example of the embodiment is not limited to this. For example, various other wires can be arranged in the pixel unit 1004. These wires can function as gate signal lines, data lines, power lines, or capacitance lines.

In the display device shown in Figure 17(A), circuit 1003_1 is formed on the same substrate 1006 as the pixel unit 1004, while circuits 1001 and 1002 are formed on a different substrate from the pixel unit 1004. The driving frequency of circuit 1003_1 is often slower than that of circuit 1001 or circuit 1002. Therefore, it becomes easy to use amorphous semiconductors, microcrystalline semiconductors, oxide semiconductors, organic semiconductors, etc., as the semiconductor layer of the transistor. As a result, the display device can be made larger, or the display device can be manufactured at a low cost.

Circuit 1001 has the function of controlling the timing of supplying signals, voltage, or current to circuits 1002 and 1003_1. Alternatively, circuit 1001 has the function of controlling circuits 1002 and 1003_1. Thus, circuit 1001 may function as a controller, control circuit, timing generator, power supply circuit, or regulator.

Circuit 1002 has the function of controlling the timing of supplying the video signal to the pixel unit 1004. Alternatively, circuit 1002 has the function of controlling the brightness or transmittance of the pixels in the pixel unit 1004. Thus, circuit 1002 has the function of a drive circuit, a source driver circuit, or a signal line drive circuit.

Circuit 1003_1 has the function of controlling the timing of supplying the gate signal to the pixel unit 1004. Alternatively, circuit 1003_1 has the function of controlling the timing of selecting a pixel. Thus, circuit 1003_1 functions as a gate driver (also called a scan line driving circuit).

As shown in Figure 17(B), the display device of this embodiment may have a circuit 1003_2. Circuit 1003_2 is assumed to have the same function as circuit 1003_1. By driving the same wiring with circuits 1003_1 and 1003_2, the load on circuits 1003_1 and 1003_2 can be reduced.

However, this embodiment is not limited to this example. For example, circuit 1003_1 can drive the odd-numbered gate signal lines, and circuit 1003_2 can drive the even-numbered gate signal lines. This allows the driving frequencies of circuits 1003_1 and 1003_2 to be reduced. As another example, the display device of this embodiment can have three or more circuits having the same function as circuit 1003_1.

In the display device shown in Figure 17(B), circuits 1003_1 and 1003_2 are formed on the same substrate 1006 as the pixel unit 1004, while circuits 1001 and 1002 are formed on a different substrate from the pixel unit 1004. The driving frequencies of circuits 1003_1 and 1003_2 are often slower than those of circuits 1001 or 1002. Therefore, it becomes easy to use amorphous semiconductors, microcrystalline semiconductors, oxide semiconductors, organic semiconductors, etc., as the semiconductor layer of the transistor. As a result, the display device can be made larger, or the display device can be manufactured at a low cost.

As shown in Figure 17(C), circuits 1002, 1003_1, and 1003_2 can be formed on the same substrate 1006 as the pixel unit 1004, while circuit 1001 can be formed on a separate substrate from the pixel unit 1004. This reduces the amount of external circuitry, thereby improving reliability, reducing manufacturing costs, or increasing yield.

As shown in Figure 17(D), some circuits 1002a, 1003_1, and 1003_2 of circuit 1002 can be formed on the same substrate 1006 as the pixel section 1004, while another part of circuit 1001, circuit 1002b, can be formed on a substrate separate from the pixel section 1004. Circuit 1002a can be a circuit with a relatively low driving frequency, such as a switch, shift register, and/or selector. This makes it easy to use amorphous semiconductors, microcrystalline semiconductors, oxide semiconductors, organic semiconductors, etc., as the semiconductor layer of the transistor. As a result, the display device can be made larger, or the display device can be manufactured at a lower cost.

Furthermore, the semiconductor devices of Embodiments 1-2 can be used as part of circuits 1003_1, 1003_2, 1002, and/or 1002a. This allows for a reduction in the drive voltage, thereby reducing power consumption.

Next, an example of a pixel in the pixel unit 1004 will be described.

Figure 17(E) shows an example of a pixel. Pixel 3020 has a transistor 3021, a liquid crystal element 3022, and a capacitive element 3023. The first terminal of transistor 3021 is connected to wiring 3031, the second terminal of transistor 3021 is connected to one electrode of liquid crystal element 3022 and one electrode of capacitive element 3023, and the gate of transistor 3021 is connected to wiring 3032. The other electrode of liquid crystal element 3022 is connected to electrode 3034, and the other electrode of capacitive element 3023 is connected to wiring 3033.

A video signal is input to wiring 3031 from circuit 1002 shown in Figures 17(A) to (D). Therefore, wiring 3031 functions as a video signal line (also called a source signal line). A gate signal is input to wiring 3032 from circuit 1003_1 and/or circuit 1003_2 shown in Figures 17(A) to (D). Therefore, wiring 3032 functions as a gate signal line. A constant voltage is supplied to wiring 3033 and electrode 3034 from circuit 1001 shown in Figures 17(A) to (D). Therefore, wiring 3033 functions as a power line or capacitance line. Alternatively, electrode 3034 functions as a common electrode or counter electrode.

However, this embodiment is not limited to this example. For example, a precharge voltage can be supplied to wiring 3031. The precharge voltage is often approximately equal to the voltage supplied to electrode 3034. As another example, a signal can be input to wiring 3033. In this way, the voltage applied to the liquid crystal element 3022 can be controlled, which can reduce the amplitude of the video signal or enable inverted drive. As yet another example, a signal can be input to electrode 3034. In this way, frame inverted drive can be realized.

Transistor 3021 has the function of controlling the conductivity between wiring 3031 and one electrode of liquid crystal element 3022. Alternatively, it has the function of controlling the timing of writing the video signal to the pixel. Thus, transistor 3021 functions as a switch. Capacitor element 3023 has the function of maintaining the potential difference between the potential of one electrode of liquid crystal element 3022 and the potential of wiring 3033. Alternatively, it has the function of maintaining the voltage applied to liquid crystal element 3022 at a constant level. Thus, capacitor element 3023 functions as a holding capacitor.

(Embodiment 4) In this embodiment, an example of a semiconductor device and an example of its operation will be described. In particular, an example of a signal line driving circuit and an example of its operation will be described.

First, an example of the signal line driving circuit of this embodiment will be described.

Figure 18(A) shows an example of a signal line drive circuit of this embodiment. The signal line drive circuit shown in Figure 18(A) has circuits 2001 and 2002. Circuit 2002 has multiple circuits called circuits 2002_1 to 2002_N (where N is a natural number). Circuits 2002_1 to 2002_N each have multiple transistors called transistors 2003_1 to 2003_k (where k is a natural number). The connection relationships of the signal line drive circuit of this embodiment will be explained using circuit 2002_1 as an example. The first terminals of transistors 2003_1 to 2003_k are connected to wirings 2004_1 to 2004_k, respectively. The second terminals of transistors 2003_1 to 2003_k are connected to wirings S1 to Sk, respectively. The gates of transistors 2003_1 to 2003_k are connected to wiring 2005_1.

Transistors 2003_1 to 2003_k are N-channel type. However, this embodiment is not limited to this example. For example, all of transistors 2003_1 to 2003_k can be P-channel type.

Circuit 2001 has the function of controlling the timing of outputting high-level signals to wiring 2005_1 to 2005_N in sequence. Alternatively, it has the function of selecting circuits 2002_1 to 2002_N in sequence. In this way, circuit 2001 functions as a shift register. However, this embodiment is not limited to this example. For example, circuit 2001 can output high-level signals to wiring 2005_1 to 2005_N in various sequences. Alternatively, it can select circuits 2002_1 to 2002_N in various sequences. In this way, circuit 2001 can function as a decoder.

Circuit 2002_1 has the function of controlling the timing of conduction between wiring 2004_1~2004_k and wiring S1~Sk. Alternatively, circuit 2002_1 has the function of controlling the timing of supplying the potential of wiring 2004_1~2004_k to wiring S1~Sk. In this way, circuit 2002_1 can function as a selector.

Circuits 2002_2 to 2002_N are assumed to have the same functionality as circuit 2002_1.

Next, transistors 2003_1 to 2003_N each have the function of controlling the timing of conduction between wirings 2004_1 to 2004_k and wirings S1 to Sk. Alternatively, transistors 2003_1 to 2003_N each have the function of controlling the timing of supplying the potential of wirings 2004_1 to 2004_k to wirings S1 to Sk. For example, transistor 2003_1 has the function of controlling the timing of conduction between wiring 2004_1 and wiring S1. Alternatively, transistor 2003_1 has the function of controlling the timing of supplying the potential of wiring 2004_1 to wiring S1. In this way, transistors 2003_1 to 2003_N can each function as switches.

In addition, signals are often input to wiring 2004_1 to 2004_k. In particular, these signals are often analog signals corresponding to image information (also called image signals). Thus, these signals can function as video signals. Therefore, wiring 2004_1 to 2004_k can function as signal lines. However, this embodiment is not limited to this example. For example, depending on the pixel configuration, the signals can be digital, analog voltages, or analog currents.

Next, we will explain an example of the operation of the signal line driving circuit shown in Figure 18(A).

Figure 18(B) shows an example of a timing chart that can be used in the signal line drive circuit of this embodiment. The timing chart shown in Figure 18(B) shows an example of signals 2015_1 to 2015_N and signals 2014_1 to 2014_k. Signals 2015_1 to 2015_N are examples of output signals of circuit 2001, and signals 2014_1 to 2014_k are examples of signals input to wiring 2004_1 to 2004_k. Note that one operating period of the signal line drive circuit corresponds to one gate selection period in the display device. One gate selection period is divided into period T0 and periods T1 to TN. Period T0 is the period for simultaneously applying a pre-charge voltage to the pixels belonging to the selected row, and functions as a pre-charge period. Periods T1 to TN are the periods for writing video signals to the pixels belonging to the selected row, and function as writing periods.

First, during period T0, circuit 2001 supplies a high-level signal to wiring 2005_1~2005_N. Then, for example, in circuit 2002_1, transistors 2003_1~2003_k are turned on, causing wiring 2004_1~2004_k and wiring S1~Sk to become conductive. At this time, a precharge voltage Vp is supplied to wiring 2004_1~2004_k. Therefore, the precharge voltage Vp is output to wiring S1~Sk via transistors 2003_1~2003_k. Thus, the precharge voltage Vp is written to the pixels belonging to the selected row, and the pixels belonging to the selected row are precharged.

During periods T1 to TN, circuit 2001 outputs a high-level signal to wirings 2005_1 to 2005_N in sequence. For example, during period T1, circuit 2001 outputs a high-level signal to wiring 2005_1. This turns on transistors 2003_1 to 2003_k, creating a conductive state between wirings 2004_1 to 2004_k and wirings S1 to Sk. At this time, Data(S1) to Data(Sk) are input to wirings 2004_1 to 2004_k. Data(S1) to Data(Sk) are written to the pixels in columns 1 to k of the selected row via transistors 2003_1 to 2003_k. In this way, during periods T1 to TN, the video signal is written to the pixels in the selected row in k columns in sequence.

As described above, by writing the video signal to the pixels in multiple columns, the number of video signals or wiring can be reduced. Therefore, the number of connections to external circuits can be reduced, leading to improved yield, increased reliability, reduced component count, and/or cost reduction. Alternatively, by writing the video signal to the pixels in multiple columns, the writing time can be increased. Therefore, insufficient writing of the video signal can be prevented, leading to improved display quality.

Furthermore, increasing k reduces the number of connections to external circuits. However, if k is too large, the writing time to the pixels will decrease. Therefore, it is preferable that k 6. More preferably, it is preferable that k 3. Even more preferably, it is preferable that k = 2. However, this example of the embodiment is not limited to these values.

In particular, when a pixel has n color elements (where n is a natural number), it is preferable that k = n or k = n × d (where d is a natural number). For example, when a pixel's color elements are divided into three parts: red (R), green (G), and blue (B), it is preferable that k = 3 or k = 3 × d. However, this example is not limited to these. For example, when a pixel is divided into m (where m is a natural number) subpixels (subpixels are also called sub-pixels or secondary pixels), it is preferable that k = m or k = m × d. For example, when a pixel is divided into two subpixels, it is preferable that k = 2. Alternatively, when a pixel has n color elements, it is preferable that k = m × n or k = m × n × d. However, this example is not limited to these.

Furthermore, it is possible for all of the signal line driving circuits of this embodiment to be formed on the same substrate as the pixel portion, or for all of the signal line driving circuits of this embodiment to be formed on a substrate separate from the pixel portion (for example, a silicon substrate or an SOI substrate). Alternatively, it is possible for a part of the signal line driving circuit of this embodiment (for example, circuit 2002) to be formed on the same substrate as the pixel portion, and another part of the signal line driving circuit of this embodiment (for example, circuit 2001) to be formed on a substrate separate from the pixel portion.

Figure 18(C) shows an example of a configuration in which circuits 2001 and 2002 are formed on the same substrate as the pixel unit 2007. In this way, the number of connections between the substrate on which the pixel unit is formed and the external circuits can be reduced, thereby improving yield, reliability, and reducing the number of components or costs. In particular, by forming the scan line drive circuits 2006A and 2006B on the same substrate as the pixel unit 2007, the number of connections to the external circuits can be further reduced.

Figure 18(D) shows an example of a configuration where circuit 2002 is formed on the same substrate as the pixel unit 2007, and circuit 2001 is formed on a separate substrate for the pixel unit 2007. Even in this case, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be reduced, thereby improving yield, reliability, reducing the number of components, or reducing costs. Alternatively, since there are fewer circuits formed on the same substrate as the pixel unit 2007, the bezel can be made smaller.

Furthermore, the semiconductor devices of Embodiments 1 and 2 can be used as circuit 2001. This allows for a reduction in the driving voltage, thereby reducing power consumption.

Alternatively, since the polarity of all transistors can be set to N-channel type, the manufacturing process can be reduced. Therefore, it is possible to improve yield, reduce manufacturing costs, or improve reliability.

(Embodiment 5) This embodiment describes an example of the structure of a semiconductor device. In particular, it describes an example of the structure of a transistor.

First, the structure of the transistor in this embodiment will be described.

Figure 19(A) shows an example of a top-gate type transistor and an example of a display element formed on it. The transistor shown in Figure 19(A) has a substrate 5260, an insulating layer 5261, a semiconductor layer 5262 having regions 5262a, 5262b, 5262c, 5262d, and 5262e, an insulating layer 5263, a conductive layer 5264, an insulating layer 5265 having an opening, and a conductive layer 5266. The insulating layer 5261 is formed on the substrate 5260. The semiconductor layer 5262 is formed on the insulating layer 5261. The insulating layer 5263 is formed to cover the semiconductor layer 5262. The conductive layer 5264 is formed on the semiconductor layer 5262 and the insulating layer 5263. The insulating layer 5265 is formed on the insulating layer 5263 and the conductive layer 5264. The conductive layer 5266 is formed on top of the insulating layer 5265 and in the openings of the insulating layer 5265. In this way, a top-gate type transistor is formed.

Figure 19(B) shows an example of a bottom-gate type transistor and an example of a display element formed on it. The transistor shown in Figure 19(B) has a substrate 5300, a conductive layer 5301, an insulating layer 5302, a semiconductor layer 5303a, a semiconductor layer 5303b, a conductive layer 5304, an insulating layer 5305 having an opening, and a conductive layer 5306. The conductive layer 5301 is formed on the substrate 5300. The insulating layer 5302 is formed to cover the conductive layer 5301. The semiconductor layer 5303a is formed on the conductive layer 5301 and the insulating layer 5302. The semiconductor layer 5303b is formed on the semiconductor layer 5303a. The conductive layer 5304 is formed on the semiconductor layer 5303b and the insulating layer 5302. The insulating layer 5305 is formed on the insulating layer 5302 and the conductive layer 5304. The conductive layer 5306 is formed on top of the insulating layer 5305 and in the openings of the insulating layer 5305. In this way, a bottom-gate type transistor is formed.

Figure 19(C) shows an example of a transistor formed on a semiconductor substrate. The transistor shown in Figure 19(C) has a semiconductor substrate 5352 having regions 5353 and 5355, an insulating layer 5356, an insulating layer 5354, a conductive layer 5357, an insulating layer 5358 having an opening, and a conductive layer 5359. The insulating layer 5356 is formed on the semiconductor substrate 5352. The insulating layer 5354 is formed on the semiconductor substrate 5352. The conductive layer 5357 is formed on the insulating layer 5356. The insulating layer 5358 is formed on the insulating layers 5354, 5356, and 5357. The conductive layer 5359 is formed on the insulating layer 5358 and in the opening of the insulating layer 5358. In this way, transistors are fabricated in regions 5350 and 5351, respectively.

In the transistor shown in Figures 19(A) to (C), as shown in Figure 19(A), it is possible to form an insulating layer 5267 with an opening, a conductive layer 5268, an insulating layer 5269 with an opening, an emitting layer 5270, and a conductive layer 5271 on the transistor. The insulating layer 5267 is formed on the conductive layer 5266 and on the insulating layer 5265. The conductive layer 5268 is formed on the insulating layer 5267 and in the opening of the insulating layer 5267. The insulating layer 5269 is formed on the insulating layer 5267 and on the conductive layer 5268. The emitting layer 5270 is formed on the insulating layer 5269 and in the opening of the insulating layer 5269. The conductive layer 5271 is formed on the insulating layer 5269 and on the emitting layer 5270.

Furthermore, in the transistors shown in Figures 19(A) to (C), it is possible to form a liquid crystal layer 5307 and a conductive layer 5308 on top of the transistor, as shown in Figure 19(B). The liquid crystal layer 5307 is placed on top of the insulating layer 5305 and the conductive layer 5306. The conductive layer 5308 is formed on top of the liquid crystal layer 5307.

In addition to the layers shown in Figures 19(A) to (C), various other structures can be formed. For example, an insulating layer functioning as an alignment film and/or an insulating layer functioning as a protrusion can be formed on the insulating layer 5305 and the conductive layer 5306. As another example, an insulating layer functioning as a protrusion, a color filter, and/or a black matrix can be formed on the conductive layer 5308. As yet another example, an insulating layer functioning as an alignment film can be formed below the conductive layer 5308.

Regions 5262c and 5262e are regions to which impurities are added and function as source or drain regions. Regions 5262b and 5262d are regions to which impurities are added at a lower concentration than in region 5262c or region 5262e and function as LDD (Lightly Doped Drain) regions. Region 5262a is a region to which no impurities are added and functions as a channel region. However, this embodiment is not limited to this example. For example, it is possible to add impurities to region 5262a. In this way, it is possible to improve the characteristics of the transistor, control the threshold voltage, etc. However, it is preferable that the concentration of impurities added to region 5262a is lower than the concentration of impurities added to region 5262b, region 5262c, region 5262d, or region 5262e. As another example, it is possible to omit region 5262c or region 5262e. Alternatively, region 5262c or region 5262e can be provided only in N-channel transistors.

Furthermore, the semiconductor layer 5303b is a semiconductor layer to which phosphorus or other impurity elements are added, and has an n-type conductivity. However, if an oxide semiconductor or a compound semiconductor is used as the semiconductor layer 5303a, the semiconductor layer 5303b may be omitted.

As an example of a semiconductor substrate (for example, semiconductor substrate 5352), a single-crystal Si substrate having an n-type or p-type conductivity can be used. Region 5353 is a region in the semiconductor substrate 5352 to which impurities are added, and it functions as a well.

For example, if the semiconductor substrate 5352 has a p-type conductivity, region 5353 shall have an n-type conductivity. On the other hand, if the semiconductor substrate 5352 has an n-type conductivity, region 5353 shall have a p-type conductivity. Region 5355 is a region in which impurities are added to the semiconductor substrate 5352 and functions as either a source region or a drain region. It is also possible to form an LDD region in the semiconductor substrate 5352.

Next, we will explain an example of the functions that each layer possesses.

The insulating layer 5261 shall function as a base film. The insulating layer 5354 shall function as an inter-element isolation layer (e.g., a field oxide film). The insulating layers 5263, 5302, and 5356 shall function as gate insulating films.

Conductive layers 5264, 5301, and 5357 shall function as gate electrodes. Insulating layers 5265, 5267, 5305, and 5358 shall function as interlayer films or planarization films. Conductive layers 5266, 5304, and 5359 shall function as wiring, transistor electrodes, or capacitive element electrodes. Conductive layers 5268 and 5306 shall function as pixel electrodes or reflective electrodes. Insulating layer 5269 shall function as a partition. Conductive layers 5271 and 5308 shall function as counter electrodes or common electrodes. However, this embodiment is not limited to this example.

Next, we will describe the materials, structure, and characteristics of each layer.

First, examples of substrates (e.g., substrate 5260 or substrate 5300) include semiconductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or flexible synthetic resins such as acrylic. Examples of laminated films include polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride. Examples of base film include polyester, polyamide, polyimide, inorganic vapor-deposited film, or paper. In particular, by manufacturing transistors using semiconductor substrates, single-crystal substrates, or SOI substrates, it is possible to manufacture transistors with less variation in characteristics, size, or shape, high current capability, and small size. When circuits are constructed using such transistors, it is possible to reduce the power consumption of the circuit or increase its integration density.

Furthermore, it is possible to form a transistor on one substrate and then transfer the transistor to another substrate. Examples of such other substrates include, in addition to the substrates mentioned above, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupro, rayon, recycled polyester), etc.), leather substrates, or rubber substrates. By using these substrates, it is possible to form transistors with good characteristics, transistors with low power consumption, manufacture devices that are less prone to breakage, provide heat resistance, reduce weight, or make the devices thinner.

Furthermore, it is possible to form all the circuits necessary to achieve a predetermined function on the same substrate (for example, a glass substrate, plastic substrate, single crystal substrate, or SOI substrate). In this way, it is possible to reduce costs by reducing the number of components, or to improve reliability by reducing the number of connection points with circuit components.

Furthermore, it is possible not to form all the circuits necessary to achieve a predetermined function on the same substrate. In other words, some of the circuits necessary to achieve a predetermined function can be formed on one substrate, and other parts of the circuits necessary to achieve a predetermined function can be formed on another substrate. For example, some of the circuits necessary to achieve a predetermined function can be formed on a glass substrate, and other parts of the circuits necessary to achieve a predetermined function can be formed on a single-crystal substrate (or SOI substrate). Then, the single-crystal substrate (also called an IC chip) on which the other parts of the circuits necessary to achieve a predetermined function are formed can be connected to the glass substrate by COG (Chip On Glass), and the IC chip can be placed on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board.

Next, examples of insulating layers (for example, insulating layers 5261, 5263, 5265, 5267, 5269, 5305, 5356, and 5358) include single-layer structures or laminated structures thereof of films containing oxygen or nitrogen (for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x&gt;y&gt;0), silicon oxide nitride (SiNxOy) (x&gt;y&gt;0), etc.), films containing carbon (for example, DLC (diamond-like carbon) etc.), organic materials (for example, siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, etc.). However, the examples of this embodiment are not limited to these.

Furthermore, if the insulating layer has a two-layer structure, it is preferable to provide a silicon nitride film as the first insulating layer and a silicon oxide film as the second insulating layer. If the insulating layer has a three-layer structure, it is preferable to provide a silicon oxide film as the first insulating layer, a silicon nitride film as the second insulating layer, and a silicon oxide film as the third insulating layer.

Next, examples of semiconductor layers (for example, semiconductor layer 5262, semiconductor layer 5303a, and semiconductor layer 5303b) include non-single-crystal semiconductors (for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.), single-crystal semiconductors, compound semiconductors or oxide semiconductors (for example, ZnO, InGaZnO, SiGe, GaAs, IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, AlZnSnO (AZTO), etc.), organic semiconductors, or carbon nanotubes.

Furthermore, by using a catalyst (such as nickel) when manufacturing polycrystalline or microcrystalline silicon, crystallinity can be further improved, making it possible to manufacture transistors with superior electrical properties. Therefore, gate driver circuits (scan line driving circuits), source driver circuits (signal line driving circuits), parts of the source driver circuits (e.g., switches for video signal splitting), and signal processing circuits (signal generation circuits, gamma correction circuits, DA conversion circuits, etc.) can be integrally formed on the substrate. In particular, when manufacturing microcrystalline silicon using a catalyst (such as nickel), crystallinity can be improved simply by applying heat treatment, without laser irradiation. This reduces unevenness in silicon crystallinity, resulting in improved image quality. However, it is possible to manufacture polycrystalline or microcrystalline silicon without using a catalyst (such as nickel).

While it is desirable to improve the crystallinity of silicon to polycrystalline or microcrystalline properties across the entire panel, it is not limited to this. Crystallinity may be improved in only a portion of the panel. Selective crystallinity improvement is possible by selectively irradiating the panel with laser light. For example, laser light can be irradiated only to areas where high-speed circuit operation is required, such as peripheral circuit areas, gate driver circuits, source driver circuits, or parts of source driver circuits (e.g., analog switches). On the other hand, since high-speed operation is less necessary in the pixel area, the pixel circuit can operate without problems even if its crystallinity is not improved. This reduces the area requiring crystallinity improvement, thus shortening the manufacturing process. This improves throughput and reduces manufacturing costs. Alternatively, it reduces the number of manufacturing devices required, further lowering manufacturing costs.

Next, an example of a conductive layer (for example, conductive layers 5264, 5266, 5268, 5271, 5301, 5304, 5306, and 5308, 5357, and 5359) is a single film or a laminated structure thereof. Examples of such elemental films include the group composed of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon (C), scandium (Sc), zinc (Zn), gallium (Ga), indium (In), tin (Sn), zirconium (Zr), and cerium (Ce); one element selected from this group; and compounds containing one or more elements selected from this group. Other examples of such single-component films include nanotube materials (e.g., carbon nanotubes, organic nanotubes, inorganic nanotubes, or metal nanotubes), films containing polymer films, or conductive plastics (e.g., polyethylenedioxythiophene (PEDOT)). These single-component films may also contain phosphorus (P), boron (B), arsenic (As), and/or oxygen (O).

Examples of such compounds include compounds containing one or more elements selected from the above group (e.g., alloys), compounds of one or more elements selected from the above group and nitrogen (e.g., nitride films), or compounds of one or more elements selected from the above group and silicon (e.g., silicide films). Examples of alloys include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), tin cadmium oxide (CTO), aluminum neodymium (Al-Nd), aluminum tungsten (Al-W), aluminum zirconium (Al-Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium silver (Mg-Ag), molybdenum niobium (Mo-Nb), molybdenum tungsten (Mo-W), and molybdenum tantalum (Mo-Ta). Examples of nitride films include titanium nitride, tantalum nitride, and molybdenum nitride. Examples of silicide films include tungsten silicide, titanium silicide, nickel silicide, aluminum silicon, and molybdenum silicon.

Next, an example of a light-emitting layer (e.g., 5270) is an organic EL element or an inorganic EL element. An example of an organic EL element is a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material, an electron transport layer made of an electron transport material, an electron injection layer made of an electron injection material, or a single-layer structure of a layer made by mixing multiple of these materials, or a stacked structure thereof.

Next, as an example of the liquid crystal layer 5307, there is an element that controls the transmission or opacity of light by the optical modulation effect of the liquid crystal. This element can be constructed from a pair of electrodes and a liquid crystal layer. The optical modulation effect of the liquid crystal is controlled by the electric field applied to the liquid crystal (including a lateral electric field, a vertical electric field, or an oblique electric field). Specifically, examples of liquid crystal elements include nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLCs), ferroelectric liquid crystals, antiferroelectric liquid crystals, main-chain liquid crystals, side-chain polymer liquid crystals, plasma-addressed liquid crystals (PALCs), and banana-type liquid crystals. Furthermore, examples of liquid crystal driving methods include TN (Twisted Nematic) mode, STN (SuperTwisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, and PVA (Patterned Vertical Alignment) mode. Modes include Alignment mode, ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest host mode, and Blue Phase mode.

Furthermore, each layer constituting the above-mentioned transistor can be formed using an inkjet method or a printing method. In this way, it can be manufactured at room temperature, at a low vacuum, or on a large substrate. Therefore, it is possible to manufacture without using a mask (reticle), making it easy to change the layout of the transistor. Alternatively, since it is possible to manufacture without using a resist, material costs are reduced and the number of process steps can be decreased.

Alternatively, since the film can be applied only to the necessary areas, it is less wasteful and less expensive than a manufacturing method that involves forming a film over the entire surface and then etching it.

The above describes one example of a transistor structure. However, the structure of a transistor is not limited to the structure described above, and various other structures are possible.

For example, MOS transistors, junction transistors, and bipolar transistors can be used as transistors. In particular, using MOS transistors allows for a reduction in transistor size. In particular, using bipolar transistors allows for the flow of large currents, thus enabling high-speed circuit operation.

As another example, a transistor can have a structure in which gate electrodes are positioned above and below the channel. By positioning gate electrodes above and below the channel, the circuit configuration becomes similar to that of multiple transistors connected in parallel. Therefore, the channel region increases, and thus the current value can be increased. Alternatively, by positioning gate electrodes above and below the channel, a depletion layer is more easily formed, which can improve the S value.

As another example, a transistor can have a structure in which the gate electrode is located above the channel region, a structure in which the gate electrode is located below the channel region, a positive staggered structure, an inverse staggered structure, a structure in which the channel region is divided into multiple regions, a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series.

As another example, a transistor can have a structure in which the source electrode and drain electrode overlap the channel region (or a part thereof). By having the source electrode and drain electrode overlap the channel region (or a part thereof), it is possible to prevent unstable operation caused by charge accumulation in a part of the channel region.

The transistor of this embodiment can be used in the semiconductor device or display device of Embodiments 1 to 4.

(Embodiment 6) In this embodiment, an example of the cross-sectional structure of the display device will be described.

Figure 20(A) shows an example of a top view of a display device. A drive circuit 5392 and a pixel section 5393 are formed on the substrate 5391. An example of the drive circuit 5392 is a scan line drive circuit or a signal line drive circuit.

Figure 20(B) shows an example of an A-B cross-section of the display device shown in Figure 20(A). The display device comprises a substrate 5400, a conductive layer 5401, an insulating layer 5402, a semiconductor layer 5403a, a semiconductor layer 5403b, a conductive layer 5404, an insulating layer 5405, a conductive layer 5406, an insulating layer 5408, a liquid crystal layer 5407, a conductive layer 5409, and a substrate 5410. The conductive layer 5401 is formed on the substrate 5400. The insulating layer 5402 is formed to cover the conductive layer 5401. The semiconductor layer 5403a is formed on the conductive layer 5401 and the insulating layer 5402. The semiconductor layer 5403b is formed on the semiconductor layer 5403a. The conductive layer 5404 is formed on the semiconductor layer 5403b and the insulating layer 5402. The insulating layer 5405 is formed on the insulating layer 5402 and the conductive layer 5404, and has openings. The conductive layer 5406 is formed on the insulating layer 5405 and in the openings of the insulating layer 5405. The liquid crystal layer 5407 is formed on the insulating layer 5405. The insulating layer 5408 is formed on the insulating layer 5405 and the conductive layer 5406. The conductive layer 5409 is formed on the liquid crystal layer 5407 and the insulating layer 5405.

The conductive layer 5401 shall function as a gate electrode. The insulating layer 5402 shall function as a gate insulating film. The conductive layer 5404 shall function as wiring, a transistor electrode, or a capacitive element electrode. The insulating layer 5405 shall function as an interlayer film or planarization film. The conductive layer 5406 shall function as wiring, a pixel electrode, or a reflective electrode. The insulating layer 5408 shall function as a sealing material. The conductive layer 5409 shall function as a counter electrode or a common electrode.

Here, parasitic capacitance may occur between the drive circuit 5392 and the conductive layer 5409. This can cause distortion or delay in the output signal of the drive circuit 5392 or the potential of each node. As a result, power consumption may increase. However, as shown in Figure 20(B), by forming an insulating layer 5408 that functions as a sealing material on the drive circuit 5392, the parasitic capacitance that occurs between the drive circuit 5392 and the conductive layer 5409 can be reduced. This is because the dielectric constant of the sealing material is often lower than that of the liquid crystal layer. Therefore, distortion or delay in the output signal of the drive circuit 5392 or the potential of each node can be reduced. As a result, power consumption can be reduced.

Furthermore, as shown in Figure 20(C), it is possible to form an insulating layer 5408 that can function as a sealing material on a part of the drive circuit 5392. Even in such a case, the parasitic capacitance that occurs between the drive circuit 5392 and the conductive layer 5409 can be reduced, thereby reducing the smearing or delay of the output signal of the drive circuit 5392 or the potential of each node.

Furthermore, the display element is not limited to liquid crystal elements; various other display elements such as EL elements or electrophoretic elements can be used.

Furthermore, the structure of the display device in this embodiment can be applied to the semiconductor device or display device of Embodiments 1 to 5. For example, when using non-single-crystal semiconductors, microcrystalline semiconductors, organic semiconductors, or oxide semiconductors as the semiconductor layer of a transistor, the channel width of the transistor is often large. However, as in this embodiment, if the parasitic capacitance of the drive circuit can be reduced, the channel width of the transistor can be reduced. Therefore, the layout area can be reduced, and the display device can have a narrow bezel. Alternatively, the display device can have a high resolution.

(Embodiment 7) In this embodiment, an example of a semiconductor device and an example of a semiconductor device manufacturing process will be described. In particular, an example of a transistor manufacturing process and an example of a capacitive device manufacturing process will be described.

In particular, the fabrication process when using an oxide semiconductor as the semiconductor layer will be described.

Figures 21(A) to (C) show an example of the manufacturing process for transistors and capacitive elements. Transistor 5441 is an inverse staggered thin-film transistor, with wiring provided on the oxide semiconductor layer via source or drain electrodes.

First, a first conductive layer is formed over the entire surface of the substrate 5420 by sputtering. Next, the first conductive layer is selectively etched using a resist mask formed by a photolithography process using a first photomask to form conductive layers 5421 and 5422. Conductive layer 5421 can function as a gate electrode, and conductive layer 5422 can function as one electrode of a capacitive element. However, it is not limited to this, and conductive layers 5421 and 5422 can have portions that function as wiring, gate electrodes, or electrodes of a capacitive element. After this, the resist mask is removed.

Next, an insulating layer 5423 is formed over the entire surface using plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer and is formed to cover the conductive layer 5421 and the conductive layer 5422. The thickness of the insulating layer 5423 is often between 50 nm and 250 nm.

Next, the insulating layer 5423 is selectively etched using a resist mask formed by a photolithography process with a second photomask to form contact holes 5424 that reach the conductive layer 5421. After this, the resist mask is removed. However, this is not limited to this procedure, and it is possible to omit the contact holes 5424. Alternatively, it is possible to form the contact holes 5424 after the formation of the oxide semiconductor layer. A cross-sectional view at this stage corresponds to Figure 21(A).

Next, an oxide semiconductor layer is formed over the entire surface by sputtering. However, it is not limited to this, and an oxide semiconductor layer is formed by sputtering, and a buffer layer (for example, n) is further placed on top of it.⁺It is possible to form a layer. The thickness of the oxide semiconductor layer is often between 5 nm and 200 nm.

Next, the oxide semiconductor layer is selectively etched using a third photomask. After this, the resist mask is removed.

Next, a second conductive layer is formed over the entire surface by sputtering. Then, the second conductive layer is selectively etched using a resist mask formed by a photolithography process using a fourth photomask to form conductive layers 5429, 5430, and 5431. Conductive layer 5429 is connected to conductive layer 5421 via a contact hole 5424.

Conductive layers 5429 and 5430 can function as source or drain electrodes, and conductive layer 5431 can function as the other electrode of a capacitive element. However, it is not limited to this, and conductive layers 5429, 5430 and 5431 may include portions that function as wiring, source or drain electrodes, or electrodes of a capacitive element. A cross-sectional view at this stage corresponds to Figure 21(B).

Next, a heat treatment is performed at 200°C to 600°C under an atmospheric or nitrogen atmosphere. This heat treatment causes atomic-level rearrangement of the In-Ga-Zn-O non-single-crystal layer. In this way, the strain that inhibits carrier movement is released by the heat treatment (including photo-annealing). Note that the timing of this heat treatment is not limited and can be performed at various times after the formation of the oxide semiconductor.

Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 can be a single layer or a multilayer structure. For example, when an organic insulating layer is used as the insulating layer 5432, a composition that is the material for the organic insulating layer is applied, and the organic insulating layer is formed by heat treatment at 200°C to 600°C in an atmospheric or nitrogen atmosphere. By forming an organic insulating layer in contact with the oxide semiconductor layer in this way, a thin-film transistor with highly reliable electrical properties can be manufactured. When an organic insulating layer is used as the insulating layer 5432, it is possible to provide a silicon nitride film or a silicon oxide film beneath the organic insulating layer.

Next, a third conductive layer is formed over the entire surface. Then, the third conductive layer is selectively etched using a resist mask formed by a photolithography process using a fifth photomask to form conductive layers 5433 and 5434. A cross-sectional view at this stage corresponds to Figure 21(C). Conductive layers 5433 and 5434 can function as wiring, pixel electrodes, reflective electrodes, translucent electrodes, or electrodes for capacitive elements. In particular, conductive layer 5434 is connected to conductive layer 5422, so it can function as an electrode for capacitive element 5442. However, it is not limited to this, and it can also have the function of connecting the first conductive layer and the second conductive layer. For example, by connecting conductive layer 5433 and conductive layer 5434, conductive layer 5422 and conductive layer 5430 can be connected via the third conductive layer (conductive layers 5433 and 5434).

By the above steps, the transistor 5441 and the capacitive element 5442 can be manufactured. The transistor of this embodiment can be used in the semiconductor device or display device of Embodiments 1 to 8.

Furthermore, as shown in Figure 21(D), it is possible to form an insulating layer 5435 on top of the oxide semiconductor layer 5425.

Furthermore, as shown in Figure 21(E), it is possible to form the oxide semiconductor layer 5425 after patterning the second conductive layer.

In addition, other embodiments or materials described herein can be used as the substrate, insulating layer, conductive layer, and semiconductor layer in this embodiment.

(Embodiment 8) This embodiment describes an example of an electronic device.

Figures 22(A) to 22(H) and 23(A) to 23(D) show electronic devices. These electronic devices may include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or operation switch), connection terminals 5006, sensors 5007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 5008, etc.

Figure 22(A) is a mobile computer, which may have, in addition to the above-mentioned components, a switch 5009, an infrared port 5010, etc. Figure 22(B) is a portable image playback device (for example, a DVD player) equipped with a recording medium, which may have, in addition to the above-mentioned components, a second display unit 5002, a recording medium reading unit 5011, etc. Figure 22(C) is a goggle-type display, which may have, in addition to the above-mentioned components, a second display unit 5002, a support unit 5012, earphones 5013, etc. Figure 22(D) is a portable gaming machine, which may have, in addition to the above-mentioned components, a recording medium reading unit 5011, etc. Figure 22(E) is a digital camera with a television receiving function, which may have, in addition to the above-mentioned components, an antenna 5014, a shutter button 5015, a receiving unit 5016, etc. Figure 22(F) is a portable gaming machine, which may have, in addition to the above-mentioned components, a second display unit 5002, a recording medium reading unit 5011, etc. Figure 22(G) is a television receiver, which may have a tuner, image processing unit, etc., in addition to those described above. Figure 22(H) is a portable television receiver, which may have a charger 5017 capable of transmitting and receiving signals, etc., in addition to those described above. Figure 23(A) is a display, which may have a support stand 5018, etc., in addition to those described above. Figure 23(B) is a camera, which may have an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc., in addition to those described above.

Figure 23(C) is a computer, which may have, in addition to the above-mentioned components, a pointing device 5020, an external connection port 5019, a reader/writer 5021, etc. Figure 23(D) is a mobile phone, which may have, in addition to the above-mentioned components, a transmitting unit, a receiving unit, a tuner for a 1-segment partial reception service for mobile phones and mobile terminals, etc.

The electronic devices shown in Figures 22(A) to 22(H) and Figures 23(A) to 23(D) can have a variety of functions. For example, they can have functions to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to connect to various computer networks using the wireless communication function, a function to transmit or receive various data using the wireless communication function, a function to read programs or data recorded on a recording medium and display them on the display unit, etc. Furthermore, electronic devices having multiple display units can have functions to primarily display image information on one display unit and primarily display text information on another display unit, or a function to display a three-dimensional image by displaying images that take parallax into consideration on multiple display units, etc. Furthermore, electronic devices having an image receiving unit can have functions to capture still images, capture videos, automatically or manually correct captured images, save captured images to a recording medium (external or built into the camera), display captured images on the display unit, etc. Furthermore, the functions that the electronic devices shown in Figures 22(A) to 22(H) and Figures 23(A) to 23(D) can have are not limited to those shown, and they can have a variety of functions.

The electronic device described in this embodiment is characterized by having a display unit for displaying some kind of information. By using the semiconductor device or display device described in Embodiments 1 to 9 as this display unit, it is possible to reduce manufacturing costs, improve reliability, or improve yield.

Next, we will explain some application examples of semiconductor devices.

Figure 23(E) shows an example of a semiconductor device being installed as an integral part of a building. Figure 23(E) includes a housing 5022, a display unit 5023, a remote control device 5024 which serves as the operating unit, a speaker 5025, etc. The semiconductor device is wall-mounted and integrated with the building, allowing it to be installed without requiring a large installation space.

Figure 23(F) shows another example in which semiconductor equipment is installed within a building and integrated with the building structure. The display panel 5026 is attached integrally with the unit bathroom 5027, allowing bathers to view the display panel 5026.

In this embodiment, walls and unit bathrooms were used as examples of buildings, but this embodiment is not limited to these, and semiconductor devices can be installed in various types of buildings.

Next, we will show an example in which a semiconductor device is integrated with a mobile device.

Figure 23(G) shows an example of a semiconductor device installed in an automobile. The display panel 5028 is mounted on the automobile body 5029 and can display information on demand that is received from inside or outside the vehicle or during the vehicle's operation. It may also have a navigation function.

Figure 23(H) shows an example of a semiconductor device being integrated with a passenger aircraft. Figure 23(H) shows the configuration when a display panel 5031 is installed on the ceiling 5030 above the seats of a passenger aircraft. The display panel 5031 is integrally attached to the ceiling 5030 via a hinge portion 5032, and passengers can view the display panel 5031 by extending and retracting the hinge portion 5032. The display panel 5031 has the function of displaying information when operated by a passenger.

In this embodiment, the mobile body is exemplified as an automobile body and an aircraft body, but it is not limited to these, and can be installed on a variety of things such as motorcycles, automobiles (including cars, buses, etc.), trains (including monorails, railways, etc.), ships, etc.

11 wiring

12 wiring

13 wiring

14 wiring

15 wiring

16 wiring

twenty one wiring

twenty two wiring

twenty three wiring

twenty four wiring

twenty five wiring

26 wiring

27 wiring

31 wiring

32 wiring

33 wiring

34 wiring

35 wiring

36 wiring

37 wiring

38 wiring

100 circuit

110 circuit

111 transistor

112 transistor

120 circuit

121 transistor

122 transistor

one two three transistor

124 transistor

125 Capacitive element

126 Capacitive element

13B Wiring

16A wiring

16B Wiring

16C wiring

300 circuit

310 circuit

311 transistor

312 transistor

313 transistor

314 transistor

315 transistor

316 transistor

317 transistor

318 transistor

319 transistor

400 circuit

401 circuit

500 circuit

501 circuit

502 circuit

1001 circuit

1002 circuit

1003 circuit

1004 Pixel section

1005 terminals

1006 substrate

111d diode

2001 circuit

2002 circuit

2003 transistor

2004 wiring

2005 wiring

2007 Pixel section

2014 signal

2015 signal

3020 pixels

3021 transistor

3022 Click the LCD button

3023 Capacitive element

3031 wiring

3032 wiring

3033 wiring

3034 electrode

5000 cabinet

5001 Display section

5002 Display section

5003 speaker

5004 LED lamp

5005 Operation keys

5006 Connection terminals

5007 sensor

5008 microphone

5009 switch

5010 Infrared port

5011 Recording medium reading unit

5012 Support part

5013 earphones

5014 antenna

5015 Shutter button

5016 Image receiving section

5017 charger

5018 support stand

5019 External connection port

5020 Pointing device

5021 Leader/Writer

5022 cabinet

5023 Display section

5024 Remote control device

5025 speaker

5026 Display panel

5027 Unit bathroom

5028 Display panel

5029 Vehicle body

5030 ceiling

5031 Display panel

5032 Hinge

5260 substrate

5261 insulating layer

5262 Semiconductor layer

5263 insulating layer

5264 conductive layer

5265 insulating layer

5266 conductive layer

5267 insulating layer

5268 conductive layer

5269 insulating layer

5270 Light-emitting layer

5271 conductive layer

5300 substrate

5301 conductive layer

5302 insulating layer

5304 conductive layer

5305 insulating layer

5306 conductive layer

5307 Liquid crystal layer

5308 conductive layer

5350 region

5351 region

5352 Semiconductor substrate

5353 region

5354 insulating layer

5355 region

5356 insulating layer

5357 conductive layer

5358 insulating layer

5359 conductive layer

5391 substrate

5392 Drive circuit

5393 Pixel section

5400 substrate

5401 conductive layer

5402 insulating layer

5404 conductive layer

5405 insulating layer

5406 conductive layer

5407 Liquid crystal layer

5408 insulating layer

5409 conductive layer

5410 substrate

5420 substrate

5421 conductive layer

5422 conductive layer

5423 insulating layer

5424 Contact hole

5425 Oxide semiconductor layer

5429 conductive layer

5430 conductive layer

5431 conductive layer

5432 insulating layer

5433 conductive layer

5434 conductive layer

5435 insulating layer

5441 transistor

5442 Capacitive element

1002a Circuit

1002b Circuit

2006A Scan Line Drive Circuit

2006B Scan Line Drive Circuit

5262a area

5262b area

5262c area

5262d area

5262e area

5303a Semiconductor layer

5303b Semiconductor layer

5403a Semiconductor layer

5403b Semiconductor layer