Semiconductor element, semiconductor device, and method for manufacturing the same

The present invention relates to a semiconductor element using an oxide semiconductor and a semiconductor device using the semiconductor element. For example, it relates to an electronic device having a semiconductor integrated circuit as a component. It also relates to methods for producing them.

In this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, electronic components, and electronic equipment are all semiconductor devices.

In recent years, semiconductor devices have been developed and used as LSIs, CPUs, and memories. A CPU is an assembly of semiconductor elements having semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and having electrodes as connection terminals formed thereon.

Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.

In addition, semiconductor devices capable of transmitting and receiving data are being developed, and such semiconductor devices are called wireless tags, RFID tags, and the like. Many of those that have been put into practical use have an antenna and a semiconductor circuit (IC chip) formed using a semiconductor substrate.

Silicon-based semiconductor materials are known as semiconductors that can be applied to transistors, but oxide semiconductors are attracting attention as other materials. Zinc oxide or a material containing zinc oxide as a component is known as an oxide semiconductor material. And the electron carrier concentration is 10¹⁸/cm³A transistor formed of an amorphous oxide (oxide semiconductor) having a density of less than 100 nm has been disclosed (Patent Documents 1 to 3).

<p><patcit num="1"><text>JP-A-2006-165527</text></patcit><patcit num="2"><text>JP-A-2006-165528</text></patcit><patcit num="3"><text>JP-A-2006-165529</text></patcit></p>

<p>A method of miniaturizing a semiconductor element by shortening the channel length L of the semiconductor element in order to increase the operation speed of the circuit and reduce the power consumption in a semiconductor integrated circuit manufactured with semiconductor elements using an oxide semiconductor. There is</p><p>In order to shorten the channel length L and miniaturize a top-gate semiconductor element using an oxide semiconductor, it is necessary to narrow the gap between the source electrode layer and the drain electrode layer formed on the oxide semiconductor layer. There is However, there is a limit to narrowing the gap between the source electrode layer and the drain electrode layer by photoprocessing, so it is difficult to manufacture a fine semiconductor element.</p><p>Thus, an object of one embodiment of the present invention is to provide a top-gate semiconductor element using an oxide semiconductor, which has a short channel length L and can be miniaturized. Another object of one embodiment of the present invention is to provide a method for manufacturing the semiconductor element.</p><p>In addition, by using fine semiconductor elements with a short channel length L in semiconductor integrated circuits such as LSIs, CPUs, and memories, one of the challenges is to increase the operating speed of circuits and reduce power consumption. do.</p><p>In addition, by improving the coverage of the source electrode layer and the drain electrode layer by the gate insulating layer and preventing a short circuit between the gate electrode layer and the source electrode layer or the drain electrode layer, a highly reliable semiconductor element, and An object is to provide a semiconductor device using the semiconductor element.</p>

<p>In a top-gate semiconductor element using an oxide semiconductor, a fine semiconductor element with a short channel length L can be manufactured by providing sidewalls in the source electrode layer and the drain electrode layer. Further, by using fine semiconductor elements with a short channel length L in semiconductor integrated circuits such as LSIs, CPUs, and memories, it is possible to increase the operating speed of circuits and reduce power consumption.</p><p>In addition, in a top-gate semiconductor element using an oxide semiconductor, side walls of the source electrode layer and the drain electrode layer are provided so that the side surfaces of the source electrode layer and the drain electrode layer are tapered. Coverage is improved, short-circuiting between the gate electrode layer and the source electrode layer or the drain electrode layer can be prevented, and a highly reliable semiconductor element can be manufactured.</p><p>A normally-off semiconductor element with low off-state current can be obtained by using a highly purified oxide semiconductor layer that has a large energy gap and whose hydrogen concentration is sufficiently reduced by removing impurities such as hydrogen and moisture. can be made. By using the semiconductor element, a semiconductor device with low power consumption due to leakage current can be realized.</p><p>One embodiment of the present invention includes an oxide semiconductor layer over an insulating surface, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, and a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer. and a gate electrode layer over the gate insulating layer, the source electrode layer and the drain electrode layer have sidewalls, and the sidewalls are in contact with the top surface of the oxide semiconductor layer.</p><p>One embodiment of the present invention includes an oxide semiconductor layer over an insulating surface, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, and the source electrode layer and the first source electrode layer. , a second source electrode layer on the first source electrode layer, a drain electrode layer consisting of the first drain electrode layer and a second drain electrode layer on the first drain electrode layer, a second The sidewall provided on the source electrode layer of is in contact with the top surface of the first source electrode layer, the sidewall provided on the second drain electrode layer is in contact with the top surface of the first drain electrode layer, and the oxide semiconductor layer and the source electrode layer are in contact with the top surface of the first drain electrode layer. , a drain electrode layer, and a gate insulating layer on the sidewalls, having a gate electrode layer on the gate insulating layer, the first source electrode layer extending from an end of the second source electrode layer, The first drain electrode layer is a semiconductor element extending from the end of the second drain electrode layer.</p><p>Each of the above configurations solves at least one of the above problems.</p><p>In addition, a conductive layer may be formed below the oxide semiconductor layer, and one of the configurations of the present invention is, in each of the above configurations, a conductive layer on the insulating surface and a first insulating layer covering the conductive layer. The conductive layer is a semiconductor element that overlaps with the oxide semiconductor layer with the first insulating layer interposed therebetween.</p><p>In order to reduce parasitic capacitance, another structure of the invention is that in each of the above structures, a gate insulating layer and a second insulating layer are provided between the gate electrode layer and the source electrode layer or the drain electrode layer. It is a semiconductor element having In other words, the source electrode layer or the drain electrode layer is a semiconductor element that partially overlaps with the gate electrode layer with the gate insulating layer and the second insulating layer interposed therebetween. By providing a gate insulating layer and a second insulating layer between the gate electrode layer and the source electrode layer or the drain electrode layer, The gap between is widened, and the parasitic capacitance can be reduced.</p><p>On the other hand, when the insulating layer is provided, it is necessary to adjust the etching conditions such as the selection ratio between the insulating layer and the source electrode layer and the drain electrode layer in order to taper the source electrode layer and the drain electrode layer. It becomes difficult to process by Unless the source electrode layer and the drain electrode layer are tapered, a problem arises in that the coverage of the gate insulating layer stacked thereover is reduced. However, in the semiconductor element of one embodiment of the present invention, side surfaces of the source electrode layer and the drain electrode layer are tapered by providing the sidewalls of the source electrode layer and the drain electrode layer. There is no need to taper the ends, which facilitates fabrication of the semiconductor element.</p><p>Further, in each of the above structures, the carrier concentration of the oxide semiconductor layer is 1×10¹²/cm³It is preferably less than In addition, in each of the above configurations, the off current value of the semiconductor element is 1×10^-13It is preferably less than A.</p><p>Another embodiment of the present invention is a semiconductor device including the semiconductor element having any of the above structures.</p><p>Further, a semiconductor circuit can be manufactured by combining a plurality of semiconductor elements each including an oxide semiconductor layer in which hydrogen concentration is sufficiently reduced. As a semiconductor circuit, for example, an EDMOS circuit can also be formed, and its configuration is such that a first semiconductor element having a first oxide semiconductor layer on an insulating surface and a second semiconductor element having a second oxide semiconductor layer on an insulating surface. , wherein the first oxide semiconductor layer and the second oxide semiconductor layer have a carrier concentration of 1×10¹²/cm³A semiconductor device that is less than</p><p>Here, the EDMOS circuit refers to an inverter circuit configured by combining enhancement type transistors and depletion type transistors.</p><p>In addition to LSIs, CPUs, and memories, power supply circuits, transmission/reception circuits, audio processing circuit amplifiers, display drive circuits, controllers, audio processing circuit converters, etc. are manufactured using the above-described semiconductor elements. You can also</p><p>Also, a so-called MCP (Multi Chip Package), which is a package in which a plurality of semiconductor integrated circuits are mounted in one package to increase the integration of the semiconductor device, may be used.</p><p>Moreover, when mounting a semiconductor integrated circuit on a circuit board, it may be in a face-up form or in a flip-chip form (face-down form).</p><p>In one embodiment of the present invention, an oxide semiconductor layer is formed over an insulating surface, a source electrode layer and a drain electrode layer are formed over the oxide semiconductor layer, and the oxide semiconductor layer, the source electrode layer, and the drain electrode are formed. A film to be a sidewall is formed over the layer, and the film to be the sidewall is etched to form sidewalls of the source electrode layer and the drain electrode layer, which are in contact with the top surface of the oxide semiconductor layer. 1, a method for manufacturing a semiconductor element, in which a gate insulating layer is formed over a source electrode layer, a drain electrode layer, and sidewalls, and the gate electrode layer is formed over the gate insulating layer.</p><p>In one embodiment of the present invention, an oxide semiconductor layer is formed over an insulating surface, a first conductive film and a second conductive film are formed over the oxide semiconductor layer, and the second conductive film is etched. Thus, a second source electrode layer and a second drain electrode layer are formed, films to be sidewalls are formed over the first conductive film, the second source electrode layer, and the second drain electrode layer, and the sidewalls are formed. By etching the film to form the second source electrode layer and the second drain electrode layer, sidewalls of the second source electrode layer and the second drain electrode layer are formed, and the first conductive film is etched using the sidewalls as a mask to form the first source electrode layer. a layer, and a first drain electrode layer, the oxide semiconductor layer, the first source electrode layer, the second source electrode layer, the first drain electrode layer, the second drain electrode layer, and the sidewalls; Forming a gate insulating layer and forming a gate electrode layer on the gate insulating layer, a first source electrode layer extends from an end of the second source electrode layer, and a first drain electrode layer extends from the first source electrode layer. 2 is a method for manufacturing a semiconductor element extending from an end portion of a drain electrode layer and having sidewalls in contact with the upper surface of the first source electrode layer or the first drain electrode layer.</p><p>In one embodiment of the present invention, in each of the above structures, a conductive layer is formed over an insulating surface, an insulating layer is formed to cover the conductive layer, and an oxide semiconductor layer is formed over the conductive layer with the insulating layer interposed therebetween. It is a method of manufacturing a semiconductor device that</p><p>Note that in this specification, the channel length L refers to the length in the direction connecting the source electrode layer and the drain electrode layer in the region where the lower end portion of the gate electrode layer and the oxide semiconductor layer overlap.</p><p>In addition, the terms "above" and "below" in this specification and the like do not limit the positional relationship between the constituent elements to be "directly above" or "directly below." For example, the expression "a gate electrode layer over a gate insulating layer" does not exclude other components between the gate insulating layer and the gate electrode layer. In addition, the terms "upper" and "lower" are merely expressions used for the convenience of explanation, and include those in which the upper and lower sides are interchanged unless otherwise specified.</p><p>In addition, the terms electrode and wiring in this specification and the like do not functionally limit these constituent elements. For example, an "electrode" may be used as part of a "wiring" and vice versa. Furthermore, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally formed.</p><p>Also, the functions of "source" and "drain" may be interchanged when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably.</p>

<p>One embodiment of the present invention can provide a top-gate semiconductor element including an oxide semiconductor layer, which has a short channel length L and can be miniaturized by providing sidewalls to a source electrode layer and a drain electrode layer. can. Further, one embodiment of the present invention can provide a method for manufacturing the semiconductor element.</p><p>Further, by using a minute semiconductor element with a short channel length L of one embodiment of the present invention in a semiconductor integrated circuit such as an LSI, a CPU, or a memory, the operation speed of the circuit can be increased and power consumption can be reduced. can.</p><p>In addition, in the semiconductor element of one embodiment of the present invention, the sidewalls of the source electrode layer and the drain electrode layer are provided so that the side surfaces of the source electrode layer and the drain electrode layer are tapered, so that the coverage of the gate insulating layer is improved. , a short circuit between the gate electrode layer and the source electrode layer or the drain electrode layer can be prevented, and a highly reliable semiconductor element can be manufactured.</p>

<figref num="1">1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention;</figref><figref num="2">1A to 1D are cross-sectional views illustrating a manufacturing method of one embodiment of the present invention;</figref><figref num="3">1A to 1D are cross-sectional views illustrating a manufacturing method of one embodiment of the present invention;</figref><figref num="4">1 is an equivalent circuit diagram showing one embodiment of the present invention; FIG.</figref><figref num="5">1A and 1B are cross-sectional views illustrating one embodiment of the present invention;</figref><figref num="6">1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention;</figref><figref num="7">1 is a cross-sectional view of a top-gate transistor FIG.</figref><figref num="8">FIG. 8 is an energy band diagram (schematic diagram) in the AA cross section shown in FIG. 7;</figref><figref num="9">FIG. 8 is an energy band diagram between BB shown in FIG. 7;</figref><figref num="10">FIG. 4 is a diagram showing the relationship between the vacuum level, the work function (φM) of metal, and the electron affinity (χ) of an oxide semiconductor;</figref><figref num="11">The figure which shows the energy required for hot carrier injection in silicon (Si).</figref><figref num="12">FIG. 4 is a diagram showing the energy required for hot carrier injection in an In--Ga--Zn--O-based oxide semiconductor (IGZO).</figref><figref num="13">The figure which shows the energy required for hot carrier injection in silicon carbide (4H-SiC).</figref><figref num="14">FIG. 4 is a diagram showing results of calculations (device simulations) regarding short channel effects;</figref><figref num="15">FIG. 4 is a diagram showing results of calculations (device simulations) regarding short channel effects;</figref><figref num="16">The figure which shows CV characteristic.</figref><figref num="17">V._gand (1/C)²A diagram showing the relationship between</figref><figref num="18">1 is a block diagram showing one embodiment of the present invention; FIG.</figref><figref num="19">4A and 4B illustrate a semiconductor device;</figref><figref num="20">4A and 4B illustrate a semiconductor device;</figref><figref num="21">4A and 4B illustrate a semiconductor device;</figref><figref num="22">4A and 4B illustrate a semiconductor device;</figref><figref num="23">4A and 4B illustrate a semiconductor device;</figref><figref num="24">1 is an equivalent circuit diagram showing one embodiment of the present invention; FIG.</figref><figref num="25">1 is an equivalent circuit diagram showing one embodiment of the present invention; FIG.</figref><figref num="26">1 is an equivalent circuit diagram showing one embodiment of the present invention; FIG.</figref><figref num="27">1A and 1B are diagrams each illustrating an example of an electronic device;</figref><figref num="28">1A and 1B are cross-sectional views illustrating one embodiment of the present invention;</figref>

Embodiments of the present invention will be described in detail below with reference to the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the forms and details thereof can be variously changed. Moreover, the present invention should not be construed as being limited to the description of the embodiments shown below.

Note that the position, size, range, etc. of each configuration shown in the drawings, etc. may not represent the actual position, size, range, etc. for ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.

It should be noted that the ordinal numbers such as "first", "second", "third" in this specification etc. are added to avoid confusion of constituent elements and are not numerically limited. do.

(Embodiment 1) In this embodiment, an example of a cross-sectional structure of a semiconductor element of one embodiment of the present invention will be described.

The semiconductor device of this embodiment will be described with reference to FIGS. 1 and 28. FIG. FIG. 1A shows a top view of a semiconductor element of one embodiment of the present invention. FIG. 1(B) shows a cross-sectional view between A1-B1 in FIG. 1(A). FIGS. 1(C) and 1(D) show enlarged views of the dashed line portion 199 in FIG. 1(B). 28A and 28B show an example of a cross-sectional structure of a semiconductor element of one embodiment of the present invention. A transistor 200 illustrated in FIG. 1 and transistors 201 and 300 illustrated in FIGS. 28A and 28B are one of top-gate transistors.

A transistor 200 illustrated in FIGS. 1A and 1B includes a first insulating layer 103, a second insulating layer 105, an oxide semiconductor layer 107, a source electrode layer 109a, and a drain over a substrate 101 having an insulating surface. It includes electrode layer 109b, sidewalls 121, gate insulating layer 117, and gate electrode layer 119. FIG.

The transistor 200 has sidewalls 121 of the source electrode layer 109a and the drain electrode layer 109b. A lower end portion of the sidewall 121 is in contact with the top surface of the oxide semiconductor layer 107 . Although there is a limit to narrowing the gap between the source electrode layer 109a and the drain electrode layer 109b by photoprocessing, anisotropic etching is used to provide the sidewall 121 in the gap, thereby narrowing the gap between the source electrode layer 109a and the drain electrode layer 109b. Since the width of the gate electrode layer 119 sandwiched between the layers 109b can be narrowed, a fine transistor with a short channel length L can be manufactured. By shortening the channel length L, short channel effects can occur. A short-channel effect in a transistor including an oxide semiconductor will be described later in this embodiment.

Note that in this specification, the channel length L refers to the length in the direction connecting the source electrode layer and the drain electrode layer in the region where the lower end portion of the gate electrode layer and the oxide semiconductor layer overlap (see FIG. 1C). )).

In addition, since the sidewalls of the transistor 200 taper the sides of the source and drain electrode layers, the coverage of the gate insulating layer is improved and a short circuit between the gate electrode layer and the source or drain electrode layer is achieved. can be prevented, and the transistor can have high reliability.

Also, if the side wall 121 is formed using an insulating material, the offset region L is formed as shown in FIG. 1(C)._offis provided. In this case, the offset area L_offis a region between the channel length L and a region A where the edge of the source electrode layer or the drain electrode layer overlaps with the oxide semiconductor layer. Offset area L_offBy providing the , the distance between the gate electrode layer and the source electrode layer or the drain electrode layer is increased, and the phenomenon of short-circuiting between the electrodes can be further prevented. In addition, parasitic capacitance between the gate electrode layer and the source or drain electrode layer can be reduced.

On the other hand, when the sidewall 121 is formed using a conductive material, the sidewall 121 functions as part of the source electrode layer or the drain electrode layer._offcan be reduced (Fig. 1(D)). In this case, the offset area L_offis the channel length L and the distance between the region B where the lower end of the sidewall 121 and the oxide semiconductor layer overlap. Therefore, high on-current and high mobility can be achieved.

In other words, by changing the material used for the sidewall 121, the offset region L_offcan be made larger or smaller.

The transistor 200 also includes the highly purified oxide semiconductor layer 107 as a channel region. The transistor 200 using a highly purified oxide semiconductor with a large energy gap has a small off current and is normally off (that is, when the gate voltage is 0 V, no current flows between the source electrode and the drain electrode). ), and the temperature dependence of the transistor characteristics is small. For example, when the drain voltage Vd is +1V or +10V, the drain current Id is sufficiently large in the region where the gate voltage Vg is positive, and the gate voltage Vg is 1×10 V in the range of -5V to -20V.^-13It can be A or lower.

Note that the carrier concentration of the highly purified oxide semiconductor layer 107 in which the hydrogen concentration is sufficiently reduced is 1×10¹²/cm³Less than, preferably 1 x 10¹¹/cm³less than or more preferably 1.45×10¹⁰/cm³take the following: A method for obtaining the carrier concentration will be described later in this embodiment.

Further, the energy gap of the oxide semiconductor layer 107 is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. A comparison with other materials with large energy gaps will be described later. In addition, a transistor including an oxide semiconductor that is highly purified and has a low carrier concentration has high resistance to hot carrier deterioration. Details of this will also be described later.

In this way, the normally-off transistor 200 with low off-state current is manufactured by using the highly purified oxide semiconductor layer 107 with a large energy gap and a sufficiently reduced hydrogen concentration. A semiconductor device having the configuration can be realized.

A transistor 201 illustrated in FIG. 28A includes an electrode layer 102, a first insulating layer 103, a second insulating layer 105, an oxide semiconductor layer 107, a source electrode layer 109a, and a drain over a substrate 101 having an insulating surface. It includes electrode layer 109b, sidewalls 121, gate insulating layer 117, and gate electrode layer 119. FIG.

That is, the transistor 201 has a structure in which the electrode layer 102 is added to the transistor 200. FIG.

The electrode layer 102 provided below the oxide semiconductor layer 107 of the transistor 201 can function as a back gate. The potential of the back gate can be a fixed potential such as 0 V or a ground potential, and can be determined appropriately by the practitioner. In addition, by providing gate electrodes above and below the oxide semiconductor layer, changes in the threshold voltage of the transistor before and after the BT test in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor. amount can be reduced. In other words, reliability can be improved by providing the gate electrodes above and below the oxide semiconductor layer.

Further, by controlling the gate voltage applied to the electrode layer 102, the threshold voltage can be controlled. By making the threshold voltage positive, the transistor can function as an enhancement type transistor. Also, by making the threshold voltage negative, the transistor can function as a depletion type transistor.

For example, an inverter circuit (an EDMOS-type inverter circuit, hereinafter simply referred to as an EDMOS circuit) can be configured by combining an enhancement-type transistor and a depletion-type transistor, and used as a drive circuit. The drive circuit has at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the EDMOS circuit. Further, the switch portion or the buffer portion preferably uses a transistor through which a large amount of on-state current can flow, and a depletion transistor or a transistor having gate electrodes above and below an oxide semiconductor layer is used.

In addition, transistors with different structures can be manufactured over the same substrate without significantly increasing the number of steps. For example, in an integrated circuit driven at high speed, an EDMOS circuit is configured using transistors having gate electrodes above and below an oxide semiconductor layer as shown in FIG. A transistor having only one gate electrode can also be formed in another region.

An n-channel transistor with a positive threshold voltage is defined as an enhancement-type transistor, and an n-channel transistor with a negative threshold voltage is defined as a depletion-type transistor. shall comply with this definition.

A transistor 300 illustrated in FIG. 28B includes a first insulating layer 303, a second insulating layer 305, an oxide semiconductor layer 307, a source electrode layer (first source electrode layer) over a substrate 301 having an insulating surface. 309a, second source electrode layer 311a), drain electrode layers (first drain electrode layer 309b, second drain electrode layer 311b), third insulating layer 315, sidewalls 321, gate insulating layer 317, and gate electrode Includes layer 319 .

The transistor 300 has sidewalls 321 of the second source electrode layer 311a and the second drain electrode layer 311b. A lower end portion of the sidewall 321 is in contact with the upper surface of the first source electrode layer 309a or the first drain electrode layer 309b. By having the sidewalls 321, a fine transistor with a short channel length L can be manufactured. By shortening the channel length L, short channel effects can occur. A short-channel effect in a transistor including an oxide semiconductor will be described later in this embodiment.

Transistor 300 has a third insulating layer 315 . By providing the third insulating layer 315, parasitic capacitance between the gate electrode layer 319 and the second source electrode layer 311a or between the gate electrode layer 319 and the second drain electrode layer 311b can be reduced. can be done. On the other hand, in order to taper the second source electrode layer 311a and the second drain electrode layer 311b by providing the third insulating layer 315, the third insulating layer 315 and the second source electrode layer It is necessary to adjust the etching conditions such as the selection ratio of the second drain electrode layer 311a and the second drain electrode layer 311b, which makes the processing by etching difficult. Unless the second source electrode layer 311a and the second drain electrode layer 311b are tapered, a problem arises in that the coverage of the gate insulating layer 317 stacked thereover is reduced. However, in the transistor of one embodiment of the present invention, the sidewalls 321 taper the sides of the second source electrode layer 311a and the second drain electrode layer 311b, so that the second source electrode layer 311a and the second drain electrode layer 311a There is no need to taper the end of the electrode layer 311b, which facilitates fabrication of the transistor.

Unlike the transistors 200 and 201, the transistor 300 has an offset region L_offoffset region L_offis determined by the thickness of the gate insulating layer.

By the way, as described above, the transistor of this embodiment can be an intrinsic or substantially intrinsic semiconductor by removing impurities that can be carrier donors (donors or acceptors) in the oxide semiconductor to an extremely low level. An oxide semiconductor is used.

The significance of making an oxide semiconductor highly purified and intrinsic (i-type), the merits of forming a semiconductor device using an oxide semiconductor, and the like will be briefly described below.

&lt;Intrinsicization of Oxide Semiconductors&gt; In oxide semiconductors, many studies on physical properties such as DOS (density of state) have been conducted, but these studies do not include the idea of sufficiently reducing localized levels themselves. In one embodiment of the disclosed invention, a highly purified oxide semiconductor is manufactured by removing water and hydrogen, which may cause localized levels, from the oxide semiconductor. This is based on the idea of sufficiently reducing the localized level itself. This makes it possible to manufacture extremely excellent industrial products.

When removing hydrogen, water, or the like, oxygen may be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal generated due to oxygen deficiency, and the localized levels due to oxygen defects are reduced, thereby further purifying the oxide semiconductor (i-type). preferred. For example, by forming an oxygen-excess oxide film in close contact with the channel formation region and performing heat treatment at a temperature condition of 200° C. to 400° C., typically about 250° C., oxygen is removed from the oxide film. can be supplied to reduce the localized levels due to oxygen defects. Further, the inert gas may be switched to a gas containing oxygen during the second heat treatment to be described later. Oxygen can also be supplied to the oxide semiconductor by performing a temperature-lowering process in an oxygen atmosphere or an atmosphere from which hydrogen and water are sufficiently removed following the second heat treatment.

Factors that degrade the characteristics of oxide semiconductors are considered to be caused by excess hydrogen at a level of 0.1 to 0.2 eV below the conduction band, a deep level by oxygen vacancies, and the like. In order to eliminate these defects, the technical idea of thoroughly removing hydrogen and sufficiently supplying oxygen would be correct.

Note that an oxide semiconductor is generally n-type, but in one embodiment of the disclosed invention, impurities such as water and hydrogen are removed and oxygen, which is a constituent element of the oxide semiconductor, is supplied to i-type. realization of In this respect, it can be said that it includes an unprecedented technical idea, unlike the i-type conversion by doping impurities like silicon.

In addition, by making the oxide semiconductor i-type, the temperature characteristics of the transistor are excellent. , off-current, field-effect mobility, S-value, and threshold voltage, and there is almost no deterioration in current-voltage characteristics due to temperature.

The technical idea of this embodiment is to intentionally remove impurities such as water and hydrogen that are unintentionally present in the oxide semiconductor without adding any impurities to the oxide semiconductor. It is to purify itself. That is, the oxide semiconductor is highly purified by removing water or hydrogen that constitutes a donor level, further reducing oxygen vacancies, and sufficiently supplying oxygen as a main component material constituting the oxide semiconductor. is.

10 at the time of oxide semiconductor film formation²⁰/cm³is measured by secondary ion mass spectrometry (SIMS) that the level of hydrogen is present in the oxide semiconductor. By intentionally removing the water or hydrogen that causes this donor level, and adding oxygen (one of the components of the oxide semiconductor), which decreases as the water or hydrogen is removed, to the oxide semiconductor , the oxide semiconductor is highly purified to be an electrically i-type (intrinsic) semiconductor.

In addition, in this embodiment, the smaller the amount of water and hydrogen in the oxide semiconductor, the better, and the smaller the number of carriers, the better. That is, the carrier concentration is 1×10¹²/cm³less than, more preferably 1.45 x 10¹⁰/cm³Less than is required. Furthermore, in terms of the technical idea of this embodiment, it is ideally close to zero or zero. In particular, the oxide semiconductor is heated at 450°C to 850°C, preferably at 450°C to 850°C, in an atmosphere of oxygen, nitrogen, or ultra-dry air (air having a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less). By performing heat treatment at 550° C. or more and 750° C. or less, water or hydrogen, which is an n-type impurity, can be removed and highly purified. In addition, by removing impurities such as water or hydrogen, the oxide semiconductor is highly purified, and the carrier concentration is reduced to 1×10¹²/cm³less than, more preferably 1.45 x 10¹⁰/cm³can be less than

By reducing or preferably eliminating carriers in the oxide semiconductor, the oxide semiconductor functions as a path through which carriers pass in the transistor.

In this way, the oxide semiconductor film is highly purified so that impurities other than the main components of the oxide semiconductor film, typically hydrogen, water, hydroxyl groups, hydrides, and the like are contained as little as possible, so that the transistor can operate well. can do. Moreover, the amount of change in the threshold voltage of the transistor before and after the BT test can be suppressed, and high reliability can be achieved. Also, the temperature dependence of electrical properties can be suppressed.

&lt;Comparison with other semiconductor materials&gt; Silicon carbide (eg, 4H-SiC) is a semiconductor material that can be compared with oxide semiconductors. Oxide semiconductors and 4H-SiC have some things in common. Carrier concentration is one example. Using the Fermi-Dirac distribution at room temperature, the number of minority carriers in oxide semiconductors is 10^-7/cm³, which is 6.7 × 10 in 4H-SiC.^-11/cm³Similar to , the value is extremely low. Intrinsic carrier concentration of silicon (1.45×10¹⁰/cm³degree), it is easy to understand that the degree is out of the ordinary.

In addition, the energy bandgap of oxide semiconductors is 3.0 to 3.5 eV, and the energy bandgap of 4HSiC is 3.26 eV. there is

On the other hand, there is a very large difference between an oxide semiconductor and silicon carbide. It is the process temperature. Since silicon carbide generally requires heat treatment at 1500° C. to 2000° C., it is difficult to form a laminated structure with semiconductor elements using other semiconductor materials. This is because semiconductor substrates and semiconductor elements are destroyed at such high temperatures. On the other hand, an oxide semiconductor can be produced by heat treatment at 300 to 800° C., and after forming an integrated circuit using another semiconductor material, a semiconductor element can be formed using the oxide semiconductor.

Further, unlike the case of silicon carbide, an oxide semiconductor has an advantage that a substrate with low heat resistance such as a glass substrate can be used. Furthermore, in that heat treatment at high temperatures is not required, there is an advantage that the energy cost can be sufficiently reduced compared to silicon carbide. Furthermore, silicon carbide is a factor in generating carriers due to crystal defects and trace amounts of unintentionally mixed impurities. Therefore, in theory, silicon carbide can have a low carrier concentration equivalent to that of the oxide semiconductor of one embodiment of the present invention.¹²/cm³It is difficult to obtain the following carrier concentration. The above also applies to comparison between gallium nitride and oxide semiconductors, which are also known as wide-gap semiconductors.

&lt;Conduction Mechanism of Transistor Using Oxide Semiconductor&gt; Here, the conduction mechanism of a transistor including an oxide semiconductor will be described with reference to FIGS. It should be noted that the following description assumes an ideal situation for easy understanding, and does not necessarily reflect the actual situation. Also, it should be added that the following explanation is merely one consideration and does not affect the effectiveness of the invention.

FIG. 7 shows a cross-sectional view of an inverted staggered transistor (thin film transistor) using an oxide semiconductor. A source electrode layer (S) and a drain electrode layer (D) are provided on an oxide semiconductor layer (OS), and a gate electrode layer (GE) is provided thereon with a gate insulating layer (GI) interposed therebetween.

FIG. 8 shows an energy band diagram (schematic diagram) in the AA' section of FIG. In FIG. 8, black circles () indicate electrons and white circles () indicate holes, each of which has an electric charge (q, +q). A positive voltage on the drain (V_D.&gt;0) and no voltage is applied to the gate (V_G.=0) with a dashed line and a positive voltage on the gate (V_G.&gt;0) is applied as a solid line. When no voltage is applied to the gate, carriers (electrons) are not injected from the electrode to the oxide semiconductor side due to the high potential barrier, indicating an off state in which no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier is lowered, indicating an ON state that allows current to flow.

At this time, electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the lowest energetically stable portion of the oxide semiconductor) as shown in FIG. 9A.

Further, as shown in FIG. 9B, when a negative potential is applied to the gate electrode (GE), the number of holes, which are minority carriers, is substantially zero, so the current becomes infinitely close to zero. .

By purifying the oxide semiconductor so as not to contain elements (impurity elements) other than the main components of the oxide semiconductor as much as possible in this way, the oxide semiconductor becomes intrinsic (i-type) or substantially intrinsic. Characteristics are revealed. Therefore, the gate insulating layer is required to form a good interface with the oxide semiconductor. Specifically, for example, it is preferable to use an insulating layer produced by a CVD method using high-density plasma generated at a power supply frequency in the VHF band to a microwave band, an insulating layer produced by a sputtering method, or the like. .

By improving the interface between the oxide semiconductor and the gate insulating layer while purifying the oxide semiconductor, for example, the channel width W of the transistor can be reduced to 1×10.⁴μm, and channel length L is 3 μm, at room temperature, 10^-13An off current of A or less and a subthreshold swing value (S value) of 0.1 V/dec. (thickness of gate insulating layer: 100 nm) can be realized.

By purifying the oxide semiconductor so as not to contain elements (impurity elements) other than the main components of the oxide semiconductor as much as possible, the operation of the transistor can be improved.

&lt;Hot Carrier Deterioration Resistance of Transistor Using Oxide Semiconductor&gt; Next, hot carrier deterioration resistance of a transistor using an oxide semiconductor will be described with reference to FIGS. It should be noted that the following description assumes an ideal situation for easy understanding, and does not necessarily reflect the actual situation. Also, it should be noted that the following description is merely one consideration.

Main causes of hot carrier degradation are channel hot electron injection (CHE injection) and drain avalanche hot carrier injection (DAHC injection). For simplicity, only electrons will be considered below.

CHE injection refers to a phenomenon in which electrons having energy higher than the barrier with the gate insulating layer in the semiconductor layer are injected into the gate insulating layer or the like. The transfer of energy to the electrons is done by being accelerated in a low electric field.

DAHC injection is a phenomenon in which new electrons generated by the collision of electrons accelerated by a high electric field are injected into the gate insulating layer or the like. The difference between DAHC implantation and CHE implantation is whether avalanche breakdown due to impact ionization is involved. DAHC injection requires electrons with a kinetic energy greater than the bandgap of the semiconductor.

FIGS. 11 and 12 show energies required for injection of various hot carriers estimated from the band structures of silicon (Si) and an In--Ga--Zn--O-based oxide semiconductor (IGZO).

In FIGS. 11 and 12, the left represents CHE injection and the right represents DAHC injection.

In silicon, the degradation caused by DAHC injection is more severe than that caused by CHE injection. This is because although the number of carriers (for example, electrons) that are accelerated without colliding in silicon is very small, silicon has a small bandgap and is prone to avalanche breakdown.

Due to the avalanche breakdown, the number of electrons that can cross the barrier of the gate insulating layer increases, and the probability of hot electron generation increases compared to the case without avalanche breakdown.

In the In-Ga-Zn-O-based oxide semiconductor, the energy required for CHE injection is not much different from that in silicon, and the probability is low as in silicon. However, the energy required for DAHC implantation is about the same as the energy required for CHE implantation due to the wide bandgap, which is higher than in the case of silicon.

In other words, the probability of both CHE injection and DAHC injection is low, and the resistance to hot carrier degradation is high compared to silicon.

By the way, the bandgap of an In--Ga--Zn--O-based oxide semiconductor is about the same as that of silicon carbide (SiC), which is attracting attention as a high breakdown voltage material. Figure 13 shows the energy required for various hot carrier injections for 4H-SiC. As for CHE injection, an In--Ga--Zn--O-based oxide semiconductor has a slightly higher threshold and can be said to be advantageous.

As described above, it can be seen that the In--Ga--Zn--O-based oxide semiconductor has much higher resistance to hot carrier degradation and source-drain breakdown than silicon. In addition, it can be said that a breakdown voltage comparable to that of silicon carbide can be obtained.

&lt;Short Channel Effect in Transistor Using Oxide Semiconductor&gt; Next, the short channel effect in a transistor using an oxide semiconductor will be described with reference to FIGS. It should be noted that the following description assumes an ideal situation for easy understanding, and does not necessarily reflect the actual situation. Also, it should be noted that the following description is merely one consideration.

The short-channel effect refers to the deterioration of electrical characteristics that manifests with miniaturization of transistors (reduction in channel length (L)). The short channel effect is caused by the effect of the electric field distribution near the drain reaching the source. Specific examples of short-channel effects include a decrease in threshold voltage, an increase in S value, and an increase in leakage current.

Here, a structure capable of suppressing the short channel effect was verified using calculation results (device simulation). Specifically, four types of models with different carrier concentrations and oxide semiconductor layer thicknesses were prepared, and the relationship between the channel length (L) and the threshold voltage (Vth) was confirmed. As a model, we adopted a bottom-gate structure transistor with a carrier concentration of 1.7 × 10^-8/cm³, or 1.0×10¹⁵/cm³, and the thickness of the oxide semiconductor layer was either 1 μm or 30 nm. Note that an In-Ga-Zn-O-based oxide semiconductor was used as the oxide semiconductor, and a silicon oxynitride film with a thickness of 100 nm was used as the gate insulating layer. Oxide semiconductor bandgap 3.15 eV, electron affinity 4.3 eV, dielectric constant 15, electron mobility 10 cm²/Vs was assumed. The dielectric constant of the silicon oxynitride film was assumed to be 4.0. Silvaco's device simulation software "Atlas" was used for the calculation.

Note that there is no significant difference in the calculation results between the top-gate structure and the bottom-gate structure.

Calculation results are shown in FIGS. 14 and 15. FIG. Figure 14 shows the carrier concentration of 1.7 × 10^-8/cm³, Figure 15 shows that the carrier concentration is 1.0 × 10¹⁵/cm³is the case. 14 and 15 show the amount of change (ΔVth) in the threshold voltage (Vth) when changing the channel length (L) from 10 μm to 1 μm, using a transistor with a channel length (L) of 10 μm as a reference. showing. As shown in Figure 14, the carrier concentration of the oxide semiconductor is 1.7 × 10^-⁸/cm³, and when the thickness of the oxide semiconductor layer was 1 μm, the amount of change in the threshold voltage (ΔVth) was ΔVth=3.6V. Also, as shown in FIG. 14, the carrier concentration of the oxide semiconductor is 1.7×10^-8/cm³, and when the thickness of the oxide semiconductor layer was 30 nm, the amount of change in the threshold voltage (ΔVth) was ΔVth=0.2V. As shown in FIG. 15, the carrier concentration of the oxide semiconductor is 1.0×10¹⁵/cm³, and when the thickness of the oxide semiconductor layer was 1 μm, the amount of change in the threshold voltage (ΔVth) was ΔVth=3.6V. Moreover, as shown in FIG. 15, the carrier concentration of the oxide semiconductor is 1.0×10¹⁵/cm³, and when the thickness of the oxide semiconductor layer was 30 nm, the amount of change in the threshold voltage (ΔVth) was ΔVth=0.2V. These results can be said to indicate that the short-channel effect can be suppressed in a transistor including an oxide semiconductor by reducing the thickness of the oxide semiconductor layer. For example, when the channel length is about 1 μm, it is understood that even if the oxide semiconductor layer has a sufficiently low carrier concentration, the short channel effect can be sufficiently suppressed by setting the thickness to about 30 nm. .

&lt;Regarding Carrier Concentration&gt; The technical idea of the disclosed invention is to sufficiently reduce the carrier concentration in the oxide semiconductor layer so as to approach intrinsic (i-type) as much as possible. Hereinafter, the method of obtaining the carrier concentration and the actually measured carrier concentration will be described with reference to FIGS. 16 and 17. FIG.

First, a brief description will be given of how to obtain the carrier concentration. The carrier concentration can be obtained by fabricating a MOS capacitor and evaluating the result (CV characteristic) of CV measurement (capacitance voltage measurement) of the MOS capacitor.

More specifically, the CV characteristics that plot the relationship between the gate voltage Vg and the capacitance C of the MOS capacitor are obtained, and the gate voltage Vg and (1/C) are obtained from the CV characteristics.²and (1/C) in the weak reversal region in the graph.²Carrier concentration N_dis required. In equation (1), q is the elementary charge, ε₀is the vacuum permittivity, and ε is the relative permittivity of the oxide semiconductor.

<math num="1"><img file="JP2022166322A_D0001.tif" /></math>

Next, carrier concentrations actually measured using the above method will be described. For the measurement, a titanium film with a thickness of 300 nm was formed on a glass substrate, a titanium nitride film with a thickness of 100 nm was formed on the titanium film, and an In-Ga-Zn-O-based film was formed on the titanium nitride film. A sample (MOS capacitor) was used in which an oxide semiconductor layer using an oxide semiconductor was formed with a thickness of 2 μm, and a silver film was formed with a thickness of 300 nm on the oxide semiconductor layer. Note that the oxide semiconductor layer is an oxide semiconductor deposition target containing In, Ga, and Zn (the composition ratio is In2O3:Ga2O3:Ga2O3:ZnO=1:1:1 [molar ratio], or In₂O₃: Ga₂O₃:ZnO=1:1:2 [molar ratio], or In₂O₃: Ga₂O₃: ZnO=1:1:4 [molar ratio]), etc., by a sputtering method. In addition, the atmosphere for forming the oxide semiconductor layer is a mixed atmosphere of argon and oxygen (the flow ratio is Ar:O₂=30(sccm):15(sccm)).

Figure 16 shows CV characteristics, and Figure 17 shows Vg and (1/C)², respectively. (1/C) in the weak inversion region of Fig. 17²The carrier concentration obtained using equation (1) from the differential value of is 6.0 × 10¹⁰/cm³Met.

Thus, an oxide semiconductor with a large energy gap and an i-type or substantially i-type (for example, a carrier concentration of 1×10¹²/cm³Less than, preferably 1.45 x 10¹⁰/cm³), a normally-off transistor with extremely excellent off-state current characteristics can be obtained.

As described above, the semiconductor element of one embodiment of the present invention is an intrinsic or substantially intrinsic semiconductor obtained by removing an impurity that serves as an electron donor (donor) in an oxide semiconductor, which is more stable than a silicon semiconductor. A channel region is preferably formed using an oxide semiconductor having a large energy gap. By manufacturing a semiconductor element using a highly purified oxide semiconductor with a large energy gap and sufficiently reduced hydrogen concentration, a normally-off semiconductor with low off current and low temperature dependence of transistor characteristics. device can be realized. Further, by using the semiconductor element, a semiconductor device that consumes less power due to leakage current can be realized.

A semiconductor element of one embodiment of the present invention is a top-gate semiconductor element using an oxide semiconductor layer, which has a short channel length L and can be miniaturized by providing sidewalls to the source electrode layer and the drain electrode layer. can do.

In addition, the semiconductor element of one embodiment of the present invention has a short channel length L and can be miniaturized. Power can be reduced.

In addition, in the semiconductor element of one embodiment of the present invention, since the side surfaces of the source electrode layer and the drain electrode layer are tapered by the sidewalls, the coverage of the gate insulating layer is improved, and the gate electrode layer and the source electrode layer or the drain electrode are formed. A short circuit between layers can be prevented, and a highly reliable semiconductor element and a highly reliable semiconductor device using the semiconductor element can be realized.

This embodiment can be freely combined with other embodiments.

(Embodiment 2) In this embodiment, an example of a method for manufacturing a semiconductor element will be described. One mode of the manufacturing method of the semiconductor element of this embodiment will be described with reference to FIG.

A process for manufacturing the transistors 200 and 201 described in Embodiment 1 over the substrate 101 having an insulating surface is described below with reference to FIGS.

There is no particular limitation on the substrate that can be used as the substrate 101 having an insulating surface, but it must have at least heat resistance to withstand heat treatment performed later. For example, a glass substrate of aluminosilicate glass, barium borosilicate glass, aluminoborosilicate glass, or the like can be used.

A substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used instead of the glass substrate. Alternatively, a crystallized glass substrate or the like can be used.

A semiconductor substrate having an insulating layer on its surface, a plastic substrate, or the like can also be used as appropriate.

First, a first insulating layer 103 is formed on a substrate 101 having an insulating surface. The first insulating layer 103 is formed of a single layer or stacked layers of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer by plasma CVD, sputtering, or the like.

Note that in the case of manufacturing the transistor 201 described in Embodiment 1, a conductive film is formed over the substrate 101 having an insulating surface, the electrode layer 102 is formed by a photolithography process, and then the electrode layer 102 is formed. A covering first insulating layer 103 is formed. As the material of the electrode layer 102, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above elements, or an alloy combining the above elements can be used. . In this embodiment, the electrode layer 102 has a laminated structure of a tungsten nitride layer and a tungsten layer.

Next, a second insulating layer 105 is formed on the first insulating layer 103. As shown in FIG. As the second insulating layer 105 in contact with the oxide semiconductor layer, an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer is preferably used. As a method for forming the second insulating layer 105, a plasma CVD method, a sputtering method, or the like can be used. It is preferable to form the second insulating layer 105 at .

In this embodiment mode, a silicon oxide layer is formed as the second insulating layer 105 by a sputtering method. The substrate 101 is transported to a processing chamber, a sputtering gas containing high-purity oxygen from which hydrogen and moisture are removed is introduced, and a silicon target is used to form a silicon oxide layer as the second insulating layer 105 on the substrate 101. . Also, the substrate 101 may be at room temperature or may be heated.

For example, quartz (preferably synthetic quartz) is used, the substrate temperature is 108°C, the distance between the substrate and the target (distance between TSs) is 60 mm, the pressure is 0.4 Pa, the power of the high frequency power supply is 1.5 kW, oxygen and argon (oxygen flow rate A silicon oxide layer is formed by RF sputtering under an atmosphere of 25 sccm:argon flow rate of 25 sccm=1:1). The film thickness is 100 nm. Note that instead of quartz (preferably synthetic quartz), a silicon target can be used as the target for forming the silicon oxide layer. Note that oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

In this case, it is preferable to form the second insulating layer 105 while removing moisture remaining in the processing chamber. This is to prevent the second insulating layer 105 from containing hydrogen, hydroxyl groups, or moisture.

In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption vacuum pump.

For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, the evacuation means may be a turbo pump with a cold trap added. A processing chamber evacuated using a cryopump can contain, for example, hydrogen atoms and water (H₂Since compounds containing hydrogen atoms such as O) are exhausted, the concentration of impurities contained in the second insulating layer 105 formed in the processing chamber can be reduced.

Further, the second insulating layer 105 may have a stacked structure, for example, a stacked structure of a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, or an aluminum nitride layer from the substrate 101 side, and the oxide insulating layer. may be

For example, a sputtering gas containing high-purity nitrogen from which hydrogen and moisture are removed is introduced between the silicon oxide layer and the substrate, and a silicon target is used to form a silicon nitride layer. Also in this case, similarly to the silicon oxide layer, it is preferable to form the silicon nitride layer while removing moisture remaining in the treatment chamber.

Also when forming a silicon nitride layer, the substrate may be heated during film formation.

When a silicon nitride layer and a silicon oxide layer are stacked as the second insulating layer 105, the silicon nitride layer and the silicon oxide layer can be deposited in the same treatment chamber using a common silicon target. First, a nitrogen-containing sputtering gas is introduced to form a silicon nitride layer using a silicon target mounted in the processing chamber. A silicon oxide layer is deposited. Since the silicon nitride layer and the silicon oxide layer can be continuously formed without being exposed to the atmosphere, adsorption of impurities such as hydrogen and moisture to the surface of the silicon nitride layer can be prevented.

Next, over the second insulating layer 105, an oxide semiconductor film with a thickness of 3 nm or more and 50 nm or less is formed. In order to sufficiently suppress the short channel effect, it is particularly preferable to form an oxide semiconductor film with a thickness of 3 nm or more and 20 nm or less.

As the oxide semiconductor film, an oxide semiconductor that has a large energy gap and is highly purified by sufficiently removing impurities such as hydrogen that serve as electron donors (donors) in the oxide semiconductor is used.

Also, the carrier concentration can be measured by Hall effect measurement. The carrier concentration of oxide semiconductors measured by Hall effect measurement is equivalent to the intrinsic carrier concentration of silicon, 1.45×10¹⁰/cm³is equal to or less than Note that the intrinsic carrier concentration of silicon is 10 using the Fermi-Dirac distribution at room temperature.¹⁰/cm³In contrast, the intrinsic carrier concentration of an oxide semiconductor with an energy gap of 3 eV or more is 10^-7/cm³is. That is, the intrinsic carrier concentration of an oxide semiconductor is extremely close to zero.

The carrier concentration of the oxide semiconductor layer 107 used in this embodiment is 1×10¹²/cm³less than, preferably 1 x 10¹¹/cm³is less than that, and the carrier concentration can be made infinitely close to zero.

In order to prevent the oxide semiconductor film from containing hydrogen, hydroxyl groups, and moisture as much as possible, the substrate 101 provided with the second insulating layer 105 is heated in a preheating chamber of a sputtering apparatus as pretreatment for film formation. Preheating is preferably performed to desorb impurities such as hydrogen and moisture adsorbed on the substrate 101 and to exhaust the substrate. A cryopump is preferably used as the evacuation means provided in the preheating chamber.

Note that this preheating process can be omitted.

Note that, before the oxide semiconductor film is formed by a sputtering method, reverse sputtering in which argon gas is introduced to generate plasma can be performed to remove dust attached to the surface of the second insulating layer 105 . preferable. Reverse sputtering is a method in which a voltage is applied to the substrate side using a high-frequency power supply in an argon atmosphere without applying a voltage to the target side, thereby forming plasma near the substrate and modifying the surface. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere.

An oxide semiconductor film is formed by a sputtering method. As the oxide semiconductor film, an In-Sn-Ga-Zn-O film which is a quaternary metal oxide, an In-Ga-Zn-O film which is a ternary metal oxide, or an In-Sn-Zn- O film, In-Al-Zn-O film, Sn-Ga-Zn-O film, Al-Ga-Zn-O film, Sn-Al-Zn-O film, In- Zn-O film, Sn-Zn-O film, Al-Zn-O film, Zn-Mg-O film, Sn-Mg-O film, In-Mg-O film, In- An oxide semiconductor film such as an O film, an SnO film, or a ZnO film can be used. In addition, SiO is added to the oxide semiconductor film.₂may include

In addition, the oxide semiconductor film is InMO₃(ZnO)_mA thin film represented by (m&gt;0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn and Co. For example, M includes Ga, Ga and Al, Ga and Mn, or Ga and Co.

In this embodiment, an oxide semiconductor film is formed by a sputtering method using an In--Ga--Zn--O-based oxide semiconductor deposition target. Alternatively, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen. Moreover, when using the sputtering method, SiO₂Film formation may be performed using a target containing 2% by weight or more and 10% by weight or less of

Examples of the In-Ga-Zn-O-based oxide semiconductor film-forming target include In, Ga, and Zn-containing oxide semiconductor film-forming targets (the composition ratio of In₂O₃: Ga₂O₃:ZnO=1:1:1 [molar ratio) etc. can also be used. In addition, as an oxide semiconductor deposition target containing In, Ga, and Zn, In₂O₃: Ga₂O₃:ZnO=1:1:2 [molar ratio], or In₂O₃: Ga₂O₃A target having a composition ratio of :ZnO=1:1:4 [molar ratio] can also be used. The filling rate of the oxide semiconductor deposition target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide semiconductor deposition target with a high filling rate, a dense oxide semiconductor film is formed.

The substrate is held in a treatment chamber which is kept in a reduced pressure state, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the treatment chamber is removed, and an oxide semiconductor film is formed over the substrate 101 using the above target. form a film. In order to remove residual moisture in the processing chamber, it is preferable to use an adsorption vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, the evacuation means may be a turbo pump with a cold trap added. A processing chamber evacuated using a cryopump can contain, for example, hydrogen atoms, water (H₂O) and other compounds containing hydrogen atoms (more preferably, compounds containing carbon atoms) are exhausted, so that the concentration of impurities contained in the oxide semiconductor film formed in the treatment chamber can be reduced. Further, the substrate may be heated during the formation of the oxide semiconductor film.

As an example of deposition conditions, the substrate temperature is room temperature, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the direct current (DC) power supply is 0.5 kW, and the atmosphere is oxygen and argon (oxygen flow rate: 15 sccm: argon flow rate: 30 sccm). The following conditions apply. Note that the use of a pulsed direct current (DC) power supply is preferable because powdery substances (also referred to as particles or dust) generated during film formation can be reduced and the film thickness distribution can be uniform.

Next, the oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 107 by a first photolithography step. Alternatively, a resist mask for forming the island-shaped oxide semiconductor layer 107 may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by an inkjet method, the manufacturing cost can be reduced.

Note that the etching of the oxide semiconductor film here may be dry etching, wet etching, or both.

As an etching gas used for dry etching, a chlorine-containing gas (a chlorine-based gas such as chlorine (Cl₂), boron trichloride (BCl₃), silicon tetrachloride (SiCl₄), carbon tetrachloride (CCl₄) etc.) are preferred.

In addition, gas containing fluorine (fluorine-based gas, such as carbon tetrafluoride (CF₄), sulfur hexafluoride (SF₆), nitrogen trifluoride (NF₃), trifluoromethane (CHF₃), hydrogen bromide (HBr), oxygen (O₂), or a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases.

As a dry etching method, a parallel plate RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used.

As an etchant used for wet etching, a mixed solution of phosphoric acid, acetic acid, and nitric acid can be used. Also, ITO07N (manufactured by Kanto Kagaku Co., Ltd.) may be used.

Also, the etchant after wet etching is removed by cleaning together with the etched material. The etchant effluent containing the removed material may be purified and the contained material may be reused. By recovering a material such as indium contained in the oxide semiconductor layer from the waste liquid after the etching and reusing it, resources can be effectively used and cost can be reduced.

Etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed into a desired processed shape.

In this embodiment, the oxide semiconductor film is processed into the island-shaped oxide semiconductor layer 107 by a wet etching method using a mixed solution of phosphoric acid, acetic acid, and nitric acid as an etchant.

In this embodiment, the oxide semiconductor layer 107 is subjected to first heat treatment. The temperature of the first heat treatment is 300° C. or higher and 800° C. or lower, preferably 400° C. or higher and 700° C. or lower. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer 107 at 450° C. for 1 hour in a nitrogen atmosphere. An oxide semiconductor layer is obtained by preventing entry of water or hydrogen into the oxide semiconductor layer. By this first heat treatment, the oxide semiconductor layer 107 can be dehydrated or dehydrogenated.

Note that the heat treatment apparatus is not limited to an electric furnace, and may be provided with a device that heats an object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be processed by heat treatment is used.

For example, as the first heat treatment, the substrate is moved into an inert gas heated to a high temperature of 650° C. to 700° C. and heated for several minutes. You can also do GRTA, which is out of the gas. Using GRTA enables high-temperature heat treatment in a short time.

Note that in the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon preferably does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen or rare gas such as helium, neon, argon, etc. to be introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

Alternatively, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film before being processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating device and the photolithography process is performed.

The heat treatment for dehydrating and dehydrogenating the oxide semiconductor layer is performed after the oxide semiconductor layer is formed, the source electrode layer and the drain electrode layer are stacked on the oxide semiconductor layer, and then the source electrode layer and the drain electrode layer are stacked on the oxide semiconductor layer. It may be performed either after providing a film to be a side wall on the drain electrode layer or after forming a gate insulating layer over the source electrode layer and the drain electrode layer.

However, if hydrogen and moisture are sufficiently reduced during film formation and a highly purified oxide semiconductor layer can be obtained, the first heat treatment is not particularly required. In order to obtain a highly purified oxide semiconductor layer in which hydrogen and moisture are sufficiently reduced during film formation, the substrate is held in a treatment chamber kept under reduced pressure, and the substrate is heated to room temperature or a temperature lower than 400°C. heat up. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the treatment chamber is removed, and an oxide semiconductor layer is formed over the substrate using a metal oxide as a target. A processing chamber evacuated using a cryopump can contain, for example, hydrogen atoms, water (H₂O) and other compounds containing hydrogen atoms (more preferably, compounds containing carbon atoms) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the treatment chamber can be reduced. By sputtering film formation while removing moisture remaining in the treatment chamber with a cryopump, the substrate temperature can be from room temperature to less than 400° C. when the oxide semiconductor layer is formed.

Next, a conductive film is formed over the second insulating layer 105 and the oxide semiconductor layer 107 . The conductive film may be formed by a sputtering method or a vacuum evaporation method. Examples of materials for the conductive film include elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, alloys containing the above-described elements, and alloy films in which the above-described elements are combined. Alternatively, a material selected from one or more of manganese, magnesium, zirconium, and beryllium may be used. Further, the metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure of stacking a titanium film over an aluminum film, a titanium film, a stack of an aluminum film over the titanium film, and a titanium film are stacked thereover. Examples include a three-layer structure that forms a film. In addition to Al, one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc) A thin film, an alloy film, or a nitride film may also be used. In this embodiment mode, a laminated film of a titanium film (thickness of 10 nm or more and 100 nm or less), an aluminum film (thickness of 20 nm or more and 500 nm or less), and a titanium film (thickness of 10 nm or more and 100 nm or less) is formed as the conductive film.

Next, a resist mask is formed over the conductive film by a second photolithography step, and selective etching is performed to form a source electrode layer 109a and a drain electrode layer 109b (FIG. 2A).

Note that each material and etching conditions are adjusted as appropriate so that the oxide semiconductor layer 107 is not removed and the underlying second insulating layer 105 is not exposed when the conductive film is etched.

In this embodiment, an In--Ga--Zn--O-based oxide is used for the oxide semiconductor layer 107, and an organic acid such as citric acid or oxalic acid, ITO07N (manufactured by Kanto Kagaku Co., Ltd.), or the like is used as an etchant. can be used.

Note that in the second photolithography step, part of the oxide semiconductor layer 107 is also etched to form an oxide semiconductor layer having grooves (depressions) in some cases. Alternatively, a resist mask for forming the source electrode layer 109a and the drain electrode layer 109b may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by an inkjet method, the manufacturing cost can be reduced.

Ultraviolet light, KrF laser light, or ArF laser light is used for exposure when forming a resist mask in the second photolithography process.

Next, an insulating layer 120 is formed over the oxide semiconductor layer 107, the source electrode layer 109a, and the drain electrode layer 109b (FIG. 2B).

As the insulating layer 120, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, a titanium oxide film, an aluminum oxide film, or the like can be formed by a sputtering method.

Next, most of the insulating layer 120 is removed by full-surface etching to form sidewalls 121 in contact with the top surface of the oxide semiconductor layer 107 on the side surfaces of the source electrode layer 109a and the drain electrode layer 109b (FIG. 2C). )). At this time, the insulating layer 120 is thicker at its lower end portion in contact with the oxide semiconductor layer 107 than in its plane portion in contact with the source electrode layer 109a and the drain electrode layer 109b, so that etching conditions are appropriately selected. By doing so, the side wall 121 having a desired shape can be left. As etching conditions, conditions are used that allow anisotropic etching in which reactive ions are perpendicularly incident on the substrate. Sidewalls 121 formed from an insulating layer provide insulating sidewalls.

Also, the sidewall 121 may be formed using a conductive material such as a metal material. Specifically, instead of the insulating layer 120, a metal film is formed over the source electrode layer 109a and the drain electrode layer 109b. The metal film can be formed by a sputtering method using a metal material such as a metal element such as titanium, aluminum, or tungsten, an alloy containing a metal element, or an alloy of a combination of metal elements.

Next, etching is performed to remove most of the metal film, so that sidewalls 121 of the source electrode layer 109a and the drain electrode layer 109b, which are in contact with the top surface of the oxide semiconductor layer 107, are formed. The sidewalls 121 formed using a conductive material serve as conductive sidewalls and are electrically connected to side surfaces of the source electrode layer 109a or the drain electrode layer 109b. In addition, each sidewall has its lower end in contact with the oxide semiconductor layer 107 for electrical connection.

Next, the gate insulating layer 117 is formed over the source electrode layer 109a, the drain electrode layer 109b, the sidewalls 121, and the oxide semiconductor layer 107. FIG.

The gate insulating layer 117 is formed by a single layer or a stack of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, a hafnium oxide layer, a tantalum oxide layer, or an aluminum oxide layer by a sputtering method or the like. can be formed by Note that the gate insulating layer 117 is preferably formed by a sputtering method so that the gate insulating layer 117 does not contain a large amount of hydrogen. When a silicon oxide film is formed by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

The gate insulating layer 117 can also have a structure in which a silicon oxide layer and a silicon nitride layer are stacked from the source electrode layer 109a and drain electrode layer 109b sides. For example, as the first gate insulating layer, a silicon oxide layer (SiO_x(x&gt;0)), and a silicon nitride layer (SiN layer) having a thickness of 50 nm or more and 200 nm or less is formed as a second gate insulating layer on the first gate insulating layer by a sputtering method._y(y&gt;0)) may be stacked to form a gate insulating layer with a thickness of 100 nm. In this embodiment, a silicon oxide layer having a thickness of 100 nm is formed by RF sputtering under an atmosphere of oxygen and argon (oxygen flow rate: 25 sccm:argon flow rate: 25 sccm=1:1) under a pressure of 0.4 Pa, a high-frequency power supply of 1.5 kW.

Next, after forming a conductive film over the gate insulating layer 117, a gate electrode layer 119 is formed by a third photolithography step. Note that the resist mask may be formed by an inkjet method. Since a photomask is not used when the resist mask is formed by an inkjet method, the manufacturing cost can be reduced.

In addition, the gate electrode layer 119 is made of a single layer or a stacked layer using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing these as main components. can be formed by

For example, the two-layer structure of the gate electrode layer 119 may be a two-layer structure in which a molybdenum layer is stacked over an aluminum layer, a two-layer structure in which a molybdenum layer is stacked over a copper layer, or a two-layer structure in which a molybdenum layer is stacked over a copper layer. A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated is preferable. A three-layer structure in which a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are stacked is preferable. Note that the gate electrode layer can also be formed using a light-transmitting conductive film. As the light-transmitting conductive film, a light-transmitting conductive oxide or the like can be given.

In this embodiment mode, a 150-nm-thick tungsten film is formed as the gate electrode layer 119 by a sputtering method.

Next, a second heat treatment (preferably 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In this embodiment mode, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. Alternatively, the second heat treatment may be performed after a protective insulating layer or a planarization insulating layer is formed over the transistor 200 .

Furthermore, heat treatment may be performed in the atmosphere at 100° C. or more and 200° C. or less for 1 hour or more and 30 hours or less. This heat treatment may be performed while maintaining a constant heating temperature, or by repeating the temperature increase from room temperature to a heating temperature of 100°C or more and 200°C or less and the temperature decrease from the heating temperature to room temperature multiple times. you can go Further, this heat treatment may be performed under reduced pressure before the oxide insulating layer is formed. When the heat treatment is performed under reduced pressure, the heating time can be shortened.

Through the above steps, the top-gate transistors 200 and 201 using oxide semiconductor layers, which have sidewalls in the source electrode layer and the drain electrode layer, have a short channel length L and can be miniaturized can be formed ( Figure 2(D)). Specifically, the channel length L can be 10 nm to 1 μm.

A protective insulating layer or a planarization insulating layer for planarization may be provided over the transistors 200 and 201 . For example, as the protective insulating layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed as a single layer or a stacked layer.

For the planarization insulating layer, a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (boron boron glass), and the like can be used. Note that the planarization insulating layer may be formed by stacking a plurality of insulating layers formed using any of these materials.

The method of forming the planarizing insulating layer is not particularly limited, and depending on the material, sputtering method, SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), A doctor knife, roll coater, curtain coater, knife coater and the like can be used.

Note that the siloxane-based resin corresponds to a resin including a SiOSi bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Moreover, the organic group may have a fluoro group.

In the transistors 200 and 201, when silicon nitride films are used for both the gate insulating layer 117 and the first insulating layer 103, the oxide semiconductor layer 107 can be sandwiched between the silicon nitride films above and below; It can effectively block the intrusion of moisture. With such a structure, the concentration of water and hydrogen contained in the oxide semiconductor layer 107 can be reduced to the lowest possible level so that they do not enter again.

Further, although the transistors 200 and 201 are described as single-gate transistors, multi-gate transistors having a plurality of channel formation regions can be formed as necessary.

As described above, by providing sidewalls to the source electrode layer and the drain electrode layer, a top-gate semiconductor element using an oxide semiconductor layer, which has a short channel length L and can be miniaturized, can be realized. In addition, the semiconductor element of one embodiment of the present invention has a short channel length L and can be miniaturized. can be reduced.

In addition, in the semiconductor element of one embodiment of the present invention, since the side surfaces of the source electrode layer and the drain electrode layer are tapered by the sidewalls, the coverage of the gate insulating layer is improved, and the gate electrode layer and the source electrode layer or the drain electrode are formed. A short circuit between layers can be prevented, and a highly reliable semiconductor element and a highly reliable semiconductor device using the semiconductor element can be realized.

Further, by using a highly purified oxide semiconductor layer which has a large energy gap and whose hydrogen concentration is sufficiently reduced by removing impurities such as hydrogen and moisture, a normally-off semiconductor with low off-state current is used. Elements can be made. By using the semiconductor element, a semiconductor device with low power consumption due to leakage current can be realized.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment Mode 3) In this embodiment mode, a method for manufacturing a transistor which is different from that in the above embodiment mode will be described with reference to drawings. Note that the manufacturing steps (applicable materials, etc.) shown in this embodiment are in common with those in the above-described second embodiment in many respects. Therefore, in the following description, overlapping descriptions will be omitted, and different points will be described in detail.

A transistor 300 illustrated in FIG. 28B includes a first insulating layer 303, a second insulating layer 305, an oxide semiconductor layer 307, a first source electrode layer 309a, and a second insulating layer over a substrate 301 having an insulating surface. source electrode layer 311a, first drain electrode layer 309b, second drain electrode layer 311b, third insulating layer 315, sidewalls 321, gate insulating layer 317, and gate electrode layer 319;

An example of a method for manufacturing the transistor 300 illustrated in FIG. 28B will be described with reference to FIGS.

First, a first insulating layer 303 is formed on a substrate 301 having an insulating surface. A second insulating layer 305 is then formed on the first insulating layer 303 . Next, on the second insulating layer 305, an oxide semiconductor film having a thickness of 3 nm or more and 50 nm or less, preferably 3 nm or more and 30 nm or less is formed, and an island-shaped oxide semiconductor layer 307 is formed by a first photolithography process. processed into

In this embodiment, the oxide semiconductor layer 307 is subjected to first heat treatment.

Next, a first conductive film 306 and a second conductive film 308 are formed over the second insulating layer 305 and the oxide semiconductor layer 307 . The first conductive film 306 and the second conductive film 308 can be formed using the same material as the source electrode layer 109a and the drain electrode layer 109b described in Embodiment 2 to have a single layer or a stacked layer.

In this embodiment, a laminated film is formed by laminating a tungsten film (10 nm or more and 100 nm or less in thickness) on a titanium film (10 nm or more and 100 nm or less in thickness) as the first conductive film 306 , and the second conductive film 308 is formed. Then, a laminated film is formed by laminating a titanium film (thickness of 10 nm or more and 100 nm or less) on an aluminum film (thickness of 20 nm or more and 500 nm or less). When a material through which a substance that contaminates an oxide semiconductor (specifically, hydrogen or the like) does not easily permeate, the first conductive film 306 functions as a barrier film. For example, if a tungsten film through which hydrogen hardly permeates is used as the first conductive film 306, the second conductive film 308 is formed using a film formation method (specifically, a CVD method) that can contaminate the oxide semiconductor layer 307. And an insulating layer 320 that serves as sidewalls can be formed.

Next, by using a plasma CVD method, a sputtering method, or the like, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer is formed in a single layer or stacked to form a film thickness on the second conductive film 308 . An insulating layer 310 with a thickness of 200 nm or more and 2000 nm or less is formed (FIG. 3(A)). As the insulating layer, a heat-resistant organic material such as polyimide, acryl, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), and the like may be used.

The method for forming the insulating layer is not particularly limited, and depending on the material, sputtering method, SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, A roll coater, curtain coater, knife coater, or the like can also be used.

Next, a resist mask is formed over the insulating layer 310 by a second photolithography process, and selective etching is performed to form a second source electrode layer 311a, a second drain electrode layer 311b, and a third insulating layer 315. form (Fig. 3(B)).

The third insulating layer 315 is provided to reduce parasitic capacitance formed between the gate electrode layer 319, which is formed later, and the second source electrode layer 311a or the second drain electrode layer 311b. there is On the other hand, in order to taper the second source electrode layer 311a and the second drain electrode layer 311b by providing the third insulating layer 315, the third insulating layer 315 and the second source electrode layer It is necessary to adjust the etching conditions such as the selection ratio of the second drain electrode layer 311a and the second drain electrode layer 311b, which makes the processing by etching difficult. Unless the second source electrode layer 311a and the second drain electrode layer 311b are tapered, a problem arises in that the coverage of the gate insulating layer 317 stacked thereover is reduced. However, in the transistor of one embodiment of the present invention, the sidewalls 321 taper the sides of the second source electrode layer 311a and the second drain electrode layer 311b, so that the second source electrode layer 311a and the second drain electrode layer 311a There is no need to taper the end of the electrode layer 311b, which facilitates fabrication of the transistor.

Next, an insulating layer 320 is formed over the first conductive film 306, the second source electrode layer 311a, the second drain electrode layer 311b, and the third insulating layer 315 (FIG. 3C).

As the insulating layer 320, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, a titanium oxide film, an aluminum oxide film, or the like can be formed by a sputtering method. Also, in addition to the insulating layer 320, a metal film may be used. In addition, when a material that does not easily transmit a substance that contaminates an oxide semiconductor (specifically, hydrogen or the like) is used for the first conductive film 306, the insulating layer 320 may be formed using a CVD method. It is preferable to form the insulating layer 320 to be the sidewalls by a CVD method because the insulating layer 320 can be formed with a uniform thickness.

Then, blanket etching is used to remove most of the insulating layer 320 to form sidewalls 321 on the sides of the second source electrode layer 311a or the second drain electrode layer 311b. At this time, the lower end of the side wall 321 is in contact with the upper surface of the first conductive film 306 (FIG. 3(D)). At this time, the insulating layer 320 is thicker at the lower end in contact with the first conductive film 306 than in the planar portion in contact with the third insulating layer 315, so the etching conditions should be appropriately selected. , the sidewalls 321 can be left in the desired shape. As etching conditions, conditions are used that allow anisotropic etching in which reactive ions are perpendicularly incident on the substrate. Moreover, the side walls 321 may be in contact with the side surfaces of the third insulating layer 315 as well.

Next, using the third insulating layer 315 and the sidewalls 321 as a hard mask, the first conductive film 306 is etched to form a first source electrode layer 309a and a first drain electrode layer 309b ( Figure 3 (E)). The channel length L can be shortened by etching using the sidewall 321 as a mask.

Next, a gate insulating layer 317 is formed over the third insulating layer 315, the sidewalls 321, the first source electrode layer 309a, the first drain electrode layer 309b, and the oxide semiconductor layer 307. FIG. Next, after forming a conductive film over the gate insulating layer 317, a gate electrode layer 319 is formed by a third photolithography step.

Next, a second heat treatment (preferably 200° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. Through the above steps, the transistor 300 in which the source electrode layer and the drain electrode layer have sidewalls can be formed (FIG. 3F).

As described above, the semiconductor element of one embodiment of the present invention is a top-gate semiconductor element using an oxide semiconductor layer, which has a short channel length L and can be miniaturized by providing sidewalls to the source electrode layer and the drain electrode layer. can be realized.

In addition, the semiconductor element of one embodiment of the present invention has a short channel length L and can be miniaturized. Power can be reduced.

In addition, in the semiconductor element of one embodiment of the present invention, since the side surfaces of the source electrode layer and the drain electrode layer are tapered by the sidewalls, the coverage of the gate insulating layer is improved, and the gate electrode layer and the source electrode layer or the drain electrode are formed. A short circuit between layers can be prevented, and a highly reliable semiconductor element and a highly reliable semiconductor device using the semiconductor element can be realized.

In addition, the semiconductor element of one embodiment of the present invention uses a highly purified oxide semiconductor layer which has a large energy gap and whose hydrogen concentration is sufficiently reduced by removing impurities such as hydrogen and moisture. A normally-off semiconductor device with a small current can be produced. By using the semiconductor element, a semiconductor device with low power consumption due to leakage current can be realized.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 4) In this embodiment, an example of configuring an inverter circuit of an integrated circuit using two n-channel transistors will be described below. Note that since the steps for manufacturing a transistor are almost the same as those in Embodiment 2, only different points will be described in detail.

Also, since an integrated circuit is configured using an inverter circuit, a capacitor, a resistor, etc., a process of forming a capacitor and two types of resistors on the same substrate in addition to the inverter circuit will also be described.

When two n-channel transistors are combined to form an inverter circuit, there are an EDMOS circuit formed by combining an enhancement type transistor and a depletion type transistor and an EEMOS circuit formed by enhancement type transistors.

This embodiment shows an example of an EDMOS circuit. Figure 4 shows an equivalent circuit of an EDMOS circuit. A cross-sectional structure of the inverter circuit is shown in FIG. 5(B).

The circuit connection shown in FIG. 5B corresponds to FIG. 4, and is an example in which the first transistor 400 is an enhancement n-channel transistor and the second transistor 401 is a depletion n-channel transistor. .

In FIG. 5B, the substrate 411 has electrode layers 412b, 412c, 412d, and 412e. The electrode layers 412b, 412c, 412d, and 412e can be formed using the same process and the same materials as the electrode layers 102 of the second embodiment.

A voltage is applied to the electrode layer 412b so that the threshold voltage is negative, so that the electrode layer 412b functions as a depletion transistor. Further, the electrode layer 412c is one electrode forming a capacitor. Further, the electrode layer 412d is one electrode connected to the first resistor. Also, the electrode layer 412e is one electrode connected to the second resistor.

A first insulating layer 413 and a second insulating layer 415 are formed to cover the electrode layers 412b, 412c, 412d, and 412e. In the capacitor portion, the first insulating layer 413 overlapping with the electrode layer 412c and the second insulating layer 415 overlapping with the electrode layer 412c are dielectrics.

Alternatively, the thickness of the second oxide semiconductor layer 417b may be larger than that of the first oxide semiconductor layer 417a. In order to make the second oxide semiconductor layer 417b thicker than the first oxide semiconductor layer 417a, film formation and patterning are performed twice. By increasing the thickness of the second oxide semiconductor layer 417b, it can function as a depletion transistor, and there is no need to apply a voltage for making the threshold voltage negative to the electrode layer 412b. Layer 412b may also be omitted.

The third oxide semiconductor layer 417c functions as a first resistor. Openings are formed in the first insulating layer 413 and the second insulating layer 415 overlapping with the electrode layer 412d, and the third oxide semiconductor layer 417c and the electrode layer 412d are electrically connected through the openings. Connected. Further, the fourth oxide semiconductor layer 417d functions as a second resistor. Openings are formed in the first insulating layer 413 and the second insulating layer 415 overlapping with the electrode layer 412e, and the fourth oxide semiconductor layer 417d and the electrode layer 412e are electrically connected through the openings. Connected.

Alternatively, the thickness of the fourth oxide semiconductor layer 417d may be larger than the thickness of the third oxide semiconductor layer 417c. By setting the third oxide semiconductor layer 417c and the fourth oxide semiconductor layer 417d to have different thicknesses, the first resistor and the second resistor can have different resistance values.

The first transistor 400 includes a first gate electrode layer 419a and a first oxide semiconductor layer 417a overlapping with the first gate electrode layer 419a with the gate insulating layer 427 provided therebetween. A first electrode layer 422a in contact with part of the semiconductor layer 417a is electrically connected to a first wiring 429a. The first wiring 429a is a power line (negative power line) to which a negative voltage VDL is applied. This power line may be a ground potential power line (ground power line).

In the present embodiment, the first electrode layer 422a is composed of three layers and is made of the same material as the source electrode layer 109a and the drain electrode layer 109b of the second embodiment. In this embodiment, after the conductive film is patterned, an insulating layer is formed (FIG. 5A), and the conductive layer and the insulating layer are selectively etched to form the first electrode layer 422a, the first electrode layer 422a, and the second electrode layer 422a. A second electrode layer 422b, a third electrode layer 422c, and a third insulating layer 416 are formed. (Figure 5(B)). The third insulating layer 416 is provided to reduce parasitic capacitance formed between the second gate electrode layer 419b and the second electrode layer 422b which are formed later.

In addition, in the capacitor portion, a fourth electrode layer 422d, which is a capacitor electrode layer, is formed in the same process and with the same material as the first electrode layer 422a. The fourth electrode layer 422d overlaps the electrode layer 412c.

In addition, the fifth electrode layer 422e is formed in the same process and with the same material as the first electrode layer 422a so as to be in contact with the fourth oxide semiconductor layer 417d, which is the second resistor.

The first transistor 400 also has sidewalls 421 of the first electrode layer 422a and the second electrode layer 422b. A lower end portion of the sidewall 421 is in contact with the top surface of the first oxide semiconductor layer 417a. Similarly, the second transistor 401 has sidewalls 431 of the second electrode layer 422b and the third electrode layer 422c. A lower end portion of the sidewall 431 is in contact with the top surface of the second oxide semiconductor layer 417b. By providing sidewalls, a fine transistor with a short channel length L can be manufactured, so that the operation speed of the circuit can be increased and power consumption can be reduced.

In addition, the second transistor 401 includes a second gate electrode layer 419b functioning as a second wiring and a second oxide semiconductor layer 417b overlapping with the second gate electrode layer 419b with the gate insulating layer 427 provided therebetween. A third wiring 429b is a power supply line (positive power supply line) to which a positive voltage VDH is applied.

In addition, the second transistor 401 includes a second electrode layer 422b and a third electrode layer 422c that partially contact and overlap with the second oxide semiconductor layer 417b. Note that the second electrode layer 422b and the third electrode layer 422c are formed in the same step and with the same material as the first electrode layer 422a.

In addition, the third insulating layer 416 and the gate insulating layer 427 are provided with openings reaching the second electrode layer 422b, and the second electrode layer 422b and the second gate electrode layer 419b functioning as a second wiring. They are electrically connected to connect the first transistor 400 and the second transistor 401 to form an EDMOS circuit.

A fourth wiring 429c having openings in the third insulating layer 416 and the gate insulating layer 427 in regions overlapping with the electrode layer 412c and connected to the fourth electrode layer 422d functions as a capacitor wiring.

In addition, the fifth wiring 429d has openings in the third insulating layer 416 and the gate insulating layer 427 in regions overlapping with the electrode layer 412d, and is in contact with the third oxide semiconductor layer 417c functioning as the first resistor. .

In the present embodiment, an example is shown in which an EDMOS circuit, a capacitor, a first resistor, and a second resistor are formed on the same substrate using the transistor of the second embodiment. There is no particular limitation, and the transistor of Embodiment 3 can also be formed over the same substrate.

FIG. 6A shows a cross-sectional structure of a terminal portion of a wiring that can be formed over the same substrate in this embodiment mode. FIG. 6(A) corresponds to a cross-sectional view taken along line C1-C2 in FIG. 6(B).

In FIG. 6A, a conductive layer 439 formed over a stack of the third insulating layer 416 and the gate insulating layer 427 is a terminal electrode for connection functioning as an input terminal. In FIG. 6A, in the terminal portion, an electrode layer 412f formed of the same material as the electrode layers 412b, 412c, 412d, and 412e is a terminal electrode layer electrically connected to the first electrode layer 422a. The first insulating layer 413 and the second insulating layer 415 are interposed below the sixth electrode layer 422f. The electrode layer 412f is not electrically connected to the sixth electrode layer 422f, and if the electrode layer 412f is set to a potential different from that of the sixth electrode layer 422f, such as floating, GND, or 0V, noise countermeasures can be taken. A capacitor for protection against static electricity or a capacitor for countermeasures against static electricity can be formed. Also, the sixth electrode layer 422f is electrically connected to the conductive layer 439 with the third insulating layer 416 and the gate insulating layer 427 interposed therebetween.

The sixth electrode layer 422f can be formed using the same material and in the same process as the first electrode layer 422a. The conductive layer 439 can be formed using the same material and the same steps as the first gate electrode layer 419a and the second gate electrode layer 419b.

This embodiment can be freely combined with other embodiments.

(Embodiment 5) In this embodiment, an example of fabricating a CPU (central processing circuit) using the EDMOS circuit shown in Embodiment 4 will be shown.

An example of a block diagram of a CPU is shown in FIG. A CPU 1001 shown in FIG. 18 comprises a timing control circuit 1002, an instruction analysis decoder 1003, a register array 1004, an address logic buffer circuit 1005, a data bus interface 1006, an ALU 1007, an instruction register 1008 and the like.

These circuits are manufactured using the transistors, inverter circuits, resistors, capacitors, and the like described in Embodiments 1 to 4. FIG. Since the transistors described in Embodiments 1 to 4 use an oxide semiconductor layer with a large energy gap and sufficiently low hydrogen concentration, the off-state current is extremely small and the transistor is normally off. It can be a transistor. In addition, since the transistors described in Embodiments 1 to 4 have sidewalls on the source electrode layer and the drain electrode layer, the channel length L is short and miniaturization is possible, and the operation speed of the circuit is increased. can be Therefore, by using the transistor of one embodiment of the present invention for at least part of the CPU 1001, low power consumption can be achieved.

Here, each circuit will be briefly described. The timing control circuit 1002 receives commands from the outside, converts them into information for internal use, and sends the information to other blocks.

In addition, according to the internal operation, instructions such as reading and writing of memory data are given to the outside. The instruction analysis decoder 1003 has the role of converting external instructions into internal instructions. Register array 1004 is a volatile memory that temporarily stores data. The address logic buffer circuit 1005 is a circuit that specifies the address of the external memory. A data bus interface 1006 is a circuit for transferring data to and from devices such as an external memory or printer. ALU 1007 is a circuit that performs arithmetic operations. The instruction register 1008 is a circuit that temporarily stores instructions. A CPU is made up of a combination of such circuits.

This embodiment can be freely combined with other embodiments.

Embodiment Mode 6 In this embodiment mode, an example of usage of the semiconductor device shown in the above embodiment mode will be described. Specifically, application examples of a semiconductor device capable of inputting and outputting data without contact are described below with reference to drawings. A semiconductor device capable of inputting/outputting data without contact is also called an RFID tag, an ID tag, an IC tag, an RF tag, a wireless tag, an electronic tag, or a wireless chip, depending on the mode of use.

An example of the top structure of the semiconductor device shown in this embodiment will be described with reference to FIG.

The semiconductor device shown in FIG. 21A includes a semiconductor integrated circuit chip 500 provided with an antenna (also referred to as an on-chip antenna) and a support substrate 506 provided with an antenna 505 (also referred to as a booster antenna). . Semiconductor integrated circuit chip 500 is provided on insulating layer 510 formed on support substrate 506 and antenna 505 . The insulating layer 510 can fix the semiconductor integrated circuit chip 500 on the support substrate 506 and the antenna 505 . FIG. 21B corresponds to a perspective view of a semiconductor device in which the semiconductor integrated circuit chip 500 and the antenna 505 formed over the supporting substrate 506 shown in FIG. 21A are stacked. FIG. 21(C) corresponds to a cross-sectional view taken along broken line XY in FIG. 21(B).

A conductive shield is provided on the surface of the semiconductor integrated circuit chip 500 in order to prevent electrostatic breakdown (circuit malfunction and semiconductor element damage) due to electrostatic discharge. When the patterns of antenna 505 are not electrically connected, antenna 505 and a conductive shield provided on the surface of semiconductor integrated circuit chip 500 may be provided in contact with each other.

A semiconductor integrated circuit provided in the semiconductor integrated circuit chip 500 is provided with elements such as a plurality of transistors that constitute a memory section and a logic section. A transistor of one embodiment of the present invention is used as a transistor included in a memory portion or a logic portion. The semiconductor device according to the present embodiment can be applied not only to a field effect transistor but also to a memory element using a semiconductor layer as a semiconductor element. can provide.

FIG. 20(A) shows an enlarged view of an antenna and a semiconductor integrated circuit included in the semiconductor integrated circuit chip 500 shown in FIG. 21(A). In FIG. 20A, antenna 501 is a rectangular loop antenna with one turn, but is not limited to this configuration. The shape of the loop antenna is not limited to having a rectangular shape, but may have a curved shape, such as a circular shape.

The number of turns is not limited to one, and may be plural. However, when the number of turns of the antenna 501 is 1, the parasitic capacitance generated between the semiconductor integrated circuit 503 and the antenna 501 can be reduced.

20(A) and 21(C), the antenna 501 is arranged so as to surround the semiconductor integrated circuit 503, and the antenna 501 except for the part corresponding to the feeding point 508 indicated by the dashed line is It is arranged in a region different from the semiconductor integrated circuit 503 . Moreover, the configuration is not limited to this, and as shown in FIG. Also good. However, as shown in FIGS. 20A and 21C, since the antenna 501 is arranged in a region different from the semiconductor integrated circuit 503, the parasitic capacitance generated between the semiconductor integrated circuit 503 and the antenna 501 can be reduced.

In FIG. 21A, the antenna 505 can exchange signals or supply power with the antenna 501 mainly in the loop-shaped portion surrounded by the dashed line 507 by electromagnetic induction. Further, the antenna 505 can mainly transmit/receive signals to/from the interrogator or supply electric power by radio waves in a region other than the portion surrounded by the dashed line 507 . The frequency of radio waves used as carriers between the interrogator and the semiconductor device is preferably about 30 MHz or more and 5 GHz or less. For example, frequency bands such as 950 MHz and 2.45 GHz may be used.

Further, the antenna 505 has a rectangular loop shape with one turn in the portion surrounded by the dashed line 507, but the configuration is not limited to this. The looped portion is not limited to having a rectangular shape, but may have a curved shape, such as a circular shape. The number of turns is not limited to one, and may be plural.

An electromagnetic induction method, an electromagnetic coupling method, or a microwave method can also be applied to the semiconductor device described in this embodiment. In the case of the microwave system, the shapes of the antennas 501 and 505 may be appropriately determined according to the wavelength of the electromagnetic wave to be used.

For example, when a microwave system (e.g., UHF band (860MHz to 960MHz band), 2.45GHz band, etc.) is applied as a signal transmission system in a semiconductor device, the wavelength of electromagnetic waves used for signal transmission should be considered. The length, shape, etc. of the antenna may be set as appropriate. For example, the antenna can be formed in a linear shape (eg, a dipole antenna), a flat shape (eg, a patch antenna or ribbon shape), and the like. Further, the shape of the antenna is not limited to a linear shape, and it may be provided in a curved shape, meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

FIG. 22 shows an example in which an antenna 501 and an antenna 505 are provided in a coil shape and an electromagnetic induction method or an electromagnetic coupling method is applied.

In FIG. 22, a semiconductor integrated circuit chip 500 provided with a coiled antenna 501 is provided on a support substrate 506 provided with a coiled antenna 505 as a booster antenna.

Next, the structure and arrangement of the semiconductor integrated circuit chip 500 and the booster antenna will be described. A semiconductor device using the transistor of one embodiment of the present invention can be used as a semiconductor integrated circuit chip 500 illustrated in FIG. .

A semiconductor integrated circuit 503 shown in FIG. 21C is sandwiched between a first insulator 512 and a second insulator 502, and its side surfaces are also sealed. In the present embodiment, after sandwiching a plurality of semiconductor integrated circuits and bonding a first insulator and a second insulator together, the semiconductor integrated circuits are separated into laminated bodies for each individual semiconductor integrated circuit. A semiconductor integrated circuit chip 500 is manufactured by forming a conductive shield on the divided laminate. The dividing means is not particularly limited as long as it can be physically divided, but in this embodiment mode, the division is performed by laser light irradiation.

In FIG. 21C, the semiconductor integrated circuit 503 is arranged closer to the antenna 505 than to the antenna 501; however, the structure is not limited to this. Antenna 501 may be placed closer to antenna 505 than semiconductor integrated circuit 503 . Moreover, the semiconductor integrated circuit 503 and the antenna 501 may be directly fixed to the first insulator 512 and the second insulator 502, or may be fixed by an adhesive layer functioning as an adhesive.

Next, the operation of the semiconductor device according to this embodiment will be described. FIG. 19 is an example of a block diagram showing a configuration of a semiconductor device according to this embodiment. A semiconductor device 520 shown in FIG. 19 has a booster antenna 522 , a semiconductor integrated circuit 523 , and an on-chip antenna 524 . When an electromagnetic wave is transmitted from the interrogator 521 , the booster antenna 522 receives the electromagnetic wave, generating an alternating current in the booster antenna 522 and generating a magnetic field around the booster antenna 522 . Electromagnetic coupling between the loop-shaped portion of booster antenna 522 and loop-shaped on-chip antenna 524 causes induced electromotive force in on-chip antenna 524 . The semiconductor integrated circuit 523 receives a signal or power from the interrogator 521 by using the induced electromotive force. Conversely, according to the signal generated in the semiconductor integrated circuit 523, current is passed through the on-chip antenna 524 to generate an induced electromotive force in the booster antenna 522. , can send a signal to the interrogator 521 .

The booster antenna 522 is mainly divided into a loop-shaped portion that is electromagnetically coupled with the on-chip antenna 524 and a portion that mainly receives radio waves from the interrogator 521 . The shape of the booster antenna 522 in the portion that mainly receives the radio wave from the interrogator 521 may be any shape as long as it can receive the radio wave. For example, a dipole antenna, a folded dipole antenna, a slot antenna, a meander line antenna, a microstrip antenna, or the like may be used.

Further, although FIG. 21 describes the configuration of the semiconductor integrated circuit having only one antenna, the present invention is not limited to this configuration. It may have two antennas, one for receiving power and one for receiving signals. Having two antennas allows you to use different frequencies for the radio waves that supply power and for sending signals.

In the semiconductor device according to this embodiment, an on-chip antenna is used, and signals or power can be transmitted and received between the booster antenna and the on-chip antenna without contact. Unlike the case of connecting to an integrated circuit, the connection between the semiconductor integrated circuit and the antenna is less likely to be broken by an external force, and the occurrence of initial failures in the connection can be suppressed. In addition, since the booster antenna is used in this embodiment, unlike the case where only the on-chip antenna is used, the size or shape of the on-chip antenna is less likely to be restricted by the area of the semiconductor integrated circuit, and the frequency band of the radio waves that can be received is reduced. is not limited, and it is possible to enjoy the advantage of an external antenna that the communication distance can be extended.

A semiconductor integrated circuit can also be formed directly on a flexible substrate. Alternatively, a semiconductor integrated circuit may be transferred from a manufacturing substrate (eg, a glass substrate) to another substrate (eg, a plastic substrate).

In the case of transferring a semiconductor integrated circuit from a manufacturing substrate to another substrate, various methods can be used without particular limitation. For example, a separation layer may be formed between the manufacturing substrate and the semiconductor integrated circuit.

For example, when a metal oxide film is formed as the separation layer, the metal oxide film is weakened by crystallization, so that the element layer including the semiconductor integrated circuit, which is the layer to be separated, can be separated from the formation substrate. In addition, after weakening the metal oxide film by crystallization, part of the peeling layer is further removed with a solution or NF.₃, BrF₃, ClF₃It may be removed by etching with a halogen fluoride gas such as a fluorohalogen gas, and the weakened metal oxide film may be peeled off.

A film containing nitrogen, oxygen, hydrogen, or the like (for example, an amorphous silicon film containing hydrogen, a hydrogen-containing alloy film, an oxygen-containing alloy film, or the like) is used as the separation layer, and a light-transmitting substrate is used as the formation substrate. When used, a method of irradiating the separation layer from the production substrate with laser light to vaporize nitrogen, oxygen, or hydrogen contained in the separation layer and separating the separation layer from the production substrate is used. can be done.

Alternatively, the layer to be separated may be separated from the formation substrate by removing the separation layer by etching.

In addition, a method of mechanically polishing and removing the production substrate, and a method of removing the production substrate by NF₃, BrF₃, ClF₃A method of removing by etching with a halogen fluoride gas such as HF or the like can be used. In this case, the release layer may not be used.

In addition, a groove that exposes the separation layer is formed by laser light irradiation, etching with a gas or solution, or a sharp knife or scalpel, and the layer to be separated is separated from the separation layer from the substrate using the groove as a trigger. You can also

As a peeling method, for example, applying a mechanical force (such as a process of peeling off with a human hand or a gripping tool, a process of separating while rotating a roller, etc.) may be used. Alternatively, the layer to be peeled may be peeled off from the peeling layer by dripping a liquid into the groove and permeating the interface with the peeling layer. Also, NF in the groove₃, BrF₃, ClF₃A method may be used in which a fluorinated gas such as a fluorinated gas is introduced, the separation layer is removed by etching with the fluorinated gas, and the layer to be separated is separated from the production substrate. Alternatively, the peeling may be performed while spraying a liquid such as water.

As another peeling method, when the peeling layer is formed of tungsten, the peeling can be performed while etching the peeling layer with a mixed solution of ammonia water and hydrogen peroxide solution.

As described above, a semiconductor device can be manufactured using the transistor of one embodiment of the present invention. Since the transistor of one embodiment of the present invention has a short channel length L and can be miniaturized, the operation speed of the circuit can be increased and the power consumption of the semiconductor device can be reduced.

This embodiment can be freely combined with other embodiments.

(Embodiment 7) In the present embodiment, application examples of a semiconductor device capable of non-contact data input/output formed using the device of the above-described Embodiment 6 will be described below with reference to the drawings. explain. A semiconductor device capable of non-contact data input/output is also called an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip, depending on the mode of use.

The semiconductor device 800 has a function of communicating data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. It has a control circuit 870, a memory circuit 880, and an antenna 890 (see FIG. 23A). The high frequency circuit 810 is a circuit that receives a signal from the antenna 890 and outputs the signal received from the data modulation circuit 860 from the antenna 890. The power supply circuit 820 is a circuit that generates a power supply potential from the received signal. is a circuit for generating a reset signal, the clock generation circuit 840 is a circuit for generating various clock signals based on the reception signal input from the antenna 890, and the data demodulation circuit 850 demodulates the reception signal to control circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870 . Also, as the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit for extracting a plurality of codes included in the command sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with the code corresponding to the reference. It is a circuit for judging the content of the command, and the CRC judging circuit 930 is a circuit for detecting the presence or absence of a transmission error or the like based on the judged code.

Next, an example of the operation of the semiconductor device described above will be described. First, a radio signal is received by antenna 890 . The radio signal is sent to the power supply circuit 820 via the high frequency circuit 810 to generate a high power supply potential (hereinafter referred to as VDD). VDD is supplied to each circuit that the semiconductor device 800 has. Also, the signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter referred to as demodulated signal). Furthermore, the signal and demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870 . The signal sent to control circuit 870 is analyzed by code extraction circuit 910, code determination circuit 920, CRC determination circuit 930, and the like. Information on the semiconductor device stored in the storage circuit 880 is output according to the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940 . Furthermore, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890 . Note that a plurality of circuits forming the semiconductor device 800 share a low power supply potential (hereinafter referred to as VSS), and VSS can be GND.

Thus, by sending a signal from the communication device to the semiconductor device 800 and receiving the signal sent from the semiconductor device 800 by the communication device, data in the semiconductor device can be read.

In addition, the semiconductor device 800 may be of a type in which a power source (battery) is not mounted and electromagnetic waves are used to supply the power supply voltage to each circuit, or a power source (battery) is mounted and each circuit is supplied with electromagnetic waves and a power source (battery). A type that supplies a power supply voltage to the circuit may be used.

Next, an example of a mode of use of a semiconductor device capable of inputting/outputting data without contact will be described.

A communication device 3200 is provided on the side of the mobile terminal including the display portion 3210, and a semiconductor device 3230 is provided on the side of the article 3220 (FIG. 23(B)). When the communication device 3200 is held over the semiconductor device 3230 included in the product 3220, the display unit 3210 displays information about the product, such as raw materials and country of origin of the product, inspection results for each production process, history of the distribution process, and product description. be. Further, when the product 3260 is conveyed by the belt conveyor, the product 3260 can be inspected using the communication device 3240 and the semiconductor device 3250 provided on the product 3260 (FIG. 23(C)). In this way, by utilizing a semiconductor device in a system, information can be easily obtained, and high functionality and high added value can be realized.

As described above, the application range of semiconductor devices is extremely wide, and they can be used in electronic devices in a wide range of fields.

(Embodiment 8) This embodiment shows an example of a memory circuit that can be configured using the transistors shown in Embodiments 1 to 4. FIG.

FIG. 24A shows a block diagram of an example of a memory circuit. The memory circuit shown in FIG. 24A has a row decoder, a write circuit and refresh circuit, a column decoder, and memory elements 1100 arranged in matrix, and is connected to the memory elements 1100 arranged in matrix. The signal lines connected to the row decoders are connected to the row decoders through write circuits and refresh circuits, and the scanning lines connected to the memory elements 1100 arranged in a matrix are connected to the column decoders. A bit signal is input to the row decoder. A write enable signal/write enable signal (RE/WE) and a data signal (data) are input to the write circuit and the refresh circuit, and an output signal (OUT) is output.

Each memory element 1100 has a capacitor and a transistor, one of the source and the drain of the transistor is connected to a signal line, the other of the source and the drain of the transistor is connected to one electrode of the capacitor, and the capacitor The other electrode of the element is connected to the low potential side (preferably, reference potential Vss).

FIG. 24B shows a specific configuration example of a refresh circuit provided in the write circuit and refresh circuit shown in FIG. 24A.

The write circuit and refresh circuit shown in FIG. 24B have a logical product circuit (AND circuit) and a sense amplifier. A signal from the row decoder is input to one input of the first AND circuit 1101, the second AND circuit 1102, and the third AND circuit 1103. FIG. The other input of the first AND circuit 1101 receives the PRC signal, the other input of the second AND circuit 1102 receives the write enable signal (WE), and the third AND circuit 1103 receives the write enable signal (WE). A read enable signal (RE) is input to the other input. The output of the first AND circuit 1101 controls on/off of the first switch 1104, the output of the second AND circuit 1102 controls on/off of the second switch 1105, and the output of the third AND circuit 1103 controls ON/OFF of third switch 1106 . The precharge signal line Vprc is connected to the signal line via the first switch 1104, and the data signal line data is connected to the signal line via the second switch 1105. FIG.

A signal line connected through the first switch 1104 and the second switch 1105 is connected through the third switch 1106 to the sense amplifier. A signal is output from the sense amplifier to an output signal line (OUT).

Note that the logical product circuit described above may have a general configuration, and preferably has a simple configuration.

Note that a sense amplifier is a circuit having a function of amplifying an input signal.

As the signal here, for example, an analog signal or a digital signal using voltage, current, resistance, frequency, or the like can be used. For example, the potential is set with at least a first potential and a second potential, and the first potential is a high level (high potential, V_H.Also notated. ) potential, and a low level (low potential, V_L.Also notated. ), a binary digital signal can be set. Also, V_H.and V_L.is preferably a constant value, but considering the effect of noise, V_H.and V_L.You can have some width.

As described above, a memory circuit can be manufactured using the transistors and capacitors described in the above embodiments.

The refresh timing of the memory circuit is determined at the design stage at certain fixed time intervals based on pre-evaluated leakage currents of the storage elements. That is, it is set in consideration of the temperature dependence of the leak current after the chip is completed and the variation of the manufacturing process.

Since the transistor of one embodiment of the present invention has sidewalls in the source electrode layer and the drain electrode layer, the transistor can be a miniaturized transistor with a short channel length L. By forming a circuit using the transistor, low power consumption can be achieved and the operation of the memory circuit can be stabilized.

Since the transistor of one embodiment of the present invention includes an oxide semiconductor layer with a large energy gap and a sufficiently low hydrogen concentration, the off-state current of the transistor can be extremely small, and the temperature is -30°C. The temperature characteristics of the off-state current from 120°C to 120°C hardly change and can be maintained at an extremely small value, making it possible to realize a normally-off transistor.

Therefore, with the transistor of one embodiment of the present invention, a longer refresh interval can be set compared to a transistor using silicon, and power consumption during standby can be reduced.

In addition, since the off-state current has almost no temperature dependence, the memory circuit of this embodiment is suitable for an electronic device mounted on a vehicle. The leakage current during standby is extremely small, and in electric vehicles, the traveling distance for a given amount of charge hardly changes during standby.

This embodiment can be freely combined with other embodiments.

Embodiment Mode 9 This embodiment mode shows an example of a shift register that can be configured using the transistors described in the above embodiment modes.

FIG. 25A shows a block diagram of an example of a shift register. The shift register shown in FIG. 25A has two clock signal lines and two stages of flip-flops electrically connected to one of these clock signal lines. Further clock signal lines may be provided, and flip-flops may be provided in more stages.

In two clock signal lines, one clock signal line is high level (V_H.), the other is set to low level (V_L.) to operate.

In the shift register shown in FIG. 25A, the first flip-flop electrically connected to the first clock signal line CLK is followed by the second flip-flop electrically connected to the second clock signal line CLKB. An example having a flip-flop of the second stage, a flip-flop of the (n-1)th stage, and a flip-flop of the nth stage will be described. However, it is not limited to this, as long as it has at least a first flip-flop and a second flip-flop.

A clock signal line CLK is a wiring to which a clock signal CK is input.

The clock signal line CLKB is a wiring to which the clock signal CKB is input.

Each of the clock signal CK and the clock signal CKB can be generated using, for example, a NOT circuit (inverter circuit).

The first flip-flop receives the start signal SP and the start signal SPB, and the clock signal CK as a clock signal. The output signal OUT1 is output accordingly. Here, the state of a signal means, for example, potential, current, or frequency of the signal.

Each of the start signal SP and the start signal SPB can be generated using, for example, a NOT circuit (inverter circuit).

As the signal here, for example, an analog signal or a digital signal using voltage, current, resistance, frequency, or the like can be used. For example, the potential is set with at least a first potential and a second potential, and the first potential is a high level (high potential, V_H.) is used as the second potential, and a low level (low potential, V_L.), a binary digital signal can be set. Also, V_H.and V_L.is preferably a constant value, but considering the effect of noise, V_H.and V_L.You can have some width.

The second flip-flop receives the output signal OUT of the first flip-flop as the start signal SP, receives the clock signal CKB as the clock signal, and outputs the signal OUT2 according to the states of the input output signal and the clock signal CKB. as an output signal.

FIG. 25(B) shows a specific configuration example of the first flip-flop shown in FIG. 25(A).

A start signal SP is input to one of the source and drain of the first transistor 1111 and one of the source and drain of the fourth transistor 1114 .

A start signal SPB is input to one of the source and drain of the second transistor 1112 and one of the source and drain of the third transistor 1113 .

A clock signal CL is input to the gates of the first transistor 1111, the second transistor 1112, the third transistor 1113, and the fourth transistor 1114. FIG.

The other of the source and drain of the first transistor 1111 is connected to the gate of the fifth transistor 1115 and one electrode of the first capacitor 1119 .

The other of the source and drain of the second transistor 1112 is connected to the gate of the sixth transistor 1116 and one electrode of the second capacitor 1120 .

The other of the source and drain of the third transistor 1113 is connected to the gate of the seventh transistor 1117 and one electrode of the third capacitor 1121 .

The other of the source and drain of the fourth transistor 1114 is connected to the gate of the eighth transistor 1118 and one electrode of the fourth capacitor 1122 .

The drain of the fifth transistor 1115 is connected to the high potential side (preferably power supply potential Vdd). The source of the fifth transistor 1115 is connected to the other electrode of the first capacitor 1119 and the drain of the sixth transistor 1116, and outputs the output signal OUT. The other electrode of the second capacitor 1120 and the source of the sixth transistor 1116 are connected to the low potential side (preferably, the reference potential Vss).

The drain of the seventh transistor 1117 is connected to the high potential side (preferably power supply potential Vdd). The source of the seventh transistor 1117 is connected to the other electrode of the third capacitor 1121 and the drain of the eighth transistor 1118, and outputs the output signal OUTB. The other electrode of the fourth capacitor 1122 and the source of the eighth transistor 1118 are connected to the low potential side (preferably, the reference potential Vss).

The first capacitor 1119, the second capacitor 1120, the third capacitor 1121, and the fourth capacitor 1122 are formed over the same substrate as the transistor using the capacitors described in the above embodiments. can be done.

As described above, a flip-flop circuit can be manufactured using a transistor including a highly purified oxide semiconductor layer of one embodiment of the present invention. A transistor of one embodiment of the present invention in which sidewalls are provided for a source electrode layer and a drain electrode layer has a short channel length L and can be miniaturized; thus, the operation speed of a circuit can be increased and power consumption can be reduced. .

This embodiment can be freely combined with other embodiments.

(Embodiment 10) This embodiment shows an example of a booster circuit (charge pump circuit) that can be configured using the transistors shown in the above embodiments.

FIG. 26 shows an example of a specific configuration of the booster circuit. The booster circuit shown in FIG. 26 has two clock signal lines CLK and CLKB, and one electrode of a plurality of capacitive elements 1124 is connected to one of the two clock signal lines. The other electrodes of the plurality of capacitive elements 1124 are connected to a wiring connecting the drain electrode of one of the plurality of diode-connected transistors 1123 in the forward direction and the source electrode and gate electrode of the adjacent transistor. . In addition, a storage capacitor element is provided with one electrode connected to the tail end of the plurality of transistors and the other electrode held at a constant potential.

Further clock signal lines may be provided.

More transistors and capacitive elements may be provided according to the potential to be output.

In two clock signal lines, one clock signal line is high level (V_H.), the other is set to low level (V_L.) to operate.

Each of the clock signal CK and the clock signal CKB can be generated using, for example, a NOT circuit (inverter circuit). The NOT circuit can be manufactured using the EDMOS circuit shown in the fourth embodiment.

By using the booster circuit shown in Figure 26, V_inV_outcan be raised to For example, V_into power supply potential V_ddto enter V_outfrom V_ddcan be output, and can be boosted to a desired potential.

A potential signal boosted to a desired potential in this manner is input to, for example, a power supply line and used by each circuit mounted on the same substrate as the booster circuit.

Note that the constant potential at which the other electrode of the storage capacitor is held is, for example, the power supply potential V_d_dor reference potential V_ssAnd it is sufficient.

As the signal here, for example, an analog signal or a digital signal using voltage, current, resistance, frequency, or the like can be used. For example, the potential is set with at least a first potential and a second potential, and the first potential is a high level (high potential, V_H.) is used as the second potential, and a low level (low potential, V_L.), a binary digital signal can be set. Also, V_H.and V_L.is preferably a constant value, but considering the effect of noise, V_H.and V_L.You can have some width.

As described above, a booster circuit can be manufactured using the transistors described in the above embodiments.

Since the transistor of one embodiment of the present invention in which the source electrode layer and the drain electrode layer are provided with sidewalls has a short channel length L and can be miniaturized, the operation speed of the circuit can be increased and power consumption can be reduced.

This embodiment can be freely combined with other embodiments.

(Embodiment 11) In this embodiment, an example of an electronic device mounting a semiconductor integrated circuit obtained in any one of Embodiments 1 to 10 will be described with reference to FIG. The semiconductor integrated circuit is mounted on a circuit board or the like and mounted inside the main body of each electronic device.

A semiconductor integrated circuit including the transistors described in the above embodiments is mounted on the motherboard. Semiconductor integrated circuits are manufactured by mounting logic circuits, flash memory circuits, SRAM circuits, DRAM circuits, and the like. Also, the CPU and the logic circuit shown in the above embodiments can be implemented. Note that the semiconductor integrated circuit may be mounted by a wire bonding method. In this case also, various shapes of integrated circuit films can be mounted.

An FPC is attached to the circuit board, and connected to, for example, a display device through the FPC. A display driver and controller can be configured. The driver of the display section includes the shift register and the EDMOS circuit shown in the above embodiment.

FIG. 27A shows a notebook personal computer manufactured by mounting at least a semiconductor integrated circuit as a component, and includes a main body 3001, a housing 3002, a display portion 3003, a keyboard 3004, and the like. Note that the notebook personal computer has the CPU, the DRAM circuit, and the like shown in the above embodiments.

FIG. 27(B) is a personal digital assistant (PDA) manufactured by mounting at least a semiconductor integrated circuit as a part, and a main body 3021 is provided with a display section 3023, an external interface 3025, operation buttons 3024, and the like. ing. There is also a stylus 3022 as an accessory for operation.

FIG. 27(C) is electronic paper manufactured by mounting at least a semiconductor integrated circuit as a part. Electronic paper can be used in electronic equipment in all fields as long as it displays information. For example, electronic paper can be used for electronic books (electronic books), posters, in-car advertisements in vehicles such as trains, and display on various cards such as credit cards. FIG. 27(C) shows an example of an electronic book. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703 . The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed with the shaft portion 2711 as an axis. With such a configuration, it is possible to operate like a paper book.

A display portion 2705 is incorporated in the housing 2701 and a display portion 2707 is incorporated in the housing 2703 . The display units 2705 and 2707 may be configured to display a continuation screen, or may be configured to display different screens. By adopting a configuration in which different screens are displayed, for example, text is displayed on the right display unit (display unit 2705 in FIG. 27(C)) and an image is displayed on the left display unit (display unit 2707 in FIG. 27(C)). can be displayed.

In addition, FIG. 27C shows an example in which the housing 2701 is provided with an operation unit and the like. For example, a housing 2701 includes a power source 2721, operation keys 2723, a speaker 2725, and the like. An operation key 2723 can be used to turn pages. Note that a keyboard, a pointing device, and the like may be provided on the same surface of the housing as the display unit. In addition, the housing may be configured to have external connection terminals (earphone terminals, USB terminals, terminals that can be connected to various cables such as AC adapters and USB cables, etc.), a recording medium insertion section, etc. on the back or side of the housing. . Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

Also, the electronic book 2700 may be configured to transmit and receive information wirelessly. It is also possible to wirelessly purchase and download desired book data from an electronic book server.

FIG. 27D shows a mobile phone manufactured by mounting at least a semiconductor integrated circuit as a component, and is composed of two housings, a housing 2800 and a housing 2801. FIG. A housing 2801 includes a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, and the like.

The housing 2801 also includes a solar cell 2810 for charging the portable information terminal, an external memory slot 2811, and the like. Also, the antenna is built inside the housing 2801 .

The display panel 2802 has a touch panel, and a plurality of operation keys 2805 displayed as images are indicated by dotted lines in FIG. 27(D). A booster circuit (the booster circuit shown in the above embodiment) is mounted to boost the voltage output from the solar cell 2810 to the voltage required for each circuit.

Further, in addition to the above configuration, the non-contact IC chip, small recording device, and the like shown in the above embodiments may be incorporated.

The display direction of the display panel 2802 is appropriately changed according to the usage pattern. In addition, since the camera lens 2807 is provided on the same plane as the display panel 2802, a videophone call is possible. The speaker 2803 and the microphone 2804 can be used not only for voice calls, but also for video calls, recording, playback, and the like. Further, the housing 2800 and the housing 2801 can be slid to change from the unfolded state shown in FIG.

The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, allowing charging and data communication with a personal computer or the like. Also, by inserting a recording medium into the external memory slot 2811, it is possible to store and move a larger amount of data.

Moreover, in addition to the above functions, an infrared communication function, a television reception function, and the like may be provided.

FIG. 27(E) is a digital camera manufactured by mounting at least a semiconductor integrated circuit as a part, and includes a main body 3051, a display section (A) 3057, an eyepiece section 3053, an operation switch 3054, a display section (B) 3055, It is composed of a battery 3056 and the like.

As described above, the application range of the semiconductor device using the transistor described in the above embodiment is extremely wide, and the semiconductor device can be used for electronic devices in a wide range of fields. A transistor of one embodiment of the present invention in which sidewalls are provided for a source electrode layer and a drain electrode layer has a short channel length L and can be miniaturized. Therefore, with the use of the transistor of one embodiment of the present invention, the operation speed of the circuit can be increased and the power consumption of the electronic device can be reduced.

This embodiment mode can be freely combined with any one of Embodiment Modes 1 to 10.

101 substrate

102 electrode layer

103 first insulating layer

105 second insulating layer

107 oxide semiconductor layer

109a source electrode layer

109b drain electrode layer

117 gate insulating layer

119 gate electrode layer

120 insulating layer

121 side wall

199 dashed line

200 transistor

201 transistor

300 transistor

301 substrate

303 first insulating layer

305 second insulating layer

306 conductive film

307 oxide semiconductor layer

308 conductive film

309a first source electrode layer

309b first drain electrode layer

310 insulating layer

311a second source electrode layer

311b second drain electrode layer

315 Third insulating layer

317 gate insulating layer

319 gate electrode layer

320 insulating layer

321 side wall

400 first transistor

401 second transistor

411 substrate

412b electrode layer

412c electrode layer

412d electrode layer

412e electrode layer

412f electrode layer

413 first insulating layer

415 second insulating layer

416 Third insulating layer

417a first oxide semiconductor layer

417b second oxide semiconductor layer

417c third oxide semiconductor layer

417d fourth oxide semiconductor layer

419a first gate electrode layer

419b second gate electrode layer

421 side wall

422a first electrode layer

422b second electrode layer

422c third electrode layer

422d fourth electrode layer

422e fifth electrode layer

422f Sixth electrode layer

427 gate insulating layer

429a 1st wiring

429b 3rd wire

429c 4th wire

429d 5th wire

431 side wall

439 conductive layer

500 semiconductor integrated circuit chip

501 antenna

502 Insulator

503 semiconductor integrated circuit

505 antenna

506 support substrate

507 dashed line

508 feeding point

510 insulating layer

512 Insulator

520 semiconductor equipment

521 interrogator

522 antenna

523 semiconductor integrated circuit

524 antenna

800 semiconductor equipment

810 high frequency circuit

820 power circuit

830 reset circuit

840 clock generator

850 data demodulation circuit

860 data modulation circuit

870 control circuit

880 memory circuit

890 antenna

910 Code extraction circuit

920 Code judgment circuit

930 CRC judgment circuit

940 Output unit circuit

1001 CPU

1002 timing control circuit

1003 instruction analysis decoder

1004 register array

1005 address logic buffer circuit

1006 data bus interface

1007 ALU

1008 instruction register

1100 memory element

1101 First AND circuit

1102 Second AND circuit

1103 Third AND circuit

1104 first switch

1105 second switch

1106 3rd switch

1111 first transistor

1112 second transistor

1113 third transistor

1114 fourth transistor

1115 fifth transistor

1116 Sixth transistor

1117 Seventh transistor

1118 eighth transistor

1119 First capacitive element

1120 Second capacitive element

1121 Third capacitive element

1122 Fourth capacitive element

1123 transistor

1124 capacitive element

2700 E-book

2701 housing

2703 housing

2705 display

2707 display

2711 Axle

2721 power supply

2723 control key

2725 speaker

2800 housing

2801 housing

2802 display panel

2803 speaker

2804 microphone

2805 control key

2806 pointing device

2807 camera lens

2808 External connection terminal

2810 solar cell

2811 External memory slot

3001 body

3002 housing

3003 display

3004 keyboard

3021 body

3022 stylus

3023 display

3024 Manual operation button

3025 external interface

3051 body

3053 eyepiece

3054 operation switch

3055 Display (B)

3056 battery

3057 Display (A)

3200 Communication device

3210 display

3220 goods

3230 semiconductor equipment

3240 Communication device

3250 semiconductor equipment

3260 Product