Semiconductor device, manufacturing method thereof, and display device including the semiconductor device

One aspect of the present invention relates to a semiconductor device having an oxide semiconductor film and a display device having the semiconductor device. Alternatively, one aspect of the present invention relates to a method for manufacturing a semiconductor device having an oxide semiconductor film.

It should be noted that one aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, the invention relates to a process, machine, manufacture, or composition (composition of matter). In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light emitting device, a power storage device, a storage device, a driving method thereof, or a method for manufacturing the same.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. A semiconductor circuit, an arithmetic unit, and a storage device, including a semiconductor element such as a transistor, are one aspect of a semiconductor device. An image pickup device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, etc.), and an electronic device may have a semiconductor device.

Attention is being paid to a technique for constructing a transistor (also referred to as a field effect transistor (FET) or thin film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). Semiconductor materials typified by silicon are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

Oxide semiconductor films containing a large amount of In on the channel side by laminating oxide semiconductor films with different compositions in order to impart stable electrical characteristics to transistors using oxide semiconductors and obtain highly reliable semiconductor devices. Discloses a semiconductor device having an oxide semiconductor film containing a large amount of stabilizers such as Ga on the back channel side (see, for example, Patent Document 1).

<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2013-175715</text></patcit></p>

<p>When an oxide semiconductor film containing a large amount of In is used, the energy band gap (Eg) may become small (for example, Eg is less than 3.0 eV). In this case, the oxide semiconductor film having a small Eg has a greater influence on light than the oxide semiconductor film having a large Eg (for example, Eg is 3.0 eV or more and 3.5 eV or less). In a bias stress test (photo-negative GBT (Gate Bias Temperature) stress test) at the time of negative application during light irradiation, the reliability of a transistor having an oxide semiconductor film with a small Eg may decrease.</p><p>The photo-negative GBT stress test is a kind of accelerated test, and can evaluate the change in transistor characteristics caused by long-term use during light irradiation in a short time. In particular, the amount of change in the threshold voltage (ΔVth) of the transistor before and after the photo-negative GBT stress test is an important index for investigating reliability. Before and after the photo-negative GBT stress test, the smaller the change in threshold voltage (ΔVth), the higher the reliability.</p><p>In view of the above problems, one of the problems in one aspect of the present invention is to suppress fluctuations in electrical characteristics and improve reliability in a transistor having an oxide semiconductor film containing a large amount of In. Alternatively, in one aspect of the present invention, one of the problems is to provide a semiconductor device with reduced power consumption. Alternatively, in one aspect of the present invention, one of the problems is to provide a novel semiconductor device. Alternatively, in one aspect of the present invention, one of the problems is to provide a method for manufacturing a novel semiconductor device. Alternatively, in one aspect of the present invention, one of the problems is to provide a new display device.</p><p>The description of the above-mentioned problem does not prevent the existence of other problems. It should be noted that one aspect of the present invention does not necessarily have to solve all of these problems. Issues other than the above are self-evident from the description of the specification and the like, and it is possible to extract problems other than the above from the description of the specification and the like.</p>

<p>One aspect of the present invention is a semiconductor device having a transistor, wherein the transistor is electrically connected to a gate electrode, a gate insulating film on the gate electrode, an oxide semiconductor film on the gate insulating film, and an oxide semiconductor film. It has a source electrode connected to and a drain electrode electrically connected to the oxide semiconductor film, and the oxide semiconductor film has a first oxide semiconductor film on the gate electrode side and a first oxidation. It has a second oxide semiconductor film on a physical semiconductor film, and the first oxide semiconductor film has an atomic number ratio of In M (M is Ti, Ga, Sn, Y, Zr, La, It has a first region, which is greater than the atomic number ratio of Ce, Nd, or Hf), and the second oxide semiconductor film has a lower In atomic number ratio of In than the first oxide semiconductor film. A semiconductor device having a second region, wherein the second region has a portion thinner than the first region.</p><p>Further, another aspect of the present invention is a semiconductor device having a transistor, wherein the transistor has a first gate electrode, a first gate insulating film on the first gate electrode, and a first gate insulation. The oxide semiconductor film on the film, the source electrode electrically connected to the oxide semiconductor film, the drain electrode electrically connected to the oxide semiconductor film, and the second gate insulation on the oxide semiconductor film. It has a film and a second gate electrode on the second gate insulating film, and the oxide semiconductor film is a first oxide semiconductor film on the first gate electrode side and a first oxide semiconductor. It has a second oxide semiconductor film on the film, and the first oxide semiconductor film has an atomic number ratio of In M (M is Ti, Ga, Sn, Y, Zr, La, Ce, The second oxide semiconductor film has a first region, which is higher than the atomic number ratio of Nd, or Hf), and the second oxide semiconductor film has a lower In atom number ratio than the first oxide semiconductor film. The second region is a semiconductor device characterized by having a portion thinner than the first region.</p><p>In each of the above configurations, the oxide semiconductor film preferably has In, M, and Zn, and M is preferably Ga. Further, in each of the above configurations, the oxide semiconductor film preferably has a crystal portion, and the crystal portion preferably has a portion in which the c-axis of the crystal portion is parallel to the normal vector of the surface to be formed of the oxide semiconductor film. ..</p><p>Further, in each of the above configurations, it is preferable that the first region has a portion in which the crystal portion occupies a higher proportion than the second region. Further, in each of the above configurations, it is preferable that the first region has a portion having a lower hydrogen concentration than the second region.</p><p>Further, another aspect of the present invention is a display device having the semiconductor device and the display element according to any one of the above configurations. Further, another aspect of the present invention is a display module having the display device and a touch sensor. Further, another aspect of the present invention is an electronic device having the semiconductor device, the display device, or the display module according to any one of the above configurations, and an operation key or a battery.</p><p>Further, another aspect of the present invention is a method for manufacturing a semiconductor device having a transistor, which includes a step of forming a gate electrode on a substrate, a step of forming a gate insulating film on the gate electrode, and a gate insulating film. The step of forming the first oxide semiconductor film on the top, the step of forming the second oxide semiconductor film on the first oxide semiconductor film, and the source electrode and drain on the second oxide semiconductor film. A step of forming an electrode, a step of forming an oxide insulating film on a second oxide semiconductor film, a step of forming an oxide conductive film on the oxide insulating film, and a step of forming an oxide conductive film via the oxide conductive film, In the step of forming the source electrode and the drain electrode, which comprises a step of adding oxygen to the oxide insulating film and a step of removing the oxide conductive film, a part of the region of the second oxide semiconductor film is formed. The step of forming the oxide insulating film, which is thinner than the first oxide semiconductor film, is carried out in a PECVD device at a temperature of 180 ° C or higher and 350 ° C or lower. This is a method for manufacturing a semiconductor device, which is characterized in that the temperature of the process of forming an insulating film is the highest.</p><p>Further, another aspect of the present invention is a method for manufacturing a semiconductor device having a transistor, which is a step of forming a first gate electrode on a substrate and a first gate insulating film on the first gate electrode. The step of forming the first oxide semiconductor film on the first gate insulating film, the step of forming the second oxide semiconductor film on the first oxide semiconductor film, and the first step. A step of forming a source electrode and a drain electrode on the oxide semiconductor film of 2, a step of forming an oxide insulating film that functions as a second gate insulating film on the second oxide semiconductor film, and an oxide. A step of forming an oxide conductive film on the insulating film, a step of adding oxygen to the oxide insulating film via the oxide conductive film, a step of removing the oxide conductive film, and a step on the oxide insulating film. In the step of forming the second gate electrode and the step of forming the source electrode and the drain electrode, a part of the region of the second oxide semiconductor film is thinner than that of the first oxide semiconductor film. Therefore, the step of forming the oxide insulating film is carried out in a PECVD apparatus at a temperature of 180 ° C or more and 350 ° C or less, and the temperature of the step of forming the oxide insulating film is the highest in the process of manufacturing a transistor. This is a method for manufacturing a semiconductor device, which is characterized by the above.</p><p>In each of the above configurations, the first oxide semiconductor film and the second oxide semiconductor film are oxygen, In, Zn, and M (M is Ti, Ga, Sn, Y, Zr, La, respectively. (Representing Ce, Nd, or Hf), and preferably. Further, in each of the above configurations, the first oxide semiconductor film and the second oxide semiconductor film each have a crystal portion, and the crystal portion has a c-axis of the crystal portion of the first oxide semiconductor film. It is preferable to have a portion parallel to the normal vector of the surface to be formed or a portion parallel to the normal vector of the surface to be formed of the second oxide semiconductor film.</p>

<p>According to one aspect of the present invention, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, according to one aspect of the present invention, it is possible to provide a semiconductor device with reduced power consumption. Alternatively, according to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, in one aspect of the present invention, it is possible to provide a method for manufacturing a novel semiconductor device. Alternatively, according to one aspect of the present invention, a new display device can be provided.</p><p>The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.</p>

<figref num="1">Top view and sectional view showing one aspect of a semiconductor device.</figref><figref num="2">The cross-sectional view which shows one aspect of the semiconductor device.</figref><figref num="3">The cross-sectional view which shows an example of the manufacturing process of a semiconductor device.</figref><figref num="4">The cross-sectional view which shows an example of the manufacturing process of a semiconductor device.</figref><figref num="5">The cross-sectional view which shows an example of the manufacturing process of a semiconductor device.</figref><figref num="6">The cross-sectional view which shows an example of the manufacturing process of a semiconductor device.</figref><figref num="7">The cross-sectional view which shows an example of the manufacturing process of a semiconductor device.</figref><figref num="8">Top view showing one aspect of a display device.</figref><figref num="9">The cross-sectional view which shows one aspect of the display device.</figref><figref num="10">The cross-sectional view which shows one aspect of the display device.</figref><figref num="11">A block diagram and a circuit diagram illustrating a display device.</figref><figref num="12">The figure explaining the display module.</figref><figref num="13">The figure explaining the electronic device.</figref><figref num="14">The figure explaining the SIMS analysis result.</figref><figref num="15">The figure explaining the TDS analysis result.</figref><figref num="16">The figure explaining the TDS analysis result.</figref><figref num="17">The figure explaining the measurement result of ESR.</figref><figref num="18">The figure explaining the measurement result of ESR.</figref><figref num="19">The figure explaining the ID-VG characteristic of a transistor which concerns on an Example.</figref><figref num="20">The figure explaining the ID-VG characteristic of a transistor which concerns on an Example.</figref><figref num="21">The figure explaining the ID-VG characteristic of a transistor which concerns on an Example.</figref><figref num="22">Transistor gate BT stress test results according to the examples.</figref><figref num="23">Transistor gate BT stress test results according to the examples.</figref><figref num="24">The figure explaining the ID-VG characteristic of a transistor which concerns on an Example.</figref><figref num="25">The figure explaining the ID-VG characteristic of a transistor which concerns on an Example.</figref><figref num="26">The figure explaining the ID-VG characteristic of a transistor which concerns on an Example.</figref><figref num="27">The figure explaining the probability distribution of Vth and Ion of a transistor which concerns on an Example.</figref><figref num="28">The figure explaining the gate BT stress test result of the transistor which concerns on Example.</figref><figref num="29">The figure explaining the gate BT stress test result of the transistor which concerns on Example.</figref><figref num="30">The top view of the pixel part of the display device which concerns on Example.</figref><figref num="31">The top view explaining the frame area of the display device which concerns on embodiment.</figref><figref num="32">FIG. 3 is a cross-sectional view of a pixel portion and a protection circuit portion according to an embodiment.</figref><figref num="33">A circuit diagram illustrating a protection circuit according to an embodiment.</figref><figref num="34">Cs-corrected high-resolution TEM image in the cross section of CAAC-OS, and schematic cross section of CAAC-OS.</figref><figref num="35">Cs-corrected high-resolution TEM image in the plane of CAAC-OS.</figref><figref num="36">The figure explaining the structural analysis by XRD of CAAC-OS and the single crystal oxide semiconductor.</figref><figref num="37">The figure which shows the electron diffraction pattern of CAAC-OS.</figref><figref num="38">The figure which shows the change of the crystal part by electron irradiation of In-Ga-Zn oxide.</figref><figref num="39">The schematic diagram explaining the film formation model of CAAC-OS and nc-OS.</figref><figref num="40">InGaZnO₄The figure explaining the crystal and the pellet of.</figref><figref num="41">The schematic diagram explaining the film formation model of CAAC-OS.</figref>

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments, and the embodiments and details can be variously changed without departing from the spirit and scope thereof. .. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings.

In addition, the ordinal numbers "1st", "2nd", and "3rd" used in this specification are added to avoid confusion of the components, and are not limited numerically. Addition.

Further, in the present specification, words and phrases indicating arrangements such as "above" and "below" are used for convenience in order to explain the positional relationship between the configurations with reference to the drawings. Further, the positional relationship between the configurations changes appropriately depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words and phrases explained in the specification, and can be appropriately paraphrased according to the situation.

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. Then, a channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current is passed through the drain, the channel region and the source. Can be done. In the present specification and the like, the channel region means a region in which a current mainly flows.

Further, the functions of the source and the drain may be switched when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably.

Further, in the present specification and the like, "electrically connected" includes the case of being connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. For example, "things having some kind of electrical action" include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

Further, in the present specification and the like, the silicon oxide film refers to a film having a higher oxygen content than nitrogen in its composition, and the silicon nitride film has a nitrogen content higher than oxygen in its composition. Refers to a membrane with a lot of oxygen.

Further, in the present specification and the like, when explaining the structure of the invention by using the drawings, the reference numerals indicating the same ones are commonly used among different drawings.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 ° or more and 10 ° or less. Therefore, the case of -5 ° or more and 5 ° or less is also included. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.

Further, in the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive layer". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

(Embodiment 1) In the present embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 to 7.

&lt;Semiconductor Device Configuration Example 1&gt; FIG. 1 (A) is a top view of the transistor 100 which is a semiconductor device of one aspect of the present invention, and FIG. 1 (B) is a alternate long and short dash line X1 shown in FIG. 1 (A). -Corresponds to the cross-sectional view of the cut surface between X2, and FIG. 1 (C) corresponds to the cross-sectional view of the cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 1 (A). In addition, in FIG. 1 (A), in order to avoid complication, a part of the constituent elements of the transistor 100 (an insulating film that functions as a gate insulating film, etc.) is omitted. Further, the alternate long and short dash line X1-X2 direction may be referred to as the channel length direction, and the alternate long and short dash line Y1-Y2 direction may be referred to as the channel width direction. In the top view of the transistor, some of the components may be omitted in the subsequent drawings as in FIG. 1 (A).

The transistor 100 includes a conductive film 104 that functions as a gate electrode on the substrate 102, an insulating film 106 on the substrate 102 and the conductive film 104, an insulating film 107 on the insulating film 106, and an oxide semiconductor film on the insulating film 107. It has 108, a conductive film 112a that functions as a source electrode electrically connected to the oxide semiconductor film 108, and a conductive film 112b that functions as a drain electrode electrically connected to the oxide semiconductor film 108. Further, insulating films 114, 116, and insulating films 118 are provided on the transistor 100, more specifically, on the conductive films 112a and 112b and the oxide semiconductor film 108. The insulating films 114, 116, and 118 have a function as a protective insulating film for the transistor 100.

Further, the oxide semiconductor film 108 includes a first oxide semiconductor film 108a on the conductive film side 104 that functions as a gate electrode, and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a. Have. Further, the insulating film 106 and the insulating film 107 have a function as a gate insulating film of the transistor 100.

As the oxide semiconductor film 108, In-M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) oxide or In-M-Zn oxide can be used. can. In particular, it is preferable to use an In-M-Zn oxide as the oxide semiconductor film 108.

Further, the first oxide semiconductor film 108a has a first region in which the atomic number ratio of In is larger than the atomic number ratio of M. Further, the second oxide semiconductor film 108b has a second region in which the atomic number ratio of In is smaller than that of the first oxide semiconductor film 108a. Also, the second region has a thinner portion than the first region.

By having a first region in the first oxide semiconductor film 108a in which the atomic number ratio of In is higher than the atomic number ratio of M, the field effect mobility of the transistor 100 (sometimes referred to simply as mobility or μFE). Can be raised. Specifically, the field effect mobility of the transistor 100 is 10 cm.²More than / Vs, more preferably the field effect mobility of transistor 100 is 30 cm²It is possible to exceed / Vs.

For example, by using the above-mentioned transistor with high field effect mobility for a gate driver (particularly, a demultiplexer connected to the output terminal of the shift register of the gate driver), the frame width is narrow (narrow). A semiconductor device (also referred to as a frame) or a display device can be provided.

On the other hand, by using the first oxide semiconductor film 108a having a first region in which the atomic number ratio of In is larger than the atomic number ratio of M, the electrical characteristics of the transistor 100 are likely to fluctuate during light irradiation. However, in the semiconductor device of one aspect of the present invention, the second oxide semiconductor film 108b is formed on the first oxide semiconductor film 108a. Further, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is smaller than the film thickness of the first oxide semiconductor film 108a.

Further, since the second oxide semiconductor film 108b has a second region in which the atomic number ratio of In is smaller than that of the first oxide semiconductor film 108a, the Eg is larger than that of the first oxide semiconductor film 108a. Become. Therefore, the oxide semiconductor film 108, which is a laminated structure of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, has high resistance to the photonegative bias stress test.

By using the oxide semiconductor film having the above structure, the amount of light absorption of the oxide semiconductor film 108 at the time of light irradiation can be reduced. Therefore, it is possible to suppress fluctuations in the electrical characteristics of the transistor 100 during light irradiation. Further, in the semiconductor device of one aspect of the present invention, since the insulating film 114 or the insulating film 116 contains excess oxygen, fluctuations in the electrical characteristics of the transistor 100 due to light irradiation can be further suppressed. ..

Here, the oxide semiconductor film 108 will be described in detail with reference to FIG.

FIG. 2 is an enlarged cross-sectional view of the vicinity of the oxide semiconductor film 108 of the transistor 100 shown in FIG. 1 (B).

In FIG. 2, the film thickness of the first oxide semiconductor film 108a is shown as t1, and the film thickness of the second oxide semiconductor film 108b is shown as t2-1 and t2-2, respectively. Since the second oxide semiconductor film 108b is provided on the first oxide semiconductor film 108a, the first oxide semiconductor film 108a is etched with an etching gas or etched when the conductive films 112a and 112b are formed. Not exposed to solutions, etc. Therefore, in the first oxide semiconductor film 108a, there is no or very little film loss. On the other hand, in the second oxide semiconductor film 108b, when the conductive films 112a and 112b are formed, the portions that do not overlap with the conductive films 112a and 112b of the second oxide semiconductor film 108b are etched to form recesses. To. That is, the film thickness of the region overlapping the conductive films 112a and 112b of the second oxide semiconductor film 108b is t2-1, and the film thickness of the region not overlapping the conductive films 112a and 112b of the second oxide semiconductor film 108b is. It becomes t2-2.

The relationship between the film thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b is preferably t2-1&gt; t1&gt; t2-2. By having such a film thickness relationship, it is possible to obtain a transistor having a high field effect mobility and a small change amount of the threshold voltage at the time of light irradiation.

Further, in the oxide semiconductor film 108 possessed by the transistor 100, when oxygen deficiency is formed, electrons as carriers are generated, and the oxide semiconductor film 108 tends to have a normally-on characteristic. Therefore, it is important to reduce oxygen deficiency in the oxide semiconductor film 108, particularly oxygen deficiency in the first oxide semiconductor film 108a, in order to obtain stable transistor characteristics. Therefore, in the configuration of the transistor according to one aspect of the present invention, excess oxygen is introduced into the insulating film on the oxide semiconductor film 108, here, the insulating film 114 and / or the insulating film 116 on the oxide semiconductor film 108. By doing so, oxygen is transferred from the insulating film 114 and / or the insulating film 116 into the oxide semiconductor film 108 to compensate for the oxygen deficiency in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a. It is a feature.

It is more preferable that the insulating films 114 and 116 have a region containing an excess of oxygen (excess oxygen region) rather than a stoichiometric composition. In other words, the insulating films 114 and 116 are insulating films capable of releasing oxygen. In order to provide the oxygen excess region in the insulating films 114 and 116, for example, oxygen is introduced into the insulating films 114 and 116 after the film formation to form the oxygen excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma implantation ion implantation method, a plasma treatment, or the like can be used.

Further, in order to compensate for the oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 &lt;t1 should be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, and more preferably 3 nm or more and 10 nm or less.

Hereinafter, other components included in the semiconductor device of the present embodiment will be described in detail.

&lt;Substrate&gt; There are no major restrictions on the material of the substrate 102, but at least it must have heat resistance that can withstand the subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. It is also possible to apply single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. made of silicon or silicon carbide, and semiconductor elements are provided on these substrates. May be used as the substrate 102. When a glass substrate is used as the substrate 102, the 6th generation (1500 mm × 1850 mm), the 7th generation (1870 mm × 2200 mm), the 8th generation (2200 mm × 2400 mm), the 9th generation (2400 mm × 2800 mm), and the 10th generation. A large display device can be manufactured by using a large area substrate such as a generation (2950 mm × 3400 mm).

Further, a flexible substrate may be used as the substrate 102, and the transistor 100 may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistor 100. The release layer can be used to separate a part or all of the semiconductor device from the substrate 102 and transfer it to another substrate. At that time, the transistor 100 can be reprinted on a substrate having inferior heat resistance or a flexible substrate.

&lt;Condensate functioning as a gate electrode, source electrode, and drain electrode&gt; The conductive film 104 functioning as a gate electrode, the conductive film 112a functioning as a source electrode, and the conductive film 112b functioning as a drain electrode include chromium (Cr). ), Copper (Cu), Aluminum (Al), Gold (Au), Silver (Ag), Zinc (Zn), Molybdenum (Mo), Tantal (Ta), Titanium (Ti), Tungsten (W), Manganese (Mn) ), Nickel (Ni), iron (Fe), cobalt (Co) selected from metal elements, alloys containing the above-mentioned metal elements as components, alloys containing the above-mentioned metal elements, etc., respectively. be able to.

Further, the conductive films 104, 112a and 112b may have a single-layer structure or a laminated structure having two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, and a tungsten film on which a tungsten film is laminated. A layer structure, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are laminated on the titanium film, and a titanium film is formed on the titanium film, etc. be. Further, an alloy film or a nitride film in which one or a plurality selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be combined with aluminum may be used.

Further, the conductive films 104, 112a and 112b include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin oxide containing titanium oxide. , Indium zinc oxide, indium tin oxide to which silicon oxide is added, and other conductive materials having translucency can also be applied.

Further, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive films 104, 112a, and 112b. By using the Cu-X alloy film, it can be processed by the wet etching process, so that the manufacturing cost can be suppressed.

&lt;Insulating film that functions as a gate insulating film&gt; As the insulating films 106 and 107 that function as the gate insulating film of the transistor 100, plasma-enhanced chemical vapor deposition (PECVD: (Plasma Enhanced Chemical Vapor Deposition)) method, sputtering method, etc. are used. Silicon oxide film, silicon nitride film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, An insulating layer containing one or more of a cerium oxide film and a neodymium oxide film can be used. In addition, instead of having a laminated structure of the insulating films 106 and 107, a single-layer insulating film selected from the above-mentioned materials or an insulating film having three or more layers may be used.

Further, the insulating film 106 has a function as a blocking film that suppresses the permeation of oxygen.

For example, when excess oxygen is supplied into the insulating films 107, 114, 116 and / or the oxide semiconductor film 108, the insulating film 106 can suppress the permeation of oxygen.

The insulating film 107 in contact with the oxide semiconductor film 108 that functions as the channel region of the transistor 100 is preferably an oxide insulating film, and is a region containing oxygen in excess of the chemical quantitative composition (oxygen excess region). ) Is more preferable. In other words, the insulating film 107 is an insulating film capable of releasing oxygen. In order to provide the oxygen excess region in the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 107 after the film formation to form an oxygen excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma implantation ion implantation method, a plasma treatment, or the like can be used.

Further, when hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium oxide has a higher relative permittivity than silicon oxide and silicon nitride. Therefore, since the film thickness of the insulating film 107 can be increased as compared with the case where silicon oxide is used, the leakage current due to the tunnel current can be reduced. That is, it is possible to realize a transistor having a small off-current. Further, hafnium oxide having a crystal structure has a higher relative permittivity than hafnium oxide having an amorphous structure. Therefore, it is preferable to use hafnium oxide having a crystal structure in order to obtain a transistor having a small off-current. Examples of the crystal structure include a monoclinic system and a cubic system. However, one aspect of the present invention is not limited to these.

In the present embodiment, the silicon nitride film is formed as the insulating film 106, and the silicon oxide film is formed as the insulating film 107. Since the silicon nitride film has a higher relative permittivity than the silicon oxide film and the film thickness required to obtain the same capacitance as the silicon oxide film is large, the silicon nitride film is used as the gate insulating film of the transistor 100. The insulating film can be made thicker by including. Therefore, it is possible to suppress a decrease in the withstand voltage of the transistor 100, further improve the withstand voltage, and suppress electrostatic breakdown of the transistor 100.

&lt;Oxide semiconductor film&gt; As the oxide semiconductor film 108, the above-mentioned material can be used. When the oxide semiconductor film 108 is an In-M-Zn oxide, the atomic number ratios of the metal elements of the sputtering target used to form the In-M-Zn oxide satisfy In M and Zn M. Is preferable. The atomic number ratios of the metal elements of such a sputtering target are In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2 and In: M: Zn = 4: 2: 4.1 are preferable. When the oxide semiconductor film 108 is an In-M-Zn oxide, it is preferable to use a target containing a polycrystalline In-M-Zn oxide as the sputtering target. By using a target containing a polycrystalline In-M-Zn oxide, it becomes easy to form a crystalline oxide semiconductor film 108. The atomic number ratio of the oxide semiconductor film 108 to be formed includes a fluctuation of plus or minus 40% of the atomic number ratio of the metal element contained in the above-mentioned sputtering target as an error. For example, when the atomic number ratio of In: Ga: Zn = 4: 2: 4.1 is used as the sputtering target, the atomic number ratio of the oxide semiconductor film 108 to be formed is In: Ga: Zn = 4: 2: 1. It may be in the vicinity of 3.

For example, as the first oxide semiconductor film 108a, the above-mentioned In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1 It may be formed by using a sputtering target such as. Further, the second oxide semiconductor film 108b may be formed by using the above-mentioned In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1: 1.2 and the like. The atomic number ratio of the metal element of the sputtering target used for the second oxide semiconductor film 108b does not have to satisfy In M and Zn M, and may be a composition satisfying In M and Zn &lt;M. Specifically, In: M: Zn = 1: 3: 2 and the like can be mentioned.

The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As described above, by using an oxide semiconductor having a wide energy gap, the off-current of the transistor 100 can be reduced. In particular, the first oxide semiconductor film 108a uses an oxide semiconductor film having an energy gap of 2 eV or more, preferably 2 eV or more and 3.0 eV or less, and the second oxide semiconductor film 108b has an energy gap of 2.5 eV. It is preferable to use an oxide semiconductor film of 3.5 eV or more. Further, it is preferable that the energy gap of the second oxide semiconductor film 108b is larger than that of the first oxide semiconductor film 108a.

The thickness of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less. It is preferable to satisfy the relationship of film thickness described above.

Further, as the second oxide semiconductor film 108b, an oxide semiconductor film having a low carrier density is used. For example, the second oxide semiconductor film 108b has a carrier density of 1 × 10.¹⁷Pieces / cm³Below, preferably 1 × 10¹⁵Pieces / cm³Below, more preferably 1 × 10¹³Pieces / cm³Below, more preferably 1 × 10¹¹Pieces / cm³It shall be as follows.

Not limited to these, a transistor having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. Further, in order to obtain the required semiconductor characteristics of the transistor, the carrier density, the impurity concentration, the defect density, and the atomic number ratio of the metal element and oxygen of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are obtained. , It is preferable that the interatomic distance, density, etc. are appropriate.

As the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, by using an oxide semiconductor film having a low impurity concentration and a low defect level density, further excellent electrical characteristics can be obtained. It is preferable because a transistor having the same can be produced. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) is referred to as high-purity intrinsic or substantially high-purity intrinsic. Oxide semiconductor films having high-purity intrinsics or substantially high-purity intrinsics have few carrier sources, so that the carrier density can be lowered. Therefore, the transistor in which the channel region is formed in the oxide semiconductor film is unlikely to have an electrical characteristic (also referred to as normally on) in which the threshold voltage becomes negative. Further, since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has a low defect level density, the trap level density may also be low. In addition, the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a remarkably small off-current and a channel width of 1 × 10.⁶Even if the device is μm and the channel length L is 10 μm, the off current is below the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 in the range of voltage (drain voltage) between the source electrode and the drain electrode in the range of 1V to 10V.^-13The characteristic of A or less can be obtained.

Therefore, the transistor in which the channel region is formed in the oxide semiconductor film having the high-purity intrinsicity or substantially the high-purity intrinsicity can be a highly reliable transistor with little variation in electrical characteristics. The charge captured at the trap level of the oxide semiconductor film takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed on an oxide semiconductor film having a high trap level density may have unstable electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals and the like.

The hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to become water, and at the same time, forms an oxygen deficiency in the oxygen-desorbed lattice (or the oxygen-desorbed portion). When hydrogen enters the oxygen deficiency, electrons that are carriers may be generated. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor film containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen is reduced as much as possible in the oxide semiconductor film 108. Specifically, in the oxide semiconductor film 108, the hydrogen concentration obtained by SIMS analysis is 2 × 10.²⁰atoms / cm³Below, preferably 5 × 10¹⁹atoms / cm³Below, more preferably 1 × 10¹⁹atoms / cm³Below, 5 × 10¹⁸atoms / cm³Below, preferably 1 × 10¹⁸atoms / cm³Below, more preferably 5 × 10¹⁷atoms / cm³Below, more preferably 1 × 10¹⁶atoms / cm³It shall be as follows.

Further, it is preferable that the first oxide semiconductor film 108a has a portion having a lower hydrogen concentration than the second oxide semiconductor film 108b. Since the first oxide semiconductor film 108a has a portion having a lower hydrogen concentration than the second oxide semiconductor film 108b, a highly reliable semiconductor device can be obtained.

Further, if silicon or carbon, which is one of the Group 14 elements, is contained in the first oxide semiconductor film 108a, oxygen deficiency increases in the first oxide semiconductor film 108a, resulting in n-type formation. Therefore, the concentration of silicon and carbon in the first oxide semiconductor film 108a and the concentration of silicon and carbon near the interface with the first oxide semiconductor film 108a (concentration obtained by SIMS analysis) are set to 2 × 10.¹⁸atoms / cm³Below, preferably 2 × 10¹⁷atoms / cm³It shall be as follows.

Further, in the first oxide semiconductor film 108a, the concentration of the alkali metal or alkaline earth metal obtained by SIMS analysis is 1 × 10.¹⁸atoms / cm³Below, preferably 2 × 10¹⁶atoms / cm³It is as follows. Alkali metals and alkaline earth metals may generate carriers when combined with oxide semiconductors, which may increase the off-current of the transistor. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the first oxide semiconductor film 108a.

Further, when nitrogen is contained in the first oxide semiconductor film 108a, electrons as carriers are generated, the carrier density increases, and the n-type is easily formed. As a result, a transistor using an oxide semiconductor film containing nitrogen tends to have normally-on characteristics. Therefore, it is preferable that nitrogen is reduced as much as possible in the oxide semiconductor film, for example, the nitrogen concentration obtained by SIMS analysis is 5 × 10.¹⁸atoms / cm³It is preferable to make the following.

Further, the first oxide semiconductor film 108a and the second oxide semiconductor film 108b may each have a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), which will be described later, a polycrystalline structure, a microcrystal structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest defect level density, and CAAC-OS has the lowest defect level density.

&lt;Insulating film that functions as a protective insulating film for a transistor&gt; The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. Further, the insulating film 118 has a function as a protective insulating film of the transistor 100. Further, the insulating films 114 and 116 have oxygen. Further, the insulating film 114 is an insulating film capable of allowing oxygen to pass through. The insulating film 114 also functions as a damage mitigating film for the oxide semiconductor film 108 when the insulating film 116 to be formed later is formed.

As the insulating film 114, silicon oxide, silicon oxide nitride, or the like having a thickness of 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less can be used.

Further, the insulating film 114 preferably has a small amount of defects, and typically, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon is 3 × 10 by ESR measurement.¹⁷spins / cm³The following is preferable. This is because if the defect density contained in the insulating film 114 is high, oxygen is bonded to the defects and the amount of oxygen permeated in the insulating film 114 is reduced.

In the insulating film 114, all the oxygen that has entered the insulating film 114 from the outside does not move to the outside of the insulating film 114, and some oxygen stays in the insulating film 114. Further, when oxygen enters the insulating film 114 and the oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, oxygen may move in the insulating film 114. When an oxide insulating film capable of transmitting oxygen is formed as the insulating film 114, oxygen desorbed from the insulating film 116 provided on the insulating film 114 is transferred to the oxide semiconductor film 108 via the insulating film 114. Can be made to.

Further, the insulating film 114 can be formed by using an oxide insulating film having a low level density due to nitrogen oxides. The level density due to the nitrogen oxide can be formed between the energy at the upper end of the valence band of the oxide semiconductor film (Ev_os) and the energy at the lower end of the conduction band of the oxide semiconductor film (Ec_os). In some cases. E_{v_os}And E_{c_os}As the oxide insulating film having a low level density of nitrogen oxides, a silicon oxide film having a small amount of nitrogen oxides released, an aluminum oxide film having a small amount of nitrogen oxides released, or the like can be used. can.

A silicon oxynitride film having a small amount of nitrogen oxides released is a film in which the amount of ammonia released is larger than the amount of nitrogen oxides released in the heated desorption gas analysis method, and is typically the amount of ammonia released. Is 1x10¹⁸Pieces / cm³Above 5 × 10¹⁹Pieces / cm³It is as follows. The amount of ammonia released is the amount released by heat treatment in which the surface temperature of the film is 50 ° C or higher and 650 ° C or lower, preferably 50 ° C or higher and 550 ° C or lower.

Nitrogen oxides (NO_{x x}, X is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO₂Or NO forms a level on the insulating film 114 or the like. The level is located within the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxides diffuse to the interface between the insulating film 114 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 114 side. As a result, the trapped electrons stay in the vicinity of the interface between the insulating film 114 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction.

Nitrogen oxides also react with ammonia and oxygen in the heat treatment. Since the nitrogen oxides contained in the insulating film 114 react with the ammonia contained in the insulating film 116 in the heat treatment, the nitrogen oxides contained in the insulating film 114 are reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating film 114 and the oxide semiconductor film 108.

By using the oxide insulating film as the insulating film 114, it is possible to reduce the shift of the threshold voltage of the transistor, and it is possible to reduce the fluctuation of the electrical characteristics of the transistor.

The insulating film 114 has a g value of 2.037 or more in the spectrum obtained by measuring with an ESR of 100 K or less by heat treatment in the transistor manufacturing process, typically 300 ° C or more and less than 350 ° C. A first signal with a g value of 2.039 or less, a second signal with a g value of 2.001 or more and 2.003 or less, and a third signal with a g value of 1.964 or more and 1.966 or less are observed. The split width of the first signal and the second signal, and the split width of the second signal and the third signal are about 5 mT in the ESR measurement of the X band. In addition, the total spin density of the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the third signal with a g value of 1.964 or more and 1.966 or less is 1 ×. Ten¹⁸spins / cm³Less than, typically 1x10¹⁷spins / cm³Above 1 × 10¹⁸spins / cm³Is less than.

In the ESR spectrum of 100 K or less, the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the third signal with a g value of 1.964 or more and 1.966 or less are nitrogen oxides. Things (NO_{x x}, X corresponds to a signal caused by 0 or more and 2 or less, preferably 1 or more and 2 or less). Typical examples of nitrogen oxides include nitric oxide and nitrogen dioxide. That is, the smaller the total spin density of the first signal having a g value of 2.037 or more and 2.039 or less, the second signal having a g value of 2.001 or more and 2.003 or less, and the third signal having a g value of 1.964 or more and 1.966 or less. It can be said that the content of nitrogen oxides contained in the oxide insulating film is low.

In addition, the above oxide insulating film has a nitrogen concentration of 6 × 10 measured by SIMS.²⁰atoms / cm³It is as follows.

By forming the above oxide insulating film using the PECVD method using silane and nitrous oxide when the substrate temperature is 220 ° C or higher and 350 ° C or lower, a dense and hard film can be obtained. Can be formed.

The insulating film 116 is formed by using an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. An oxide insulating film containing more oxygen than oxygen satisfying a stoichiometric composition is partially desorbed by heating. Oxide insulating films containing more oxygen than oxygen satisfying the stoichiometric composition have an oxygen desorption amount of 1.0 × 10 in terms of oxygen atoms in TDS analysis.¹⁹atoms / cm³Above, preferably 3.0 × 10²⁰atoms / cm³The above is the oxide insulating film. The surface temperature of the film during the TDS analysis is preferably in the range of 100 ° C or higher and 700 ° C or lower, or 100 ° C or higher and 500 ° C or lower.

As the insulating film 116, silicon oxide, silicon oxide nitride, or the like having a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less can be used.

Further, the insulating film 116 preferably has a small amount of defects, and typically, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon is 1.5 × 10 by ESR measurement.¹⁸spins / cm³Less than, even 1x10¹⁸spins / cm³The following is preferable. Since the insulating film 116 is farther from the oxide semiconductor film 108 than the insulating film 114, the defect density may be higher than that of the insulating film 114.

Further, since the insulating films 114 and 116 can use insulating films of the same material, the interface between the insulating film 114 and the insulating film 116 may not be clearly confirmed. Therefore, in the present embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a broken line. In the present embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described, but the present invention is not limited to this, and for example, a single-layer structure of the insulating film 114 may be used.

The insulating film 118 has nitrogen. Further, the insulating film 118 has nitrogen and silicon.

Further, the insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal and the like. By providing the insulating film 118, oxygen diffused from the oxide semiconductor film 108 to the outside, oxygen contained in the insulating films 114 and 116 diffused to the outside, and hydrogen from the outside to the oxide semiconductor film 108, It is possible to prevent the ingress of water and the like. As the insulating film 118, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride. In addition, instead of the nitride insulating film having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal and the like, an oxide insulating film having a blocking effect of oxygen, hydrogen, water and the like may be provided. Examples of the oxide insulating film having a blocking effect on oxygen, hydrogen, water and the like include aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide and the like.

Various films such as the conductive film, the insulating film, and the oxide semiconductor film described above can be formed by a sputtering method or a PECVD method, but other methods, for example, a thermal CVD (Chemical Vapor Deposition) method. , Or may be formed by the ALD (Atomic Layer Deposition) method. An example of the thermal CVD method is the MOCVD (Metal Organic Chemical Vapor Deposition) method.

Since the thermal CVD method is a film forming method that does not use plasma, it has an advantage that defects are not generated due to plasma damage.

In the thermal CVD method, the raw material gas and the oxidizing agent may be sent into the chamber at the same time, the inside of the chamber is placed under atmospheric pressure or reduced pressure, and the reaction may be carried out in the vicinity of the substrate or on the substrate to deposit the film on the substrate. ..

Further, in the ALD method, a film may be formed by setting the inside of the chamber under atmospheric pressure or reduced pressure, the raw material gas for the reaction is sequentially introduced into the chamber, and the order of introducing the gas is repeated.

For example, each switching valve (also called a high-speed valve) is switched to supply two or more types of raw material gas to the chamber in order, and it is not possible to mix the multiple types of raw material gas at the same time as or after the first raw material gas. An active gas (argon, nitrogen, etc.) is introduced, and a second raw material gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the first raw material gas may be discharged by vacuum exhaust and then the second raw material gas may be introduced. The first raw material gas is adsorbed on the surface of the substrate to form a first layer, and reacts with the second raw material gas introduced later, so that the second layer is laminated on the first layer. A thin film is formed. By repeating this process a plurality of times while controlling the gas introduction order until the desired thickness is reached, a thin film having excellent step covering property can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction order is repeated, precise film thickness adjustment is possible, and it is suitable for manufacturing a fine FET.

The thermal CVD method such as the MOCVD method can form various films such as the conductive film, the insulating film, the oxide semiconductor film, and the metal oxide film of the above-described embodiment. For example, an In-Ga-ZnO film is formed. If so, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In (CH).₃)₃Is. The chemical formula of trimethylgallium is Ga (CH).₃)₃Is. The chemical formula of dimethylzinc is Zn (CH).₃)₂Is. Further, the combination is not limited to these, and triethylgallium (chemical formula Ga (C) is used instead of trimethylgallium.₂H₅)₃) Can also be used, and instead of dimethylzinc, diethylzinc (chemical formula Zn (C)) can be used.₂H₅)₂) Can also be used.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamide hafnium (TDMAH)) is vaporized. Raw material gas and ozone (O) as an oxidizing agent₃) Two types of gas are used. The chemical formula of tetrakisdimethylamide hafnium is Hf [N (CH).₃)₂]₄Is. Further, as another material liquid, there is tetrakis (ethylmethylamide) hafnium and the like.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)) and H as an oxidizing agent are used.₂Two types of gas, O, are used. The chemical formula of trimethylaluminum is Al (CH).₃)₃Is. Other material liquids include tris (dimethylamide) aluminum, triisobutylaluminum, and aluminum tris (2,2,6,6-tetramethyl-3,5-heptane dionate).

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the surface to be formed, chlorine contained in the adsorbent is removed, and an oxidizing gas (O) is formed.₂, Nitrogen monoxide) radicals to react with the adsorbent.

For example, when a tungsten film is formed by a film forming apparatus using ALD, WF₆Gas and B₂H₆Gas is introduced repeatedly in sequence to form an initial tungsten film, and then WF₆Gas and H₂Gas is introduced at the same time to form a tungsten film. In addition, B₂H₆SiH instead of gas₄Gas may be used.

For example, when an oxide semiconductor film, for example, an In-Ga-ZnO film is formed by a film forming apparatus using ALD, In (CH) is formed.₃)₃Gas and O₃Gas is introduced repeatedly in sequence to form an In-O layer, and then Ga (CH)₃)₃Gas and O₃Gas is introduced repeatedly in sequence to form a GaO layer, and then Zn (CH).₃)₂And O₃Gas is sequentially and repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. Further, these gases may be mixed to form a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, and a Ga-Zn-O layer. In addition, O₃H obtained by bubbling with an inert gas such as Ar instead of gas₂O gas may be used, but O that does not contain H₃It is preferable to use gas. Also, In (CH₃)₃Instead of gas, In (C₂H₅)₃Gas may be used. Also, Ga (CH₃)₃Instead of gas, Ga (C₂H₅)₃Gas may be used. Also, Zn (CH)₃)₂Gas may be used.

&lt;Semiconductor Device Configuration Example 2&gt; Next, a configuration example different from the transistor 100 shown in FIGS. 1 (A), (B), and (C) will be described with reference to FIGS. 3 (A), (B), and (C). In addition, when it has the same function as the function described above, the hatch pattern may be the same and no particular reference numeral may be added.

FIG. 3A is a top view of the transistor 170, which is a semiconductor device according to one aspect of the present invention, and FIG. 3B is a cross section of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 3A. Corresponding to the figure, FIG. 3 (C) corresponds to a cross-sectional view of the cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 3 (A).

The transistor 170 has a conductive film 104 that functions as a first gate electrode on the substrate 102, an insulating film 106 on the substrate 102 and the conductive film 104, an insulating film 107 on the insulating film 106, and an oxidation on the insulating film 107. The semiconductor semiconductor film 108, the insulating film 114 on the oxide semiconductor film 108, the insulating film 116 on the insulating film 114, and the conductive film 112a that functions as a source electrode electrically connected to the oxide semiconductor film 108, 112b that functions as a drain electrode electrically connected to the oxide semiconductor film 108, an insulating film 114 on the oxide semiconductor film 108, an insulating film 116 on the insulating film 114, and an insulating film 118 on the insulating film 116. And a conductive film 120a on the insulating film 118 and a conductive film 120b on the insulating film 118. The insulating films 114, 116, and 118 have a function as a second gate insulating film of the transistor 170. Further, the conductive film 120a is electrically connected to the conductive film 112b via the openings 142c provided in the insulating films 114, 116, 118. Further, in the transistor 170, the conductive film 120a has a function as a pixel electrode used in, for example, a display device. Further, in the transistor 170, the conductive film 120b functions as a second gate electrode (also referred to as a back gate electrode).

Further, as shown in FIG. 3C, the conductive film 120b is connected to the conductive film 104 that functions as the first gate electrode in the openings 142a and 142b provided in the insulating films 106, 107, 114, 116 and 118. Will be done. Therefore, the same potential is applied to the conductive film 120b and the conductive film 104.

In the present embodiment, the configuration in which the openings 142a and 142b are provided and the conductive film 120b and the conductive film 104 are connected is illustrated, but the present invention is not limited to this. For example, a configuration in which only one of the openings 142a and 142b is formed to connect the conductive film 120b and the conductive film 104, or the conductive film 120b and the conductive film 120b are not provided without the opening 142a and the opening 142b. The configuration may be such that the conductive film 104 is not connected. In the case of the configuration in which the conductive film 120b and the conductive film 104 are not connected, different potentials can be applied to the conductive film 120b and the conductive film 104, respectively.

Further, as shown in FIG. 3B, the oxide semiconductor film 108 is positioned so as to face each of the conductive film 104 functioning as a gate electrode and the conductive film 120b functioning as a second gate electrode. It is sandwiched between two conductive films that function as gate electrodes. The length in the channel length direction and the length in the channel width direction of the conductive film 120b functioning as the second gate electrode are longer than the length in the channel length direction and the length in the channel width direction of the oxide semiconductor film 108, respectively. The entire oxide semiconductor film 108 is covered with the conductive film 120b via the insulating films 114, 116, 118. Further, since the conductive film 120b functioning as the second gate electrode and the conductive film 104 functioning as the gate electrode are connected at the openings 142a and 142b provided in the insulating films 106, 107, 114, 116 and 118, they are connected. The side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 120b that functions as a second gate electrode via the insulating films 114, 116, 118.

In other words, in the channel width direction of the transistor 170, the conductive film 104 that functions as a gate electrode and the conductive film 120b that functions as a second gate electrode are the insulating films 106, 107 and the second gate that function as the gate insulating film. Insulating films 106, 107 that function as a gate insulating film and insulating films 114, 116, 118 that function as a second gate insulating film while being connected at openings provided in the insulating films 114, 116, 118 that function as an insulating film. It is a configuration that surrounds the oxide semiconductor film 108 via the above.

By having such a configuration, the oxide semiconductor film 108 included in the transistor 170 can be electrically surrounded by the electric fields of the conductive film 104 functioning as the gate electrode and the conductive film 120b functioning as the second gate electrode. can. The device structure of a transistor that electrically surrounds an oxide semiconductor film in which a channel region is formed by the electric fields of the gate electrode and the second gate electrode, such as the transistor 170, is called a surrounded channel (s-channel) structure. can.

Since the transistor 170 has an s-channel structure, an electric field for inducing a channel by the conductive film 104 functioning as a gate electrode can be effectively applied to the oxide semiconductor film 108, so that the current drive of the transistor 170 can be performed. The capacity is improved and it becomes possible to obtain high on-current characteristics. Further, since the on-current can be increased, the transistor 170 can be miniaturized. Further, since the transistor 170 has a structure surrounded by the conductive film 104 that functions as the gate electrode and the conductive film 120b that functions as the second gate electrode, the mechanical strength of the transistor 170 can be increased.

The other configurations of the transistor 170 are the same as those of the transistor 100 shown above, and have the same effect.

Further, the transistor according to the present embodiment can be freely combined with each of the above structures. For example, the transistor 100 shown in FIG. 1 can be used as the transistor of the pixel of the display device, and the transistor 170 shown in FIG. 3 can be used as the transistor of the gate driver of the display device.

&lt;Method for Manufacturing a Semiconductor Device 1&gt; Next, a method for manufacturing a transistor 100, which is a semiconductor device according to an aspect of the present invention, will be described in detail below with reference to FIGS. 4 to 6. 4 to 6 are cross-sectional views illustrating a method for manufacturing a semiconductor device.

The film (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor 100 is formed by using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum vapor deposition method, or a pulse laser deposition (PLD) method. can do. Alternatively, it can be formed by a coating method or a printing method.

As a film forming method, a sputtering method and a plasma chemical vapor deposition (PECVD) method are typical, but a thermal CVD method or an ALD (atomic layer deposition) method may also be used. An example of the thermal CVD method is the MOCVD (Metalorganic Chemical Vapor Deposition) method.

In the thermal CVD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and the raw material gas and the oxidizing agent are sent into the chamber at the same time, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate to form a film. As described above, since the thermal CVD method is a film forming method that does not generate plasma, it has an advantage that defects are not generated due to plasma damage.

Further, in the ALD method, the inside of the chamber is placed under atmospheric pressure or reduced pressure, the raw material gas for the reaction is sequentially introduced into the chamber, and the film formation is performed by repeating the order of gas introduction. For example, each switching valve (also called a high-speed valve) is switched to supply two or more types of raw material gas to the chamber in order, and at the same time as or after the first raw material gas so that multiple types of raw material gas are not mixed. Introduce an inert gas (argon, nitrogen, etc.) and introduce a second source gas. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced.

Further, instead of introducing the inert gas, the first raw material gas may be discharged by vacuum exhaust and then the second raw material gas may be introduced. The first raw material gas is adsorbed on the surface of the substrate to form a first monatomic layer, and reacts with the second raw material gas introduced later, so that the second monoatomic layer becomes the first monoatomic layer. A thin film is formed by being laminated on the atomic layer.

By repeating this process a plurality of times while controlling the gas introduction order until the desired thickness is reached, a thin film having excellent step covering property can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction order is repeated, the film thickness can be precisely adjusted, which is suitable for manufacturing a fine transistor.

First, a conductive film is formed on the substrate 102, and the conductive film is processed by performing a lithography step and an etching step to form a conductive film 104 that functions as a gate electrode. Next, insulating films 106 and 107 that function as gate insulating films are formed on the conductive film 104 (see FIG. 4 (A)).

The conductive film 104 functioning as a gate electrode can be formed by using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum vapor deposition method, or a pulsed laser deposition (PLD) method. Alternatively, it can be formed by a coating method or a printing method. Sputtering method and plasma chemical vapor deposition (PECVD) method are typical as the film forming method, but thermal CVD method such as the organic metal chemical vapor deposition (MOCVD) method described above or atomic layer deposition (Atomic layer deposition) is typical. The ALD) method may be used.

In the present embodiment, a glass substrate is used as the substrate 102, and a tungsten film having a thickness of 100 nm is formed as a conductive film 104 functioning as a gate electrode by a sputtering method.

The insulating films 106 and 107 that function as the gate insulating film can be formed by using a sputtering method, a PECVD method, a thermal CVD method, a vacuum vapor deposition method, a PLD method, or the like. In the present embodiment, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 and a silicon oxide film having a thickness of 50 nm is formed as the insulating film 107 by the PECVD method.

The insulating film 106 may have a laminated structure of a silicon nitride film. Specifically, the insulating film 106 can have a three-layer laminated structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. As an example of the three-layer laminated structure, it can be formed as follows.

As the first silicon nitride film, for example, silane having a flow rate of 200 sccm, nitrogen having a flow rate of 2000 sccm, and ammonia gas having a flow rate of 100 sccm are supplied to the reaction chamber of the PE-CVD apparatus as raw materials, and the pressure in the reaction chamber is controlled to 100 Pa. Then, a high-frequency power supply of 27.12 MHz may be used to supply 2000 W of power, and the thickness may be 50 nm.

As the second silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm are supplied to the reaction chamber of the PECVD equipment as raw materials, and the pressure in the reaction chamber is controlled to 100 Pa, 27.12 MHz. It is sufficient to supply 2000 W of power using the high frequency power supply of the above and form it so that the thickness is 300 nm.

As the third silicon nitride film, silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm are supplied to the reaction chamber of the PECVD equipment as raw materials, the pressure in the reaction chamber is controlled to 100 Pa, and a high frequency power supply of 27.12 MHz is used. It should be formed so that the thickness is 50 nm by supplying 2000 W of electric power.

The substrate temperature at the time of forming the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be 350 ° C. or less.

By forming the insulating film 106 into a three-layer laminated structure of a silicon nitride film, for example, when a conductive film containing copper (Cu) is used as the conductive film 104, the following effects are obtained.

The first silicon nitride film can suppress the diffusion of copper (Cu) element from the conductive film 104. The second silicon nitride film has a function of releasing hydrogen and can improve the withstand voltage of the insulating film that functions as a gate insulating film. The third silicon nitride film emits less hydrogen from the third silicon nitride film, and can suppress the diffusion of hydrogen released from the second silicon nitride film.

The insulating film 107 is formed of an insulating film containing oxygen in order to improve the interface characteristics with the oxide semiconductor film 108 (more specifically, the first oxide semiconductor film 108a) to be formed later. preferable.

Next, the first oxide semiconductor film 108a is formed on the insulating film 107. Then, a second oxide semiconductor film 108b is formed on the first oxide semiconductor film 108a (see FIG. 4 (B)).

In the present embodiment, a first oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn metal oxide target (In: Ga: Zn = 3: 1: 2 (atomic number ratio)). Then, continuously in a vacuum, a second oxide semiconductor is subjected to a sputtering method using an In-Ga-Zn metal oxide target (In: Ga: Zn = 1: 1: 1.2 (atomic number ratio)). By forming a film, a laminated oxide semiconductor film is formed. Next, a mask is formed on the oxide semiconductor film of the previous layer by a lithography process, and the laminated oxide semiconductor film is processed into a desired region to form an island-shaped oxide semiconductor film 108.

When the oxide semiconductor film 108 is formed by the sputtering method, a rare gas (typically argon), oxygen, a mixed gas of rare gas and oxygen is appropriately used as the sputtering gas. In the case of a mixed gas, it is preferable to increase the gas ratio of oxygen to the rare gas. It is also necessary to purify the sputtering gas. For example, oxygen gas and argon gas used as a sputtering gas have a dew point of -40 ° C or less, preferably -80 ° C or less, more preferably -100 ° C or less, and more preferably -120 ° C or less. By using the converted gas, it is possible to prevent water and the like from being taken into the oxide semiconductor film 108 as much as possible.

When the oxide semiconductor film 108 is formed by the sputtering method, the chamber in the sputtering apparatus is an adsorption type vacuum exhaust pump such as a cryopump in order to remove water and the like which are impurities for the oxide semiconductor film 108 as much as possible. High vacuum using (1 × 10)^-45x10 from Pa^-7It is preferable to exhaust (up to about Pa). Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas, particularly a gas containing carbon or hydrogen, from flowing back from the exhaust system into the chamber.

Next, a conductive film 112 that functions as a source electrode and a drain electrode is formed on the insulating film 107 and the oxide semiconductor film 108a (see FIG. 4C).

In the present embodiment, as the conductive film 112, a laminated film in which a tungsten film having a thickness of 50 nm and an aluminum film having a thickness of 400 nm are sequentially laminated is formed by a sputtering method.

In the present embodiment, the structure is a laminated structure of two layers of the conductive film 112, but the present invention is not limited to this. For example, the conductive film 112 may have a three-layer laminated structure in which a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm are sequentially laminated.

Next, masks 140a and 140b are formed in the desired region on the conductive film 112 (see FIG. 4 (D)).

In the present embodiment, the masks 140a and 140b are formed by applying a photosensitive resin film and patterning the photosensitive resin film by a lithography process.

Next, the conductive film 112 and the second oxide semiconductor film 108b are processed by using the etching gas 138 from above the conductive film 112 and the masks 140a and 140b (see FIG. 5 (A)).

In the present embodiment, the conductive film 112 and the second oxide semiconductor film 108b are processed by using a dry etching apparatus. However, the method for forming the conductive film 112 is not limited to this, and for example, by using a chemical solution for the etching gas 138, the conductive film 112 and the second oxide semiconductor film 108b can be formed by using a wet etching apparatus. It may be processed. However, rather than processing the conductive film 112 and the second oxide semiconductor film 108b using a wet etching apparatus, the conductive film 112 and the second oxide semiconductor film 108b were processed using a dry etching apparatus. This is preferable because a finer pattern can be formed.

Next, by removing the masks 140a and 140b, the conductive film 112a that functions as a source electrode on the second oxide semiconductor film 108b and the conductive film that functions as a drain electrode on the second oxide semiconductor film 108b. 112b and are formed. Further, the oxide semiconductor film 108 has a laminated structure of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b (see FIG. 5 (B)).

Further, the chemical solution may be applied from above the second oxide semiconductor film 108b and the conductive films 112a and 112b to clean the surface (back channel side) of the second oxide semiconductor film 108b.

Examples of the cleaning method include cleaning with a chemical solution such as phosphoric acid. By cleaning with a chemical solution such as phosphoric acid, impurities adhering to the surface of the second oxide semiconductor film 108b (for example, elements contained in the conductive films 112a and 112b) can be removed. The cleaning does not necessarily have to be performed, and in some cases, the cleaning may not be performed.

Further, at the time of forming the conductive films 112a and 112b and / or in the cleaning step, the second oxide semiconductor film 108b is formed with a second region having a thinner film thickness than the first oxide semiconductor film 108a. To.

Next, the insulating films 114 and 116 are formed on the oxide semiconductor film 108 and the conductive films 112a and 112b (see FIG. 5 (C)).

After forming the insulating film 114, it is preferable to continuously form the insulating film 116 without exposing it to the atmosphere. After forming the insulating film 114, the insulating film 114 and the insulating film are continuously formed by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature of the raw material gas without opening to the atmosphere. At the interface of 116, the concentration of impurities derived from atmospheric components can be reduced, and the oxygen contained in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108, so that the amount of oxygen deficiency in the oxide semiconductor film 108 can be reduced. Can be reduced.

For example, the silicon oxide film can be formed as the insulating film 114 by using the PECVD method. In this case, it is preferable to use a sedimentary gas containing silicon and an oxidizing gas as the raw material gas. Typical examples of the sedimentary gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include nitrous oxide, nitrogen dioxide and the like. Further, by using the PECVD method in which the oxidizing gas with respect to the above-mentioned sedimentary gas is larger than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the treatment chamber is less than 100 Pa, preferably 50 Pa or less. The insulating film 114 is an insulating film containing nitrogen and having a small amount of defects.

In the present embodiment, the insulating film 114 has a temperature at which the substrate 102 is held at 220 ° C, a silane having a flow rate of 50 sccm and a dinitrogen monoxide having a flow rate of 2000 sccm as a raw material gas, and a pressure in the treatment chamber of 20 Pa, which is parallel. High-frequency power supplied to the flat plate electrode is 13.56MHz, 100W (power density is 1.6 × 10)^-2W / cm²) Is used to form a silicon oxide nitride film.

As the insulating film 116, the substrate placed in the vacuum-exhausted processing chamber of the PECVD equipment is held at 180 ° C or more and 350 ° C or less, and the raw material gas is introduced into the processing chamber to increase the pressure in the processing chamber to 100 Pa or more. 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less, and 0.17 W / cm for the electrodes provided in the processing chamber.²More than 0.5W / cm²Below, more preferably 0.25 W / cm²More than 0.35W / cm²A silicon oxide film or a silicon nitride film is formed under the following conditions for supplying high-frequency power.

By supplying high-frequency power with the above power density in the reaction chamber under the above pressure as the film forming condition of the insulating film 116, the decomposition efficiency of the raw material gas is increased in the plasma, oxygen radicals are increased, and the raw material gas is oxidized. Therefore, the oxygen content in the insulating film 116 is higher than that in the chemical quantitative composition. On the other hand, in a film formed at a substrate temperature of the above temperature, the binding force between silicon and oxygen is weak, so that a part of oxygen in the film is desorbed by the heat treatment in a later step. As a result, it is possible to form an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition and desorbing a part of oxygen by heating.

Further, the step of forming the insulating film 116 is carried out in a PECVD apparatus at a temperature of 180 ° C or more and 350 ° C or less, and when the temperature of the step of forming the insulating film 116 becomes the highest in the manufacturing process of the transistor 100. preferable. For example, by implementing the temperature at which the insulating film 116 is formed at 350 ° C., the transistor 100 can be directly formed on a flexible substrate or the like.

In the process of forming the insulating film 116, the insulating film 114 serves as a protective film for the oxide semiconductor film 108. Therefore, the insulating film 116 can be formed by using high frequency power having a high power density while reducing the damage to the oxide semiconductor film 108.

It is possible to reduce the amount of defects in the insulating film 116 by increasing the flow rate of the sedimentary gas containing silicon with respect to the oxidizing gas under the film forming conditions of the insulating film 116. Typically, by ESR measurement, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon is 6 × 10.¹⁷spins / cm³Less than, preferably 3x10¹⁷spins / cm³Below, preferably 1.5 × 10¹⁷spins / cm³The following oxide insulating layer with a small amount of defects can be formed. As a result, the reliability of the transistor can be improved.

Further, after forming the insulating films 114 and 116, heat treatment may be performed. By the heat treatment, nitrogen oxides contained in the insulating films 114 and 116 can be reduced. Further, by the above heat treatment, a part of oxygen contained in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108, and the amount of oxygen deficiency contained in the oxide semiconductor film 108 can be reduced.

The temperature of the heat treatment on the insulating films 114 and 116 is typically 150 ° C or higher and 350 ° C or lower, or lower. The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air having a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (argon, helium, etc.). It is preferable that the nitrogen, oxygen, ultra-dry air, or noble gas does not contain hydrogen, water, or the like. An electric furnace, an RTA device, or the like can be used for the heat treatment.

In this embodiment, heat treatment is performed at 350 ° C. for 1 hour in a nitrogen atmosphere. In the step of forming the transistor 100, the temperature at which the insulating film 116 is formed may be the highest, and the heat treatment at a temperature equivalent to the temperature formed by the insulating film 116 may be performed in different steps.

Next, the oxide conductive film 131 is formed on the insulating film 116 (see FIG. 5 (D)).

The oxide conductive film 131 has oxygen and a metal (at least one selected from indium, zinc, titanium, aluminum, tungsten, tantalum, or molybdenum).

Examples of the oxide conductive film 131 include a tantalum oxide film, a titanium oxide film, an indium tin oxide (hereinafter also referred to as ITO) film, an aluminum oxide film, and an oxide semiconductor film (for example, IGZO film (In: Ga: Zn). = 1: 4: 5 (atomic number ratio)) etc.) can be used. Further, the oxide conductive film 131 can be formed by using a sputtering method. The thickness of the oxide conductive film 131 is preferably 1 nm or more and 20 nm or less, or 2 nm or more and 10 nm or less. In this embodiment, indium tin oxide (hereinafter referred to as ITSO) to which silicon oxide having a thickness of 5 nm is added is used as the oxide conductive film 131.

Next, oxygen 139 is added to the insulating films 114 and 116 and the oxide semiconductor film 108 via the oxide conductive film 131 (see FIG. 6 (A)).

Examples of the method of adding oxygen 139 to the insulating films 114 and 116 and the oxide semiconductor film 108 via the oxide conductive film 131 include an ion doping method, an ion implantation method, and a plasma treatment method. Further, when oxygen 139 is added, oxygen 139 can be effectively added to the insulating films 114 and 116 and the oxide semiconductor film 108 by applying a bias to the substrate side. As the above bias, for example, the power density is 1 W / cm.²More than 5W / cm²It may be as follows. By providing the oxide conductive film 131 on the insulating film 116 and adding oxygen, the oxide conductive film 131 functions as a protective film for suppressing the desorption of oxygen from the insulating film 116. Therefore, more oxygen can be added to the insulating films 114 and 116 and the oxide semiconductor film 108.

Next, the oxide conductive film 131 is removed by the etchant 142 (see FIG. 6 (B)).

Examples of the method for removing the oxide conductive film 131 include a dry etching method, a wet etching method, and a method of combining a dry etching method and a wet etching method. In the case of the dry etching method, the etchant 142 is an etching gas, and in the case of the wet etching method, the etchant 142 is a chemical solution. In the present embodiment, the oxide conductive film 131 is removed by using a wet etching method.

Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 6 (C)).

The heat treatment is performed before the formation of the insulating film 118 or after the formation of the insulating film 118 to diffuse the excess oxygen contained in the insulating films 114 and 116 into the oxide semiconductor film 108, and the excess oxygen contained in the oxide semiconductor film 108 is diffused into the oxide semiconductor film 108. The oxygen deficiency can be compensated. Alternatively, by forming the insulating film 118 into a heat film, the excess oxygen contained in the insulating films 114 and 116 can be diffused into the oxide semiconductor film 108 to compensate for the oxygen deficiency in the oxide semiconductor film 108. ..

When the insulating film 118 is formed by the PECVD method, it is preferable that the substrate temperature is 180 ° C or higher and 350 ° C or lower because a dense film can be formed.

For example, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, it is preferable to use a sedimentary gas containing silicon, nitrogen, and ammonia as raw material gases.

By using a smaller amount of ammonia compared to nitrogen, ammonia is dissociated in the plasma and active species are generated. The active species cleaves the bonds of silicon and hydrogen contained in the sedimentary gas containing silicon, and the triple bonds of nitrogen. As a result, the bond between silicon and nitrogen is promoted, the bond between silicon and hydrogen is small, the number of defects is small, and a dense silicon nitride film can be formed. On the other hand, when the amount of ammonia with respect to nitrogen is large, the decomposition of the sedimentary gas containing silicon and nitrogen does not proceed, silicon and hydrogen bonds remain, and defects are increased and a coarse silicon nitride film is formed. It ends up. For these reasons, it is preferable that the flow rate ratio of nitrogen to ammonia is 5 or more and 50 or less and 10 or more and 50 or less in the raw material gas.

In the present embodiment, a silicon nitride film having a thickness of 50 nm is formed from the raw material gases of silane, nitrogen, and ammonia by using a PECVD apparatus as the insulating film 118. The flow rate is 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia. The pressure in the processing chamber is 100 Pa, the substrate temperature is 350 ° C, and 1000 W of high frequency power is supplied to the parallel plate electrode using a 27.12 MHz high frequency power supply. PECVD equipment has an electrode area of 6000 cm²It is a parallel plate type PECVD device, and when the supplied power is converted into the power per unit area (power density), it is 1.7 x 10^-1W / cm²Is.

The transistor 100 shown in FIG. 1 can be formed by the above steps.

&lt;Method for Manufacturing a Semiconductor Device 2&gt; Next, a method for manufacturing a transistor 170, which is one aspect of the present invention, will be described in detail below with reference to FIG. 7. Note that FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device. Further, FIGS. 7 (A), (C), (E), and (G) are cross-sectional views in the channel length direction in the process of manufacturing the transistor 170, and FIGS. 7 (B), (D), (F), and (H) are transistors. It is sectional drawing in the channel width direction in the process of making 170.

First, the same steps as the method for manufacturing the transistor 100 shown above (steps shown in FIGS. 4 to 6) are performed, and the conductive film 104, the insulating films 106, 107, the oxide semiconductor film 108, and the conductive film 112a are performed on the substrate 102. , 112b, and insulating films 114, 116, 118 (see FIGS. 7 (A) (B)).

Next, a mask is formed on the insulating film 118 by a lithography process, and an opening 142c is formed in a desired region of the insulating films 114, 116, 118. Further, a mask is formed on the insulating film 118 by a lithography process to form openings 142a and 142b in desired regions of the insulating films 106, 107, 114, 116 and 118. The opening 142c is formed so as to reach the conductive film 112b. Further, the openings 142a and 142b are formed so as to reach the conductive film 104, respectively (see FIGS. 7 (C) and 7 (D)).

The openings 142a and 142b and the openings 142c may be formed in the same step or may be formed in different steps. When the openings 142a and 142b and the openings 142c are formed in the same process, they can be formed by using, for example, a gray tone mask or a halftone mask. Further, the openings 142a and 142b may be formed in a plurality of times. For example, the insulating films 106 and 107 are processed, and then the insulating films 114, 116 and 118 are processed.

Next, the conductive film 120 is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c (see FIGS. 7 (E) and 7 (F)).

As the conductive film 120, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) can be used. In particular, the conductive film 120 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium tin oxide (ITO). A translucent conductive material such as indium tin oxide or indium tin oxide (ITSO) to which silicon oxide is added can be used. Further, the conductive film 120 can be formed by using, for example, a sputtering method. In the present embodiment, an ITSO film having a film thickness of 110 nm is formed by a sputtering method.

Next, a mask is formed on the conductive film 120 by a lithography process, and the conductive film 112 is processed into a desired shape to form the conductive films 120a and 120b (see FIGS. 7 (G) and 7 (H)).

Examples of the method for forming the conductive films 120a and 120b include a dry etching method, a wet etching method, and a method of combining a dry etching method and a wet etching method. In the present embodiment, the conductive film 120 is processed into the conductive films 120a and 120b by using the wet etching method.

The transistor 170 shown in FIG. 3 can be manufactured by the above steps.

As described above, the configuration and method shown in this embodiment can be used in appropriate combination with the configuration and method shown in other embodiments.

(Embodiment 2) In the present embodiment, the structure of the oxide semiconductor included in the semiconductor device of one aspect of the present invention will be described in detail.

&lt;Structure of oxide semiconductor&gt; Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Non-single crystal oxide semiconductors include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline Oxide Semiconductor), and pseudoamorphous oxide semiconductor (a-like OS: amorphous like). Oxide Semiconductor), amorphous oxide semiconductors, etc.

From another viewpoint, the oxide semiconductor is divided into an amorphous oxide semiconductor and other crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

As a definition of an amorphous structure, it is generally known that it is not immobilized in a metastable state, and that it is isotropic and does not have an anisotropic structure. In addition, it can be rephrased as a structure in which the coupling angle is flexible and the structure has short-range order but does not have long-range order.

On the contrary, an essentially stable oxide semiconductor cannot be called a completely amorphous oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, having a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has a void (also referred to as a void) and has an unstable structure. Therefore, it can be said that the physical characteristics are close to those of an amorphous oxide semiconductor.

&lt;CAAC-OS&gt; First, CAAC-OS will be explained.

CAAC-OS is one of oxide semiconductors having a plurality of c-axis oriented crystal portions (also referred to as pellets).

Multiple pellets can be confirmed by observing a composite analysis image (also called a high-resolution TEM image) of a bright-field image of CAAC-OS and a diffraction pattern with a transmission electron microscope (TEM). .. On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the grain boundary (also referred to as grain boundary) cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries.

The CAAC-OS observed by TEM will be described below. FIG. 34 (A) shows a high-resolution TEM image of the cross section of CAAC-OS observed from a direction substantially parallel to the sample surface.

The Spherical Aberration Corrector function was used to observe the high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The acquisition of the Cs-corrected high-resolution TEM image can be performed by, for example, the atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

A Cs-corrected high-resolution TEM image obtained by enlarging the area (1) of FIG. 34 (A) is shown in FIG. 34 (B). From FIG. 34 (B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface on which the CAAC-OS film is formed, and is parallel to the formed surface or the upper surface of CAAC-OS.

As shown in FIG. 34 (B), CAAC-OS has a characteristic atomic arrangement. FIG. 34 (C) shows the characteristic atomic arrangement with auxiliary lines. From FIGS. 34 (B) and 34 (C), the size of one pellet may be 1 nm or more, or 3 nm or more, and the size of the gap created by the inclination between the pellet and the pellet is about 0.8 nm. You can see that.

Therefore, pellets can also be referred to as nanocrystals (nc: nanocrystals). CAAC-OS can also be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals).

Here, if the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown based on the Cs-corrected high-resolution TEM image, the structure is as if bricks or blocks were stacked (Fig. 34 (D)). reference.). The location of the tilt between the pellets observed in FIG. 34 (C) corresponds to the region 5161 shown in FIG. 34 (D).

In addition, Fig. 35 (A) shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. Cs-corrected high-resolution TEM images obtained by enlarging the region (1), region (2), and region (3) of FIG. 35 (A) are shown in FIGS. 35 (B), 35 (C), and 35 (D), respectively. show. From FIGS. 35 (B), 35 (C) and 35 (D), it can be confirmed that the metal atoms are arranged in a triangular, square or hexagonal shape in the pellet. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, InGaZnO₄When structural analysis is performed by the out-of-plane method for CAAC-OS having crystals of, a peak may appear in the diffraction angle (2θ) near 31 ° as shown in Fig. 36 (A). This peak is InGaZnO₄Since it is attributed to the (009) plane of the crystal, it can be confirmed that the CAAC-OS crystal has c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface.

In the structural analysis by the CAAC-OS out-of-plane method, in addition to the peak near 31 ° in 2θ, the peak may appear near 36 ° in 2θ. The peak with 2θ near 36 ° indicates that some of the CAAC-OS contains crystals that do not have c-axis orientation. For more preferable CAAC-OS, 2θ shows a peak near 31 ° and 2θ does not show a peak near 36 ° in the structural analysis by the out-of-plane method.

On the other hand, when structural analysis is performed by the in-plane method in which X-rays are incident on CAAC-OS from a direction substantially perpendicular to the c-axis, a peak appears near 56 ° in 2θ. This peak is InGaZnO₄It is attributed to the (110) plane of the crystal. In the case of CAAC-OS, even if 2θ is fixed near 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Fig. 36 (B) shows. No clear peaks appear as shown. On the other hand, InGaZnO₄In the case of a single crystal oxide semiconductor, when 2θ is fixed near 56 ° and φ scan is performed, there are 6 peaks assigned to the crystal plane equivalent to the (110) plane as shown in Fig. 36 (C). Observed. Therefore, it can be confirmed from the structural analysis using XRD that the orientation of the a-axis and the b-axis of CAAC-OS is irregular.

Next, CAAC-OS analyzed by electron diffraction will be described. For example, InGaZnO₄When an electron beam having a probe diameter of 300 nm is incident on CAAC-OS having crystals of the above, a diffraction pattern (also referred to as a selected area diffraction pattern) as shown in FIG. 37 (A) is obtained. May appear. InGaZnO is used for this diffraction pattern.₄Includes spots due to the (009) plane of the crystal. Therefore, it can be seen from electron diffraction that the pellets contained in CAAC-OS have c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. On the other hand, FIG. 37 (B) shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface. From FIG. 37 (B), a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation even by electron diffraction. The first ring in Fig. 37 (B) is InGaZnO.₄It is considered to be caused by the (010) plane and the (100) plane of the crystal of. Further, it is considered that the second ring in FIG. 37 (B) is caused by the surface (110) and the like.

As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of oxide semiconductors may deteriorate due to the inclusion of impurities or the formation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (oxygen deficiency, etc.) from the opposite perspective.

Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than a metal element constituting an oxide semiconductor, deprives the oxide semiconductor of oxygen, disturbs the atomic arrangement of the oxide semiconductor, and lowers the crystallinity. It becomes a factor. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in an oxide semiconductor may be a carrier trap or a carrier generation source. In addition, oxygen deficiency in the oxide semiconductor may become a carrier trap or a carrier generation source by capturing hydrogen.

CAAC-OS, which has few impurities and oxygen deficiency, is an oxide semiconductor with a low carrier density. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

&lt;nc-OS&gt; Next, nc-OS will be described.

The nc-OS has a region in which a crystal portion can be confirmed and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal part contained in nc-OS is often 1 nm or more and 10 nm or less, or 1 nm or more in size. An oxide semiconductor having a crystal portion larger than 10 nm and 100 nm or less may be referred to as a microcrystalline oxide semiconductor. In nc-OS, for example, in a high-resolution TEM image, the grain boundaries may not be clearly confirmed. It should be noted that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, in the following, the crystal part of nc-OS may be referred to as a pellet.

nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors depending on the analysis method. For example, when X-rays with a diameter larger than the pellet are used for nc-OS, the peak indicating the crystal plane is not detected by the analysis by the out-of-plane method. Further, when electron diffraction using an electron beam having a probe diameter larger than that of the pellet (for example, 50 nm or more) is performed on nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, spots are observed when nanobeam electron diffraction is performed on nc-OS using an electron beam with a probe diameter close to or smaller than the pellet size. In addition, when nanobeam electron diffraction is performed on nc-OS, a region with high brightness (ring-shaped) may be observed in a circular motion. Furthermore, multiple spots may be observed in the ring-shaped region.

As described above, since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS has an oxide semiconductor having RANC (Random Aligned nanocrystals) or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.

nc-OS is an oxide semiconductor with higher regularity than the amorphous oxide semiconductor. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher defect level density than CAAC-OS.

&lt;a-like OS&gt; a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor.

In a-like OS, voids may be observed in high-resolution TEM images. Further, in the high-resolution TEM image, it has a region where the crystal portion can be clearly confirmed and a region where the crystal portion cannot be confirmed.

The a-like OS has an unstable structure because it has voids. In the following, we show that a-like OS has an unstable structure compared to CAAC-OS and nc-OS, so we show the structural changes due to electron irradiation.

Prepare a-like OS (denoted as sample A), nc-OS (denoted as sample B) and CAAC-OS (denoted as sample C) as samples to be subjected to electron irradiation. Both samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, it can be seen that each sample has a crystal portion.

It should be noted that the determination as to which portion is regarded as one crystal portion may be performed as follows. For example, InGaZnO₄It is known that the unit cell of the crystal of is having three layers of In-O and six layers of Ga-Zn-O, and has a structure in which a total of nine layers are layered in the c-axis direction. .. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, InGaZnO is located where the spacing between the plaids is 0.28 nm or more and 0.30 nm or less.₄It can be regarded as the crystal part of. The plaid is InGaZnO.₄Corresponds to the ab plane of the crystal.

FIG. 38 is an example of investigating the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 38, it can be seen that in the a-like OS, the crystal portion becomes larger according to the cumulative irradiation amount of electrons. Specifically, as shown in (1) in Fig. 38, the crystal part (also called the initial nucleus), which had a size of about 1.2 nm at the initial stage of observation by TEM, has a cumulative irradiation dose of 4.2 × 10.⁸e^-/ nm²It can be seen that the size of the plant has grown to about 2.6 nm. On the other hand, nc-OS and CAAC-OS have a cumulative electron irradiation amount of 4.2 × 10 from the start of electron irradiation.⁸e^-/ nm²It can be seen that there is no change in the size of the crystal part in the range up to. Specifically, as shown in (2) and (3) in FIG. 38, the size of the crystal part of nc-OS and CAAC-OS is about 1.4 nm, respectively, regardless of the cumulative irradiation amount of electrons. It can be seen that it is about 2.1 nm.

In this way, in a-like OS, growth of the crystal part may be seen by electron irradiation. On the other hand, in nc-OS and CAAC-OS, it can be seen that almost no growth of the crystal part due to electron irradiation is observed. That is, it can be seen that a-like OS has an unstable structure as compared with nc-OS and CAAC-OS.

In addition, because it has voids, a-like OS has a lower density structure than nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. The density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a density of less than 78% of a single crystal.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], a single crystal InGaZnO having a rhombohedral crystal structure₄Density is 6.357g / cm³Will be. Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm.³More than 5.9g / cm³Will be less than. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm.³More than 6.3g / cm³Will be less than.

In some cases, a single crystal having the same composition does not exist. In that case, the density corresponding to the single crystal in the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, and each has various characteristics.

The oxide semiconductor may be, for example, a laminated film having two or more of amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

&lt;Film film model&gt; An example of a CAAC-OS and nc-OS film film model will be described below.

FIG. 39 (A) is a schematic view of a film forming chamber showing how CAAC-OS is formed by the sputtering method.

Target 5130 is glued to the backing plate. Multiple magnets are placed at positions facing the target 5130 via the backing plate. A magnetic field is generated by the plurality of magnets. For the arrangement and configuration of the magnets, refer to the description of the film formation chamber described above. A sputtering method that uses the magnetic field of a magnet to increase the film formation speed is called a magnetron sputtering method.

The target 5130 has a polycrystalline structure, and any of the crystal grains contains a cleavage plane.

As an example, the cleavage plane of the target 5130 having an In-Ga-Zn oxide will be described. Figure 40 (A) shows InGaZnO contained in target 5130.₄The crystal structure of is shown. In Fig. 40 (A), InGaZnO is shown with the c-axis facing upward and from the direction parallel to the b-axis.₄It is a structure when the crystal of is observed.

From FIG. 40 (A), it can be seen that in two adjacent Ga-Zn-O layers, the oxygen atoms in each layer are arranged at a short distance. Then, due to the negative charge of the oxygen atom, two adjacent Ga-Zn-O layers repel each other. As a result, InGaZnO₄Crystals have a cleavage plane between two adjacent Ga-Zn-O layers.

The substrate 5120 is arranged so as to face the target 5130, and the distance d (the distance between the target and the substrate (also referred to as the distance between TSs)) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. .. The film forming chamber is mostly filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen in a proportion of 5% by volume or more), and is controlled to 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Will be done. Here, by applying a voltage above a certain level to the target 5130, discharge starts and plasma is confirmed. A high-density plasma region is formed in the vicinity of the target 5130 by a magnetic field. In the high-density plasma region, ionization of the film-forming gas produces ions 5101. Ion 5101 is, for example, a cation of oxygen (O).⁺) And Argon cations (Ar)⁺) And so on.

Ion 5101 is accelerated toward the target 5130 by the electric field and eventually collides with the target 5130. At this time, the pellets 5100a and the pellets 5100b, which are flat plate-shaped or pellet-shaped sputtered particles, are peeled off from the cleaved surface and beaten out. The structures of the pellets 5100a and the pellets 5100b may be distorted due to the impact of the collision of the ions 5101.

Pellet 5100a is a flat or pellet-like sputtered particle having a triangular, eg equilateral triangular plane. Further, the pellet 5100b is a flat plate-shaped or pellet-shaped sputtered particle having a hexagonal surface, for example, a regular hexagonal plane. Plate-shaped or pellet-shaped sputtered particles such as pellets 5100a and pellets 5100b are collectively referred to as pellets 5100. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, and may be, for example, a shape in which a plurality of triangles are combined. For example, two triangles (eg, an equilateral triangle) may be combined into a quadrangle (eg, a rhombus).

The thickness of the pellet 5100 is determined according to the type of film-forming gas and the like. The reason will be described later, but it is preferable that the thickness of the pellet 5100 is uniform. Further, it is preferable that the sputtered particles are in the form of pellets having no thickness, rather than in the form of thick dice. For example, the pellet 5100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Further, for example, the pellet 5100 has a width of 1 nm or more. The pellet 5100 corresponds to the initial nucleus described in (1) in FIG. 38 above. For example, when ion 5101 is made to collide with a target 5130 having an In-Ga-Zn oxide, as shown in FIG. 40 (B), the Ga-Zn-O layer, the In-O layer and the Ga-Zn-O layer Pellet 5100 with 3 layers pops out. Note that FIG. 40 (C) shows the structure when the pellet 5100 is observed from a direction parallel to the c-axis. Therefore, the pellet 5100 can also be referred to as a nano-sized sandwich structure having two Ga-Zn-O layers (bread) and an In-O layer (ingredient).

The pellet 5100 may be negatively or positively charged on the sides by receiving a charge as it passes through the plasma. The pellet 5100 has an oxygen atom on the side surface, and the oxygen atom may be negatively charged. As described above, the side surfaces are charged with the same polarity, so that the charges repel each other and the flat plate shape can be maintained. When CAAC-OS is an In-Ga-Zn oxide, the oxygen atom bonded to the indium atom may be negatively charged. Alternatively, an indium atom, a gallium atom, or an oxygen atom bonded to a zinc atom may be negatively charged. Further, the pellet 5100 may grow by binding with indium atom, gallium atom, zinc atom, oxygen atom and the like when passing through plasma. This corresponds to the difference in size between (2) and (1) in FIG. 38 described above.

Here, when the substrate 5120 is at room temperature, the pellet 5100 does not grow any more, so that it becomes nc-OS (see FIG. 39 (B)). Since the temperature at which film formation is possible is about room temperature, nc-OS film formation is possible even when the substrate 5120 has a large area. In order to grow the pellet 5100 in plasma, it is effective to increase the film forming power in the sputtering method. By increasing the film forming power, the structure of the pellet 5100 can be stabilized.

As shown in FIGS. 39 (A) and 39 (B), for example, the pellet 5100 flies like a kite in the plasma and flutters up onto the substrate 5120. Since the pellet 5100 is charged, repulsive force is generated when the area where other pellets 5100 are already deposited approaches. Here, on the upper surface of the substrate 5120, a magnetic field (also referred to as a horizontal magnetic field) in a direction parallel to the upper surface of the substrate 5120 is generated. Further, since a potential difference is given between the substrate 5120 and the target 5130, a current flows from the substrate 5120 toward the target 5130. Therefore, the pellet 5100 receives a force (Lorentz force) on the upper surface of the substrate 5120 by the action of a magnetic field and an electric current. This can be understood by Fleming's left-hand rule.

Pellet 5100 has a larger mass than a single atom. Therefore, it is important to apply some force from the outside in order to move the upper surface of the substrate 5120. One of the forces may be the force generated by the action of a magnetic field and an electric current. In order to increase the force applied to the pellet 5100, the magnetic field in the direction parallel to the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably 50 G or more on the upper surface of the substrate 5120. It is advisable to provide an area that becomes. Alternatively, on the upper surface of the substrate 5120, the magnetic field in the direction parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, more preferably than the magnetic field in the direction perpendicular to the upper surface of the substrate 5120. It is advisable to provide an area that is 5 times or more.

At this time, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change due to the relative movement or rotation of the magnet unit and / and the substrate 5120. Therefore, on the upper surface of the substrate 5120, the pellet 5100 receives a force in various directions and can move in various directions.

Further, as shown in FIG. 39 (A), when the substrate 5120 is heated, the resistance due to friction or the like is small between the pellet 5100 and the substrate 5120. As a result, the pellet 5100 glides over the top surface of the substrate 5120. The movement of the pellet 5100 occurs with the flat plate surface facing the substrate 5120. After that, when it reaches the side surface of the other pellet 5100 that has already accumulated, the side surfaces are bonded to each other. At this time, the oxygen atom on the side surface of the pellet 5100 is eliminated. The desorbed oxygen atoms may fill the oxygen deficiency in CAAC-OS, resulting in CAAC-OS with a low defect level density. The temperature of the upper surface of the substrate 5120 should be, for example, 100 ° C or more and less than 500 ° C, 150 ° C or more and less than 450 ° C, 170 ° C or more and less than 400 ° C, or 170 ° C or more and 350 ° C or less. Just do it. That is, CAAC-OS can be formed even when the substrate 5120 has a large area.

Further, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged and the structural distortion caused by the collision of the ions 5101 is alleviated. The strain-relieved pellet 5100 becomes almost a single crystal. Since the pellets 5100 become almost single crystals, even if the pellets 5100 are heated after being bonded to each other, expansion and contraction of the pellets 5100 itself can hardly occur. Therefore, the widening of the gap between the pellets 5100 does not form defects such as grain boundaries and cause crevasses.

In CAAC-OS, the single crystal oxide semiconductor is not like a single plate, but the aggregate of pellets 5100 (nanocrystals) is arranged like a stack of bricks or blocks. In addition, there are no grain boundaries between them. Therefore, even if the CAAC-OS is deformed such as shrinkage due to heating during film formation, heating or bending after film formation, it is possible to relax the local stress or release the strain. Therefore, the structure is suitable for a semiconductor device having flexibility. In addition, nc-OS has an array in which aggregates of pellets 5100 (nanocrystals) are randomly stacked.

When the target is sputtered with ions, not only pellets but also zinc oxide and the like may pop out. Since zinc oxide is lighter than pellets, it reaches the top surface of substrate 5120 first. Then, a zinc oxide layer 5102 of 0.1 nm or more and 10 nm or less, 0.2 nm or more and 5 nm or less, or 0.5 nm or more and 2 nm or less is formed. FIG. 41 shows a schematic cross-sectional view.

As shown in FIG. 41 (A), pellets 5105a and pellets 5105b are deposited on the zinc oxide layer 5102. Here, the pellets 5105a and the pellets 5105b are arranged so that their side surfaces are in contact with each other. Further, the pellet 5105c is deposited on the pellet 5105b and then slides on the pellet 5105b. Further, on another side of the pellet 5105a, a plurality of particles 5103 ejected from the target together with zinc oxide crystallize by heating the substrate 5120 to form a region 5105a1. The plurality of particles 5103 may contain oxygen, zinc, indium, gallium and the like.

Then, as shown in FIG. 41 (B), the region 5105a1 is assimilated with the pellet 5105a to become the pellet 5105a2. Also, the pellet 5105c is arranged so that its side surface is in contact with another side surface of the pellet 5105b.

Next, as shown in FIG. 41 (C), the pellet 5105d is further deposited on the pellet 5105a2 and on the pellet 5105b, and then slides on the pellet 5105a2 and on the pellet 5105b. Also, the pellet 5105e slides on the zinc oxide layer 5102 toward another side surface of the pellet 5105c.

Then, as shown in FIG. 41 (D), the pellet 5105d is arranged so that its side surface is in contact with the side surface of the pellet 5105a2. Also, the pellet 5105d is arranged so that its side surface is in contact with another side surface of the pellet 5105c. Also, on another side of the pellet 5105d, the plurality of particles 5103 ejected from the target together with zinc oxide crystallize by heating the substrate 5120 to form the region 5105d1.

As described above, the deposited pellets are arranged so as to be in contact with each other, and crystal growth occurs on the side surface of the pellets to form CAAC-OS on the substrate 5120. Therefore, each pellet of CAAC-OS is larger than that of nc-OS. This corresponds to the difference in size between (3) and (2) in FIG. 38 described above.

Further, when the gap between the pellets 5100 becomes extremely small, one large pellet may be formed. Large pellets have a single crystal structure. For example, the size of a large pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less when viewed from the upper surface. Therefore, when the channel forming region of the transistor is smaller than the large pellet, a region having a single crystal structure can be used as the channel forming region. Further, as the pellet becomes larger, it may be possible to use a region having a single crystal structure as a channel formation region, a source region, and a drain region of the transistor.

As described above, the frequency characteristic of the transistor may be improved by forming the channel forming region of the transistor in the region having a single crystal structure.

It is considered that the pellet 5100 is deposited on the substrate 5120 by the above model. Therefore, unlike epitaxial growth, it can be seen that CAAC-OS can be formed even when the surface to be formed does not have a crystal structure. For example, even if the structure of the upper surface (formed surface) of the substrate 5120 is an amorphous structure (for example, amorphous silicon oxide), it is possible to form a CAAC-OS film.

Further, in CAAC-OS, it can be seen that the pellets 5100 are arranged along the shape even when the upper surface of the substrate 5120, which is the surface to be formed, has irregularities. For example, when the upper surface of the substrate 5120 is flat at the atomic level, the pellet 5100 juxtaposes the flat plate surface, which is a plane parallel to the ab surface, downward, so that the layer has a uniform thickness, is flat, and has high crystallinity. Is formed. Then, CAAC-OS can be obtained by stacking the layers in n stages (n is a natural number).

On the other hand, even if the upper surface of the substrate 5120 has irregularities, CAAC-OS has a structure in which layers in which pellets 5100 are juxtaposed along the convex surface are stacked in n stages (n is a natural number). Due to the unevenness of the substrate 5120, CAAC-OS may be prone to gaps between the pellets 5100. However, the intramolecular force acts between the pellets 5100, and even if there are irregularities, the gaps between the pellets are arranged so as to be as small as possible. Therefore, it is possible to obtain CAAC-OS having high crystallinity even if it has irregularities.

Therefore, CAAC-OS does not require laser crystallization and can form a uniform film even on a glass substrate having a large area.

Since CAAC-OS is formed by such a model, it is preferable that the sputtered particles are in the form of pellets with no thickness. When the sputtered particles are in the shape of a thick dice, the surface facing the substrate 5120 may not be constant, and the thickness and the orientation of the crystals may not be uniform.

With the film formation model shown above, CAAC-OS having high crystallinity can be obtained even on a surface to be formed having an amorphous structure.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 3) In the present embodiment, an example of a display device having a transistor exemplified in the previous embodiment will be described below with reference to FIGS. 8 to 10.

FIG. 8 is a top view showing an example of the display device. The display device 700 shown in FIG. 8 has a pixel unit 702 provided on the first substrate 701, a source driver circuit unit 704 and a gate driver circuit unit 706 provided on the first substrate 701, a pixel unit 702, and a source. It has a sealing material 712 arranged so as to surround the driver circuit unit 704 and the gate driver circuit unit 706, and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealing material 712. That is, the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 are sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in FIG. 8, a display element is provided between the first substrate 701 and the second substrate 705.

Further, the display device 700 is electrically connected to the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 in a region different from the region surrounded by the sealing material 712 on the first substrate 701. An FPC terminal 708 (FPC: Flexible printed circuit) is provided. Further, the FPC 716 is connected to the FPC terminal unit 708, and various signals and the like are supplied to the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 by the FPC 716. Further, a signal line 710 is connected to the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708, respectively. Various signals and the like supplied by the FPC 716 are given to the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708 via the signal line 710.

Further, the display device 700 may be provided with a plurality of gate driver circuit units 706. Further, the display device 700 shows an example in which the source driver circuit unit 704 and the gate driver circuit unit 706 are formed on the same first substrate 701 as the pixel unit 702, but the present invention is not limited to this configuration. For example, only the gate driver circuit unit 706 may be formed on the first substrate 701, or only the source driver circuit unit 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. .. The method for connecting the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

Further, the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 of the display device 700 have a plurality of transistors, and the transistor which is the semiconductor device of one aspect of the present invention can be applied. ..

Further, the display device 700 can have various elements. As an example of the element, a liquid crystal element, an EL (electroluminescence) element (EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.), Display element using transistor (transistor that emits light according to current), electron emitting element, electronic ink, electrophoresis element, grating light valve (GLV), plasma display (PDP), MEMS (micro electro mechanical system) , Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), MIRASOL®, IMOD (Interference Modulation) Element, Shutter MEMS Display Element, Optical Interference MEMS Display, Electro It has at least one such as a wetting element, a piezoelectric ceramic display, and a display element using carbon nanotubes. In addition to these, a display medium whose contrast, brightness, reflectance, transmittance and the like are changed by an electric or magnetic action may be provided. An example of a display device using an EL element is an EL display. As an example of a display device using an electron emitting element, a field emission display (FED) or an SED type planar display (SED:) Surface-conduction Electron-emitter Display) and so on. An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display). An example of a display device using electronic ink or an electrophoresis element is electronic paper. In the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

As the display method in the display device 700, a progressive method, an interlaced method, or the like can be used. Further, the color elements controlled by the pixels when displaying colors are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels of R pixel, G pixel, B pixel, and W (white) pixel. Alternatively, as in the pentile array, one color element may be composed of two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display device for color display, and can be applied to the display device for monochrome display.

Further, in order to display the display device in full color by using white light (W) for the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.), a colored layer (also referred to as a color filter) may be used. good. As the colored layer, for example, red (R), green (G), blue (B), yellow (Y) and the like can be appropriately combined and used. By using the colored layer, the color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, the white light in the region without the colored layer may be directly used for display by arranging the region having the colored layer and the region without the colored layer. By arranging a region that does not have a colored layer in a part, it is possible to reduce the decrease in brightness due to the colored layer and reduce the power consumption by about 20% to 30% in a bright display. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from an element having each emission color. .. By using the self-luminous element, the power consumption may be further reduced as compared with the case of using the colored layer.

In the present embodiment, a configuration in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. 9 and 10. Note that FIG. 9 is a cross-sectional view of the one-dot chain line QR shown in FIG. 8, and is configured by using a liquid crystal element as a display element. Further, FIG. 10 is a cross-sectional view of the one-dot chain line QR shown in FIG. 8, and has a configuration in which an EL element is used as a display element.

First, the common parts shown in FIGS. 9 and 10 will be described first, and then the different parts will be described below.

&lt;Explanation of Common Part of Display Device&gt; The display device 700 shown in FIGS. 9 and 10 includes a routing wiring unit 711, a pixel unit 702, a source driver circuit unit 704, and an FPC terminal unit 708. Further, the routing wiring portion 711 has a signal line 710. Further, the pixel unit 702 has a transistor 750 and a capacitive element 790. Further, the source driver circuit unit 704 has a transistor 752.

As the transistor 750 and the transistor 752, the transistor shown above can be used.

The transistor used in this embodiment has an oxide semiconductor film that has been purified to a high degree and suppresses the formation of oxygen deficiency. The transistor can lower the current value (off current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, since the transistor used in this embodiment can obtain a relatively high field effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion can be formed on the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, even in the pixel portion, by using a transistor capable of high-speed driving, it is possible to provide a high-quality image.

The capacitive element 790 has a structure having a dielectric between a pair of electrodes. More specifically, as one electrode of the capacitive element 790, a conductive film formed in the same step as the conductive film functioning as the gate electrode of the transistor 750 is used, and as the other electrode of the capacitive element 790, the source of the transistor 750 is used. A conductive film that functions as an electrode and a drain electrode is used. Further, as the dielectric sandwiched between the pair of electrodes, an insulating film that functions as a gate insulating film of the transistor 750 is used.

Further, in FIGS. 9 and 10, an insulating film 764, 766, 768, an oxide semiconductor film 767, and a flattening insulating film 770 are provided on the transistor 750, the transistor 752, and the capacitive element 790.

The insulating films 764, 766, and 768 can be formed by the same materials and manufacturing methods as the insulating films 114, 116, and 118 shown in the previous embodiments, respectively. Further, the oxide semiconductor film 767 can be formed by the same material and manufacturing method as the oxide semiconductor film 108 shown in the previous embodiment. Further, as the flattening insulating film 770, an organic material having heat resistance such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, and an epoxy resin can be used. The flattening insulating film 770 may be formed by laminating a plurality of insulating films formed of these materials.

Further, the flattening insulating film 770 may not be provided.

Further, the signal line 710 is formed in the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. The signal line 710 may be a conductive film formed in a process different from that of the source and drain electrodes of the transistors 750 and 752, for example, a conductive film that functions as a gate electrode. When, for example, a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small, and display on a large screen is possible.

Further, the FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed in the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Further, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

Further, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching the insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. A spherical spacer may be used as the structure 778. Further, in the present embodiment, the configuration in which the structure 778 is provided on the first substrate 701 side is illustrated, but the present invention is not limited to this. For example, the structure 778 may be provided on the second substrate 705 side, or the structure 778 may be provided on both the first substrate 701 and the second substrate 705.

Further, on the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 that is in contact with the light-shielding film 738 and the colored film 736 are provided.

&lt;Structure example of a display device using a liquid crystal element as a display element&gt; The display device 700 shown in FIG. 9 has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the side of the second substrate 705 and has a function as a counter electrode. The display device 700 shown in FIG. 9 can display an image by controlling the transmission and non-transmission of light by changing the orientation state of the liquid crystal layer 776 by the voltage applied to the conductive film 772 and the conductive film 774.

Further, the conductive film 772 is connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed on the flattening insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element. Further, the conductive film 772 has a function as a reflective electrode. The display device 700 shown in FIG. 9 is a so-called reflective color liquid crystal display device that uses external light to reflect light by the conductive film 772 and display the light through the colored film 736.

As the conductive film 772, a conductive film having a translucent light in visible light or a conductive film having a reflective light in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having a reflective property in visible light, for example, a material containing aluminum or silver may be used. In the present embodiment, as the conductive film 772, a conductive film having a reflective property in visible light is used.

Further, when a conductive film having a reflective property in visible light is used as the conductive film 772, the conductive film may have a laminated structure. For example, an aluminum film having a thickness of 100 nm is formed in the lower layer, and a silver alloy film having a thickness of 30 nm (for example, an alloy film containing silver, palladium, and copper) is formed in the upper layer. By adopting the above-mentioned structure, the following excellent effects are obtained.

(1) The adhesion between the undercoat film and the conductive film 772 can be improved. (2) It is possible to etch the aluminum film and the silver alloy film at once with a chemical solution. (3) The cross-sectional shape of the conductive film 772 can be a good shape (for example, a tapered shape). The reason for (3) is that the aluminum film has a slower etching rate with the chemical solution than the silver alloy film, or is lower than the silver alloy film when the lower aluminum film is exposed after etching the upper silver alloy film. This is because electrons are extracted from aluminum, which is a metal having a high ionization tendency, so that the etching of the silver alloy film is suppressed and the etching of the underlying aluminum film is accelerated.

Further, in the display device 700 shown in FIG. 9, unevenness is provided in a part of the flattening insulating film 770 of the pixel portion 702. The unevenness can be formed, for example, by forming the flattening insulating film 770 with an organic resin film or the like and providing the unevenness on the surface of the organic resin film. Further, the conductive film 772 that functions as a reflective electrode is formed along the above-mentioned unevenness. Therefore, when external light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772, and the visibility can be improved.

The display device 700 shown in FIG. 9 is an example of a reflective color liquid crystal display device, but the present invention is not limited to this. For example, the conductive film 772 is transmitted in visible light by using a translucent conductive film. It may be a type color liquid crystal display device. In the case of the transmissive color liquid crystal display device, the unevenness provided on the flattening insulating film 770 may not be provided.

Although not shown in FIG. 9, an alignment film may be provided on the side of the conductive films 772 and 774 in contact with the liquid crystal layer 776, respectively. Further, although not shown in FIG. 9, an optical member (optical substrate) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like depending on the conditions.

Further, when the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response rate and is optically isotropic. Further, the liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent does not require an orientation treatment and has a small viewing angle dependence. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. ..

When a liquid crystal element is used as the display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated) Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used.

Further, a normally black type liquid crystal display device, for example, a transmissive type liquid crystal display device adopting a vertical orientation (VA) mode may be used. As the vertical alignment mode, for example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV mode and the like can be used.

&lt;Display device using a light emitting element as a display element&gt; The display device 700 shown in FIG. 10 has a light emitting element 782. The light emitting element 782 has a conductive film 784, an EL layer 786, and a conductive film 788. The display device 700 shown in FIG. 10 can display an image by emitting light from the EL layer 786 included in the light emitting element 782.

Further, the conductive film 784 is connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is formed on the flattening insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element. As the conductive film 784, a conductive film having a translucent light in visible light or a conductive film having a reflective light in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having a reflective property in visible light, for example, a material containing aluminum or silver may be used.

Further, in the display device 700 shown in FIG. 10, an insulating film 730 is provided on the flattening insulating film 770 and the conductive film 784. The insulating film 730 covers a part of the conductive film 784. The light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has translucency and transmits the light emitted by the EL layer 786. In the present embodiment, the top emission structure is exemplified, but the present invention is not limited to this. For example, it can be applied to a bottom emission structure that emits light to the conductive film 784 side and a dual emission structure that emits light to both the conductive film 784 and the conductive film 788.

Further, a colored film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the routing wiring section 711, and the source driver circuit section 704. Further, the colored film 736 and the light-shielding film 738 are covered with the insulating film 734. Further, the space between the light emitting element 782 and the insulating film 734 is filled with the sealing film 732. In the display device 700 shown in FIG. 10, the configuration in which the colored film 736 is provided has been illustrated, but the present invention is not limited to this. For example, when the EL layer 786 is formed by painting separately, the structure may be such that the colored film 736 is not provided.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 4) In the present embodiment, a display device having a semiconductor device according to one aspect of the present invention will be described with reference to FIG.

The display device shown in FIG. 11A has a region having pixels of the display element (hereinafter referred to as a pixel unit 502) and a circuit unit (hereinafter referred to as a circuit unit) arranged outside the pixel unit 502 and having a circuit for driving the pixels. , Drive circuit unit 504), a circuit having an element protection function (hereinafter referred to as protection circuit 506), and a terminal unit 507. The protection circuit 506 may not be provided.

It is desirable that a part or all of the drive circuit unit 504 is formed on the same substrate as the pixel unit 502. This makes it possible to reduce the number of parts and the number of terminals. When a part or all of the drive circuit unit 504 is not formed on the same substrate as the pixel unit 502, a part or all of the drive circuit unit 504 is caused by COG or TAB (Tape Automated Bonding). Can be implemented.

The pixel unit 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in the X row (X is a natural number of 2 or more) and the Y column (Y is a natural number of 2 or more). The drive circuit unit 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (hereinafter referred to as a gate driver 504a). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507 and outputs the signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which the scanning signal is given. A plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can also supply another signal.

The source driver 504b has a shift register and the like. In the source driver 504b, in addition to the signal for driving the shift register, a signal (image signal) that is the source of the data signal is input via the terminal portion 507. The source driver 504b has a function of generating a data signal to be written to the pixel circuit 501 based on the image signal. Further, the source driver 504b has a function of controlling the output of a data signal according to a pulse signal obtained by inputting a start pulse, a clock signal, or the like. Further, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) to which the data signal is given. Alternatively, the source driver 504b has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured by using, for example, a plurality of analog switches.

The source driver 504b can output a time-division signal of an image signal as a data signal by sequentially turning on a plurality of analog switches. Further, the source driver 504b may be configured by using a shift register or the like.

In each of the plurality of pixel circuits 501, a pulse signal is input via one of a plurality of scan line GLs to which a scan signal is given, and a data signal is input through one of a plurality of data line DLs to which a data signal is given. Entered. also. In each of the plurality of pixel circuits 501, the writing and holding of the data of the data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the mth row and nth column, a pulse signal is input from the gate driver 504a via the scanning line GL_m (m is a natural number of X or less), and the data line DL_n (n) is input according to the potential of the scanning line GL_m. Is a natural number less than or equal to Y), and the data signal is input from the source driver 504b.

The protection circuit 506 shown in FIG. 11A is connected to, for example, a scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to the wiring between the source driver 504b and the terminal portion 507. The terminal portion 507 is a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 506 is a circuit that makes the wiring connected to the protection circuit 506 in a conductive state when a potential outside a certain range is applied to the wiring.

As shown in FIG. 11A, by providing protection circuits 506 in the pixel section 502 and the drive circuit section 504, respectively, the resistance of the display device to overcurrent generated by ESD (Electro Static Discharge) or the like is enhanced. be able to.

However, the configuration of the protection circuit 506 is not limited to this, and for example, the configuration may be such that the protection circuit 506 is connected to the gate driver 504a or the protection circuit 506 is connected to the source driver 504b. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

Further, FIG. 11A shows an example in which the drive circuit unit 504 is formed by the gate driver 504a and the source driver 504b, but the present invention is not limited to this configuration. For example, a configuration may be configured in which only the gate driver 504a is formed and a substrate on which a separately prepared source driver circuit is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted.

Further, the plurality of pixel circuits 501 shown in FIG. 11A can be configured as shown in FIG. 11B, for example.

The pixel circuit 501 shown in FIG. 11B includes a liquid crystal element 570, a transistor 550, and a capacitive element 560. The transistor shown in the previous embodiment can be applied to the transistor 550.

The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the written data. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 of each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, as a driving method of a display device provided with a liquid crystal element 570, TN mode, STN mode, VA mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode and the like may be used.

In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a guest host mode, or the like. However, the present invention is not limited to this, and various liquid crystal elements and various driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and n-th column, one of the source electrode or the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. To. Further, the gate electrode of the transistor 550 is electrically connected to the scanning line GL_m. The transistor 550 has a function of controlling data writing of a data signal by turning it on or off.

One of the pair of electrodes of the capacitive element 560 is electrically connected to the wiring to which the potential is supplied (hereinafter, the potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Ru. The potential value of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitive element 560 has a function as a holding capacitance for holding the written data.

For example, in the display device having the pixel circuit 501 of FIG. 11 (B), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 11 (A), the transistor 550 is turned on, and the data signal is displayed. Write data.

The pixel circuit 501 to which the data is written is in the holding state when the transistor 550 is turned off. By doing this sequentially line by line, the image can be displayed.

Further, the plurality of pixel circuits 501 shown in FIG. 11A can be configured as shown in FIG. 11C, for example.

Further, the pixel circuit 501 shown in FIG. 11C has transistors 552 and 554, a capacitive element 562, and a light emitting element 572. The transistor shown in the previous embodiment can be applied to either or both of the transistor 552 and the transistor 554.

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n) to which a data signal is given. Further, the gate electrode of the transistor 552 is electrically connected to the wiring (hereinafter referred to as scanning line GL_m) to which the gate signal is given.

The transistor 552 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitive element 562 is electrically connected to the wiring to which the potential is applied (hereinafter referred to as the potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Will be done.

The capacitive element 562 has a function as a holding capacitance for holding the written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of the anode and cathode of the light emitting device 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

A high power supply potential VDD is given to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is given to the other.

In the display device having the pixel circuit 501 of FIG. 11 (C), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 11 (A), the transistor 552 is turned on, and the data of the data signal is input. Write.

The pixel circuit 501 to which the data is written is in the holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

(Embodiment 5) In the present embodiment, the display module and the electronic device having the semiconductor device of one aspect of the present invention will be described with reference to FIGS. 12 and 13.

The display module 8000 shown in FIG. 12 has a touch panel 8004 connected to the FPC8003, a display panel 8006 connected to the FPC8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery between the upper cover 8001 and the lower cover 8002. Has 8011.

The semiconductor device of one aspect of the present invention can be used, for example, for the display panel 8006.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006.

The touch panel 8004 can be used by superimposing a resistance film type or capacitance type touch panel on the display panel 8006. It is also possible to equip the facing substrate (sealed substrate) of the display panel 8006 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 8006 to form an optical touch panel.

The backlight 8007 has a light source 8008. Note that FIG. 12 illustrates a configuration in which the light source 8008 is arranged on the backlight 8007, but the present invention is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusing plate may be used. When a self-luminous light emitting element such as an organic EL element is used, or when a reflective panel or the like is used, the backlight 8007 may not be provided.

In addition to the protective function of the display panel 8006, the frame 8009 also has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. Further, the frame 8009 may have a function as a heat sink.

The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power supply for supplying power to the power supply circuit may be an external commercial power supply or a power supply using a separately provided battery 8011. The battery 8011 can be omitted when using a commercial power source.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

13 (A) to 13 (G) are diagrams showing electronic devices. These electronic devices include housing 9000, display unit 9001, speaker 9003, operation key 9005 (including power switch or operation switch), connection terminal 9006, sensor 9007 (force, displacement, position, speed, acceleration, angular velocity, Includes the ability to measure speed, distance, light, liquid, magnetism, temperature, chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared. ), Microphone 9008, etc.

The electronic devices shown in FIGS. 13 (A) to 13 (G) can have various functions.

For example, a function to display various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), Wireless communication function, function to connect to various computer networks using wireless communication function, function to transmit or receive various data using wireless communication function, read and display programs or data recorded on recording media It can have a function of displaying on a unit, and the like. The functions that the electronic devices shown in FIGS. 13 (A) to 13 (G) can have are not limited to these, and can have various functions. Further, although not shown in FIGS. 13 (A) to 13 (G), the electronic device may have a configuration having a plurality of display units. In addition, the electronic device is provided with a camera or the like, a function for shooting a still image, a function for shooting a moving image, a function for saving the shot image on a recording medium (external or built in the camera), and a function for displaying the shot image on the display unit. It may have a function to perform, etc.

The details of the electronic devices shown in FIGS. 13 (A) to 13 (G) will be described below.

FIG. 13A is a perspective view showing the mobile information terminal 9100. The display unit 9001 included in the mobile information terminal 9100 has flexibility. Therefore, it is possible to incorporate the display unit 9001 along the curved surface of the curved housing 9000. In addition, the display unit 9001 is equipped with a touch sensor and can be operated by touching the screen with a finger or stylus. For example, the application can be started by touching the icon displayed on the display unit 9001.

FIG. 13B is a perspective view showing the mobile information terminal 9101. The mobile information terminal 9101 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone. Although the mobile information terminal 9101 is shown by omitting the speaker 9003, the connection terminal 9006, the sensor 9007, etc., the mobile information terminal 9101 can be provided at the same position as the mobile information terminal 9100 shown in FIG. 13 (A). In addition, the mobile information terminal 9101 can display character and image information on a plurality of surfaces thereof. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one side of the display unit 9001. Further, the information 9051 indicated by the broken line rectangle can be displayed on the other surface of the display unit 9001. As an example of information 9051, a display notifying an incoming call such as e-mail, SNS (social networking service), or telephone, a title such as e-mail or SNS, a sender name such as e-mail or SNS, date and time, and time. , Battery level, antenna reception strength, etc. Alternatively, the operation button 9050 or the like may be displayed instead of the information 9051 at the position where the information 9051 is displayed.

FIG. 13C is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user of the mobile information terminal 9102 can check the display (here, information 9053) with the mobile information terminal 9102 stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position that can be observed from above the mobile information terminal 9102. The user can check the display and determine whether or not to receive the call without taking out the mobile information terminal 9102 from his pocket.

FIG. 13 (D) is a perspective view showing a wristwatch-type mobile information terminal 9200. The personal digital assistant 9200 can execute various applications such as mobile phone, e-mail, text viewing and writing, music playback, Internet communication, and computer games. Further, the display unit 9001 is provided with a curved display surface, and can display along the curved display surface. In addition, the mobile information terminal 9200 can execute short-range wireless communication with communication standards. For example, by communicating with a headset capable of wireless communication, it is possible to make a hands-free call. Further, the mobile information terminal 9200 has a connection terminal 9006, and can directly exchange data with another information terminal via a connector. It can also be charged via the connection terminal 9006. The charging operation may be performed by wireless power supply without going through the connection terminal 9006.

13 (E) (F) (G) is a perspective view showing a foldable mobile information terminal 9201. Further, FIG. 13 (E) is a perspective view of the mobile information terminal 9201 in the expanded state, and FIG. 13 (F) shows the state in which the mobile information terminal 9201 is in the process of being changed from one of the expanded state or the folded state to the other. FIG. 13 (G) is a perspective view of the mobile information terminal 9201 in a folded state. The mobile information terminal 9201 is excellent in portability in the folded state, and is excellent in the listability of the display due to the wide seamless display area in the unfolded state. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the mobile information terminal 9201 can be reversibly transformed from the unfolded state to the folded state. For example, the mobile information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

The electronic device described in the present embodiment is characterized by having a display unit for displaying some information. However, the semiconductor device of one aspect of the present invention can also be applied to an electronic device having no display unit. Further, in the display unit of the electronic device described in the present embodiment, a configuration having flexibility and being able to display along a curved display surface, or a configuration of a foldable display unit has been exemplified. However, the present invention is not limited to this, and the configuration may be such that the display is performed on a flat surface portion without having flexibility.

The configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate.

<p>In this example, samples for analysis of samples A1 to A3 were prepared, and SIMS analysis of the samples for analysis was performed.</p><p>First, the analytical sample prepared in this example will be described below.</p><p>(Sample A1 to Sample A3) First, an oxide semiconductor film having a thickness of 100 nm was formed on a glass substrate having a thickness of 0.7 mm. The composition of the oxide semiconductor film is different between the sample A1, the sample A2, and the sample A3.</p><p>As the oxide semiconductor film of sample A1, the substrate temperature is set to 170 ° C, argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm are introduced into the chamber, the pressure is set to 0.6 Pa, and polycrystalline metal oxide sputtering is performed. Target Polycrystalline metal oxide sputtering A film was formed by applying 2500 W of AC power to a target (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio]).</p><p>As the oxide semiconductor film of sample A2, the substrate temperature was set to 170 ° C, argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber, the pressure was set to 0.6 Pa, and polycrystalline metal oxide sputtering was performed. An AC power of 2500 W was applied to the target (In: Ga: Zn = 3: 1: 2 [atomic number ratio]) to form a film.</p><p>As the oxide semiconductor film of sample A3, the substrate temperature was set to 170 ° C, argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber, the pressure was set to 0.6 Pa, and polycrystalline metal oxide sputtering was performed. An AC power of 2500 W was applied to the target (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]) to form a film.</p><p>Next, heat treatment was performed. The heat treatment was performed in a nitrogen atmosphere at 450 ° C for 1 hour, followed by a heat treatment at 450 ° C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen. In this example, each sample was heat-treated at 450 ° C in order to reduce the hydrogen concentration in the oxide semiconductor film, but in the process of manufacturing an actual transistor, the heat treatment is performed at 350 ° C or less. Is more preferable.</p><p>By the above steps, Sample A1 to Sample A3 of this example were prepared.</p><p>Next, SIMS analysis was performed in order to measure the hydrogen concentration in the oxide semiconductor film of the prepared samples A1 to A3. The analysis results of samples A1 to A3 are shown in FIG. In FIG. 14, the vertical axis is the hydrogen concentration (atoms / cm).³), And the horizontal axis represents the depth (nm).</p><p>From the results shown in Fig. 14, the hydrogen concentration in the oxide semiconductor film of sample A1 is 6.33 × 10.¹⁹atoms / cm³Met. The hydrogen concentration in the oxide semiconductor film of sample A2 is 8.64 × 10.¹⁸atoms / cm³Met. The hydrogen concentration in the oxide semiconductor film of sample A3 is 1.46 × 10.¹⁹atoms / cm³Met. The hydrogen concentration in the oxide semiconductor film here is a numerical value at a film thickness of 50 nm.</p><p>For example, by forming the oxide semiconductor film of sample A1 on the oxide semiconductor film of sample A2, the IGZO film (In: Ga: Zn = 3: 1: 2) \ IGZO film (In: Ga: Zn =) The structure is 1: 1: 1.2). Alternatively, by forming the oxide semiconductor film of sample A1 on the oxide semiconductor film of sample A3, the IGZO film (In: Ga: Zn = 4: 2: 4.1) \ IGZO film (In: Ga: Zn =) The structure is 1: 1: 1.2).</p><p>As described above, in the semiconductor device of one aspect of the present invention, it is preferable to form the oxide semiconductor film in a laminated structure so that the hydrogen concentration of the upper oxide semiconductor film is higher than that of the lower oxide semiconductor film. Further, in the lower oxide semiconductor film, the atomic number ratio of In is larger than the atomic number ratio of Ga, and the atomic number ratio of In in the upper oxide semiconductor film is smaller than that in the lower oxide semiconductor film. By forming a laminated structure of oxide semiconductor films having such a composition, it is possible to obtain a semiconductor device having high field effect mobility and high reliability.</p><p>The configuration shown in this embodiment may be used in combination with other embodiments or other embodiments as appropriate.</p>

<p>In this example, the amount of hydrogen and water released from the insulating film of the semiconductor device according to one aspect of the present invention was evaluated using TDS. In addition, defects that serve as carrier traps in the insulating film of the semiconductor device of one aspect of the present invention were evaluated using ESR. In this example, the following samples B1 to B4 and samples C1 to C4 were prepared.</p><p>First, the details of Sample B1 to Sample B4 will be described.</p><p>&lt;Sample B1&gt; Sample B1 has a structure in which a silicon nitride film having a thickness of 100 nm is formed on a glass substrate.</p><p>As the film forming conditions for the silicon nitride film of sample B1, the substrate temperature was set to 350 ° C, silane gas with a flow rate of 200 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was 100 Pa. Then, 2000 W of RF power was supplied between the electrodes of the parallel flat plate installed in the PECVD equipment to form a film.</p><p>&lt;Sample B2&gt; Sample B2 has a structure in which a silicon nitride film having a thickness of 100 nm is formed on a glass substrate.</p><p>As the film forming condition of the silicon nitride film of the sample B2, the flow rate of ammonia gas was set to 2000 sccm, and the silicon nitride film was formed. The conditions other than the flow rate of ammonia gas were the same as those of sample B1.</p><p>&lt;Sample B3&gt; Sample B3 has a structure in which a silicon oxide film having a thickness of 200 nm is formed on a glass substrate.</p><p>As the film forming conditions for the silicon oxide film of sample B3, the substrate temperature was set to 350 ° C, silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 3000 sccm were introduced into the chamber, the pressure was set to 40 Pa, and PECVD was performed. A film was formed by supplying 1000 W of RF power between the electrodes of the parallel flat plate installed in the device.</p><p>&lt;Sample B4&gt; Sample B4 has a structure in which a silicon oxide film having a thickness of 200 nm is formed on a glass substrate.</p><p>As the film forming condition of the silicon oxynitride film of the sample B4, the RF power was set to 100 W, and the silicon oxynitride film was formed. The conditions other than RF power were the same as those for sample B3.</p><p>&lt;TDS measurement&gt; Next, TDS measurement of the above-prepared samples B1 to B4 was performed. In TDS measurement, each sample was heated from 50 ° C to 550 ° C, and the amount of gas contained in the insulating film in each sample was evaluated. In sample B1 and sample B2, the amount of hydrogen released from the silicon nitride film was evaluated. As the amount of hydrogen released, the amount of gas released having a mass-to-charge ratio (M / z) of 2 was measured. Further, in sample B3 and sample B4, H contained in the silicon oxynitride film is contained.₂The amount of O released was evaluated. In addition, H₂As the amount of O released, the amount of gas released having a mass-to-charge ratio (M / z) of 18 was measured.</p><p>FIG. 15A shows the TDS measurement result of sample B1, FIG. 15B shows the TDS measurement result of sample B2, FIG. 16A shows the TDS measurement result of sample B3, and FIG. 16B shows the sample. The TDS measurement results of B4 are shown below. In FIGS. 15 (A) (B) and 16 (A) (B), the vertical axis represents the strength (arbitrary unit) and the horizontal axis represents the substrate temperature (° C).</p><p>From the results shown in FIGS. 15 (A) and 15 (B), it was found that a silicon nitride film having a small amount of hydrogen released can be formed by reducing the flow rate of ammonia gas.</p><p>From the results shown in FIGS. 16 (A) and 16 (B), it was found that a silicon oxide film with a small amount of water released can be formed by increasing the RF power.</p><p>Next, the details of the samples C1 to C4 will be described.</p><p>&lt;Sample C1&gt; Sample C1 has a structure in which a silicon nitride film having a thickness of 100 nm is formed on a glass substrate.</p><p>As the film forming conditions for the silicon nitride film of sample C1, the substrate temperature was set to 350 ° C, silane gas with a flow rate of 200 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 100 Pa. , 2000W RF power was supplied between the electrodes of the parallel flat plate installed in the PECVD equipment to form a film.</p><p>&lt;Sample C2&gt; Sample C2 has a structure in which a silicon nitride film having a thickness of 100 nm is formed on a glass substrate.</p><p>As the film forming conditions for the silicon nitride film of sample C2, the substrate temperature was set to 280 ° C, silane gas with a flow rate of 100 sccm, nitrogen gas with a flow rate of 1000 sccm, and ammonia gas with a flow rate of 50 sccm were introduced into the chamber, and the pressure was set to 100 Pa. , 750W RF power was supplied between the electrodes of the parallel flat plate installed in the PECVD equipment to form a film.</p><p>&lt;Sample C3&gt; Sample C3 has a structure in which a silicon oxide film having a thickness of 100 nm is formed on a glass substrate.</p><p>As the film forming conditions for the silicon oxide nitride film, the substrate temperature was set to 280 ° C, silane gas with a flow rate of 50 sccm and dinitrogen monoxide gas with a flow rate of 1250 sccm were introduced into the chamber, the pressure was set to 20 Pa, and the pressure was set to 20 Pa in the PECVD equipment. A film was formed by supplying 750 W of RF power between the electrodes of the installed parallel flat plate.</p><p>&lt;Sample C4&gt; Sample C4 has a structure in which a silicon oxide film having a thickness of 100 nm is formed on a glass substrate.</p><p>As the sample C4, the silicon oxide film was formed with the RF power of 250 W under the film forming conditions of the silicon oxide film of the sample C3. The conditions other than RF power were the same as those for sample C3.</p><p>&lt;ESR measurement&gt; Next, the ESR measurement of the prepared samples C1 to C4 was performed. ESR measurement is the value of the magnetic field where microwave absorption occurs at a given temperature (H).₀) From the equation g = hν / βH₀, Is used to obtain a parameter called g value. Note that ν is the frequency of the microwave. h is Planck's constant and β is Bohr magneton, both of which are constants.</p><p>For sample C1 and sample C2, ESR measurement was performed under the following conditions. The measurement temperature was room temperature (25 ° C), the high frequency power (microwave power) of 9.2 GHz was 0.1 mW, and the direction of the magnetic field was parallel to the film surface of the prepared sample. The lower limit of detection of the spin density of the signal caused by K-center contained in the silicon nitride film is 1.5 × 10.¹⁶spins / cm³Met.</p><p>For sample C3 and sample C4, ESR measurement was performed under the following conditions. The measurement temperature was room temperature (25 ° C), the high frequency power (microwave power) of 9.2 GHz was 0.005 mW, and the direction of the magnetic field was parallel to the film surface of the prepared sample. The lower limit of detection of the spin density of the signal caused by E'-center contained in the silicon oxide nitride film is 1.5 × 10.¹⁶spins / cm³Met.</p><p>FIG. 17 is an ESR spectrum obtained by measuring the ESR of sample C1 and sample C2. FIG. 18 is an ESR spectrum obtained by measuring the ESR of the sample C3 and the sample C4.</p><p>As shown in FIG. 17, it can be seen that the intensity of the signal caused by the K-center is smaller in the sample C1 than in the sample C2. The K-center is a defect due to the dangling bond of silicon as shown in FIG. From this, it was found that a silicon nitride film having less silicon dangling bonds can be formed by supplying high RF power at a higher temperature under the film forming conditions.</p><p>As shown in FIG. 18, it can be seen that the intensity of the signal caused by E'-center is smaller in sample C3 than in sample C4. The E'-center is a defect due to the dangling bond of silicon as shown in FIG. From this, it was found that a silicon oxide film with less dangling bonds of silicon can be formed by supplying higher RF power under the film forming conditions.</p><p>The configuration shown in this embodiment may be used in combination with other embodiments or other embodiments as appropriate.</p>

<p>In this embodiment, a transistor corresponding to the transistor 170 shown in FIG. 3 was manufactured, and the ID-VG characteristics of the transistor were evaluated. In this example, the following samples D1 to D3 were prepared and evaluated. Note that Sample D1 and Sample D2 are samples having a transistor which is a comparative example, and Sample D3 is a sample having a transistor according to one aspect of the present invention. The samples D1 to D3 are a transistor having a channel length L = 2 μm and a channel width W = 50 μm, a transistor having a channel length L = 3 μm and a channel width W = 50 μm, and a channel length L = 6 μm and a channel width W =, respectively. It is a structure in which a total of three types of transistors with a size of 50 μm are formed.</p><p>The sample prepared in this example will be described below. In the following description, reference numerals will be given to the transistor 170 shown in FIG.</p><p>&lt;Method for producing sample D1&gt; First, the conductive film 104 was formed on the substrate 102. A glass substrate was used as the substrate 102. Further, as the conductive film 104, a tungsten film having a thickness of 100 nm was formed by using a sputtering device.</p><p>Next, the insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the insulating film 106, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. As the insulating film 107, a silicon oxynitride film having a thickness of 50 nm was formed using a PECVD apparatus.</p><p>As the film forming conditions for the insulating film 106, the substrate temperature was set to 350 ° C, silane gas with a flow rate of 200 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 100 Pa. 2000W RF power is supplied between the electrodes of the parallel flat plate installed inside to form a silicon nitride film with a thickness of 50nm, and then the flow rate of ammonia gas is changed to 2000sccm to make the thickness 300nm. A silicon nitride film was formed, and then the flow rate of ammonia gas was changed to 100 sccm to form a silicon nitride film having a thickness of 50 nm.</p><p>As the film forming conditions for the insulating film 107, the substrate temperature was set to 350 ° C, silane gas with a flow rate of 20 sccm and nitrous oxide gas with a flow rate of 3000 sccm were introduced into the chamber, the pressure was set to 40 Pa, and the pressure was set to 40 Pa in the PECVD equipment. An RF power of 100 W was supplied between the electrodes of the installed parallel flat plate to form a film.</p><p>Next, the oxide semiconductor film 108 was formed on the insulating film 107. As the oxide semiconductor film 108, a single-layer IGZO film was formed using a sputtering device. Further, as the oxide semiconductor film 108, an IGZO film having a thickness of 35 nm was formed. As the film forming conditions for the oxide semiconductor film 108, the substrate temperature was set to 170 ° C, argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 Pa. Metal Oxide Sputtering Target (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio]</p><p>) Was applied with 2500 W of AC power to form a film.</p><p>Next, the first heat treatment was performed. As the first heat treatment, a heat treatment at 450 ° C for 1 hour was performed in a nitrogen atmosphere, followed by a heat treatment at 450 ° C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.</p><p>Next, the conductive films 112a and 112b were formed on the insulating film 107 and the oxide semiconductor film 108. As the conductive films 112a and 112b, a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm were continuously formed in a vacuum using a sputtering device.</p><p>Next, the insulating film 114 and the insulating film 116 were formed on the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. As the insulating film 114, a silicon oxynitride film having a thickness of 50 nm was formed using a PECVD apparatus. As the insulating film 116, a silicon oxynitride film having a thickness of 400 nm was formed using a PECVD apparatus. The insulating film 114 and the insulating film 116 were continuously formed in vacuum by a PECVD apparatus.</p><p>As the film forming conditions for the insulating film 114, the substrate temperature was set to 220 ° C, silane gas with a flow rate of 50 sccm and nitrous oxide gas with a flow rate of 2000 sccm were introduced into the chamber, the pressure was set to 20 Pa, and the film was installed in the PECVD equipment. An RF power of 100 W was supplied between the electrodes of the parallel flat plate to form a film. As the film forming conditions for the insulating film 116, the substrate temperature was set to 220 ° C, silane gas with a flow rate of 160 sccm and nitrous oxide gas with a flow rate of 4000 sccm were introduced into the chamber, the pressure was set to 200 Pa, and the pressure was set in the PECVD equipment. An RF power of 1500 W was supplied between the electrodes of the installed parallel flat plate to form a film.</p><p>Next, a second heat treatment was performed. The second heat treatment was performed at 350 ° C for 1 hour in a nitrogen gas atmosphere.</p><p>Next, the following two steps were performed.</p><p>(1. ITSO film forming step) An ITSO film having a thickness of 5 nm was formed on the insulating film 116 by using a sputtering device. And, oxygen gas with a flow rate of 5 sccm was introduced into the chamber, the pressure was set to 0.15 Pa, and the metal oxide target (In) installed in the sputtering device.₂O₃: SnO₂: SiO₂= 85: 10: 5 [weight%]) was supplied with 1000 W of DC power to form a film.</p><p>(2. Oxygen addition treatment step) Next, oxygen addition treatment was performed on the oxide semiconductor film 108 and the insulating films 114 and 116 via the ITSO film. As the oxygen addition treatment, an ashing device is used, the substrate temperature is set to 40 ° C, oxygen gas having a flow rate of 250 sccm is introduced into the chamber, the pressure is set to 15 Pa, and the ashing device is applied so that a bias is applied to the substrate side. RF power of 4500W was supplied for 600 seconds between the electrodes of the parallel plate installed inside.</p><p>Next, the substrate temperature was set to 350 ° C., and after heat treatment in a nitrogen atmosphere of 175 Pa, an insulating film 118 was formed on the ITSO film. As the insulating film 118, a silicon nitride film having a thickness of 100 nm was formed using a PECVD apparatus.</p><p>Next, the openings 142c reaching the conductive film 112b and the openings 142a and 142b reaching the conductive film 104 were formed. The openings 142a, 142b, and 142c were formed using a dry etching apparatus.</p><p>Next, a conductive film was formed on the insulating film 118 so as to cover the openings 142a, 142b, 142c, and the conductive film was processed to form the conductive films 120a, 120b. As the conductive films 120a and 120b, an ITSO film having a thickness of 100 nm was formed by using a sputtering device. The composition of the target used for the ITSO film was the same as the composition used in the ITSO film forming step described above.</p><p>Next, a third heat treatment was performed. The third heat treatment was performed at 250 ° C. for 1 hour in a nitrogen gas atmosphere.</p><p>Sample D1 of this example was prepared by the above steps. The maximum temperature in the process of sample D1 was 450 ° C.</p><p>&lt;Method for preparing sample D2&gt; Sample D2 differs from sample D1 shown above in the following steps. The other steps were the same as for sample D1.</p><p>The first heat treatment was not performed on the sample D2.</p><p>Further, in the sample D2 (2, oxygen addition treatment step), the oxygen addition treatment time was set to 120 sec. Next, the ITSO film was removed to expose the insulating film 116. As a method for removing the ITSO film, a wet etching device is used, etching is performed for 300 seconds using an aqueous solution of oxalic acid having a concentration of 5%, and then etching is performed for 15 seconds using hydrofluoric acid having a concentration of 0.5%. Was done.</p><p>Next, the insulating film 118 was formed on the insulating film 116 without heat treatment.</p><p>The sample D2 of this example was prepared by the above steps. The maximum temperature in the process of sample D2 was 350 ° C.</p><p>&lt;Method for preparing sample D3&gt; Sample D3 differs from sample D1 shown above in the following steps. The other steps were the same as for sample D1.</p><p>In sample D3, the oxide semiconductor film 108 includes a first oxide semiconductor film 108a on the conductive film side 104 that functions as a gate electrode and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a. Was formed by laminating. Further, an IGZO film having a thickness of 10 nm was formed as the first oxide semiconductor film 108a, and an IGZO film having a thickness of 15 nm was formed as the second oxide semiconductor film 108b.</p><p>As the film forming conditions for the first oxide semiconductor film 108a, the substrate temperature was set to 170 ° C, argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 Pa. A film was formed by applying 2500 W of AC power to a polycrystalline metal oxide sputtering target (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]).</p><p>As the film forming conditions for the second oxide semiconductor film 108b, the substrate temperature was set to 170 ° C, argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 Pa. A film was formed by applying 2500 W of AC power to a polycrystalline metal oxide sputtering target (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio]).</p><p>Further, the sample D3 was not subjected to the first heat treatment.</p><p>Further, in the sample D3 (2, oxygen addition treatment step), the oxygen addition treatment time was set to 120 sec. Next, the ITSO film was removed to expose the insulating film 116. As a method for removing the ITSO film, a wet etching device is used, etching is performed for 300 seconds using an aqueous solution of oxalic acid having a concentration of 5%, and then etching is performed for 15 seconds using hydrofluoric acid having a concentration of 0.5%. Was done.</p><p>Next, the insulating film 118 was formed on the insulating film 116 without heat treatment.</p><p>The sample D3 of this example was prepared by the above steps. The maximum temperature in the process of sample D3 was 350 ° C.</p><p>Next, the ID-VG characteristics of the prepared samples D1 to D3 were measured. The ID-VG characteristic results of Samples D1 to D3 are shown in FIGS. 19 to 21. Note that FIG. 19 shows the ID-VG characteristic result of sample D1, FIG. 20 shows the ID-VG characteristic result of sample D2, and FIG. 21 shows the ID-VG characteristic result of sample D3. Further, in FIGS. 19 to 21, the vertical axis represents ID (A) and the horizontal axis represents VG (V). Further, in FIGS. 19 to 21, (A) is the ID-VG characteristic result of the transistor having a channel length L = 2 μm and a channel width W = 50 μm, and (B) is a channel length L = 3 μm and a channel width W. It is the ID-VG characteristic result of the transistor of = 50 μm, and (C) is the ID-VG characteristic result of the transistor of the channel length L = 6 μm and the channel width W = 50 μm.</p><p>Further, a voltage applied to the conductive film 104 functioning as the first gate electrode of the transistor 170 (hereinafter, also referred to as a gate voltage (VG)) and a voltage applied to the conductive film 120b functioning as the second gate electrode (hereinafter, also referred to as a gate voltage (VG)). VBG) was applied in steps of 0.25V from -15V to + 20V. Further, the voltage applied to the conductive film 112a functioning as the source electrode (hereinafter, also referred to as source voltage (VS)) is set to 0V (commom), and the voltage applied to the conductive film 112b functioning as the drain electrode (hereinafter, drain voltage). (Also called (VD)) was set to 1V or 10V.</p><p>From the results shown in FIGS. 19 to 21, it was confirmed that there was no significant difference in the ID-VG characteristics of the transistors even when the maximum temperature in the process was lowered from 450 ° C to 350 ° C. Further, as compared with the sample D2, the sample D3 has a laminated structure of the oxide semiconductor film, so that the variation in the electrical characteristics is reduced. In addition, sample D3 has an improved on-current and a low subthreshold swing value. As described above, it was confirmed that the semiconductor device of one aspect of the present invention has excellent electrical characteristics.</p><p>Next, the reliability of the prepared samples D1 to D3 was evaluated. As a reliability evaluation, a bias-heat stress test (hereinafter referred to as GBT test) was used.</p><p>The GBT test conditions in this example are as follows: gate voltage (VG) is ± 30V, drain voltage (VD) and source voltage (VS) are 0V (COMMON), stress temperature is 60 ° C, and stress is applied. The time was set to 1 hour, and the measurement environment was set to two environments, a dark environment and a light irradiation environment (irradiating light of about 10000 lx with a white LED). That is, the source electrode and the drain electrode of the transistor were set to the same potential, and a potential different from that of the source electrode and the drain electrode was applied to the gate electrode for a certain period of time (here, 1 hour). Further, the case where the potential applied to the gate electrode was higher than the potentials of the source electrode and the drain electrode was defined as positive stress, and the case where the potential applied to the gate electrode was lower than the potentials of the source electrode and the drain electrode was defined as negative stress. Therefore, the reliability was evaluated under a total of 4 conditions of plus GBT stress (dark), minus GBT stress (dark), plus GBT stress (light irradiation), and minus GBT stress (light irradiation), together with the measurement environment. ..</p><p>The GBT test results of Samples D1 to D3 are shown in FIG. In FIG. 22, the vertical axis indicates the amount of change in the threshold voltage of the transistor (ΔVth) and the amount of change in the shift value (ΔShift), and the horizontal axis indicates each sample name, process conditions, and the like. The Shift value is the tangent of the maximum slope of the drain current (ID) expressed in logarithm in the drain current (ID) -gate voltage (VG) characteristics of the transistor and 1 × 10.^-12The gate voltage (VG) at the intersection with the axis of A. Further, ΔShift is the amount of change in the Shift value.</p><p>From the results shown in FIG. 22, the amount of change in the threshold voltage (ΔVth) of the sample D2 was about three times that of the sample D1. On the other hand, in the sample D3 of one aspect of the present invention, the amount of change in the threshold voltage (ΔVth) in the GBT test was about twice that of the sample D1. It was confirmed that even if the maximum temperature in the process was lowered from 450 ° C to 350 ° C, the decrease in reliability could be suppressed by forming the oxide semiconductor film in a laminated structure.</p><p>Subsequently, for Samples D1 to D3, the amount of change in the threshold voltage when the plus gate BT stress test (Dark + GBT) and the minus gate BT stress test (Dark -GBT) were repeated alternately was measured. .. As a measurement method, the ID-VG characteristics of the transistor were first measured (initial). After that, the plus gate BT stress test and the minus gate BT stress test were alternately performed twice. In each gate BT stress test, the stress temperature was 60 ° C and the stress time was 3600 seconds. Here, measurements were made for a transistor with a channel length L = 6 μm and a channel width W = 50 μm.</p><p>FIG. 23 shows the threshold voltages of Samples D1 to D3 before the stress test (initial) and after each gate BT stress test. In FIG. 23, the vertical axis shows the threshold voltage (Vth) when the drain voltage is 10 V, and the horizontal axis shows the stress test name. In addition, FIG. 23 shows before the stress test (initial), after the plus gate BT stress test (+ GBT), after the minus gate BT stress test (-GBT), after the plus gate BT stress test (+ GBT), and minus gate BT stress. It is the result of performing GBT test alternately in the order after the test (-GBT).</p><p>Here, when the plus gate BT stress test and the minus gate BT stress test are alternately performed and the threshold voltage value repeatedly increases and decreases, the carrier to the trap level due to the voltage application to the gate electrode. It is presumed that the fluctuation of the threshold voltage is caused by the trap and detrap of. On the other hand, when the change in the threshold voltage is biased in one direction (for example, when it tends to gradually increase or decrease), the threshold voltage due to the carriers trapped at the trap level behaving as a fixed charge. It is presumed that it is a fluctuation of.</p><p>From the results shown in FIG. 23, the threshold voltage of the transistor after each gate BT stress test is smaller in the sample D3 of one aspect of the present invention than in the sample D2. Recognize.</p><p>From the above, one aspect of the present invention is to improve reliability and suppress variations in electrical characteristics by forming an oxide semiconductor film in a laminated structure even if the process temperature is lowered, as in the transistor of sample D3. It was shown that it has excellent electrical characteristics, which are satisfied with the improvement of on-current and the low S value.</p><p>As described above, the configuration shown in this embodiment can be used in combination with other embodiments or examples as appropriate.</p>

<p>In this embodiment, a transistor corresponding to the transistor 170 shown in FIG. 3 was manufactured, and the ID-VG characteristics of the transistor were evaluated. In this example, the following samples E1 and E2 were prepared and evaluated. The sample E1 is a sample having a transistor which is a comparative example, and the sample E2 is a sample having a transistor of one aspect of the present invention. In addition, Sample E1 and Sample E2 have a transistor with a channel length L = 2 μm and a channel width W = 50 μm, a transistor with a channel length L = 3 μm and a channel width W = 50 μm, and a channel length L = 6 μm and a channel width W =, respectively. It is a structure in which a total of three types of transistors with a size of 50 μm are formed. In addition, 40 of the above three types of transistors were formed in each of the three substrates.</p><p>The sample prepared in this example will be described below. In the following description, reference numerals will be given to the transistor 170 shown in FIG.</p><p>&lt;Method for producing sample E1&gt; First, the conductive film 104 was formed on the substrate 102. A glass substrate was used as the substrate 102. The size of the glass substrate was 600 mm x 720 mm and the thickness was 0.7 mm. Further, as the conductive film 104, a tungsten film having a thickness of 100 nm was formed by using a sputtering device.</p><p>Next, the insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the insulating film 106, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. As the insulating film 107, a silicon oxynitride film having a thickness of 50 nm was formed using a PECVD apparatus.</p><p>As the film forming conditions for the insulating film 106, the substrate temperature was set to 350 ° C, silane gas with a flow rate of 200 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 100 Pa. 2000W RF power is supplied between the electrodes of the parallel flat plate installed inside to form a silicon nitride film with a thickness of 50nm, and then the flow rate of ammonia gas is changed to 2000sccm to make the thickness 300nm. A silicon nitride film was formed, and then the flow rate of ammonia gas was changed to 100 sccm to form a silicon nitride film having a thickness of 50 nm.</p><p>As the film forming conditions for the insulating film 107, the substrate temperature was set to 350 ° C, silane gas with a flow rate of 20 sccm and nitrous oxide gas with a flow rate of 3000 sccm were introduced into the chamber, the pressure was set to 40 Pa, and the pressure was set to 40 Pa in the PECVD equipment. An RF power of 100 W was supplied between the electrodes of the installed parallel flat plate to form a film.</p><p>Next, the oxide semiconductor film 108 was formed on the insulating film 107. The oxide semiconductor film 108 is formed by laminating a first oxide semiconductor film 108a on the conductive film side 104 that functions as a gate electrode and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a. Formed. Further, an IGZO film having a thickness of 10 nm was formed as the first oxide semiconductor film 108a, and an IGZO film having a thickness of 15 nm was formed as the second oxide semiconductor film 108b.</p><p>As the film forming conditions for the first oxide semiconductor film 108a, the substrate temperature was set to 170 ° C, argon gas with a flow rate of 140 sccm and oxygen gas with a flow rate of 60 sccm were introduced into the chamber, and the pressure was set to 0.6 Pa. A film was formed by applying 2500 W of AC power to a polycrystalline metal oxide sputtering target (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]).</p><p>As the film forming conditions for the second oxide semiconductor film 108b, the substrate temperature was set to 170 ° C, argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 Pa. A film was formed by applying 2500 W of AC power to a polycrystalline metal oxide sputtering target (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio]).</p><p>Next, the first heat treatment was performed. As the first heat treatment, a heat treatment at 450 ° C for 1 hour was performed in a nitrogen atmosphere, followed by a heat treatment at 450 ° C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.</p><p>Next, the conductive films 112a and 112b were formed on the insulating film 107 and the oxide semiconductor film 108. As the conductive films 112a and 112b, a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm were continuously formed in a vacuum using a sputtering device.</p><p>Next, the insulating film 114 and the insulating film 116 were formed on the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. As the insulating film 114, a silicon oxynitride film having a thickness of 50 nm was formed using a PECVD apparatus. As the insulating film 116, a silicon oxynitride film having a thickness of 400 nm was formed using a PECVD apparatus. The insulating film 114 and the insulating film 116 were continuously formed in vacuum by a PECVD apparatus.</p><p>As the film forming conditions for the insulating film 114, the substrate temperature was set to 220 ° C, silane gas with a flow rate of 50 sccm and nitrous oxide gas with a flow rate of 2000 sccm were introduced into the chamber, the pressure was set to 20 Pa, and the film was installed in the PECVD equipment. An RF power of 100 W was supplied between the electrodes of the parallel flat plate to form a film. As the film forming conditions for the insulating film 116, the substrate temperature was set to 220 ° C, silane gas with a flow rate of 160 sccm and nitrous oxide gas with a flow rate of 4000 sccm were introduced into the chamber, the pressure was set to 200 Pa, and the pressure was set in the PECVD equipment. An RF power of 1500 W was supplied between the electrodes of the installed parallel flat plate to form a film.</p><p>Next, a second heat treatment was performed. The second heat treatment was performed at 350 ° C for 1 hour in a nitrogen gas atmosphere.</p><p>Next, the following three steps were performed.</p><p>(1. ITSO film forming step) An ITSO film having a thickness of 5 nm was formed on the insulating film 116 using a sputtering device. As the film forming conditions of the ITSO film, the substrate temperature was set to room temperature, argon gas having a flow rate of 72 sccm and oxygen gas having a flow rate of 5 sccm were introduced into the chamber, the pressure was set to 0.15 Pa, and the metal oxidation installed in the sputtering apparatus was performed. Object target (In₂O₃: SnO₂: SiO₂= 85: 10: 5 [weight%]) was supplied with 1000 W of DC power to form a film.</p><p>(2. Oxygen addition treatment step) Next, oxygen addition treatment was performed on the oxide semiconductor film 108 and the insulating films 114 and 116 via the ITSO film. As the oxygen addition treatment, an ashing device is used, the substrate temperature is set to 40 ° C, oxygen gas having a flow rate of 250 sccm is introduced into the chamber, the pressure is set to 15 Pa, and the ashing device is applied so that a bias is applied to the substrate side. RF power of 4500W was supplied for 120 seconds between the electrodes of the parallel flat plate installed inside.</p><p>(3, ITSO film removing step) Next, the ITSO film was removed to expose the insulating film 116. As a method for removing the ITSO film, a wet etching device is used, etching is performed for 300 seconds using an aqueous solution of oxalic acid having a concentration of 5%, and then etching is performed for 15 seconds using hydrofluoric acid having a concentration of 0.5%. Was done.</p><p>Next, the insulating film 118 was formed on the insulating film 116. As the insulating film 118, a silicon nitride film having a thickness of 100 nm was formed using a PECVD apparatus. The substrate temperature in the PECVD apparatus at the time of forming the insulating film 118 was set to 350 ° C.</p><p>Next, the openings 142c reaching the conductive film 112b and the openings 142a and 142b reaching the conductive film 104 were formed. The openings 142a, 142b, and 142c were formed using a dry etching apparatus.</p><p>Next, a conductive film was formed on the insulating film 118 so as to cover the openings 142a, 142b, 142c, and the conductive film was processed to form the conductive films 120a, 120b. As the conductive films 120a and 120b, an ITSO film having a thickness of 100 nm was formed by using a sputtering device. The composition of the target used for the ITSO film was the same as the composition used in the ITSO film forming step described above.</p><p>Next, a third heat treatment was performed. The third heat treatment was performed at 250 ° C. for 1 hour in a nitrogen gas atmosphere.</p><p>The sample E1 of this example was prepared by the above steps. The maximum temperature in the process of sample E1 was 450 ° C.</p><p>&lt;Method for preparing sample E2&gt; Sample E2 differs from sample E1 shown above in the following steps. The other steps were the same as for sample E1.</p><p>The first heat treatment was not performed on the sample E2.</p><p>The sample E2 of this example was prepared by the above steps. The maximum temperature in the process of sample E2 was 350 ° C.</p><p>Next, the ID-VG characteristics of the prepared samples E1 and E2 were measured. The ID-VG characteristic results of sample E1 and sample E2 are shown in FIGS. 24 and 25. In addition, FIG. 24 is the ID-VG characteristic result of the sample E1, and FIG. 25 is the ID-VG characteristic result of the sample E2. Further, in FIGS. 24 and 25, the first vertical axis is ID (A) and the second vertical axis is μFE (cm).²/ Vs) and VG (V) on the horizontal axis. Further, in FIGS. 24 and 25, (A) is the ID-VG characteristic result of the transistor having a channel length L = 2 μm and a channel width W = 50 μm, and (B) is a channel length L = 3 μm and a channel width W. It is the ID-VG characteristic result of the transistor of = 50 μm, and (C) is the ID-VG characteristic result of the transistor of the channel length L = 6 μm and the channel width W = 50 μm. Further, in FIGS. 24 and 25, a total of 10 transistor characteristics are superimposed and displayed.</p><p>Further, a voltage applied to the conductive film 104 functioning as the first gate electrode of the transistor 170 (hereinafter, also referred to as a gate voltage (VG)) and a voltage applied to the conductive film 120b functioning as the second gate electrode (hereinafter, also referred to as a gate voltage (VG)). VBG) was applied in steps of 0.25V from -15V to + 20V. The voltage applied to the conductive film 104 and the conductive film 120b was changed from -15V to + 15V only for the transistor having the channel length L = 2 μm and the channel width W = 50 μm. Further, the voltage applied to the conductive film 112a functioning as the source electrode (hereinafter, also referred to as source voltage (VS)) is set to 0V (common), and the voltage applied to the conductive film 112b functioning as the drain electrode (hereinafter, drain voltage). (Also called (VD)) was set to 0.1V or 20V. Regarding the field effect mobility (μFE), the result of VD = 20V is shown.</p><p>From the results shown in FIGS. 24 and 25, it was confirmed that there was no significant difference in the ID-VG characteristics of the transistors even when the maximum temperature in the process was lowered from 450 ° C to 350 ° C.</p><p>Next, the variation in the substrate surface (600 mm × 720 mm) of the transistor having the channel length L = 3 μm and the channel width W = 50 μm of the sample E1 and the sample E2 was evaluated.</p><p>First, the ID-VG characteristics of the transistors of Sample E1 and Sample E2 with a channel length L = 3 μm and a channel width W = 50 μm were evaluated. The ID-VG characteristic results of sample E1 and sample E2 are shown in FIGS. 26 (A) and 26 (B). Note that FIG. 26 (A) is the ID-VG characteristic result of sample E1, and FIG. 26 (B) is the ID-VG characteristic result of sample E2. Further, in FIGS. 26 (A) and 26 (B), the vertical axis represents ID (A) and the horizontal axis represents VG (V). Further, in FIGS. 26 (A) and 26 (B), a total of 40 transistor characteristics are superimposed and displayed. The ID-VG characteristics shown in FIGS. 26 (A) and 26 (B) differ from the ID-VG characteristics shown in FIGS. 24 and 25 in measurement conditions. Specifically, as the measurement conditions for the ID-VG characteristics shown in FIGS. 26 (A) and 26 (B), the gate voltage (VG) and (VBG) are conductive films from -15V to + 20V in steps of 0.25V. It was applied to 104 and the conductive film 120b. The source voltage (VS) was set to 0V (common), and the drain voltage (VD) was set to 10V.</p><p>Next, the results of comparing the variations of the threshold voltage (Vth) and the on-current (Ion) of the transistors of the samples E1 and E2 shown in FIGS. 26 (A) and 26 (B) are shown in FIGS. 27 (A) (A). Shown in B). Note that FIG. 27 (A) is a diagram for explaining the probability distribution of Vth in the substrate surface (600 mm × 720 mm), and FIG. 27 (B) is a diagram showing the probability of Ion in the substrate surface (600 mm × 720 mm). It is a figure explaining the distribution. In FIG. 27 (B), Ion was set to the value at VG = 20V.</p><p>From the results shown in FIGS. 26 and 27, it was confirmed that the sample E2 had a good transistor characteristic with little variation in the substrate surface, although a slight decrease in Ion was confirmed as compared with the sample E1.</p><p>Next, the reliability of the prepared samples E1 and E2 was evaluated. The GBT test was used as the reliability evaluation.</p><p>The GBT test conditions in this example are as follows: gate voltage (VG) is ± 30V, drain voltage (VD) and source voltage (VS) are 0V (COMMON), stress temperature is 60 ° C, and stress is applied. The time was set to 1 hour, and the measurement environment was set to two environments, a dark environment and a light irradiation environment (irradiating light of about 10000 lx with a white LED). That is, the source electrode and the drain electrode of the transistor were set to the same potential, and a potential different from that of the source electrode and the drain electrode was applied to the gate electrode for a certain period of time (here, 1 hour). Further, the case where the potential applied to the gate electrode was higher than the potentials of the source electrode and the drain electrode was defined as positive stress, and the case where the potential applied to the gate electrode was lower than the potentials of the source electrode and the drain electrode was defined as negative stress. Therefore, the reliability was evaluated under a total of 4 conditions of plus GBT stress (dark), minus GBT stress (dark), plus GBT stress (light irradiation), and minus GBT stress (light irradiation), together with the measurement environment. .. In addition, plus GBT stress (dark) is PBTS (Positive Bias) Temperature Stress), minus GBT stress (dark) is NBTS (Nagative Bias Temperature Stress), plus GBT stress (light irradiation) is PBITS (Positive Bias Illuminations Temperature Stress), and minus GBT stress (light irradiation) is NBITS (Nagative). Bias Illuminations Temperature Stress) may be described below.</p><p>The GBT test results of sample E1 and sample E2 are shown in FIG. 28. In FIG. 28, the vertical axis indicates the amount of change in the threshold voltage of the transistor (ΔVth) and the amount of change in the shift value (ΔShift), and the horizontal axis indicates each sample name, process conditions, and the like.</p><p>From the results shown in FIG. 28, it can be confirmed that the sample E2 has a slightly larger change in threshold voltage (ΔVth) than the sample E1, but the negative fluctuation of GBT is 1 V or less and the positive fluctuation is 2 V or less. rice field.</p><p>Subsequently, for Sample E1 and Sample E2, the amount of change in the threshold voltage when PBTS and NBTS were alternately repeated was measured. As a measurement method, the ID-VG characteristics of the transistor were first measured (initial). After that, PBTS and NBTS were alternately performed twice. In each GBT stress test, the stress temperature was 60 ° C and the stress time was 3600 seconds. Here, measurements were made for a transistor with a channel length L = 6 μm and a channel width W = 50 μm.</p><p>The threshold voltages before the stress test (initial) and after each GBT stress test in sample E1 are shown in FIG. 29 (A), and the threshold voltages before the stress test (initial) and after each GBT stress test in sample E2 are shown in FIG. 29 (A). The voltages are shown in FIG. 29 (B), respectively. In FIGS. 29 (A) and 29 (B), the vertical axis indicates the threshold voltage (Vth) when the drain voltage is 10 V, and the horizontal axis indicates the stress test name. In addition, FIGS. 29 (A) and 29 (B) show the results of GBT tests alternately performed in the order of pre-stress test (initial), PBTS, NBTS, PBTS, and NBTS.</p><p>From the results shown in FIGS. 29 (A) and 29 (B), the amount of change in the threshold voltage of the transistor of sample E2 is larger than the amount of change in the threshold voltage of the transistor of sample E1, but the amount of change within ± 4 V. It was confirmed that.</p><p>From the above, one aspect of the present invention is to improve reliability and suppress variations in electrical characteristics by forming an oxide semiconductor film in a laminated structure even if the process temperature is lowered, as in the transistor of sample E2. It was shown that it has excellent electrical characteristics, which are satisfied with the improvement of on-current and the low S value.</p><p>As described above, the configuration shown in this embodiment can be used in combination with other embodiments or examples as appropriate.</p>

<p>In this embodiment, a transistor corresponding to the transistor 100 shown in FIG. 1 and the transistor 170 shown in FIG. 3 is manufactured, and a display device having the transistor is manufactured.</p><p>First, Table 1 shows the specifications of the display device produced in this embodiment.</p><p><tables><img file="JP2022017592A_D0001.tif" /></tables></p><p>Next, a top view of the pixel portion of the display device produced in this embodiment is shown in FIGS. 30 (A) and 30 (B). Note that FIG. 30 (A) is a top view of the pixel portion 840A when the minimum processing dimension of the process is 2 μm, and FIG. 30 (B) is a pixel portion when the minimum processing dimension of the process is 3.5 μm. It is a top view of 840B. In addition, in FIGS. 30A and 30B, each of them represents three pixels.</p><p>Further, FIGS. 31 (A) and 31 (B) show a top view of the gate driver portion of the display device manufactured in this embodiment. Note that FIG. 31 (A) is a top view when the minimum processing dimension of the process is 2 μm, and FIG. 31 (B) is a top view when the minimum processing dimension of the process is 3.5 μm. In FIG. 31 (A), the area 800 is the frame width, the area 801 is the dummy pixel part, the area 802 is the protection circuit part, the area 803 is the gate driver circuit part, and the area 804 is the margin area for division. Are represented respectively. Further, in FIG. 31B, the area 850 is the frame width, the area 851 is the dummy pixel part, the area 852 is the protection circuit part, the area 853 is the gate driver circuit part, and the area 854 is the margin area for division. Are represented respectively.</p><p>Further, in this embodiment, the region 800 is 0.7 mm, the region 801 is 0.05 mm, the region 802 is 0.08 mm, the region 803 is 0.41 mm, and the region 804 is 0.16 mm, as shown in FIG. 31 (A). did. Further, in this embodiment, the region 850 is 0.8 mm, the region 851 is 0.05 mm, the region 852 is 0.07 mm, the region 853 is 0.55 mm, and the region 854 is 0.13 mm, as shown in FIG. 31 (B). did.</p><p>In this embodiment, as shown in FIGS. 31 (A) and 31 (B), a configuration in which a protection circuit unit (region 802 or region 852) is provided is illustrated, but the present invention is not limited to this, and the protection circuit unit is provided. It doesn't have to be. In this case, since the protection circuit unit can be omitted, the frame width can be further reduced. For example, the region 800 shown in FIG. 31 (A) can be reduced to 0.6 mm, and the region 850 shown in FIG. 31 (B) can be reduced to 0.7 mm.</p><p>As described above, since the transistor of one aspect of the present invention has high field effect mobility and high reliability, it has a built-in gate driver circuit and has a frame width (here, the width of the area 800 and the area 850). , 1 mm or less, preferably 0.8 mm or less, and more preferably 0.6 mm or less. Therefore, it is possible to manufacture a display device with a narrow frame.</p><p>Further, a cross-sectional view corresponding to the cut surface between the alternate long and short dash lines M1-N1 shown in FIG. 30 (A) is shown in FIG. 32 (A), and the cut surface between the alternate long and short dash lines M2-N2 shown in FIG. 31 (A). The corresponding cross-sectional views are shown in FIG. 32 (B), respectively.</p><p>The pixel portion 840A shown in FIG. 32 (A) has a conductive film 904a on the substrate 902, an insulating film 906 on the substrate 902 and the conductive film 904, an insulating film 907 on the insulating film 906, and an oxidation on the insulating film 907. A semiconductor film 908, an oxide semiconductor film 909 on an insulating film 907, a conductive film 912a electrically connected to the oxide semiconductor film 908 and functioning as a source electrode, and electrically connected to the oxide semiconductor film 908. A conductive film 912b that functions as a drain electrode, an insulating film 907, an insulating film 914 on the oxide semiconductor films 908 and 909, an insulating film 916 on the insulating film 914, an insulating film 916, and an oxide semiconductor film 909. It has an insulating film 918, a conductive film 920a that functions as a pixel electrode on the insulating film 918, and an insulating film 918 and an insulating film 924 on the conductive film 920a.</p><p>The oxide semiconductor film 908 includes a first oxide semiconductor film 908a and a second oxide semiconductor film 908b. Further, the oxide semiconductor film 909 has a first oxide semiconductor film 909a and a second oxide semiconductor film 909b.</p><p>Further, the insulating film 918 is formed so as to cover the openings provided in the insulating films 914 and 916, and is in contact with the oxide semiconductor film 909. Further, the conductive film 920 functioning as a pixel electrode is formed so as to cover the openings provided in the insulating films 914, 916, 918 and is electrically connected to the conductive film 912b functioning as a drain electrode.</p><p>In FIGS. 32 (A) and 32 (B), the liquid crystal element, the element on the opposite substrate side, and the like are omitted.</p><p>Further, the region 802 functioning as the protection circuit portion shown in FIG. 32 (B) is insulated from the conductive film 904b on the substrate 902, the conductive film 904c on the substrate 902, and the insulating film 906 on the conductive films 904b and 904c. The insulating film 907 on the film 906, the oxide semiconductor film 910 on the insulating film 907, the conductive film 912c electrically connected to the oxide semiconductor film 910, and electrically connected to the oxide semiconductor film 910. The conductive film 912d, the conductive film 912e on the insulating film 907, the insulating film 907, the oxide semiconductor film 910, and the insulating film 914 on the conductive films 912c, 912d, 912e, and the insulating film 916 on the insulating film 914, The insulating film 918 on the insulating films 907 and 916, the conductive film 920b provided on the insulating film 918 and overlapping the oxide semiconductor film 910, the conductive film 920c on the insulating films 918 and the conductive film 912e, and the insulating film 918. , And the insulating film 924 on the conductive films 920b and 920c.</p><p>The conductive film 904a, the conductive film 904b, and the conductive film 904c were formed through the same step of processing the conductive film. Further, the oxide semiconductor film 908, the oxide semiconductor film 909, and the oxide semiconductor film 910 were formed through the process of processing the same oxide semiconductor film. Further, the conductive film 912a, the conductive film 912b, the conductive film 912c, the conductive film 912d, and the conductive film 912e were formed through the same step of processing the conductive film. Further, the conductive film 920a, the conductive film 920b, and the conductive film 920c were formed through the same step of processing the conductive film.</p><p>As the transistor structure used for the region 803 functioning as the gate driver circuit unit shown in FIG. 31 (A), a transistor having the same configuration as the transistor 170 shown in FIG. 3 can be used.</p><p>A glass substrate was used as the substrate 902. As the conductive films 904a, 904b, and 904c, a tungsten film having a thickness of 200 nm was formed by a sputtering device. As the insulating film 906, a silicon nitride film having a thickness of 400 nm was formed by a PECVD apparatus. As the insulating film 907, a silicon oxynitride film having a thickness of 50 nm was formed by a PECVD apparatus.</p><p>As the first oxide semiconductor films 908a, 909a, and 910a, an IGZO film (In: Ga: Zn = 3: 1: 2 [atomic number ratio]) having a thickness of 10 nm was formed by a sputtering apparatus. As the second oxide semiconductor films 908b, 909b, and 910b, IGZO films (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio]) having a thickness of 15 nm were formed by a sputtering apparatus.</p><p>As the conductive films 912a, 912b, 912c, 912d, and 912e, a laminated film of a tungsten film having a thickness of 50 nm, an aluminum film having a thickness of 400 nm, and a titanium film having a thickness of 100 nm was formed by a sputtering apparatus. ..</p><p>As the insulating film 914, a silicon oxynitride film having a thickness of 50 nm was formed by a PECVD apparatus. As the insulating film 916, a silicon oxynitride film having a thickness of 400 nm was formed by a PECVD apparatus. As the insulating film 918, a silicon nitride film having a thickness of 100 nm was formed using a PECVD apparatus.</p><p>As the conductive films 920a, 920b, and 920c, an ITSO film having a thickness of 100 nm was formed by a sputtering device.</p><p>Further, a so-called diode-connected transistor is provided in the region 802 functioning as the protection circuit unit shown in FIG. 32 (B). FIG. 33 shows an example of a circuit diagram of a protection circuit that can be provided in the region 802 that functions as the protection circuit unit shown in FIG. 32 (B).</p><p>The protection circuit 870 shown in FIG. 33 includes a first wiring 861 that functions as a gate line, a second wiring 862 that functions as a low-potential power line, a third wiring 863 that functions as a high-potential power line, and a transistor. It has 871 and a transistor 872. The transistor 871 and the transistor 872 are transistors having a so-called dual gate structure having two gate electrodes. The same potential is applied to the two gate electrodes.</p><p>Also, the gate of transistor 871 is electrically connected to either the source or drain of transistor 871 and the first wire 861. Also, one of the source or drain of transistor 871 is electrically connected to one of the source or drain of transistor 872. Also, the other of the source or drain of transistor 871 is electrically connected to the second wire 862. Also, the other of the source or drain of transistor 872 is electrically connected to the gate of transistor 872 and the third wire 863.</p><p>By providing the protection circuit 870 shown in FIG. 33 between the area 801 and the area 803, that is, in the area 802, the reliability of the display device can be improved.</p><p>However, the display device according to one aspect of the present invention is not limited to this, and may be configured without the protection circuit 870, for example. In this case, the frame width of the display device can be further reduced.</p><p>As described above, the configuration shown in this embodiment can be used in combination with other embodiments or examples as appropriate.</p>

100 Transistor

102 substrate

104 Conductive film

106 Insulating film

107 107 Insulating film

108 Oxide semiconductor film

108a Oxide semiconductor film

108b Oxide semiconductor film

112 112 Conductive film

112a Conductive

112b Conductive film

114 114 Insulating film

116 Insulating film

118 Insulating film

120 Conductive film

120a Conductive

120b Conductive

131 131 Oxide conductive film

138 Etching gas

139 oxygen

140a mask

140b mask

142 Etchant

142a opening

142b opening

142c opening

170 Transistor

501 Pixel circuit

502 Pixel part

504 Drive circuit section

504a Gate driver

504b source driver

506 Protection circuit

507 Terminal part

550 Transistor

552 Transistor

554 Transistor

560 Capacitive element

562 Capacitive element

570 Liquid crystal element

572 Light emitting element

700 700 Display device

701 substrate

702 Pixel part

704 Source driver circuit section

705 substrate

706 Gate driver circuit section

708 FPC terminal part

710 Signal line

711 Wiring part

712 Sealing material

716 FPC

730 Insulating film

732 Sealing membrane

734 Insulating film

736 Colored film

738 Light-shielding film

750 Transistor

752 Transistor

760 Connection electrode

764 Insulating film

766 Insulating film

767 Oxide semiconductor film

768 Insulating film

770 Flattening insulating film

772 Conductive film

774 Conductive film

775 Liquid crystal element

776 Liquid crystal layer

778 Structure

780 780 Anisotropic conductive film

782 Light emitting element

784 Conductive film

786 EL layer

788 Conductive film

790 Capacitive element

800 region

801 region

802 region

803 region

804 region

840A pixel part

840B pixel part

850 region

851 region

852 region

853 region

854 region

861 wiring

862 wiring

863 wiring

870 Protection circuit

871 Transistor

872 Transistor

902 substrate

904 Conductive film

904a Conductive

904b Conductive

904c Conductive

906 Insulating film

907 Insulating film

908 Oxide semiconductor film

908a Oxide semiconductor film

908b Oxide semiconductor film

909 Oxide semiconductor film

909a Oxide semiconductor film

909b Oxide semiconductor film

910 Oxide semiconductor film

910a Oxide semiconductor film

910b Oxide semiconductor film

912a Conductive

912b Conductive

912c Conductive

912d Conductive

912e Conductive

914 Insulating film

916 Insulating film

918 Insulating film

920 Conductive film

920a Conductive

920b Conductive

920c conductive film

924 Insulating film

5100 pellet

5100a pellets

5100b pellets

5101 ion

5102 Zinc oxide layer

5103 particle

5105a pellets

5105a1 area

5105a2 pellets

5105b pellets

5105c pellets

5105d pellet

5105d1 area

5105e pellet

5120 substrate

5130 target

5161 region

8000 Display module

8001 Top cover

8002 Bottom cover

8003 FPC

8004 Touch panel

8005 FPC

8006 Display panel

8007 Backlight

8008 light source

8009 flame

8010 Printed board

8011 Battery

9000 Housing

9001 Display

9003 Speaker

9005 Operation key

9006 Connecting terminal

9007 Sensor

9008 microphone

9050 Manual operation button

9051 information

9052 information

9053 information

9054 information

9055 Hinge

9100 Mobile information terminal

9101 Mobile information terminal

9102 Mobile information terminal

9200 Mobile information terminal

9201 Mobile information terminal