Selector device for two-terminal memory

0001Cross-reference of related applications This patent application is filed on December 31, 2014, under the name of SELECTOR DEVICE FOR TWO-TERMINAL MEMORY, US non-provisional patent application number 14 / 588,185 and on March 11, 2014, SELECTOR DEVICE FOR TWO. Claiming priority of US provisional application number 61 / 951,454 under the name of TERMINAL DEVICE and US provisional application number 62/021660 under the name of SELECTOR DEVICE FOR TWO-TERMINAL MEMORY filed on July 7, 2014. Each shall be cited herein for all and all purposes thereof.

0002Technical field This disclosure relates generally to electronic memory, for example, the disclosure describes a selector element configured to provide a non-linear current-voltage response to the memory element.

0003background A recent innovation in the field of integrated circuit technology is resistive memory. While much of the resistive memory technology is in the development stage, various technical concepts about resistive memory are presented by the assignees of the present invention, which may prove or overturn one or more related theories. Are in one or more verification stages. Nevertheless, resistive memory technology may have substantial advantages over competing technologies in the semiconductor electronics industry.

0004Resistive random access memory (RRAM) is an example of resistant memory. The inventors of the present disclosure believe that RRAM has potential as a high-density non-volatile information storage technology. In general, RRAM stores information by controllably switching different resistance states. As provided by the various memory models proven by the assignee, a single resistive memory can store single-bit or multi-bit information, a one-time programmable cell or programmable and erase. It can be configured as a possible element.

0005Various theories have been proposed by the inventors to explain the phenomenon of resistive switching. According to one such theory, resistive switching is the result of the formation of conductive structures in other electrical insulators. Conductive structures can be formed from ions, atoms that can be ionized under the right conditions (eg, the right electric field) or other charge transfer mechanisms. According to another of these theories, field-assisted atomic diffusion can occur in response to the appropriate potential applied to the resistant memory cell. According to yet another theory proposed by the present inventors, the formation of conductive filaments is a binary oxide (eg, NiO, TiO).₂Etc.) can be generated in response to Joule heating and electrochemical processes, or by redox methods for ionic conductors containing oxides, chalcogenides, polymers and the like.

0006The present inventors are expecting a resistance element based on an electrode insulator electrode model that exhibits good durability and life cycle. Furthermore, the inventors are expecting such devices with high on-chip densities. Therefore, the resistive element may be a viable alternative to metal oxide semiconductor (MOS) transistors used for digital information storage devices. The inventors of the patent application in question believe that, for example, a model of a resistive switching memory device offers some potential technical advantages over a non-volatile flash MOS device.

0007In view of the above points, the inventors are committed to further improving the memory technology and the resistive memory.

0008Overview A brief summary of the specification is provided below to provide a basic knowledge of some aspects of the specification. This summary is not an exhaustive overview of this specification. It is not intended to identify key or important elements herein, nor is it intended to delineate any particular scope of any particular embodiment or any scope of the claims. An object of the present invention is to present some concepts herein in a simple form as a prelude to the more detailed description presented in this disclosure.

0009In various embodiments of the present disclosure, selector elements for solid state memory applications are provided. The selector element can be configured to have a non-linear current-voltage (I to V) relationship in various embodiments. Further, the selector element may be a volatile element having a first electric state corresponding to the first electric condition and a second electric state not the first electric condition at the time of insulation.

0010In one or more embodiments, a monolithic solid-state structure formed in series with a non-volatile memory element is disclosed. The monolithic solid-state structure can be a selector element, as provided herein. Further, the selector element can provide a substantially non-linear I-V response suitable for reducing the leakage current of the non-volatile memory element. Thus, in at least some embodiments, a series combination of a monolithic solid-state structure and a non-volatile memory element is one of a set of memory cells in a 1-transistor, multi-register (1T-nR) resistant memory cell array (eg). , 1-selector, 1-register (1S-1R) configuration memory cell).

0011In a further additional embodiment, a selector element configured to exhibit a non-linear I-V relationship for various polar signals is disclosed. For example, the selector element can show a first nonlinear I to V relationship according to a signal of the first polarity and a second nonlinear I to V relationship corresponding to a second signal of the second polarity. In some embodiments, the first nonlinear I-V relationship and the second nonlinear I-V relationship can have the same or similar curvilinearity, while in other embodiments, the first nonlinear I-V. The relationship and the second non-linear I to V relationship can have various curvilinearities. In a further embodiment, the selector element can be provided in series with the bipolar memory element. In such an embodiment, the selector element can provide a non-linear response for a second polarity erase operation and a first polarity read / write operation.

0012In a further embodiment, a method of forming a selector element for a 2-terminal memory element is provided. This method can include a step of providing a first layer structure containing a first metal substance and a step of providing a layer of a selector member that comes into contact with the first layer structure. Further, the method can include a step of providing a second layer structure containing a second metallic material and in contact with the layer of the selector member. In various embodiments, the first metal material or the second metal material is conductive to the selector member depending on the voltage of the first polarity or the second polarity applied over the first layer structure and the second layer structure, respectively. It can be configured to provide ions, and the selector member allows conductive ions to permeate through the layers of the selector member depending on the voltage applied over the first and second layer structures. It is composed of. In an alternative or additional embodiment, the first layer structure, the layer of the selector member and the second layer structure form a selector element, which is electrically arranged in series with the 2-terminal memory element. Will be done.

0013In yet another disclosed embodiment, the disclosure of interest provides a selector element for 2-terminal memory. The selector element may include a first layer structure containing a first metal substance and a layer of a selector member that comes into contact with the first layer structure. Further, the selector element can include a second layer structure that is in contact with the layer of the selector member and contains a second metallic substance. In some embodiments, the primary or secondary metallic material is a selector member depending on the primary or secondary polar threshold voltage applied across the first and second layer structures, respectively. Can be configured to provide conductive ions. In another embodiment, the selector member is configured to allow conductive ions to permeate through the layers of the selector member depending on the threshold voltage applied across the first and second layer structures. .. According to still another embodiment, the selector element is electrically arranged in series with the 2-terminal memory element.

0014Further, with respect to the above, the present disclosure provides a method of operating a crossbar memory array including a plurality of 2-terminal memory elements and a plurality of selector elements, and each of the plurality of 2-terminal memory elements is described. It is related in series with one selector element of the plurality of selector elements, and each selector element is associated with the first electrical characteristic according to the applied voltage below the threshold voltage, and the second according to the applied voltage above the threshold voltage. Related to electrical properties. The method can include applying a first voltage that exceeds the threshold voltage to a first memory structure that includes a first 2-terminal memory element in series with the first selector element. In addition, the above method is a step of applying a second voltage lower than the threshold voltage and simultaneously applying the first voltage to the second memory structure including the second 2-terminal memory element in series with the second selector element. Can be included. Further, the method can include a step of determining the current according to the step of applying the first voltage at the same time as applying the second voltage. In at least one embodiment, the current includes a first current associated with the first selector element and a second current associated with the second selector element. In one or more additional embodiments, the current ratio of the first current to the second current is in the range of about 1,000 to about 10,000, about 10,000 to about 100,000, about 100,000 to about 1,000,000, and about 1,000,000 to about 10,000,000. It is within the range of the more selected ratio. With this disclosure in mind, current ratios above 10,000,000 are expected.

0015The following description and drawings describe certain descriptive aspects of this specification. These aspects show in various ways just a few examples in which the principles herein can be used. Other advantages and novel features herein are apparent from the following detailed description of the specification when considered in connection with the drawings.

0016Various aspects or features of the present disclosure are described with reference to the drawings, and the use of the same reference numerals represents the same elements throughout. A number of specific details are described herein to provide detailed knowledge of the present disclosure. However, it should be understood that certain aspects of the disclosure in question can be performed without these particular details and can be performed with other methods, components, substances, etc. In other examples, well-known structures and devices are shown in the form of block diagrams to facilitate the description of the subject disclosure.

0017<figref num="1">FIG. 1 represents a block diagram of an exemplary monolithic structure that provides a solid-state selector element according to various disclosed embodiments.</figref>

0018<figref num="2">FIG. 2 shows a block diagram of an example selector element behavior according to the electrical characteristics of the first polarity.</figref>

0019<figref num="3">FIG. 3 shows a block diagram of an example selector element behavior according to the electrical characteristics of the second polarity.</figref>

0020<figref num="4">FIG. 4 shows a block diagram of an exemplary selector element according to another additional aspect of the present disclosure.</figref>

0021<figref num="5">FIG. 5 illustrates an exemplary current-voltage (I-V) response diagram of a selector element in some embodiments.</figref>

0022<figref num="6">FIG. 6 shows a diagram of the I-V response of an example of a selector element in another disclosed embodiment.</figref>

0023<figref num="7">FIG. 7 represents a block diagram of an exemplary selector element provided with a memory element according to one embodiment.</figref>

0024<figref num="8">FIG. 8 shows a block diagram of an exemplary arrangement of memory cells containing each selector element in series with 2-terminal memory.</figref>

0025<figref num="9">FIG. 9 illustrates a schematic crossbar memory architecture showing the effects of leakage current and the benefits of non-linear I-V responses.</figref>

0026<figref num="10">FIG. 10 shows a flowchart of an example method of manufacturing a selector element according to various disclosed embodiments.</figref>

0027<figref num="11">FIG. 11 shows a flowchart of an exemplary method of manufacturing a solid state selector element in series with a 2-terminal memory element.</figref>

0028<figref num="12">FIG. 12 shows a flowchart of an exemplary method of activating an array of memory cells according to a further disclosed embodiment.</figref>

0029<figref num="13">FIG. 13 shows a block diagram of an example operation and control environment for a memory element according to various disclosed embodiments.</figref>

0030<figref num="14">FIG. 14 shows a block diagram of an exemplary computing environment that can be implemented with various embodiments.</figref>

0031Detailed explanation The present disclosure relates to a selector element of a 2-terminal memory cell used in a digital information storage device. In some embodiments, the 2-terminal memory cell can have a resistance technique (eg, a resistive switching 2-terminal memory cell). Resistive Switching 2-Terminal memory cells (also known as Resistive Switching Memory Cells or Resistive Switching Memory) are conductive, having an active region between two conductive contacts, as used herein. Includes circuit components with contacts. 2-The active region of the terminal memory element shows a plurality of stable or semi-stable resistance states (resistive states having different electrical resistances from each other) in the contents of the resistant switching memory. In addition, each of the plurality of states can be formed or activated in response to an appropriate electrical signal applied to the two conductive contacts. Appropriate electrical signals can be voltage values, current values, voltage or current polarity, etc., or a suitable combination thereof. Examples of resistive switching 2-terminal memory elements include, but are not exhaustive, resistive random access memory (RRAM), phase change RAM (PCRAM), and magnetic RAM (MRAM).

0032The disclosed embodiments of interest can provide a volatile selector element that can be integrated with a non-volatile memory cell. In various embodiments, the volatile selector element or non-volatile memory cell can be a filamentary-based element. As an example of a filament-based device, a layer containing metal-doped p-type (or n-type) silicon (Si) (for example, p-type or n-type polycrystalline silicon, p-type or n-type polycrystalline SiGe, etc.), Conductive layers such as a resistive switching layer (RSL) and an ionizable active metal layer can be mentioned. Under suitable conditions, the active metal layer can provide filament-forming ions to the RSL. In such embodiments, the conductive filament (eg, formed by ions) can promote conductivity through at least a subset of RSL, and the resistance of the filament-based element is between the filament and the conductive layer. It can be determined by the tunnel type resistance of.

0033In various embodiments relating to the memory cells of the present disclosure, the p-type or n-type Si layer can have p-type or n-type polycrystalline silicon, p-type or n-type polycrystalline SiGe, and the like. RSL (also known as Resistive Switching Medium (RSM) in this art) includes, for example, non-doped amorphous Si layers, semiconductor layers with intrinsic characteristics, Si suboxides (eg, SiOx (x is 0.1 to 2)). (Value between) etc. can be included. As another example of a substance suitable for RSL, Si_XGe_YO_Z(X, Y and Z are appropriate positive numbers for each), silicon oxide (eg SiO)_N(N is an appropriate positive number)), Amorphous Si (a-Si), Amorphous SiGe (a-SiGe), TaO_B(B is an appropriate positive number), HfO_C(C is an appropriate positive number), TiO_D(D is an appropriate number) and Al₂O_E(E is an appropriate positive number) etc. or an appropriate combination thereof can be mentioned. In various embodiments, the RSL contains many material voids or defects.

0034Active metal layers for filament-based memory cells include, among others, silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN) or titanium, nickel (Ni), copper (Cu), aluminum (Al). ), Chromium (Cr), Titanium (Ta), Iron (Fe), Manganese (Mn), Tungsten (W), Vanadium (V), Cobalt (Co), Platinum (Pt), Hafnium (Hf) and Palladium (Pd) ) Other suitable compounds can be mentioned. Combinations of other suitable conductive materials with compounds, alloys or substances mentioned above or similar can be used for active metal layers in certain aspects of the disclosure of interest. Some details relating to the subject disclosure embodiment similar to the previous example are licensed to the assignee of this patent application: The following US patent application: filed October 19, 2007. It can be found in Application No. 11 / 875,541 and Application No. 12 / 575,921, filed October 8, 2009, each cited herein for all and for all purposes. It shall be.

0035In various disclosed embodiments, filament-based switching devices are disclosed and their operations are described. In some embodiments, filament-based switching devices exhibit first measurable different states in the absence of a suitable external stimulus and are second measurable in response to a suitable external stimulus. It can be a volatile switching element that indicates the state. Volatile filament-based switching elements are often referred to as selector elements or selection elements, filament selector elements, filament-based selector elements, and the like in the present specification. Even with such devices, their configuration or use is not limited by this terminology. In other embodiments, the filament-based switching devices are in a first measurable state different from each other until a suitable first external stimulus is applied to change the non-volatile switching device into a second measurable state. It can be a non-volatile switching element showing the above. The non-volatile switching elements then exhibit a second measurable different state until a suitable second external stimulus is applied. Despite the general limitations of the binary case, the present disclosure allows non-volatile filament-based switching devices to have two or three or more measurable states different from each other, thereby eliciting multi-level cell functionality. The non-volatile filament-based switching element is generally referred to as a memory cell, a resistive memory cell, a filament-based memory cell, or the like in the present specification. It is not limited by this terminology.

0036The filament selector element can exhibit a first state (eg, first electrical resistance or other suitable measurable feature) in the absence of a suitable external stimulus. The stimulus can have a threshold or range of such values that induces the filament selector element to change from the first state to the second state while the stimulus is applied. In response to a stimulus below the threshold (or a range of thresholds), the filament selector element returns to its initial state. In certain disclosed embodiments, filament-based selector devices can operate in a bipolar fashion that behaves differently in response to external stimuli of various polarities (or directions, energy flows, energy source orientations, etc.). By way of example, the filament selector element can change from a first state to a second state in response to a first polarity stimulus that exceeds the first threshold voltage (or voltage set). Further, the filament selector element can change from the first state to the third state in response to the second polarity stimulus exceeding the second threshold voltage. In certain embodiments, the third state has the same or similar measurable different characteristics (eg, conductivity, etc.) or the same or similar threshold stimulus magnitude (whether of different polarities or directions). It can be substantially the same as the first state such as having. In another embodiment, the third state is a point of measurable features (eg, values of various electrical conductivity in response to reverse polarization compared to forward polarization), or a transition from the first state. Any of the threshold stimuli associated with (eg, the magnitude of the various positive voltages required to transition to the second state compared to the magnitude of the negative voltage required to transition to the third state). Can be distinguished from the second state with.

0037In some embodiments, and by way of example, the disclosed filament-based selector elements are capable of forming conductive paths or filaments through relatively high resistance portions in response to appropriate external stimuli. Due to an external stimulus, the metal particles in the active metal layer move (or ionize) in the RSL layer of the filament selector element. In addition, the RSL can be selected to have relatively small physical defect locations with respect to the volatile filament switching device, which results in relatively good mobility of the metal particles in the RSL. Thus, below the associated threshold stimulus (or narrow threshold range), the metal particles disperse in the RSL and the formation of sufficient conductive paths through the RSL reduces the high resistance associated with the first state. Can be inhibited. Above the threshold, the external stimulus keeps the metal particles in a form sufficient to provide a conductive path, eliciting a relatively low resistance of the second state. A similar mechanism can control the operation of the third state in the bipolar content.

0038For non-volatile filament-based resistant switching memory cells, RSL can be selected to have sufficient physical defect sites in it to trap the appropriate particles in the absence of appropriate external stimuli. This reduces the mobility and dispersibility of the particles. Conductive paths or filaments are formed through the RSL, depending on the appropriate program voltage applied across the memory cells. In particular, when a program bias voltage is applied, metal ions are generated from the active metal layer and move to the RSL layer. More specifically, metal ions migrate to voids or defective sites in the RSL layer. In some embodiments, excluding the bias voltage, the metal ions become neutral metal particles and remain trapped in the voids or defects of the RSL layer. When a sufficient amount of particles are trapped, filaments are formed and the memory cell switches from a relatively high resistance state to a relatively low resistance state. More specifically, the trapped metal particles provide a conductive path or filament through the RSL layer, and the resistance is generally determined by the tunneled resistance through the RSL layer. In a resistive switching element, an erase method is performed in which the conductive filament is at least partially deformed to return the memory cell from a low resistance state to a high resistance state. More specifically, when an erasing bias voltage is applied, the metal particles trapped in the voids or defects of the RSL become more mobile and move back towards the active metal layer. This state change can be associated with each state of the binary bit in the memory contents. For arrays of multiple memory cells, memory cell words, bytes, pages, blocks, etc. represent 0 or 1 of the binary information, and a program or by holding their state with the effect of storing the binary information for a long time. It can be erased. In various embodiments, multi-level information (eg, multi-bits) may be stored in such memory cells.

0039It should be understood that different embodiments of the present specification can utilize different memory cell techniques with different physical properties. For example, different resistive switching memory cell technologies can have different programmable discrete resistors, different associated program / erase voltages, and other distinguishing features. For example, various embodiments of the disclosure of interest include a first switching response to a first-polarity electrical signal (eg, programming for one of a set of programming states) and a first for a second-polarity electrical signal. Bipolar switching elements can be used that exhibit a two-switching response (eg, erase to erased state). Bipolar switching devices are in contrast to unipolar devices, which exhibit, for example, a first switching response (eg, a program) and a second switching response (eg, erasure) in response to electrical signals of the same polarity and varying magnitude.

0040If a particular memory cell technique or program / erasure voltage is not specified in the specification for various aspects and embodiments, such aspects and embodiments will be as those known to those of skill in the art or provided herein. As is known to those of skill in the art, it is intended to incorporate any suitable memory cell technology and operate with a program / erase voltage suitable for that technology. If replacing various memory cell techniques requires a circuit modification known to those of skill in the art or a change to an operating signal level known to those of skill in the art, the replaced memory cell technique or signal level change. It should be further understood that the embodiments including the above are within the scope of the subject disclosure.

0041The inventor of the present application of interest is familiar with additional non-volatile 2-terminal memory structures in addition to resistant memory. For example, ferroelectric memory (RAM) is an example. Some others include magnetoresistive RAM, organic RAM, phase change RAM, conductive bridge RAM, and the like. 2-Terminal memory technology has various strengths and weaknesses, and the trade-offs between the strengths and weaknesses are common. Resistive switching memory techniques are mentioned with many embodiments disclosed herein, but at the convenience of one of ordinary skill in the art, any of the other 2-terminal memory techniques will be disclosed. Can be used for

0042High-density integration of memory often utilizes an array structure to connect multiple cells along the conductive lines of the integrated chip (eg, bit lines, word lines, data lines, source lines, etc.). While the inventors of the present disclosure can increase the memory density by connecting multiple cells to a common conductive line, such arrangements also have electrical problems (eg, leakage current (eg, Figure 8 below). See), lowering of sensing margin, excessive power consumption, etc.). This can be especially apparent for memory cells programmed into low resistance states. As an example, the operating voltage applied to a selected conductive line, commonly connected to a target memory cell and some non-target memory cells, can cause a huge amount of current to flow through the low resistance non-target memory cell. it can. If a large number of non-target memory cells are connected to selected conductive lines (eg, to achieve high memory densities), this current consumes enormous amounts of power. In addition, the capacitive voltage near the conductive line caused by the operating voltage can be a leakage current from the vicinity of the conductive line to the selected conductive line. In addition to consuming additional power, this leakage current reduces the sensing margin of memory operations performed on the target memory cell.

0043To reduce the excess power consumption and leakage current of the memory array, transistors may be connected to each memory cell, which is sometimes referred to as a 1-transistor-1 memory cell architecture. The transistor can be in an inactive state that closes the current through the memory cell, thereby minimizing the leakage current in that memory cell. However, the addition of transistors for each memory cell can significantly increase the size of the memory cell (and reduce the density of the associated array of memory). Some memory arrays balance memory density and leakage current by implementing a one-transistor-n memory cell architecture (n is an integer greater than one). In this architecture, increasing the number of memory cells (n) per transistor is a trade-off between memory density, leakage current, and power consumption. Therefore, the inventor understands that conventional attempts to achieve increased memory density can solve increased power consumption and associated Joule heating, reduced sensing margins and other problems.

0044Various embodiments of the present disclosure provide a selector element (eg, a volatile switching element), which is a non-volatile current-voltage (eg, a non-volatile switching element) relating to a memory cell (eg, a non-volatile switching element) associated with the selector element. I ~ V) It is configured to provide a response. In particular, the non-linear I-V response can significantly reduce the leakage current in the associated memory cell. Further, the selector element can be a monolithic solid state structure manufactured with associated memory cells that do not substantially increase the size of the memory cells. In the content of resistive memory cell technology, the disclosed selector elements can facilitate a one-transistor-n-register (1T-nR) architecture with high memory density. In some embodiments, the number of memory cells (n) per transistor can be 512, 102 or higher without significantly affecting the leakage current of the memory array. Therefore, the disclosed selector elements can facilitate high memory densities with low leakage current, low power consumption, and good sensing margins.

0045Refer to the drawing here. FIG. 1 shows a block diagram of an exemplary selector element 100 according to one or more embodiments of the present disclosure. The selector element 100 can be a 2-terminal element configured to be operable in response to an appropriate electrical signal applied to one or more 2-terminals of the selector element 100. In various disclosed embodiments, the selector element 100 can have a non-linear I-V response and the selector element 100 is in the second range for current and voltage within the first range for the first range for voltage. Indicates the current in the corresponding second range (eg, the voltage is much higher than the first range) (see, eg, Figures 5 and 6 below). The first range of voltage and the second range of voltage can be distinguished, for example, by the threshold voltage or the range of the threshold voltage (eg, the voltage between the first range for voltage and the second range for voltage). .. In a further embodiment, the selector element 100 can be manufactured in series with the 2-terminal memory element as part of a monolithic manufacturing process (eg, photolithography process, mask and etching process, etc.) (FIG. 7 below). And 8). In these later embodiments, the selector element 100 reduces leakage current and reduces power consumption while facilitating an increase in the memory density of an array of such memory cells in series with each of the selector elements 100. 2-It can be configured to provide a non-linear I-V response for the terminal memory device. For example, in the case of a 2-terminal resistive memory cell, the selector element 100 reduces leakage current, reduces power consumption for the 1T-nR memory array, while having a relatively high n value, high density 1T-nR. The memory array can be facilitated. In various embodiments, the selector element 100 is a FAST currently under development by the current assignee of this patent application.^TMIt may be embodied as a selector element.

0046The selector element 100 is represented in FIG. 1 to have an upper electrode 102 and a lower electrode 106. The upper electrode 102 and the lower electrode 106 are electrical conductors and are made of a suitable substance that promotes the conduction of electric current. In one or more embodiments, the upper electrode 102 and the lower electrode 106 may contain a substance that provides or facilitates the supply of mobile atoms or ions in response to appropriate stimuli. Examples of suitable stimuli include electrical fields (eg, programmed voltage), Joule heating, magnetic fields or other suitable stimuli that induce or partially induce particle transport. In at least one embodiment, the motility of the particles may respond to uninduced or partially uninduced dispersion or similar phenomena.

0047Examples of materials suitable for the upper electrode 102 or lower electrode 106 are precious metals (eg, Ag, Pd, Pt, Au, etc.) or metal alloys partially containing precious metals (eg, Ag-Al, Ag-Pd-Cu, etc.). Ag-W, Ag-Ti, Ag-TiN, Ag-TaN, etc.). The noble metal or alloy thereof can be used, for example, to facilitate the reduction of the interaction between the upper electrode 102 or the lower electrode 106 and the selector layer 104. This reduced particle interaction (eg, reducing or avoiding chemical bonds between the particles in the selector layer 104 and the particles in the upper electrode 102 or lower electrode 106) is, by way of example, the lifetime and reliability of the selector element 100. Can be easily improved. Another example of a material suitable for the upper electrode 102 or the lower electrode 106 is a material having particles that diffuse relatively rapidly. More rapid diffusion may include, for example, the ability to move through defective sites in solids (eg, voids or gaps in molecular material) that facilitate the dispersion of relatively rapid diffuse particles that lack cohesive force. it can. A substance having particles that diffuse relatively rapidly can facilitate rapid state switching of the selector element 100 (eg, from a non-conductive state to a conductive state) at a lower bias value. Examples of suitable rapid diffusing materials include suitable alloys thereof such as Ag, Cu, Au, Co, Ni, Al or Fe, or suitable combinations of those described above.

0048In at least one embodiment, the upper electrode 102 may consist of the same material or substantially the same material as the lower electrode 106. In other embodiments, the upper electrode 102 and the lower electrode 106 may be different substances from each other. In yet another embodiment, the upper electrode 102 and the lower electrode 106 may be at least partially the same substance and partially different substances. For example, the upper electrode 102 may contain a suitable conductive material, for example, the lower electrode 106 may at least partially contain a suitable conductive material in combination with an alloy of the suitable conductive material or other suitable conductor. Can include.

0049In addition to those described above, the selector element 100 includes a selector layer 104. In contrast to the upper electrode 102 or the lower electrode 106, the selector layer 104 can be an electrical insulator or an ionic conductor. Further, the selector layer 104 can be a substance (for example, an oxide) having low permeability to at least the particles of the upper electrode 102 or the lower electrode 106. In some embodiments, the selector layer 104 can be a non-stoichiometric material. As an example of a material suitable for the selector layer 104, SiO_X, TiO_X, AlO_X, WO_X, Ti_XN_YO_Z, HfOx, TaOx, NbOx, etc., or appropriate combinations thereof, and x, y, and z can be appropriate non-stoichiometric values. In some embodiments, the selector layer 104 can be a chalcogenide or a solid electrolyte material containing one or more Ge, Sb, S, Te. In yet another embodiment, the selector member may include a stack of the plurality of substances described above (eg, SiOx / GeTe, TiOx / AlOx). In at least one embodiment of the present disclosure, the selector layer 104 can be metal doped during production to facilitate metal ion implantation from the upper or lower electrodes.

0050During operation, an appropriate electrical signal can be applied to the upper electrode 102 or the lower electrode 106 to induce a state change of the selector element 100. The state change can be, for example, a change in resistance or conductivity. As an example, a voltage, field, current, etc. can be applied to the upper electrode 102 or the lower electrode 106 having at least a threshold value associated with inducing a state change of the selector element 100. Depending on the signal at the threshold, the selector element 100 has a high electrical resistance and a first current (or a current in the first range) from a non-conductive state to a low electrical resistance and a second current (or a second range). It is possible to shift to a relatively conductive state having an electric current). In various embodiments, the current ratio of the first current to the second current is at least about 1,000 or more. For example, in one embodiment, the current ratio can be selected from the range of current ratios of about 1,000 to about 10,000. In another embodiment, the current ratio can be selected from the range of current ratios from about 10,000 to about 100,000. In yet another embodiment, the current ratio can be selected from the range of current ratios from about 100,000 to about 1,000,000. In yet another embodiment, the current ratio can be selected from a range of current ratios of about 1,000,000 to about 10,000,000 or more. Other suitable current ratios can be provided for the selector element 100 in various other suitable embodiments.

0051FIG. 2 shows a block diagram depicting the operation behavior of the selector element 200 according to the applied signal according to the additional embodiment of the present disclosure. For example, the selector element 200 includes an upper electrode 202, a selector layer 204, and a lower electrode 206 as shown in the drawing. In at least some embodiments, the selector element 200 can be substantially similar to the selector element 100 of FIG. 1 below, but the disclosures of interest are not limited thereto.

0052On the upper side of FIG. 2, the selector element 200 is shown together with the first signal 202A applied to the selector element 200. The first signal 202A is greater than the threshold associated with the non-linear I-V response of the selector element 200. In various embodiments, the threshold may be embodied as a narrow range of thresholds (see, eg, below). The reference herein of the threshold (eg, voltage) associated with the non-linear I-V response of the selector element is a narrow range of thresholds for the I-V response to transition from linear (or substantially linear) behavior to non-linear behavior. It should be understood that (eg, the range of voltage values) can be mentioned. The range of thresholds can be varied depending on the suitability of the various material sets selected for the components of the selector element, the arrangement of such materials, the characteristics of such materials (eg, thickness, area, conductivity), etc. ..

0053The first signal 202A is, for example, the upper electrode voltage V._TEIs the first threshold voltage V of the selector element 200_TH1Although depicted as a higher voltage, in other embodiments the first signal 202A is another signal that induces particle motility of the particles of the upper electrode 202 or lower electrode 206 (eg, electrical field or current joules, and further. , Temperature associated with heating). In addition to those mentioned above, the first signal 202A can be of primary polarity (eg, at least in the electrical sense). For example, the first signal 202A can have a positive gradient applied from the upper electrode 202 to the lower electrode 206 (eg, a positive or field at the upper electrode 202 and a ground or negative voltage or field at the 206). Current flow from the upper electrode 202 to the lower electrode 206, etc.).

0054Depending on the first signal 202A (upper electrode 202 relative to lower electrode 206), the particles of the upper electrode 202 (or lower electrode 206) may form conductive paths or filaments in the selector layer 204, as depicted. it can. In some embodiments, the particles can move from the top electrode 202 (or bottom electrode 206) to the selector layer 204 in response to the first signal 202A. In other embodiments, for example, when the selector layer 204 is doped with metal particles, the particles in the selector layer 204 are ionized or aligned (eg, spatial along the conductive path) in response to the first signal 202A. Can be organized). In yet another embodiment, when the selector layer is doped with metal particles, the particles are ionized or aligned in response to the first signal 202A, along with the existing particles in the selector layer 204, along with the top electrode 202 (or , The lower electrode 206) can be moved to form a conductive path. The formation of the conductive path can facilitate the transition from the non-conductive state to the conductive state associated with the non-linear I-V response of the selector element 200. Further, the conductive path can be appropriately formed depending on the size of the first signal 202A that satisfies or exceeds the first threshold value. Therefore, the first threshold is associated with inducing a transition to a conductive state.

0055On the lower side of FIG. 2, the selector element 200 recognizes the second signal 202B applied to the upper electrode 202 (relative to the lower electrode 206). The second signal 202B is made smaller than the first threshold (for example, V)._TE &lt;V_TH1, For example V_TE 0V), and accordingly, the selector element 200 can transition from a (high) conductive state to a (relatively) non-conductive state. Also, in various embodiments, the first threshold may extend over a narrow threshold range. The conductive path formed in response to the first signal 202A depends on the second signal 202B or in response to the removal of the first signal 202A, as shown in the lower selector layer 204 of FIG. , Can be at least partially dissipated. Dissipation of the selector layer 204 if the external force (eg, second signal 202B) is not strong enough to hold the particles in the conductive path through the selector layer 204 (from the top electrode 202 to the bottom electrode 206). It can occur as a result of the tendency of particles to move in or out of it. Thus, in one embodiment below the lowest threshold of the narrow threshold range, the conductive path is at least partially deformed, while above the highest threshold of the narrow threshold range, it causes the selector element 200 to be conductive. Can sufficiently form a sufficient conductive path. To reiterate the above, in various embodiments herein, references to threshold voltages are, in fact, a set of threshold voltages associated with the formation and deformation of conductive paths (eg, within a narrow voltage range). ) Should be understood.

0056As described above, the selector element 200 can transition from the non-conductive state to the conductive state and return to the non-conductive state in a volatile manner. In other words, the selector element 200 can be brought into a conductive state according to the first signal 202A having the first threshold value applied to the selector element 200. The selector element 200 can be brought into a non-conductive state according to the second signal 202B applied to the selector element 200, which is smaller than the first threshold value.

0057In some embodiments, the selector element 200 can be electrically connected in series with a 2-terminal memory cell (eg, a resistive switching memory). When the selector element 200 is provided in series with the 2-terminal memory cell, it can provide non-linear I-V characteristics to the 2-terminal memory cell. Further, the non-linear I-V characteristics can be provided by whether the 2-terminal memory cell is in a conductive or non-conductive state. For example, a signal below the first threshold causes the selector element 200 to be in a non-conductive state. In the non-conductive state, the selector element 200 interferes with the current passing through the series-connected selector element 200 and the 2-terminal memory cell when the signal is less than the first threshold. When the signal is greater than or equal to the threshold, the selector element 200 is conductive and the state of the 2-terminal memory cell can determine the electrical characteristics of the series-connected selector element 200 and the 2-terminal memory cell. Therefore, activation of the selector element 200 facilitates operational access to the 2-terminal memory cell. Deactivation of the selector element 200 (eg, by blocking the current through the series connection and by dropping most of the voltage applied across the series connection) to the 2-terminal memory cell. Block operational access. The selector element 200 is volatile and is in a non-conductive state in the absence of a signal with a first threshold, so that the 2-terminal memory cell cannot be accessed and information is retained (eg, its current state). Will be retained). The selector element 200, on the other hand, provides non-linear I-V responses in series to block leakage currents and facilitate high-density memory arrays.

0058FIG. 3 represents a block diagram depicting the operational behavior of an exemplary selector element 300 according to a further aspect of the subject disclosure. In one or more embodiments, the selector element 300 may be substantially similar to the selector element 100 or the selector element 200. However, the disclosures covered are not limited to these.

0059The operation behavior of the selector element 300 is shown according to the signal of the second polarity, and is different from the first polarity of the first signal 202A and the second signal 202B described with respect to FIG. 2 described above. For example, in various embodiments, the second polarity can be opposite or substantially opposite to the first polarity. As shown, the second polarity can include signal gradients (eg, voltage gradients, current gradients, Joule thermal gradients) where the measurements of the lower electrode 306 are large and the measurements of the upper electrode 302 are small.

0060On the upper side of FIG. 3, the first signal 302A equal to or higher than the second threshold value (or, if matched, the second threshold value range) is applied to the lower electrode 306 with respect to the upper electrode 302. The particles of the lower electrode 306 move in and through the selector layer 304 in response to the first signal 302A. The second threshold is related to the proper formation of a conductive path across the selector layer 304 from the lower electrode 306 to the upper electrode 302 that induces the conductive state of the selector element 300. In some embodiments, the second threshold (or threshold range) is the first threshold (or threshold range) associated with the formation of a conductive path from the upper electrode 202 to the lower electrode 206 shown in FIG. 2 above. It should be noted that they can be different (different values). Differences in thresholds can occur, for example, when the upper and lower electrodes are made of different materials with different particle motility, different ionic strengths, different sizes or different shapes, and the like. The above differences with respect to the upper electrode 302 or the lower electrode 306, the use of different materials, the order of the materials (eg, the addition of an additional layer (eg, barrier layer) between the selector layer 304 and the upper electrode 302 or the lower electrode 306), the material. Depending on the nature or characteristics of, the threshold voltage associated with filament formation from the lower electrode 306 (drawn in FIG. 3) to the upper electrode 302 and the filament formation from the upper electrode 202 to the lower electrode 206 (drawn in FIG. 2). It can cause a difference from the associated threshold voltage.

0061As depicted in FIG. 3, the formation of the conductive path is a selector that aligns / moves to form the appropriate particles or conductive path of the lower electrode 306 that moves through the selector layer 304 from the lower electrode 306 to the upper electrode 302. Existing metal particles in layer 304 (eg, metal particles doped in the selector layer) can be included. At the bottom of FIG. 3, a second signal 302B smaller than the second threshold (or threshold range) is applied to the lower electrode 306. In response to the second signal, the particles in the conductor disperse through (or in / towards the lower electrode 306) the selector layer 304, causing the conductor to deform at least partially. As a result, the non-conductive state of the selector element 300 is induced. Thus, in one embodiment below the lowest threshold of the narrow threshold range, the conductive path is at least partially deformed, while above the highest threshold of the narrow threshold range, it causes the selector element 300 to be conductive. Can sufficiently form a sufficient conductive path. To reiterate the above, in various embodiments herein, reference to threshold voltage is, in fact, dependent on whether the conductive path is formed or deformed (from a narrow voltage range). It should be understood that it can refer to a set of threshold voltages.

0062In another embodiment, where the polarity of the voltage source is defined as positive to negative with respect to the upper and lower electrodes 302, below the lowest threshold in a narrow threshold range will cause the selector element 300 to be conductive. Can sufficiently form a sufficient conductive path, while above the highest threshold in a narrow threshold range, the conductive path is at least partially deformed. An example of this is shown below.

0063In various embodiments, the selector element 300 can have the above-mentioned properties with respect to the selector element 200, depending on the signal of the first polarity. Therefore, the selector element 300 can form a conductive path containing particles extending from the upper electrode 302 through the selector layer 304 in response to a signal of the first polarity, and in response to a signal of the second polarity. , A second conductive path containing particles can be formed that extends from the lower electrode 306 through the selector layer 304. In at least some embodiments, the conductive path can contain particles of the lower electrode 306 at least partially (eg, near the boundary of the lower electrode 306), and similarly, the second conductive path is the upper electrode 302. Particles can be contained at least partially (eg, near the boundary of the top electrode 302). Therefore, the selector element 300 may have a first threshold that promotes the transition to the first conductive state along the first polarity and a second threshold that promotes the transition to the second conductive state along the second polarity. it can. This operation can be performed with a bipolar memory cell to provide non-linear I-V characteristics for the second and first polarity signals. In practical conditions, the bidirectional nonlinear I-V characteristics can facilitate the inhibition of leakage currents from positive or negative signals. Therefore, the selector elements 300 and 2-terminal memory cells connected in series reduce the leakage current generated from the program signal or read signal (for example, having the first polarity) or the erase signal (for example, having the second polarity). Can be done. It should be understood that in at least some embodiments, this description (and other suitable description of FIG. 3) with respect to the selector element 300 is as applicable as the selector element 200 of FIG. 2 above. And vice versa, the exemplary embodiments described for the selector element 200 can be applied to the selector element 300, which is an appropriate embodiment. Therefore, the exemplary embodiments described in FIGS. 3 and 2 should be considered interchangeable if compatible.

0064In various embodiments, the selector element 300 can operate within a set of operating parameters. In some embodiments, the set of operating parameters is long, maintaining volatile state switching of selector layer 304 (eg, by forming a relatively weak filament that deforms at least partially below the threshold signal). It can be selected to provide lifespan switching, achieve target power consumption, etc., or in the appropriate combination thereof. In some embodiments, the current through the selector element 300 (and, for example, the selector element 300 and the 2-terminal memory cell connected in series) can be limited to the maximum current value.

0065For example, the maximum current value can be limited to 300 microamperes (μA) or less, 300 μA or less, or any other suitable maximum value. In other embodiments, the selector layer 304 can have a thickness that is maintained within a target thickness range. For example, the thickness of the selector layer 304 can range from about 0.5 nanometers (nm) to about 50 nm. In various embodiments, based on current experimental data, typical thicknesses that provide surprisingly effective results based on a threshold voltage of about 1 volt are about 1 to about 20 nm, more specifically about 1 nm to about. It may be in the range of 10 nm. In at least one embodiment, the thickness of the selector layer 304 (or, for example, the selector layer 204 in FIG. 2 below) is a signal threshold (or associated with state switching of the selector element 300 having or within a target range). For example, voltage thresholds, current thresholds, field intensity thresholds, etc.) can be selected to be provided. As one exemplary example, the thickness can be selected to provide a threshold voltage associated with state switching, from about 0.1 volt to about 4 volt. By maintaining the threshold voltage at the target value, the formation of the non-volatile filament can be reduced or avoided.

0066In some embodiments, the stoichiometric value of the material utilized in the selector layer 304 (or selector layer 204) can be provided as a target value. For example, the stoichiometric value for "x" in the SiOx selector layer 304 (or selector layer 204) can be about 0.5 to about 2. In at least one embodiment, stoichiometric values can be selected such that the target width of the conductive path (eg, filament) through the selector layer 304 (or selector layer 204) is achieved. In some embodiments, the increase in stoichiometric values of the material utilized in the selector layer 304 (or selector layer 204) is due to the defect density of the selector layer 304 or 204 (eg, dungling bond density, particles). Void densities, etc.) can be reduced, and stoichiometric values can be selected to achieve the target defect density that results in the conduction path of the target width. In at least one of the disclosed embodiments, the thickness and stoichiometric values of the selector layer can each be selected so that a target compromise between the maximum threshold voltage and the maximum defect density can be achieved.

0067FIG. 4 shows a block diagram of an exemplary solid-state switching device 400 according to an alternative or additional aspect of the present disclosure. In one or more embodiments, the solid-state switching element 400 can be configured to operate as a volatile switching element in series with a 2-terminal memory element. In other embodiments, the solid-state switching device 400 is manufactured as a stand-alone solid-state electronic circuit component (eg, a volatile switch) or with one or more other electronic devices (eg, on or on a CMOS substrate). It can be configured to operate as an electronic circuit component (which can operate with one or more CMOS elements).

0068As shown in the drawing, the solid-state switching element 400 has an upper electrode 402 and an ion conductive layer.₁404, selector layer 406, ion conductive layer₂A 408 and a lower electrode 410 can be provided. In various alternative embodiments, the solid-state switching device 400 is an ionic conduction layer.₁404 or ionic conductive layer₂The 408 can be equipped with one or the other, rather than both. In alternative or additional embodiments, the upper electrode 402, selector layer 406 and lower electrode 410 can be made substantially similar to layers of similar name in FIGS. 3 and 2 above, but with subject. In the disclosure, various substances or properties are associated with the selector layer 406 within the scope of the present disclosure (the selector layer 406 is an ion conductive layer).₁404 or ionic conductive layer₂Can be selected for suitability when adjacent to 408).

0069The upper electrode 402 or lower electrode 410 may be a noble metal, a suitable metal alloy partially containing the noble metal, a rapidly diffusing substance (eg, Cu, Al, Ti, Co, Ni, Ag, etc.) or a rapidly diffusing metal. Appropriate alloys, etc., or appropriate combinations thereof can be mentioned. In various embodiments, the upper electrode 402 or lower electrode 410 can be an active metal, while in other embodiments, the upper electrode 402 or lower electrode 410 is an integrated circuit wiring metal (eg, W, Al, Cu, TiN, TiW, TaN, WN, etc.). In some embodiments, the upper electrode 402 and the lower electrode 410 can be made of the same material, and in other embodiments, the upper electrode 402 and the lower electrode 410 can be made of different materials.

0070In addition to the above, the solid state switching element 400 can include a selector layer 406. The selector layer 406 can have an electrically resistant material having low permeability to ions of the upper electrode 402 or the lower electrode 410. The low permeability can promote reliable deformation or dispersion of conductive ions in the selector layer 406 in response to signals below the threshold, as described herein. In other words, the low permeability can promote the volatility formation and deformation of the conductive path in the selector layer 406.

0071In addition to the above, the solid-state switching element 400 is an ion conductive layer.₁404 and ionic conductive layer₂408 can be included. Ion conductive layer₁404 or ionic conductive layer₂408 is a solid electrolyte (eg, Ag-Ge-S, Cu-Ge-S, Ag-Ge-Te, Cu-Ge-Te, GeSb, etc.), a metal oxide alloy (eg, AgSiO).₂, CuAl₂Ox etc.) can be possessed. In some embodiments, the solid-state switching ion conductive layer₁The 404 can at least partially depend on the ion diffusion coefficient metric of the top electrode 402. In another embodiment, the ionic conductive layer₂The presence of 408 can at least partially depend on the ion diffusion coefficient metric of the lower electrode 410. In a further embodiment, the ionic conductive layer₁404 or ionic conductive layer₂The 408 can be selected to result in faster ion generation (ie, faster switching or lower voltage switching) of the selector layer 406 as compared to the upper electrode 402 or the lower electrode 408.

0072FIG. 5 shows a diagram of an exemplary electrical response 500 for a selector element according to one or more additional embodiments described herein. In particular, the electrical response 500 may be associated with the selector layer of the selector element described herein. As shown, the vertical axis of the electrical response 500 represents the current (ampere [A]) guided across the selector element (eg, from the top electrode to the bottom electrode), and the horizontal axis of the electrical response 500 spans the selector element. Represents the applied voltage (volt [V]). Note that the left side of the horizontal axis is the negative voltage and the right side of the horizontal axis is the positive voltage (as measured by the top electrode, for example).

0073The sharp nonlinear inflection point of the current value is the positive threshold voltage Vth.₁Near and negative threshold voltage Vth₂Occurs in the vicinity. In some embodiments, the positive threshold voltage Vth₁Is the negative threshold voltage Vth₂Can have the same or substantially the same voltage as. However, in other embodiments, the positive threshold voltage Vth₁Is the negative threshold voltage Vth₂Can have different sizes.

0074In various embodiments, the blue arrow labeled selector "off" current 502 indicates the inflection point of the current, where the lower part shows the current slowly dropping with respect to the voltage and the upper part. The part increases the current very rapidly with increasing voltage to current compliance level 506 (eg, set by a tester or external input device). Selector "on" current 504 is Vth₁Or Vth₂Achieved at a slightly higher voltage. In the example of Figure 5, between 0 and about 1.5 volts, the off-state current is shown to be lower than about 1E-9 amps. In other experiments, low off-state currents were achieved in embodiments with an inflection point voltage of about 1 volt, for example, at values below 1E-10 amps or below 1E-11 amps.

0075As mentioned above, Vth₁Is Vth₂It may be similar to or different from. Further, the amount of current for the inflection point at reverse polarization (eg V &lt;0) may be different from the current for the inflection point where V&gt; 0. In the example of FIG. 5, the off-state current may be lower than about 5E-9. In other experiments, low off-state currents were achieved in embodiments with an inflection point voltage of about -0.5 volts, for example, at values lower than 1E-10 amperes or lower than 1E-11 amperes. In various embodiments, the electrical response 500 is Vth.₁(Vth₁Refers to a narrow voltage range) The voltage is Vth compared to a voltage lower than the range₁Can be characterized by a relatively abrupt change in current as a function of voltage, which meets or exceeds the range of and before current compliance. For example, the electrical response 500 is the number of digits of current per voltage (eg, changes in the digits of current) or I._DECADEVoltage per digit of current or as a function of / V (V / I)_DECADE) Can have a measured current increase as a function. In some embodiments, the electrical response 500 is Vth.₁For these voltage subsets, it can be increased from about 3.5 digits to about 4 digits per 100 millivolts (mV), or from about 0.035 digits / mV to about 0.04 digits / mV.

0076Alternatively, the electrical response 500 can be characterized by a change between about 25 and about 29 V / number of digits between the lowest Vth value and the highest Vth value. In another embodiment, the electrical response 500 is Vth.₂For the following subset of negative voltages, it is possible to have an electrical response of 500 (eg, depending on the negative voltage) between about 0.030 digits / mV and about 0.040 digits / mV. As a different reference, the electrical response 500 is Vth₂It can be between about 25 mV / digit and about 33 mV / digit for a subset of voltages in the range of. In other experiments, the electrical response was measured to be about 17 mV / digit (Vth range of about 100 mV per 6 digits) or about 0.06 digits / mv. In such an embodiment, the nominal Vth value is about 1 volt. Considering the present disclosure, an electrical response of 500 in the range of about 10 mV / digit to about 100 mV / digit is currently achievable. Furthermore, an electrical response of about 0.1 mV / digit to about 0.01 mV / digit is considered to be effective at present.

0077The nominal threshold voltage for the electrical response 500 is between about 1.5 and about 2 volts. In some embodiments, the nominal threshold voltage can be between about 1.5 volts and about 1.8 volts. With respect to these threshold voltage ranges, in FIG. 5, the difference in magnitude between the selector "off" current 502 and the selector "on" current 504 is about four orders of magnitude (eg, 1x10) with respect to the positive voltage.⁴Or 10,000), about 3 and 1/2 digits (eg 5x10) for negative voltage³Or 5,000). Low threshold voltage Vth₁And Vth₂In one embodiment with, a very large difference can be achieved in the magnitude of the selector "off" current 502 vs. the selector "on" current 504. For example, in an embodiment where the nominal threshold voltage Vth1 is about 1.1 volts, the electrical response is about 16 mV / digit.

0078In various embodiments, the electrical response 500 may vary depending on the various selector elements. For example, a variation of the material used in the selector element can be a variation of the selector "off" current 502, a selector "on" current 504 and an electrical response 500 including positive and negative threshold voltages. In another embodiment, the thickness of the selector member layer can additionally affect the electrical response 500. Therefore, the target electrical response 500 can be achieved to some extent by selecting the appropriate top electrode material, selector layer member or thickness or bottom electrode material for the selector element.

0079FIG. 6 depicts a diagram of the electrical response 600 for a selector element, according to an additional embodiment of the disclosed disclosure of interest. The vertical axis of the electrical response 600 represents the current (A) induced by the selector element, and the horizontal axis of the electrical response 600 represents the voltage (V) applied across the selector element. The selector "off" current 602 has an on / off ratio in the range of about 6 to about 10 digits with respect to the selector "on" current 604 in current compliance 606, 1x10.^-11Amps (10.0x10^-12) To 1x10^-4Amps (100.0x10^-6), Shown by a very sharp non-linear response. In one example, a 7-digit current ratio or 10,000,000 ratio of "on" current to "off" current is achieved. This ratio is a nominal positive threshold voltage or Vth less than just 300 millivolts.₁And a nominal negative threshold voltage or Vth of about -200 millivolts₂It can be achieved with. By utilizing a selector element 600 with a suitable selector and top or bottom electrode material, a smaller ratio of "on" current to "off" current can be achieved. For example, in one embodiment, current ratios in the range of 1,000,000 to about 10,000,000 can be achieved. In another embodiment, current ratios in the range of about 100,000 to about 1,000,000 can be achieved. In yet another embodiment, current ratios in the range of about 10,000 to about 100,000 can be achieved. In still other embodiments, current ratios in the range of about 1,000 to about 10,000 can be achieved. In at least one disclosed embodiment, a current ratio of about 100,000 or more can be achieved. In at least one further embodiment, about 10.0x10^-9A current ratio of the same magnitude can be achieved.

0080The electrical response 600 can also be characterized by an increase in current as a function of voltage and vice versa. Vth₁For a subset of the above voltages, the electrical response 600 can have an electrical response 600 between about 3.5 mV / digit and about 14 mV / digit in one embodiment. In another embodiment, the electrical response 600 is Vth.₁For a subset of the above voltages, an electrical response of 600 can be between about 0.07 digits / mV and about 0.25 digits / mV. In a further embodiment, Vth₂For the second subset of voltages below, the electrical response 600 can be between about 7 mV / digit and about 7.5 mV / digit. In another embodiment, for a second subset of voltage, the electrical response 600 can be between about 0.15 digits / mV and about 0.12 digits / mV. In at least one additional example, the electrical response of the disclosed selector element can be about 1.5 mV / digit or about 0.7 digits / mV. In a further embodiment, the electrical response can be selected from the range of about 1 mV / digit to about 60 mV / digit. In yet another embodiment, the electrical response can be selected from a range of about 1 digit / mV to about 0.15 digits / mV.

0081FIG. 7 shows a block diagram of an exemplary memory element 700 according to a further embodiment of the present disclosure. The memory element 700 can include a 2-terminal memory component 702 that is electrically connected to the selector element 706. In addition, the memory element 700 can include a first terminal 702A and a second terminal 702B for applying an operation signal (for example, a read signal, an erase signal, a program signal, a rewrite signal, etc.) over the memory element 700.

0082The memory element 700 can be a non-volatile two-terminal switching element. Resistive Memory, Resistive Switching Memory (eg Resistive Random Access Memory (RRAM)), Phase Change Memory (PCRAM), Magnetoresistive Memory (MRAM), Ferroelectric Memory (FeRAM), Organic Memory (ORAM), Conductive Examples include bridge memory (CBRAM) and one-time programmable memory (OTP). In certain embodiments, the memory element 700 can be a bipolar memory element. Therefore, the memory element 700 can program or write according to the signal of the first polarity. Further, the memory element 700 can be erased according to the signal of the second polarity. According to various embodiments, the selector element 706 can be configured as a bipolar switching element. In such an embodiment, the selector element 706 has a first polarity threshold of threshold 1 (eg, first polarity threshold voltage Vth).₁Etc.), it is possible to switch from the non-conductive state to the conductive state according to the signal of the first polarity. Further, the selector element 706 has a threshold value 2 (for example, a second polarity threshold voltage Vth) which is a second polarity threshold.₂Etc.), it is possible to switch from the non-conductive state to the conductive state according to the second signal of the second polarity.

0083In various embodiments, the selector element 706 can have a higher electrical resistance in the non-conductive state than an electrical resistance in the associated off state (eg, erased state) of the 2-terminal memory component 702. Similarly, the selector element 706 can be configured to have a higher conductivity in the conductive state than in the associated on-state (eg, programmed state) of the 2-terminal memory component 702. Therefore, the selector element 706 can serve as an activating / deactivating component of the memory element 700, and in the non-conductive state, it hinders the memory operation in the 2-terminal memory component 702 and is in the conductive state. If 2-Enable memory operation on Terminal Memory Component 702. 2-Regarding an embodiment in which the terminal memory component 702 and the selector element 706 are bipolar switching elements, the activation / deactivation effect of the selector element 706 is not only a secondary polarity signal (eg, an erase signal, etc.), but also a first It can be generated in response to a unipolar signal (eg, read signal, program signal, etc.).

0084In at least one embodiment, the activation / deactivation of the memory element 700 can be characterized by a voltage divider. For example, in the off state, the selector element 706 can be selected to have a appropriately greater resistance than the 2-terminal memory component 702. Therefore, in the off state, the selector element 706 can be configured to drop most of the voltage applied between the two terminal terminals 702A and 702B, thereby the 2-terminal memory component 702. 2-Terminal memory component 702 is isolated from voltage suitable for programming, erasing or reading. A voltage above the first polarity threshold turns on the selector element 706 and reduces the resistance of the selector element 706 to a resistance lower than that of the 2-terminal memory component 702. As a result, the signal applied to the memory element 700 affects the 2-terminal memory component 702. In embodiments where the selector element 706 is a bipolar element, the selector element 706 is a second polarity signal that is less than or equal to the second polarity threshold (which insulates the 2-terminal memory component 702 from such signal) or (2-terminal). (Exposing the memory component 702 to such a signal) It is possible to respond to a signal exceeding the second polarity threshold in the same manner as described above for the signal of the first polarity. However, in some embodiments, the selector element 706 can respond at least partially differently with respect to the first and second polarity signals. As an example, the selector element 706 can have a different first threshold value corresponding to the first polarity signal as compared with a second threshold value corresponding to the second polarity signal. In another example, the selector element 706 can have a different non-linear response with respect to the first polar signal as compared to the relevant non-linear response with respect to the second polar signal or the like or a suitable combination thereof.

0085The inventors of the present disclosure believe that the memory element 700 can provide significant advantages over other proposed or theorized mechanisms that bring high density memory to advanced technology nodes. As described herein, the selector element 706 can provide a non-linear I-V response to the 2-terminal memory component 702. The non-linear response can significantly reduce leakage current for 1T-nR memory arrays with large values of n (eg, n is 512, 1024, or greater) (see, eg, Figure 9 below). ).

0086In addition, the selector element 706 can provide significant advantages over other non-linear electronic circuit components such as solid state diodes. As an example, the selector element 706 can be manufactured at relatively low temperatures, while solid state diodes generally need to exceed 500 ° C. High temperatures can impede back end device manufacturing (eg, back end of line) on integrated circuits if the temperature exceeds the thermal budget of the integrated circuit. While the selector element 706 can be manufactured within the thermal budget of many integrated circuits, solid-state diodes generally cannot. In some embodiments, the selector element 706 can be manufactured below 400 ° C, in other embodiments the selector element 706 can be manufactured below 300 ° C, and yet in other embodiments. In, the selector element 706 can be manufactured at 200 ° C. or less than 200 ° C. These temperatures allow the back-end manufacture of memory devices 700 on many integrated circuits, including manufactured CMOS devices, silicon-on-insulator (SoI) devices, etc. or appropriate combinations thereof (see, eg, Figure 8 below). Becomes possible.

0087In addition to those mentioned above, solid-state diodes cannot be reliably manufactured or operated reliably at 22 nm or less technology nodes. In contrast, selector element 706 can operate at 22 nm technology node in some embodiments, and in additional embodiments, selector element 706 can operate at 14 nm technology node, yet in other embodiments. In the embodiment, the selector element 706 can operate on a 10 nm technology node, a 7 nm technology node, a 5 nm technology node, etc. (or a suitable half node smaller than 22 nm). Moreover, solid-state diodes generally do not work in a bipolar mode that switches from high resistance to low resistance in response to positive and negative signals. Therefore, solid-state diodes cannot generally be used with bipolar memory for rewritable memory applications. The selector element 706 can provide non-linear properties to the bipolar memory, but not limited to, thereby providing a non-linear I-V response for the erasing signal of the second polarity, as well as the first polarity. Non-linear I-V responses to the program or read signal can be facilitated. With respect to the above, the selector element 706 can be utilized in a 3D array of memory elements 700 in addition to the 2D array, which results in a much higher memory density than the technology limited by the 2D array. Is brought.

0088In an alternative or additional embodiment of the present disclosure, the selector element 706 can include a selector member associated with a first current corresponding to an applied voltage smaller than the threshold voltage associated with the selector element 706. Further, the selector member can be associated with a second current depending on the applied voltage above the threshold voltage. The ratio of the second current to the first current can be selected from the range of ratios of about 1,000 to about 10,000 in one or more embodiments. In other embodiments, the ratio of the second current to the first current can be selected from the range of ratios from about 10,000 to about 100,000. In yet another embodiment, the ratio of the second current to the first current can be selected from the range of ratios from about 100,000 to about 1,000,000. According to a further embodiment, the ratio of the second current to the first current can be selected from the range of the ratio of about 1,000,000 to about 10,000,000.

0089According to other disclosed embodiments, the selector element 706 can include an upper electrode 708 made of a first metal and a lower electrode 716 made of a second metal. In various embodiments, the first metal can be similar to the second metal, while in at least one embodiment the first metal can be the same as the second metal. In a further embodiment, the primary or secondary metal can be selected from the group consisting of active metals, W, Al, Cu, TiN, TaN, WN and TiW. In other embodiments, the selector element 706 can include a first ion conductor 710 or a second ion conductor 714. In one embodiment, the first ion conductor 710 or the second ion conductor 714 may be selected from the group consisting of ion conductors, electrolytes (eg, solid electrolytes), chalcogenides, metal oxides and metal oxide alloys. it can.

0090According to additional embodiments, the selector element 706 can include a selector layer 712. The selector layer 712 can include a selector member, which is configured to allow conductive ions to permeate through the selector member of the selector layer 712 in response to a voltage across the upper electrode 708 and the lower electrode 716. ing. In a further embodiment, the selector member can include a material selected from the group consisting of insulators, non-stoichiometric oxides, solid electrolytes, chalcogenides, and metal-doped materials.

0091According to other embodiments, the selector element 706 can have a first-polarity threshold voltage or a second-polarity second threshold voltage that is approximately half the program voltage of the 2-terminal memory component 702. In such an embodiment, the read voltage of the 2-terminal memory component 702 can be smaller than the program voltage and greater than the threshold voltage of the first polarity or the second threshold voltage of the second polarity.

0092FIG. 8 comprises an exemplary memory architecture comprising a multiple array of 2-terminal memory devices according to one or more embodiments of the subject disclosure, configured to reduce leakage current on the conductors of this array. A block diagram from the side of the Char 800 is shown. In some embodiments, the memory architecture 800 can facilitate the improvement of memory density even at advanced technology nodes (eg, 22 nm and below). In another embodiment, Memory Architecture 800 provides high capacity, rapidly switchable, long-life memory integrated with integrated circuits, including manufactured electronic circuit components, at a very low manufacturing cost. Can be facilitated.

0093As shown in the drawing, the memory element 800 can include a substrate 802. The substrate 802 can be a silicon wafer or other suitable insulating semiconductor material used in the manufacture of one or more electronic devices 804 therein, or in part, on the substrate 802 (eg, electrons). The element 804 may include a plurality of electronic elements, SoI elements, or the like, or an appropriate combination thereof). In the example of FIG. 8, the electronic element 804 can be formed in the substrate 802 at least partially. Although electronic device 804 is shown entirely within substrate 802, it should be understood that electronic device 804 can be constructed at least partially on or above substrate 802 (eg, substrate process layer). Is. For example, the one or more electronic elements 804 may include a transistor having source or drain contacts formed within the substrate 802, a floating gate in a layer above the substrate 802, and the like. The one or a plurality of electronic elements 804 may be a drive circuit, a logic circuit, a processing element, an array logic, or the like. The back end of line can be formed within or interspersed with one or more layers of 807 insulators. The back end of line includes a conductive layer, a memory layer (eg, a resistive switching layer or other suitable 2-terminal memory active region layer), a selector layer, a barrier layer, a conductive contact layer or an insulator layer, or any other suitable. A combination of them can be mentioned.

0094The memory element 800 may include one or more select transistors 806 for activating or deactivating the memory cell 812 of the memory element 800. The select transistor 806 is a via which is the first via layer.₁Bitline, the first bitline associated with memory cell 812, through 808₁Can be connected to 810. When the select transistor 806 is activated, the appropriate signal (eg, program signal, read signal, erase signal, etc.) will be via.₁Bitline through 808₁It can be applied to 810. Bit line₁The 810 is sequentially connected to each of the first contacts of the first set of memory cells 812 (the lower set of memory cells shown in FIG. 8). Bit line from operating signal by deactivating select transistor 806₁810 can be quarantined, thereby via₁The current on the 808 is blocked. Thus, the select transistor 806 can serve as a 1T transistor in a 1T-nR memory architecture (n is defined by the number of memory cells 812 activated by the select transistor 806).

0095Memory cells in the first (bottom) array are bitlines₁It has each first contact connected to the 810 and each second contact connected to each of the wordlines 818. Note that each memory cell 812 has a selector component 814 that is electrically connected to the memory component 816. The memory component 816 can include, for example, the 2-terminal switching elements (eg, resistive memory, phase change memory, magnetoresistive memory, etc.) described with respect to the 2-terminal memory component 702 of FIG. 7 above. Similarly, the selector component 814 is a selector element, selector layer and optionally 1 described herein having one or more electrodes (see, eg, FIGS. 1, 2, 3, 4, 7 above). Alternatively, a plurality of ion conductor layers can be provided.

0096In addition, the orientation of selector component 814 and memory component 816 can be reversed, for example, the first array of memory cell 812 shows the selector component 814 under memory component 816 and the second array of memory cell 812 ( It should be understood that the upper array) can show the selector component 814 on the memory component 816. The memory cell 812 is not limited to the drawn arrangement, and in an alternative embodiment, the memory cell 812 may uniformly include its own selector component 814 under each memory component 816, and other An embodiment may uniformly include each selector component 814 on each memory component 816, yet another embodiment may include the combinations described above, and a further embodiment may include memory cell 812. It should be understood that for a subset, each selector component 814 and memory component 816 can contain non-uniform orientations.

0097The second array (upper array) of memory cell 812 connects to each of the wordlines 818 at each memory component 816 and is the second bitline at the associated selector component 814.₂Connected to 820. Bit line₂The 820 is a first layer via (activated by a select transistor).₁806, second layer via₂822 and third layer vias₃It can be activated through a series of vias, including 824. In other embodiments, more or less vias are bitlined.₂It can be used to connect the 820 and its associated select transistor 806.

0098In some embodiments, vias₁806, beer₂822 or via₃824 (collectively referred to as via layers 806, 822, 824) is known in the art, or as known to those skilled in the art by the content provided herein, bitline 810, 820 or word. A line 818, a source line (not shown), etc. can be connected to the component of the electronic element 804 or the 2-terminal switching element 812. The via layers 806, 822, and 824 can have a metal, a conductive silicon-based substance, or the like. In some disclosed embodiments, via layers 806, 822, 824 or other via layers (not shown) can be utilized to form one or more layers of nonlinear memory cell 812 (eg, memory). One or more layers of component 814 or selector component 816 can be manufactured at least partially with via layers 806, 822, 824).

0099It should be understood that the memory element 800 can include an array of memory cells 812 estimated in additional dimensions, such as a two-dimensional or three-dimensional array. For example, the memory element 800 may include an additional array of memory cells 812 inside and outside FIG. In a further embodiment, the memory element 800 is a bit line.₂An additional layer of bitlines and wordlines can be provided on the 820 with each array of memory cells 812 in between, which can increase the number of vertical memory cells 812.

0100Note that the memory cell 812 is shown as a vertical arrangement (eg, the memory component 814 on the selector component 816), and in other embodiments, the non-linear memory cell 812 can be arranged along the tilt angle. I want to be. For example, the memory component 816, the selector component 814, or a subset of the solid-state layers described above can be sequentially arranged along a direction that is not perpendicular to the top surface of the substrate 802. In at least one embodiment, the memory component 814 and the selector component 816 can be arranged in a direction parallel or substantially parallel to the top surface of the substrate 802 or in any other suitable direction. In such an embodiment, wordline 818 or bitline₁810 or bit line₂The 820 can be reoriented in a manner appropriate to adapt to oblique orientation (eg, as a film or filler in vias).

0101The inventors of the present disclosure understand that some prior art for manufacturing nonlinear electronic components involves very high temperatures (eg, temperatures of 500 ° C, 600 ° C or higher). The inventors understand that these high temperature processes are generally incompatible with advanced CMOS processing (eg, the maximum permissible process temperature is &lt;370-430 ° C). Therefore, the present inventors understand that the manufacture of the memory element 800 has conventionally required a non-monolithic process. However, the inventors consider that non-monolithic manufacturing is more complex, costly, longer manufacturing time, and more costly than, for example, a monolithic process. In contrast, monolithic manufacturing, as an example, has a non-linear memory cell 812 (or, for example, the interconnect layer 806,) in a single integrated chip (with electronic components 804 manufactured in (or above) it). It simply involves a set of additional masks or etching steps to form the via layers 810, 812 or metal conductors 818).

0102FIG. 9 shows a block diagram of an exemplary array 900 of memory cells in an additional embodiment of the present disclosure. As depicted, the array 900 can be a crossbar memory array with a first set of conductors, the bitline 902, a second set of conductors, the wordline 904, and a 2-terminal memory element. The bitline 902, which is a set of conductors, is substantially parallel to the wordline 904, which is a second set of conductors, and each 2-terminal memory element is the intersection of each bitline 902 and the wordline 904. Exists in. The array 900 has a sneak path current (eg, capacitive voltage) caused by a program supply signal applied to a selected one of the word lines 904, in addition to a sneak path current caused by an inter-bitline potential (eg, capacitive voltage). Also known as leakage current). Array 900 presents a problem with sneak pass current. Therefore, the array 900 is useful for demonstrating the benefits of the non-linear characteristics of 2-terminal memory.

0103As mentioned above, the array 900 comprises a set of bitlines 902 that are substantially orthogonal to the set of wordlines 904. Where each bitline 902A, 902B, 902C intersects one of the wordlines 904A, 904B, 904C, the non-linear 2-terminal memory cell is the first terminal connected to one of the bitlines 902 and the wordline 904. Arranged to have a second terminal connected to one of the. In addition, the selected cell 906 is a non-linear 2-terminal memory cell that is the target of program manipulation. In particular, the programming operation includes a programming signal 910 of about 3 volts applied to the wordline 904B. In some embodiments, a medium signal of about 1.5 volts can be applied to the non-selected wordlines 904A, 904C, while in other embodiments the wordlines 904A, 904C can remain floating. it can. In addition, the bit lines 902B can add zero volts (eg, provide a potential difference of 3 volts across the selected cell 906), while the bit lines 902A, 902C can add 1.5 volts (or, for example, at least). Can remain floating in one embodiment). Capacitive coupling between bitlines 902A, 902C and wordline 904 induces voltages above zero volts and less than 3 volts to bitlines 902A, 902C.

0104The program operating voltage can cause multiple sneak path currents; a sneak path caused by the signal program 910 (referred to as the program sneak current 912), and a sneak path on the bitline 902B (referred to as the bitline sneak current 914). is there. The bitline sneak current 912 is drawn by the dashed line, while the program sneak current 912 is drawn by the narrow solid line. Two paths are drawn for the bitline sneak current 914 through the non-selected cell 908 on the wordlines 904A, 904C. Each of the bitline sneak currents 914 shares the bitline 902B as a common component of their respective paths. The program sneak current 912 is transmitted to the bit lines 902A and 902C through the selected local word line 904B, respectively.

0105Note that the program supply current sneak path on the wordline other than the selected wordline 904B of the memory array 900 is not drawn. If the non-selected wordlines 904A, 904C can float, the capacitive coupling, in some embodiments, induces a voltage on the non-selected wordlines 904A, 904C to 1.5 volts (eg, depending on the inter-wordline capacitance). be able to. Sneak paths on these non-selected wordlines can exist, but can have a small impact on the sensing margin, and this is not depicted.

0106Over 5 volts). Therefore, despite the fact that the memory component 918 of the unselected cell 908 is in the "on" memory state, the magnitude of the sneak pass current in the array 900 is very small and its effect on the sensing margin of the selected cell 908 is negligible. This is because the selector component 916 of non-selected cell 908 is in a non-conductive state, which is non-conducting even though the memory component 918 of non-selected cell 908 is programmed to be relatively conductive. The current through the selected cell 906 is reduced by about 4 orders of magnitude. In other embodiments, the effect of capacitive coupling between bitlines and between wordlines is further reduced (eg, by utilizing a relatively small local wordline or local bitline with the low capacitance of the array 900). Can be done. The capacitive coupling effect is reduced (or the program voltage is reduced) so that the floating bit lines 902A, 902C or the floating word lines 904A, 904C each have a voltage of less than about 200 millivolts, I-V in Figure 6. A responsive non-linear memory cell can be utilized for the array 900. In this case, the magnitude of the sneak pass current can be further reduced (eg, up to about 7 digits) by the respective selector component 916. This large current reduction can greatly increase the number n of memory cells in the 1T-nR array architecture, while maintaining an acceptable sensing margin for the selected cell 908. Therefore, such a 1T-nR architecture can provide very good memory density even for high technology nodes (eg 22nm or less).

0107The diagram described above describes the interaction between a memory cell, its conductive layer, or some component (eg, layer) of the memory architecture consisting of such memory cell / conductive layer. Understand that, in a suitable alternative embodiment of the subject matter disclosure, such a diagram may include specific components and layer fingers, some specific components / layers or additional components / layers. Should be. A subcomponent can also be implemented to be electrically connected to another subcomponent rather than being contained within the parent component / layer. For example, an intermediate layer may be provided adjacent to one or more disclosed layers. As an example, a suitable barrier layer that reduces or controls unexpected oxidation can be placed between one or more disclosed layers. In yet other embodiments, the disclosed set of memory stacks or film layers can have fewer layers than the one depicted. For example, the switching layer can be in direct electrical contact with the conductive wire rather than being sandwiched between electrode layers. In addition, it should be noted that one or more disclosed steps can be combined into a single step that provides collective functionality. The components of the disclosed architecture are not specifically described herein, but may also interact with one or more other components known to those of skill in the art.

0108Considering the exemplary diagram above, the processing methods that can be implemented according to the disclosed subject matter are better understood by reference to the flowchart of FIG. 10-12. For simplicity, the method of FIG. 10-12 is displayed and described as a series of blocks, while some blocks exist in different order or are drawn and described herein. It should be understood and recognized that the subject matter of the claim is not limited to the block order, as it may co-exist with other blocks of origin. Moreover, not all blocks shown are necessarily required to carry out the methods described herein. In addition, it should be further understood that some or all of the methods disclosed throughout this specification can be stored in the product to facilitate transfer and transfer of such procedures to electronic devices. .. The term product used is intended to include any computer-readable device, carrier-linked device, or computer program accessible from a recording medium.

0109FIG. 10 shows a flowchart of an exemplary method 1000 for manufacturing a solid state selector element. In 1002, method 1000 can have a step of providing a first layer structure containing a first metallic material. In 1004, method 1000 can have a step of providing a layer of selector members adjacent to the first layer structure. In at least one embodiment, the layer of the selector member can be in contact with the first layer structure. In 1006, the method 1000 can have a step of providing a second layer structure containing a second metallic material so as to be adjacent to the layer of the selector member. In at least one embodiment, the second layer structure can be in contact with the layer of the selector member. In alternative or additional embodiments, the first metallic material can be configured to provide conductive ions to the selector member depending on the voltage applied across the first and second layer structures. In another embodiment, the selector member can be configured to allow conductive ions to permeate through the layers of the selector member in response to a voltage applied across the first and second layer structures. According to yet another embodiment, the first layer structure, a layer and a second layer structure selector member, it can form a solid-state selector element Ru. In a further embodiment, the selector element can be electrically arranged in series with the 2-terminal memory element.

0110According to other embodiments, the second metallic material is a selector depending on a second voltage of a polarity different (eg, opposite polarity) than the voltage applied across the first and second layer structures. It can be configured to provide additional conductive ions to the member. In at least one embodiment, the additional conductive ions can be at least partially dissipated from the layer of the selector member in response to a voltage below the threshold voltage or a second voltage. In a further embodiment, the conductivity of the layer of the selector member can be reduced in response to at least partial dissipation of the additional conductive ions from the layer of the selector member.

0111In yet other embodiments, the primary metallic material is a noble metal (eg Pt, Pd, Ag, Au), a metal alloy partially containing the noble metal, a rapid electric field enhancing diffuser (eg Ni, Cu, Ag, Co, etc.). It can be selected from the group consisting of Fe) and CMOS wiring metals (eg W, Al, Ti, TiN, TaN, WN). In another embodiment, the layer of the selector member may be selected from the group consisting of insulators, non-stoichiometric oxides, chalcogenides, solid electrolytes containing one or more of Ge, Sb, S and Te, and metal-doped materials. it can. In yet another embodiment, the step of providing the first layer structure is a step of providing a first electrode containing a metallic substance selected from the group consisting of active metal, W, Al, Cu, TiN and TiW. Can include. In yet another embodiment, the step of providing the first layer structure is additionally selected from a layer of selector members and a second group consisting of an ionic conductor, an electrolyte, a metal oxide, and a metal oxide alloy. A step of providing a first ion conductor placed between the metal material and the metal material can be included.

0112According to a further embodiment, the method 1000 can additionally have a step of forming a plurality of 2-terminal memory elements on the semiconductor substrate and a step of forming a plurality of selector elements. In one or more embodiments, each of the 2-terminal memory elements can be associated with at least one selector element from the plurality of selector elements. In another embodiment, the plurality of 2-terminal memory elements may include a 2-terminal memory element, and the plurality of selector elements may include a selector element. In another embodiment, the method may additionally include a step of forming a crossbar memory structure from a plurality of 2-terminal memory elements and a plurality of selector elements.

0113FIG. 11 shows a flow chart of an exemplary method 1100 for manufacturing a 2-terminal memory with non-linear I-V characteristics according to an additional embodiment of the present disclosure. At 1102, method 1100 can include the step of forming a first layer structure on the substrate containing the first metallic material. In at least one embodiment, the substrate may include one or more electronic elements (eg, CMOS elements, SOI elements, etc.) formed therein or on it. In 1104, method 1100 can include the step of forming an ionic conductive layer in contact with the first layer structure. In addition, in 1106, method 1100 can include the step of forming a layer of selector members in contact with the ionic conduction layer. At 1108, method 1100 can include the step of forming a second ion conductive layer in contact with the selector member. Further, in 1110, method 1100 can include the step of forming a second layer structure having a metallic material and in contact with the second ion conductor. In addition to those mentioned above, in 1112, method 1100 can include the step of forming a 2-terminal memory element that is electrically in series with the second layer structure. In 1114, method 1100 can include the step of connecting the first conductor of the memory device to the first layer structure. In 1116, method 1100 can include the step of connecting the second conductor of the memory device to the 2-terminal memory device.

0114FIG. 12 shows a flowchart of an exemplary method 1200 for activating a crossbar memory array, according to a further embodiment of the disclosed disclosure of interest. For example, a crossbar memory array can include a plurality of 2-terminal memory elements and a plurality of selector elements, each of the plurality of 2-terminal memory elements in series with one selector element from the plurality of selector elements. Each selector element can be associated with a first electrical characteristic depending on the applied voltage below the threshold voltage and can be associated with a second electrical characteristic depending on the applied voltage above the threshold voltage. .. At 1202, method 1200 can include a step of applying a first voltage above the threshold voltage to a first memory structure that includes a first 2-terminal memory element in series with the first selector element. In 1204, method 1200 applies a second voltage below the threshold voltage to a second memory structure containing a second 2-terminal memory element in series with the second selector element and at the same time applies the first voltage. Can have. In 1206, the method 1200 can have a step of determining the current in response to applying the first voltage at the same time as applying the second voltage. In various embodiments, the current includes a first current associated with the first selector element and a second current associated with the second selector element. Further, the current ratio of the first current to the second current is within the range of the ratio selected from the group consisting of about 1,000 to about 10,000, about 10,000 to about 100,000, about 100,000 to about 1,000,000 and about 1,000,000 to about 10,000,000. Can be. In a further embodiment, both the 1st 2-terminal memory element and the 2nd 2-terminal memory element can be in a programmed state.

0115According to one or more additional embodiments, the selector element of the plurality of selector elements is between the first active metal layer, the second active metal layer and the first active metal layer and the second active metal layer. It can be provided with a selection layer to be arranged. In another embodiment, the step of applying the first voltage at the same time as applying the second voltage applies the first voltage above the threshold voltage to the first selector element, thereby the metal of the first active metal layer. The first active metal layer further includes a step in which a conductive filament of ion particles is formed in the selection layer of the first selector element, and a step in which a second voltage lower than the threshold voltage is applied to the second selector element. The conductive filament of the metal ion particles of the above is not formed in the selective layer of the second selector element (or is formed only in a subset of the selective layer of the second selector element and is a conductive path passing through the selective layer of the second selector element. Does not provide).

0116According to a further embodiment, the threshold voltage can be in a range selected from the group consisting of about 0.1 volt to about 2 volt and about 2 volt to about 4 volt. In other embodiments, the second current is about 1x10.^-8About 1x10 from amps^-14It can be selected from the amperage range. In yet another embodiment, the first current is about 1x10.^-3About 1x10 from amps^-6It can be selected from the amperage range.

0117In an additional embodiment, the step of applying the first voltage at the same time as applying the second voltage sets the second voltage below the threshold voltage to the second plurality of selector elements (unlike the plurality of selector elements). It may further have a step of applying to a second plurality of 2-terminal memory elements in series (unlike a plurality of 2-terminal memory elements). In another embodiment, the number of 2-terminal memory elements in the second plurality of 2-terminal memory elements can be selected from the range of about 1,000 to about 250,000. In yet another embodiment, both the 1st 2-terminal memory element and the 2nd 2-terminal memory element are in the erased state. In yet another embodiment, the 2-terminal memory device includes a filament-based resistant memory device.

0118In various embodiments of the disclosed disclosure, the disclosed memory or memory architecture can be used as a stand-alone or integrated internal memory element with a CPU or microcomputer. Certain embodiments can be implemented, for example, as part of computer memory (eg, random access memory, cache memory, read-only memory, storage memory, etc.). Other embodiments can be implemented, for example, as portable memory elements. Examples of suitable portable memory elements include removable memory (eg, secure digital (SD) cards, universal serial bus (USB) memory sticks or compact flash (CF) cards, etc., or suitable combinations described above). (See Figures 13 and 14 below).

0119NAND FLASH is used in compact FLASH devices, USB devices, SD cards, solid state drives (SSDs) and storage class memory as well as other form factors. NAND has proven to be a successful technology for scaling down to smaller devices and higher chip densities over the last few decades, but scale-down technology exceeds 25 nanometer (nm) memory cell technology. From the beginning, some structural problems, performance problems and reliability problems became clear. These subsets or similar considerations are addressed by the disclosed aspects.

0120To provide content regarding the various aspects of the disclosed subject matter, FIG. 13 and the following description provide a concise and general description of the appropriate environment in which the various aspects of the disclosed subject matter can be implemented or processed. The purpose is to provide. While the subject matter has been described above in the general content of the processing procedures for manufacturing and manipulating solid-state memory and semiconductor architectures alongside memory or architectures, those skilled in the art will disclose the subject disclosure to other architects. You will recognize that it can also be implemented in combination with chars or processing procedures. Further, as will be apparent to those skilled in the art, the disclosed processing can be performed by the processing system or computer processor alone or with a host computer (eg, computer 1402 in FIG. 14 below), which can be done simply. Single-processor or multi-processor computer systems, mini-computing devices, mainframe computers, as well as personal computers, portable computing devices (eg, PDA, smartphones, watches) and microprocessor-type or programmable home or industrial electronics It can include equipment and the like. The indicated embodiment may be performed in a distributed computing environment in which tasks are performed by remote processing devices linked through a communication network. However, some, if not all, aspects of major innovations of interest, otherwise all aspects are in stand-alone electronic devices (eg memory cards, flash memory modules or removable memory, etc.). Can be executed. In a distributed computing environment, program modules can be installed in local and remote memory storage modules or devices.

0121FIG. 13 shows a block diagram of an exemplary operation and control environment 1300 of the memory cell array 1302 according to the aspect of the subject disclosure. In at least one aspect of the disclosed disclosure, the memory cell array 1302 can include various memory cell technologies. In at least one embodiment, the memory cell of the memory cell technique can include a 2-terminal memory having a non-linear I-V response, as described herein. In another embodiment, the memory cell array 1302 can store an operation configured to electrically connect a 2-terminal memory cell electrically connected to a selector element.

0122The column controller 1306 can be formed adjacent to the memory cell array 1302. In addition, the column controller 1306 can be electrically connected to the bit lines of the memory cell array 1302. The column controller 1306 can control each bitline so that the appropriate program, erase or read voltage can be applied to the selected bitline.

0123In addition, the operating and controlling environment 1300 can include a row controller 1304. The row controller 1304 is formed adjacent to the column controller 1306 and can be electrically connected to the word line of the memory cell array 1302. Row controller 1304 can select a particular row of memory cells with the appropriate selection voltage. In addition, row controller 1304 can facilitate programming, erasing or reading operations by applying the appropriate voltage to the selected wordline.

0124The clock source 1308 can provide each clock pulse to facilitate read, write, and program operations on the row controller 1304 and column controller 1306. The clock source 1308 can further facilitate the selection of wordlines or bitlines, depending on the external or internal commands received by the operating and controlling environment 1300. The input / output buffer 1312 is an external host device such as a computer or other processing device via an I / O buffer or other I / O communication interface (not drawn, but for example, the computer 802 in FIG. 12 below. Can be connected to). The input / output buffer 1312 receives write data, erase instructions, outputs readout data, receives address data and command data, and addresses data for each instruction. Can be configured to receive. Address data can be transferred from row controller 1304 and column controller 1306 by address register 1310. In addition, the input data is transmitted to the memory cell array 1302 via the signal input line and the output data is received from the memory cell array 1302 via the signal output line. The input data can be received from the host device and the output data can be sent to the host device via the I / O buffer.

0125The command received from the host device can be provided to the command interface 1314. The command interface 1314 can be configured to receive an external control signal from the host device and can determine whether the data input to the input / output buffer 1312 is write data, a command or an address. .. Input commands can be transferred to state machine 1316.

0126The state machine 1316 can be configured to manage the programming and reprogramming of the memory cell array 1302. The state machine 1316 receives commands from the host device via the input / output buffer 1312 and command interface 1314 and manages read, write, erase, data input, data output and similar functions associated with the memory cell array 1302. .. In some embodiments, the state machine 1316 can send and receive acknowledgments and negative responses regarding the receipt or execution of various commands.

0127The state machine 1316 can control the clock source 1308 to implement functions such as read, write, input, and output. Control of the clock source 1308 can trigger output pulses configured to facilitate the row controller 1304 and column controller 1306 to perform certain functions. For example, the output pulse can be transferred, for example, to the selected bitline by the column controller 1306, or, for example, to the wordline by the row controller 1304.

0128With respect to FIG. 14, the systems and processes described below can be embedded in hardware such as a single integrated circuit (IC) chip, multiple ICs, and an application specific integrated circuit (ASIC). Furthermore, the order in which some or all processing blocks appear within each processing should not be considered limited. Rather, it should be understood that some processing blocks can be executed in different orders, all of which may not be explicitly illustrated here.

0129With reference to FIG. 14, a suitable operating environment 1400 for performing various features of the claims includes computer 1402. Computer 1402 includes a processing unit 1404, system memory 1406, codec 1435, and system bus 1408. System bus 1408 combines system components, including but not limited to system memory 1406, into processing unit 1404. Processing unit 1404 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures can also be used as processing unit 1404.

0130System Bus 1408 includes Industry Standard Architecture (ISA), Microchannel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), and Card Bus. Includes, but is limited to, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association Bus (PCMCIA), Firewire (IEEE 1394), and Small Computer System Interface (SCSI). It can be any of the various types of bus structures, including memory buses or memory controllers, peripheral or external buses, and / or local buses, which use a variety of available bus architectures.

0131System memory 1406 includes volatile memory 1410 and non-volatile memory 1414, which may use one or more of the disclosed memory architectures in various embodiments. The basic input / output system (BIOS), which includes basic routines for transmitting information between components in computer 1402, such as at boot time, is stored in non-volatile memory 1412. In addition, according to this innovation, codec 1435 may include at least one of the encoders or decoders, where at least one of the encoders or decoders consists of hardware, software, or a combination of hardware and software. Good. Codec 1435 may be included in non-volatile memory 1412, although codec 1435 is shown as a separate component. By way of example, but not by limitation, the non-volatile memory 1412 may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The non-volatile memory 1412 may use one or more disclosed memory architectures in at least some of the disclosed embodiments. Further, the non-volatile memory 1412 can be computer memory (eg, physically integrated with computer 1402 or its mainboard) or removable memory. Examples of suitable removable memory capable of implementing the disclosed embodiments may include secure digital (SD) cards, CompactFlash (CF) cards, universal serial bus (USB) memory sticks, and the like. Volatile memory 1410 includes random access memory (RAM) acting as external cache memory and may use one or more of the disclosed memory architectures in various embodiments. By way of example, but not by limitation, RAM includes static RAM (SRAM), dynamic RAM (DRAM), and system.

0132Computer 1402 may also include removable / non-removable volatile / non-volatile computer storage media. FIG. 14 shows, for example, disk storage 1414. Disk storage 1414 includes devices such as magnetic disk drives, solid state disks (SSDs), floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Not limited. In addition, the disk storage 1414 can use the storage medium separately or as a compact disc ROM device (CD-ROM), CD recordable drive (CD-R drive), CD rewritable drive (CD-RW drive), or , Can be included in combination with other optical disk drives such as Digital Versatile Disc ROM Drives (DVD-ROMs), but may be included in combination with other storage media without limitation. Detachable or non-removable interfaces, such as interface 1416, are commonly used to facilitate connection of disk storage 1414 to system bus 1408. It should be understood that disk storage 1414 can store information about the user. Such information may be stored or provided on a server or in an application running on your device. In one embodiment, the user may be informed (eg, via output device 1436) of the type of information stored in disk storage 1414 and / or sent to a server or application. Users may be offered the opportunity to opt in or out of having information that is collected and / or shared with a server or application (eg, via input from input device 1428).

0133It should be understood that Figure 14 describes software that acts as an intermediary between the user and the listed basic computer resources in a suitable operating environment 1400. Such software includes operating system 1418. The operating system 1418 can be stored in disk storage 1414 and operates to control and allocate resources for computer 1402. Application 1420 utilizes resource management by operating system 1418 through program module 1424 and program data 1426, such as boot / shutdown transaction tables stored in system memory 1406 or disk storage 1414. It should be understood that the claims can be implemented in various operating systems or combinations of operating systems.

0134The user inputs an instruction or information into the computer 1402 through the input device 1428. The input device 1428 includes pointing devices such as mice, trackballs, stylus, touchpads, keyboards, microphones, joysticks, gamepads, satellite dishes, scanners, TV tuner cards, digital cameras, digital video cameras, webcams, etc. , Not limited to this. These and other input devices connect to processing unit 1404 via system bus 1408 via interface port 1430. Interface port 1430 includes, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device 1436 uses some of the same types of ports as input device 1428. Thus, for example, a USB port may be used to provide input to computer 1402 and to output information from computer 1402 to output device 1436. In addition to other output devices, output adapter 1434 is provided to indicate that there are some output devices that require special adapters, such as monitors, speakers, and printers. Output adapter 1434 may include video and sound cards that provide a means of connecting output device 1436 and system bus 1408 for illustration purposes, but not limitation. It should be noted that other devices and / or systems of devices, such as the remote computer 1438, provide both input and output capabilities.

0135Computer 1402 can operate in a network environment that uses logical coupling to one or more remote computers, such as remote computer 1438. The remote computer 1438 can be a personal computer, server, router, network PC, workstation, microprocessor device, peer device, smartphone, tablet, or other network node, and generally has many of the elements described for computer 1402. Including. For brevity, only the memory storage device 1440 is shown with the remote computer 1438. The remote computer 1438 is logically coupled to computer 1402 through network interface 1442 and then connected via communication connection 1444. Network interface 1442 includes wired and / or wireless communication networks such as local area networks (LANs) and wide area networks (WANs) as well as cellular networks. LAN technologies include fiber optic distributed data interface (FDDI), stranded fiber distributed data interface (CDDI), Ethernet, Token Ring and more. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks such as Integrated Services Digital Network (ISDN) and variants thereof, packet-switched networks, and Digital Subscriber Line (ADSL).

0136Communication connection 1444 refers to the hardware / software used to connect network interface 1442 to system bus 1408. Communication connection 1444 is shown inside computer 1402 for clarity, but can also be outside computer 1402. The hardware / software required to connect to the network interface 1442 is, for illustrative purposes only, regular telephone grade modems, modems including cable and DSL modems, ISDN adapters, wired and wireless Ethernet cards, hubs, and Includes internal and external technologies such as routers.

0137The indicated disclosure aspects may be performed in a distributed computational processing environment in which certain tasks are performed by remote processing devices linked through a communication network. In a distributed computing environment, a program module or stored information or instructions can be located in a local or remote storage device.

0138Further, it is understood that the various components described herein can include electrical circuits that can include components and circuit elements of appropriate values in order to implement the embodiments of interest. Should. Moreover, it is understandable that many of the various components can be mounted on one or more IC chips. For example, in one embodiment, a set of components can be mounted on a single IC chip. In other embodiments, each component of one or more is manufactured or mounted on a separate IC chip.

0139As used herein, terms such as "component," "system," and "architecture" are either hardware, a combination of hardware and software, software (eg, at runtime), or firmware, computer or electronics. It is intended to refer to related objects. For example, a component can be one or more transistors, memory cells, transistor or memory cell arrangements, gate arrays, programmable gate arrays, application-specific integrated circuits, controllers, processors, processes running on processors, objects, executable files. , Programs, or applications, computers, etc. that access or interfere with semiconductor memory, or an appropriate combination thereof. The component may include erasable programming (eg, process instructions stored in erasable memory at least partially) or hard programming (eg, process instructions burned into non-erasable memory at the time of manufacture).

0140For illustration purposes, both processes and processors running from memory can be components. As another example, the architecture may include placement of electronic hardware (eg, parallel or serial transistors), process instructions and a processor, which executes the process instructions in a manner suitable for the placement of electronic hardware. In addition, the architecture can be a single component (eg, a transistor, a gate array, etc.) or an arrangement of components (eg, a serial or parallel arrangement of transistors, a gate array connected to a program circuit, power leads, electricity. Can include gates, input signal lines, output signal lines, etc.). A system can include one or more architectures in addition to one or more components. An example of one system could include crossed input / output lines and passgate transistors, as well as a switching block architecture that includes power supplies, signal generators, communication buses, controllers, I / O interfaces, address registers, and so on. It should be understood that some duplication is expected in the definition and that the architecture or system can be a stand-alone component or a component of another architecture, system, etc.

0141In addition to the above, the subject of disclosure is a general manufacturing technique for producing hardware, firmware, software, or an appropriate combination thereof, for controlling an electronic device that implements the subject of disclosure. It can be implemented as a method, device or product using programming or engineering techniques. The terms "device" and "product" as used herein are intended to include a computer program, carrier, or medium accessible from any electronic device, semiconductor device, computer, computer readable device. .. Computer-readable media may include hardware or software media. In addition, the medium may include a non-temporary medium or a transport medium. In one example, the non-temporary medium may include a computer-readable hardware medium. Specific examples of computer-readable hardware media include magnetic storage devices (eg, hard disks, floppy disks, magnetic strips, etc.), optical disks (eg, compact discs (CDs), digital versatile disks (DVDs), etc.), It may include, but is not limited to, smart cards and flash memory devices (eg, cards, sticks, key drives, etc.). Computer-readable transport media may include carriers and the like. Of course, one of ordinary skill in the art will recognize that many changes can be made to this configuration without departing from the scope and spirit of the subject matter of the disclosure.

0142What has been described above includes an example of this innovation. Of course, it is not possible to describe any possible combination of components or techniques to illustrate the Innovation, but one of ordinary skill in the art will be able to make other further combinations and sorts of the Innovation. Can be recognized. Accordingly, the subject matter of disclosure is intended to include all modifications, changes, and changes that fall within the spirit and scope of this specification. In addition, the terms "includes", "including", "has" or "having" and their variants are detailed descriptions or patents of the invention. Within the scope used in any of the claims, those terms "comprising", as the term "comprising" is used as a diversion of the claims. It is intended to be as comprehensive as "containing)".

0143Further, the term "exemplary" is used herein in the sense that it serves as an example, instance, or illustration. Any feature or design described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other features or designs. Rather, the use of the term "exemplary" is intended to present the concept in concrete form. The term "or" as used in this application is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any natural inclusive arrangement. That is, when "X uses A", "X uses B", or "X uses both A and B", in any of these examples, "X uses A or B" is It is filled. In addition, the articles "a" and "an" used in the specification and the appended claims are generally "unless otherwise specified to indicate the singular form or are not clear from the context. It should be interpreted as meaning "one or more".

0144In addition, some parts of the detailed description of the invention are expressed in terms of algorithms or processing operations of data bits in electronic memory. The description or description of these processes is a mechanism used by persons in the art who know to effectively convey the substance of their work to others who are equally skilled. Processing, here, is generally considered to be a coherent sequence of actions leading to the desired result. The act is an act that requires a physical manipulation of a physical quantity. In general, but not necessarily, these quantities take the form of electrical and / or magnetic signals that can be manipulated in storage, transfer, coupling, comparison, and / or other aspects.

0145We have found it convenient to refer to these signals as bits, values, elements, signs, letters, terms, numbers, etc., mainly for normal use. However, it should be remembered that all of these or similar terms are related to appropriate physical quantities and are only convenient indicators attached to those quantities. Unless otherwise stated specifically and is not clear from the above description, explanations using terms such as processing, calculating, duplicating, imitating, determining, or communicating throughout the subject matter of disclosure are electronic. Manipulating or transforming data or signals represented as physical (electrical or electronic) quantities in the circuit, registers or memory of a device to manipulate or transform the memory or register or other such information storage device of a machine or computer system. Describes the operation and processing of processing systems and / or similar consumer or industrial electronic devices or machines, which are other data or signals also represented as physical quantities in transmission and / or display devices. You should understand that.

0146With respect to the various functions performed by the components, architectures, circuits, processes, etc. described above, the terms used to describe those components (including references to "means") are used unless otherwise indicated. It is intended to correspond (eg, functional equivalence) to any component that performs the specified function of the described component, even if it is not structurally equivalent to the structure of the disclosure that performs the function shown in the exemplary features of the form. ing. In addition, specific features may have been disclosed for only one of several embodiments, such features as desired and for any given or specific application. May be combined with one or more other features of other embodiments to the advantage of. It should also be recognized that embodiments include not only the system, but also computer-readable media, including computer-executable instructions for performing various processing operations and / or events.