Semiconductor device

0001One embodiment of the present invention relates to a display device. For example, a liquid crystal display device is exemplified, and other gate signals are used. Technology for display devices that display images by selecting pixels according to the line and source signal line Included as one of the fields. In addition, semiconductor devices such as drive circuits and display devices used in display devices. Electronic devices using the above are also included as one of the technical fields.

0002A game composed of amorphous silicon transistors (also called a-Si TFTs) Development of a driver circuit is underway (for example, Patent Document 1 to Patent Document 2). like this The gate driver is a transistor that controls the timing of outputting a high voltage to the gate line ( It also has a pull-up transistor). Pull-up transistor is source and drain One of the ins is connected to the clock signal line, and the other of the source and drain is the gate signal line. Be connected. Then, the potential of the gate of the pull-up transistor is clocked by capacitive coupling. A driving method is used in which the signal is raised to a value higher than the H level potential of the signal. Achieve this Therefore, it is necessary to float the gate of the pull-up transistor. Therefore, All transistors connected to the gate of the Luup transistor need to be turned off is there.

<p num="0003"><patcit num="1"><text>Japanese Patent Application Laid-Open No. 2007-207413</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2008-009393</text></patcit></p>

<p num="0004">However, in the prior art, all transistors connected to the gate of the pull-up transistor. Even if the Langista is turned off, the pull-up transistor is due to the off current of the transistor. The charge held by the Gista gate was lost over time. Therefore, the gate driver It has been difficult to reduce the drive frequency of semiconductor devices such as circuits. In addition, semiconductor devices operate The range of drive frequencies that can be created was narrowing. As a result, the drive capability of the semiconductor device There was a limit to the improvement of power.</p><p num="0005">In view of the above problems, one aspect of the present invention sets the timing at which a predetermined voltage is output to the subsequent circuit. In a semiconductor device having a transistor (pull-up transistor) to control, a semiconductor One of the issues is to realize better operation of the device. Alternatively, one aspect of the present invention is the latter stage. Transistor (pull-up transition) that controls the timing of outputting a predetermined voltage to the circuit of One of the issues is to improve the driving ability of semiconductor devices with semiconductor devices. And.</p>

<p num="0006">One aspect of the present invention is electrically connected to the first transistor and the gate of the first transistor. It has a second transistor and the first terminal of the first transistor is connected to the first wiring. Air-connected, the second terminal of the first transistor is electrically connected to the second wire, the second The gate of one transistor is electrically connected to the first or second terminal of the second transistor. A semiconductor device is configured by being connected. In the above, the first and second Transistor has an oxide semiconductor at least in the channel region and has a small off-current. You can use a small one. Or, in the above, at least the second transistor Uses an oxide semiconductor that has an oxide semiconductor at least in the channel region and has a small off-current. Can be Specifically, the room temperature converted per 1 μm of channel width (here, 20 ° C). And. ) With an off current of 1 aA / μm or less can be used. Above Therefore, one or a plurality of second transistors may be provided. The second transistor When there are a plurality of transistors, all the transistors are oxide semiconductors at least in the channel region. It is preferable to use the one having the above and having a small off current. In the above, the second arrangement The wire may be electrically connected to the circuit in the subsequent stage. As a result, the first The Langista is a transistor that controls the timing of outputting a predetermined voltage to the circuit in the subsequent stage ( It can function as a pull-up transistor).</p><p num="0007">Another aspect of the present invention is a first transistor, a second transistor, and a third transition. It has a star, and the first terminal of the first transistor is electrically connected to the first wiring, and the first The second terminal of the 1st transistor is electrically connected to the 2nd wire and the 2nd transistor The first terminal of the second transistor is electrically connected to the second wiring, and the second terminal of the second transistor is Electrically connected to the gate of the first transistor, the gate of the second transistor is the first Electrically connected to the wiring of the third transistor, the first terminal of the third transistor is electrically connected to the third wiring. Connected, the second terminal of the third transistor is electrically connected to the gate of the first transistor Being connected, the gate of the third transistor is electrically connected to the third wire It is a more semiconductor device. In the above, the first transistor to the third A transistor having at least a channel region formed of an oxide semiconductor is used. The off current of the first transistor to the third transistor can be 1aA / μm or less. Can be used. Or, in the above, at least the second transistor The third transistor has at least a channel region formed of an oxide semiconductor. Can be used, and at least the off current of the second transistor to the third transistor Can be used for 1aA / μm or less.</p><p num="0008">Another aspect of the present invention is a first transistor, a second transistor, and a third transition. It has a star, and the first terminal of the first transistor is electrically connected to the first wiring, and the first The second terminal of the 1st transistor is electrically connected to the 2nd wire and the 2nd transistor The first terminal of the second transistor is electrically connected to the third wiring, and the second terminal of the second transistor is Electrically connected to the second wire, the first terminal of the third transistor is electrically connected to the fourth wire. The second terminal of the third transistor is electrically connected to the gate of the first transistor. The gate of the third transistor is electrically connected to the fourth wire. A semiconductor device is configured by the above. In the above, the first transistor to the first Transistor 3 uses at least a channel region formed of an oxide semiconductor. The off-current of the first transistor to the third transistor can be 1aA / μm. The following can be used. Or, in the above, at least the third transition As the data, at least a channel region formed of an oxide semiconductor can be used. , At least the off current of the third transistor can be 1aA / μm or less. Wear.</p><p num="0009">Another aspect of the present invention is a first transistor, a second transistor, and a third transition. It has a star and a fourth transistor, and the first terminal of the first transistor is the first wiring. The second terminal of the first transistor is electrically connected to the second wire. The first terminal of the second transistor is electrically connected to the third wire, and the second transistor The second terminal of the Gista is electrically connected to the second wire and is the first end of the third transistor. The child is electrically connected to the third wire, and the second terminal of the third transistor is the first transistor. Electrically connected to the gate of the transistor, the gate of the third transistor is the second transition. It is electrically connected to the gate of the star, and the first terminal of the fourth transistor is the fourth wiring and electricity. Air-connected, the second terminal of the fourth transistor is connected to the gate of the first transistor. It is air-connected and the gate of the 4th transistor is electrically connected to the 4th wire. This constitutes a semiconductor device. In the above, the first transistor The fourth transistor has at least a channel region formed of an oxide semiconductor. It can be used, and the off-current of the first transistor to the fourth transistor is 1aA. Those of / μm or less can be used. Or, in the above, at least the second tiger At least the channel region of the transistor to the fourth transistor is formed by an oxide semiconductor. Can be used, at least the second transistor to the fourth transistor The off current of 1aA / μm or less can be used.</p><p num="0010">Another aspect of the present invention is a first transistor, a second transistor, and a third transition. It has a star and a fourth transistor, and the first terminal of the first transistor is the first wiring. The second terminal of the first transistor is electrically connected to the second wire. The first terminal of the second transistor is electrically connected to the third wire, and the second transistor The second terminal of the Gista is electrically connected to the second wire and is the first end of the third transistor. The child is electrically connected to the 4th wire, and the 2nd terminal of the 3rd transistor is the 1st transistor. Electrically connected to the gate of the transistor, the gate of the third transistor is connected to the fourth wiring and electricity. Air-connected, the first terminal of the fourth transistor is electrically connected to the third wire, The second terminal of the fourth transistor is electrically connected to the gate of the first transistor, The gate of the fourth transistor is a semiconductor because it is electrically connected to the fifth wire. The device is configured. In the above, the first transistor to the fourth transistor As the data, at least a channel region formed of an oxide semiconductor can be used. , The off current of the 1st transistor to the 4th transistor should be 1aA / μm or less. Can be Alternatively, in the above, at least the second transistor to the fourth transistor The Langista should be one in which at least the channel region is formed of an oxide semiconductor. And at least the off current of the 2nd to 4th transistors is 1aA / Those of μm or less can be used.</p><p num="0011">Another aspect of the present invention is a display device having a gate driver circuit, which is a gate driver. The above semiconductor device is used as a circuit.</p><p num="0012">In addition, in this specification etc., when it is explicitly stated that X and Y are connected, X This includes the case where and Y are electrically connected. Where X and Y are objects (eg For example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). X and Y As an example of the case where and is electrically connected, it is possible to electrically connect X and Y. Elements (eg switches, transistors, capacitive elements, inductors, resistor elements, diodes Etc.), but there is a configuration in which one or more are connected between X and Y.</p>

<p num="0013">One aspect of the present invention is a transistor that controls the timing of outputting a high voltage to a subsequent circuit ( In a semiconductor device having a pull-up transistor), a pull-up transistor game The electric charge accumulated in the battery can be retained for a long period of time. As a result, the drive frequency of the semiconductor device The number can be reduced. Also, the range of drive frequencies in which the semiconductor device can operate. Can be widened. As a result, better operation of the semiconductor device can be realized. To. Alternatively, the driving ability of the semiconductor device can be improved.</p>

0014<figref num="1">The figure explaining the structure of the circuit which concerns on Embodiment 1. FIG.</figref><figref num="2">A timing chart for explaining the operation of the circuit according to the first embodiment, and a schematic diagram for explaining the operation of the circuit according to the first embodiment.</figref><figref num="3">The schematic diagram for demonstrating the operation of the circuit which concerns on Embodiment 1. FIG.</figref><figref num="4">The figure explaining the structure of the circuit which concerns on Embodiment 1. FIG.</figref><figref num="5">A timing chart for explaining the operation of the circuit according to the first embodiment.</figref><figref num="6">The figure explaining the structure of the circuit which concerns on Embodiment 1. FIG.</figref><figref num="7">A diagram for explaining the configuration of the circuit according to the first embodiment, and a schematic diagram for explaining the operation of the circuit according to the first embodiment.</figref><figref num="8">The figure explaining the structure of the shift register circuit which concerns on Embodiment 2. FIG.</figref><figref num="9">A timing chart for explaining the operation of the shift register circuit according to the second embodiment.</figref><figref num="10">The figure explaining the structure of the shift register circuit which concerns on Embodiment 2. FIG.</figref><figref num="11">An example of a diagram for explaining a manufacturing process of a transistor according to a third embodiment.</figref><figref num="12">The figure explaining the structure of the display device which concerns on Embodiment 4. FIG.</figref><figref num="13">The figure which illustrates the mode of the apparatus which embodied the technical idea of this invention.</figref><figref num="14">The figure which illustrates the mode of the apparatus which embodied the technical idea of this invention.</figref>

0015Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments are many different It is possible to carry out in such a form, and the form and its range without deviating from the purpose and its scope. It is easily understood by those skilled in the art that various details can be changed. Therefore, the present embodiment It is not limited to the contents described in. In addition, in the configuration described below, the same A part or a part having a similar function is shown by using a common reference numeral between different drawings, and the same part is shown. Alternatively, a detailed description of a portion having a similar function will be omitted. In the drawing to be referenced, the size, Layer thickness, or area, may be exaggerated for clarity. Therefore, it is not always Not limited to the scale of.

0016(Embodiment 1) In the present embodiment, a circuit related to a display device, which is one aspect of the present invention, will be described.

0017FIG. 1 (A) shows a transistor 101, a transistor 102, a transistor 103, and a transistor. A configuration example of a circuit having a gista 104, a transistor 105, and a circuit 200 is shown. Figure 1( The transistors that make up the circuit shown in A) shall be N-channel type. N-channel type tran The gista is turned on when the potential difference between the gate and source is greater than the threshold voltage. It is a transistor.

0018It should be noted that the semiconductor layer of the transistor constituting the circuit shown in FIG. 1 (A) has a sufficient hydrogen concentration. Reduced and purified, carrier concentration low enough, true (type i) or substantially true Oxide semiconductors made of sex (i type) can be used. As a result, the transistor The S value can be improved. The off-current of the transistor can be reduced. The withstand voltage of the transistor can be improved. Fig. Improvement of temperature characteristics of the transistor Can be

0019The oxide semiconductor is used as the semiconductor layer of some transistors, and other transistors are used. As the semiconductor layer of the gista, a semiconductor other than the above oxide semiconductor (for example, silicon (amorphous silicon) , Microcrystalline silicon or polycrystalline silicon, etc.), organic semiconductors, etc.) can be used. However, at least the source or drain is electrically connected to the gate of transistor 101. The oxide semiconductor is used as the semiconductor layer of the transistor.

0020Next, the connection relationship of the circuits shown in FIG. 1 (A) will be described. First of transistor 101 The terminal (one of the source and drain) is connected to the wiring 111, and the first of the transistor 101 The terminal 2 (the other of the source and drain) is connected to the wire 112. Transistor 10 The first terminal of 2 is connected to the wiring 113, and the second terminal of the transistor 102 is the wiring 1 Connected to 12, the gate of transistor 102 is connected to circuit 200. Transistor The first terminal of 103 is connected to the wiring 112, and the second terminal of transistor 103 is It is connected to the gate of the Langista 101, and the gate of the transistor 103 is in contact with the wiring 111. It will be continued. The first terminal of transistor 104 is connected to wiring 114 and transistor 1 The second terminal of 04 is connected to the gate of transistor 101, and the second terminal of transistor 104 is connected to the gate of transistor 104. The wire is connected to the wiring 114. The first terminal of the transistor 105 is in contact with the wiring 113. Subsequently, the second terminal of the transistor 105 is connected to the gate of the transistor 101, The gate of the transistor 105 is connected to the wiring 115. In addition, the transistor 101 Gate, second terminal of transistor 103, second terminal of transistor 104, and transition The connection point with the second terminal of the star 105 is referred to as node 11. Transistor 102 gate The connection point between the circuit 200 and the circuit 200 is shown as node 12.

0021The circuit related to the display device according to one aspect of the present invention is limited to the configuration shown in FIG. 1 (A). Absent. For example, as shown in FIG. 1 (B), the gate of transistor 103 is a transistor. It can be connected to 102 gates. As another example, as shown in Fig. 1 (C). , The first terminal of the transistor 103 is connected to the wiring 113, and the transistor 103 is connected. The gate can be connected to the gate of the transistor 102. As another example, Figure 1 As shown in (D), the second terminal of the transistor 105 shall be connected to the wiring 112. Is possible. As another example, as shown in FIG. 1 (E), the first end of transistor 104. The child can be connected to the wiring 116. As another example, as shown in Fig. 1 (F). In addition, the gate of the transistor 104 can be connected to the wiring 116. In addition, it should be noted. It is possible to combine at least two or more configurations of FIGS. 1B to 1F. Example For example, by combining FIG. 1 (C) and FIG. 1 (E), the first transistor 103 The terminal of is connected to the wiring 113, and the first terminal of the transistor 104 is the wiring 116. It is possible to connect with.

0022The circuit 200 shall be connected to any wiring or any node according to its configuration. Is possible. For example, the circuit 200 has wiring 111, wiring 112, wiring 113, and wiring 11. It is possible to connect with at least one of 4 and node 11.

0023A clock signal is input to the wiring 111. The wiring 112 has the circuit of this embodiment. A force signal is supplied. The voltage V2 is supplied to the wiring 113. Wiring 114 has a star The top pulse is input. A reset signal is input to the wiring 115. Where wiring 11 1. For convenience, the H level potential of the signal input to the wiring 112, wiring 114 and wiring 115 The potential is V1, and the signals input to the wiring 111, wiring 112, wiring 114, and wiring 115 The potential at the L level is assumed to be the potential V2 for convenience.

0024The wiring 111 is used to transfer a clock signal or the like from an external circuit such as a controller to the circuit of the present embodiment. It is a wiring for transmitting a signal, and has a function as a signal line or a clock signal line. Distribution The line 112 transmits the output signal of the circuit of the present embodiment to a circuit such as a pixel circuit or a demultiplexer. It is a wiring for transmission and has a function as a signal line or a gate signal line. Wiring 113 Supply a power supply voltage such as voltage V2 to the circuit of this embodiment from an external circuit such as a power supply circuit. It is a wiring for the purpose, and has a function as a power supply line, a negative power supply line, or a ground line. Wiring 114 From an external circuit such as a timing controller or another circuit to the circuit of this embodiment, It is a wiring for transmitting a signal and has a function as a signal line. Wiring 115 is Reset signal from an external circuit such as an iming controller or another circuit to the circuit of this embodiment. It is a wiring for transmitting the number and has a function as a signal line.

0025The transistor 101 serves as a switch for controlling the conduction state between the wiring 111 and the wiring 112. Has the function of. Further, the transistor 101 is capacitively coupled between the second terminal and the gate. , Has a function of controlling the timing of raising the potential of the node 11. Transistor 10 2 has a function as a switch for controlling the conduction state between the wiring 113 and the wiring 112. To. The transistor 103 is a switch that controls the conduction state between the node 11 and the wiring 112. It has a function as a chi. Transistor 104 is the continuity between wire 114 and node 11. It has a function as a switch for controlling the state. Further, the transistor 104 is an input terminal. Is connected to the wiring 114 and the output terminal functions as a diode connected to the node 11. Have. The transistor 105 controls the conduction state between the wiring 113 and the node 11. It has a function as a switch.

0026Next, with respect to an example of the operation of the circuits shown in FIGS. 1 (A) to 1 (F), the timing shown in FIG. 2 (A) Refer to the chart and the schematic diagrams shown in FIGS. 2 (B) to (E) and FIGS. 3 (A) to 3 (C). explain. Here, the circuit shown in FIG. 1 (A) will be described as an example.

0027FIG. 2 (A) shows the timing of the potentials of the wiring 111, the wiring 114, the wiring 115, and the wiring 112. An example of a jar is shown. It also shows the potentials of node 11 and node 12. Thailand shown in Fig. 2 (A) The mining chart has a period A, a period B, a period C, a period D and a period E. In Fig. 2 (A) In the timing chart shown, the period in which period A, period B, and period C are arranged in order, and the period It has a period in which D and period E are arranged alternately.

0028First, the period A will be described with reference to FIGS. 2 (A), 2 (B), and 2 (C). period At A, the potential of the wiring 111 (denoted as potential V111) becomes V2 (L level potential). .. As a result, the transistor 103 is turned off, so that the wiring 112 and the node 11 are separated from each other. It becomes a non-conducting state. The potential of wiring 114 (denoted as potential V114) is V1 (H level potential) Will be. As a result, the transistor 104 is turned on, so that the wiring 114 and the node 1 are turned on. 1 is in a conductive state. The potential of the wiring 115 (denoted as the potential V115) is V2. to this Since the transistor 105 is turned off, the wiring 113 and the node 11 are non-conducting. Become a voice. Therefore, the potential of the wiring 114 is supplied to the node 11, so that the node 1 The potential of 1 (denoted as potential V11) begins to rise. Eventually, the potential of node 11 is V2 + V It exceeds th101 (Vth101 is the threshold voltage of transistor 101). As a result Since the Langista 101 is turned on, the wiring 112 is in a conductive state with the wiring 111. The potential of node 12 (denoted as potential V12) is V2 or at least V2, depending on circuit 200. It becomes less than + Vth102 (Vth102 is the threshold voltage of the transistor 102). By this Since the transistor 102 is turned off, the wiring 113 and the wiring 112 are in a non-conducting state. become. Therefore, since the potential of the wiring 111 is supplied to the wiring 112, the wiring 112 (Indicated as potential V112) becomes V2 (see Fig. 2 (B)).

0029After that, the potential of node 11 rises further. Eventually, the potential of node 11 is V1-V. It rises to th104 (Vth104 is the threshold voltage of the transistor 104). Then, Since the Langista 104 is turned off, the wiring 114 and the node 11 are in a non-conducting state. .. Therefore, since node 11 is in a floating state, the potential of node 11 is V1-Vth1. It is maintained at 04 (see Fig. 2 (C)).

0030Period B will be described with reference to FIGS. 2 (A) and 2 (D). In period B, node 12 The potential of remains less than V2 or V2 + Vth102 by circuit 200. By this Therefore, the transistor 102 remains in the off state, so that the wiring 113 and the wiring 112 are not connected. It remains in a normal state. The potential of the wiring 111 becomes V1. Then, the transistor 101 is The potential of the wiring 112 rises because it remains in the state. At the same time, transistor 103 is on Since it is in a state, the wiring 112 and the node 11 are in a conductive state. However, the power of wiring 112 The rank rose to V1-Vth103 (Vth103 is the threshold voltage of transistor 103) By the way, the transistor 103 is turned off. Therefore, wiring 112 and node 11 Becomes non-conducting. The potential of wiring 114 is V2. As a result, the transistor 104 Remains off, so wiring 114 and node 11 remain non-conducting. Distribution The potential of line 115 remains V2. This leaves the transistor 105 in the off state. Therefore, the wiring 113 and the node 11 remain in a non-conducting state. Therefore, the node 11 goes into a floating state. At this time, the potential of the wiring 112 continues to rise. Therefore, The potential of the disk 11 is due to the parasitic capacitance between the gate of the transistor 101 and the second terminal. It can rise to V1 + Vth101 + Va (Va is a positive number). So-called boot It is a strap operation. In this way, the potential of the wiring 112 rises to a value equal to the potential V1. (See Figure 2 (D)).

0031Period C will be described with reference to FIGS. 2 (A), 2 (E), and 3 (A). In period C , The potential of the wiring 111 is V2. This leaves transistor 103 in the off state. Therefore, the wiring 112 and the node 11 remain in a non-conducting state. The potential of wiring 114 is V It remains 2. This leaves the transistor 104 in the off state, so wiring 1 14 and node 11 remain non-conducting. The potential of the wiring 115 becomes V1. to this Since the transistor 105 is turned on, the wiring 113 and the node 11 are in a conductive state. become. Therefore, the potential of the wiring 113 is supplied to the node 11. Wiring 113 electricity Since the position is V2, the potential of node 11 is V2. As a result, the transistor 101 is Since the wiring 111 and the wiring 112 are in a non-conducting state, the wiring 111 and the wiring 112 are in a non-conducting state. The potential of node 12 is , Circuit 200 remains less than V2 + Vth102. This makes the transistor 102 remains off, so wire 113 and wire 112 remain non-conducting. (See Figure 2 (E)). However, the timing when the potential of the wiring 111 becomes V2 is a transition. It is often earlier than the timing when the star 101 turns off. Therefore, the transistor Since the potential of the wiring 111 is supplied to the wiring 112 before the 101 is turned off, the wiring 1 The potential of 12 becomes V2 (see Fig. 3 (A)).

0032The period D will be described with reference to FIGS. 2 (A) and 3 (B). In period D, wiring 111 The potential of is V1. As a result, the transistor 103 is turned on, so that the wiring 11 2 and node 11 are in a conductive state. The potential of wiring 114 remains V2. This will , Transistor 104 remains off, so wiring 114 and node 11 are non-conducting Stay in the state. The potential of the wiring 115 becomes V2. This results in wiring 113 and node 1 1 is a non-conducting state. The potential of node 12 is V2 + Vth102 by circuit 200. It becomes a value that exceeds. As a result, the transistor 102 is turned on, so that the wiring 113 and It becomes conductive with the wiring 112. Therefore, the potential of the wiring 113 is supplied to the node 11. Therefore, the potential of node 11 becomes V2. As a result, the transistor 101 is in the off state. Therefore, the wiring 111 and the wiring 112 are in a non-conducting state. Wiring 112 has wiring 11 Since the potential of 3 is supplied, the potential of the wiring 112 becomes V2 (see FIG. 3 (B)).

0033The period E will be described with reference to FIGS. 2 (A) and 3 (C). In period E, wiring 111 The potential of is V2. As a result, the transistor 103 is turned off, so that the wiring 11 2 and node 11 are in a non-conducting state. The potential of wiring 114 remains V2. By this Therefore, the transistor 104 remains in the off state, so that the wiring 114 and the node 11 are not connected. It remains in a normal state. The potential of wiring 115 remains V2. As a result, with wiring 113 It becomes non-conducting with node 11. The potential of node 12 is V2 or V2 depending on the circuit 200. It becomes less than + Vth102. As a result, the transistor 102 is turned off, so that it is distributed. The wire 113 and the wiring 112 are in a non-conducting state. Therefore, node 11 is in a floating state. So the potential of node 11 remains V2. As a result, the transistor 101 is turned off. Since it remains in the state, the wiring 111 and the wiring 112 remain in a non-conducting state. Wiring 112 Will be in a floating state, so the potential of wiring 112 will remain at V2 (see Figure 3 (C)).

0034In the semiconductor device shown in FIG. 1 (C), the potential of the node 12 is V2 + in the period D. It is preferable that the value exceeds Vth102 and exceeds V2 + Vth103. to this Since the transistor 103 is turned on, the wiring 113 and the node 11 are in a conductive state. become. Therefore, the potential of the wiring 113 is supplied to the node 11. Thus, wiring 113 Since the potential of is supplied to the node 11 via one transistor, the potential of the node 11 Can be stabilized.

0035In the circuit shown in FIG. 1 (D), the transistor 105 is turned on during the period C. Then, the wiring 113 and the wiring 112 become conductive. Therefore, the potential of the wiring 113 is distributed. It is supplied to line 112. This shortens the potential fall time of the wiring 112. Can be done.

0036In the circuit shown in Fig. 1 (E), the potential of the wiring 116 is V1 during the period A. I. In period B to period E, the potential of wiring 116 can be V1 and V2. It is possible that Therefore, the voltage V1 can be supplied to the wiring 116. is there. Alternatively, the wiring 116 is out of phase with the clock signal input to the wiring 111. The clock signal or the inverted signal of the clock signal input to the wiring 111 is input. It is possible. In the semiconductor device shown in FIG. 1 (F), the potential of the wiring 116 is set to the period A. It is good to become V1 and then V2 in period B. In period C to period E, wiring 11 The potential of 6 can be V1 and can be V2. Therefore, distribution The line 116 is a clock signal that is out of phase with the clock signal input to the wiring 111. Or the inverted signal of the clock signal input to the wiring 111 can be input. ..

0037As described above, the above circuit uses the bootstrap operation to connect the wiring 112. The potential can be equal to the potential of the wiring 111.

0038In the conventional technique, the S value of the transistor is high. Therefore, wiring 114 The time from when the potential of the transistor becomes V1 until the transistor 104 is turned off becomes longer. Was there. Or, it is difficult to increase the drive frequency because the period A needs to be lengthened. there were. Alternatively, the rise time of the potential of the wiring 112 was long (the rise of the output signal). The rise time was long). Or, the load that can be connected to the wiring 112 is small. It was. Alternatively, the channel width of the transistor 101 was increased. Or layout The area was getting bigger.

0039On the other hand, in the present embodiment, the S value of the transistor is low. Therefore, the driving ability is improved. Can be planned. For example, due to the low S value of the transistor 104, the wiring 114 To shorten the time from when the potential of the transistor becomes V1 until the transistor 104 turns on. Can be done. Therefore, the time of period A can be shortened. As a result, the drive frequency Can be improved. As another example, due to the low S value of transistor 101 , The rise time of the potential of the wiring 112 can be shortened. Or, it is large for wiring 112 Even if a key load is connected, the load can be driven. Or the transistor 101 Since the channel width can be reduced, the layout area can be reduced.

0040In the conventional technique, the off-current of the transistor is large. Therefore, time The amount of charge lost from node 11 was large with the passage of time. Or the potential of node 11 It was declining. Or, the potential of node 11 is equal to or greater than the value at which transistor 101 is turned on. The time that can be maintained was shortened. Or it was difficult to lower the drive frequency .. Alternatively, the range of drive frequencies that can be operated has been narrowed.

0041On the other hand, in the present embodiment, the off current of the transistor is small. Therefore, the driving ability Can be improved. For example, transistor 103, transistor 104 and tiger Due to the small off-current of the engineer 105, the amount of charge lost from the node 11 is small. Can be squeezed. Therefore, it is possible to suppress a decrease in the potential of the node 11. Tsuma Therefore, the time during which the potential of the node 11 can be maintained above the value at which the transistor 101 is turned on is maintained. , Can be lengthened. As a result, the drive frequency can be lowered, so that it operates. The range of drive frequencies that can be used can be widened.

0042Other elements such as transistors can be provided in the circuits shown in FIGS. 1 (A) to 1 (F). To. An example thereof will be described.

0043FIG. 4A is an example in which the transistor 121 is provided in the circuit shown in FIG. 1A. Similarly Transistors 121 can be provided in the circuits shown in FIGS. 1B to 1F. To The first terminal of the Langista 121 is connected to the wiring 113 and is the second terminal of the transistor 121. The terminal is connected to the wire 112 and the gate of the transistor 121 is connected to the wire 116. .. It is preferable that a clock signal is input to the wiring 116. As a result, in period E Then, when the transistor 121 is turned on, the potential of the wiring 113 is changed to the wiring 112. Can be supplied to. Therefore, the noise of the wiring 112 can be reduced.

0044FIG. 4B is an example in which the transistor 122 is provided in the circuit shown in FIG. 1A. Similarly Transistors 122 are provided in the circuits shown in FIGS. 1B to 1F and 4A. It is possible. The first terminal of the transistor 122 is connected to the wiring 113 and is a transition. The second terminal of the star 122 is connected to the wiring 112, and the gate of the transistor 122 is the wiring 1 Connected with 15. As a result, the transistor 122 is turned on in the period C. Thereby, the potential of the wiring 113 can be supplied to the wiring 112. Therefore, wiring 1 The fall time of the potential of 12 can be shortened.

0045FIG. 4C is an example in which the transistor 123 is provided in the circuit shown in FIG. 1A. Similarly In the circuits shown in FIGS. 1B to 1F and 4A to 4B, the transistor 12 It is possible to provide 3. The first terminal of transistor 123 is connected to wire 114 The second terminal of the transistor 123 is connected to the node 11 of the transistor 123. The gate is connected to wiring 116. As a result, the potential of the wiring 114 can be increased even in the period E. It can be supplied to node 11. Therefore, it is possible to reduce the noise of node 11. Wear.

0046FIG. 4 (D) is an example in which the transistor 124 is provided in the circuit shown in FIG. 1 (A). Similarly In the circuits shown in FIGS. 1B to 1F and 4A to 4C, the transistor 12 It is possible to provide 4. The first terminal of transistor 124 is connected to wire 111 The second terminal of the transistor 124 is connected to the wiring 117, and the transistor 124 The gate is connected to node 11. As a result, the potential of the wiring 117 can be changed to the electric potential of the wiring 112. It can be changed at the same timing as the rank. In this case, wiring 112 and wiring 117 One may be connected to the load and the other to another circuit. As a result, the potential due to the load The other circuit can be driven without being subject to fluctuations in the above.

0047In FIG. 4 (E), the transistor 124 and the transistor 125 are installed in the circuit shown in FIG. 1 (A). This is a digit example. Similarly, in the circuits shown in FIGS. 1 (B) to (F) and FIGS. 4 (A) to 4 (C). Therefore, it is possible to provide the transistor 124 and the transistor 125. Transi The first terminal of the star 125 is connected to the wiring 113, and the second terminal of the transistor 125 is arranged. It is connected to line 117 and the gate of transistor 125 is connected to node 12. By this Therefore, the potential of the wiring 117 can be maintained at V2. Or, reduce the noise of wiring 117. Can be reduced.

0048FIG. 4 (F) is an example in which the capacitive element 126 is provided in the circuit shown in FIG. 1 (A). Similarly, Figure 1 In the circuits shown in (B) to (F) and FIGS. 4 (A) to 4 (E), the capacitive element 126 is provided. It is possible. The capacitive element 126 has a gate of the transistor 101 and a second terminal. It is provided in between.

0049The circuits shown in FIGS. 1 (A) to 1 (F) include transistors 121 to 125 and capacitive elements. It is possible to provide two or more elements in the child 126.

0050The circuit of this embodiment includes not only the timing chart shown in FIG. 2 (A) but also various other circuits. Timing chart can be used. An example thereof will be described. For example, no The potential of de 12 is V2 + Vth10 in at least period B in period A to period E. It should be less than 2. Therefore, in period A and period C to E, the potential of node 12 is , Can be less than V2 + Vth102, and more than V2 + Vth102 It is possible that there is. However, in one of period D and period E (especially period D), node 1 The potential of 2 is preferably a value exceeding V2 + Vth102. And period D and period On the other side of E (especially period E), the potential of node 12 should be less than V2 + Vth102. Is preferable. This can shorten the time that the transistor 102 is turned on. Therefore, the shift of the threshold voltage of the transistor 102 can be suppressed. In addition, the figure In the circuit shown in 1 (C), the potential of node 12 exceeds V2 + Vth102 in period A. When the value is reached, the transistor 103 is turned on and the potential of the node 11 is reduced. Let's go. Therefore, in period A, the potential of node 12 is less than V2 + Vth102. Is preferable. As another example, as shown in FIG. 5 (A), the signal input to the wiring 111 is It can be non-equilibrium. As a result, in the period C, the potential of the wiring 111 becomes V2. It is possible to delay the timing when the potential of the wiring 115 becomes V1 than the timing when it becomes. Therefore, the fall time of the potential of the wiring 112 can be shortened. As another example As shown in FIG. 5 (B), the signal input to the wiring 111 shall be a multi-phase clock signal. Is possible. As a result, power consumption can be reduced. Figure 5 (B) shows an example. Then, the timing chart when the 4-phase clock signal is input to the wiring 111 is shown.

0051For example, the W / L (W: channel width, L: channel length) ratio of the transistor 101 is a transistor. Gista 102, transistor 103, transistor 104, transistor 105, transistor Gista 121, transistor 122, transistor 123, transistor 124 and tiger It should be larger than all W / L ratios of the engineer 125. As a result, the wiring 112 starts up. It is possible to shorten the rising time and the falling time. Specifically, transistor 101 The W / L ratio of the transistor 104 is preferably more than twice and less than 20 times the W / L ratio of the transistor 104. Castanopsis. More preferably, it is 3 times or more and less than 15 times. More preferably, 5 times or more, 1 Less than double. As another example, the W / L ratio of transistor 105 is transistor 104. It should be smaller than the W / L ratio of. As a result, in period C, the transistor 101 is Since the timing to enter the state can be delayed, when the potential of the wiring 112 falls. The interval can be shortened. Specifically, the W / L ratio of the transistor 105 is the transistor. It is preferable that the W / L ratio of the data 104 is 0.3 times or more and less than 1 time. More preferably It is preferably 0.4 times or more and 0.9 times or less. More preferably, 0.5 times or more, It is preferably 0.8 times or less. As another example, the W / L ratio of transistor 103 is It should be smaller than the W / L ratio of the transistor 104. As a result, in period B, no It is possible to prevent the potential of the device 11 from decreasing too much. Specifically, transistor 1 The W / L ratio of 03 shall be 0.1 times or more and less than 1 times the W / L ratio of transistor 104. Is preferable. More preferably, it is 0.3 times or more and 0.9 times or less. More preferably It is 0.4 times or more and 0.7 times or less.

0052For example, the W / L ratio of transistor 122 is greater than the W / L ratio of transistor 102. It is good. Thereby, the fall time of the potential of the wiring 112 can be shortened. Specifically The W / L ratio of the transistor 122 is more than twice the W / L ratio of the transistor 102. It is preferably less than 20 times. More preferably, it is 3 times or more and 15 times or less. Furthermore It is preferably 5 times or more and less than 10 times. As another example, W / of transistor 124 The L ratio should be smaller than the W / L ratio of the transistor 101. Because it is in contact with wiring 117 This is because the load that follows is often smaller than the load that is connected to the wiring 112. another As an example, the W / L ratio of transistor 125 is smaller than the W / L ratio of transistor 102. Good. This is because the load connected to the wire 117 is greater than the load connected to the wire 112. Is often small.

0053For example, the amplitude voltage of node 12 is node 11, wiring 111, wiring 112, wiring 114, Preferably less than at least one amplitude voltage of wire 115, wire 116 and wire 117 Good. As a result, power consumption can be reduced. Specifically, the vibration of node 12 The width voltage is preferably 0.3 times or more and less than 1 times the amplitude voltage of the wiring 111. Than Preferably, it is 0.5 times or more and less than 1 time. More preferably, 0.6 times or more, 0.9 It is less than double. As another example, the amplitude voltage of node 11 is node 12, wire 111, wire. At least one amplitude electric power of 112, wiring 114, wiring 115, wiring 116 and wiring 117 It is preferable that the pressure is exceeded. As a result, the gate and source of transistor 101 are connected. Since the potential difference between them can be increased, the rising time and standing of the potential of the wiring 112 The falling time can be shortened. Specifically, the amplitude voltage of the node 11 is the wiring 111. It is preferable that the amplitude voltage is more than 1 times and not more than 2 times the amplitude voltage of. More preferably, 1.2 times or more It is 1.8 times or less above. More preferably, it is 1.4 times or more and 1.6 times or less.

0054For example, when the transistor 102 is in the off state, the potential of the wiring 111 becomes H level. It is preferable that the time is longer than the time required.

0055In the technique using amorphous silicon, the mobility of the transistor was low. Furthermore In addition, the transistor 101 drives a large load (for example, a gate signal line), so that the transistor 101 is a transistor. It was necessary to increase the channel width of Gista 101. Therefore, the transistor 101 The channel width was larger than the wiring width of the wiring 111. On the other hand, the circuit of this embodiment The mobility of the transistors that make up is the movement of the transistor using amorphous silicon. Higher than degree. Therefore, the channel width of the transistor 101 can be reduced.

0056Therefore, the channel width of the transistor 101 is the wiring width of at least a part of the wiring 111. Should be smaller than. In particular, the channel width of the transistor 101 is as small as that of the wiring 111. It is preferable that the width is 0.3 times or more and less than 1 times the width of some wirings. More preferably, 0.4 times or more , 0.9 times or less. More preferably, it is 0.5 times or more and 0.8 times or less.

0057Next, a specific example of the circuit 200 will be described. FIG. 7 (A) shows the capacitive element 201 and the transition. A configuration example of the circuit 200 having the star 202 is shown. One electrode of the capacitive element 201 is wired Connected to 111, the other electrode of the capacitive element 201 is connected to node 12. Transi The first terminal of the star 202 is connected to the wiring 113, and the second terminal of the transistor 202 is , Connected to node 12, the gate of transistor 202 is connected to node 11. Na Oh, the gate of transistor 202 can be connected to wire 112 or wire 114 Is.

0058Next, an example of the operation of the circuit 200 will be described with reference to FIGS. 7 (B) to 7 (F).

0059In period A and period B, the potential of node 11 is high (eg V2 + Vth202 (Vth)). 202 can have a value) that exceeds the threshold voltage) of the transistor 202. For example The potential of node 11 has a value of V1-Vth104 in period A and V1 + Vt in period B. It has a value of h101 + Va. As a result, the transistor 202 is turned on, so that The wiring 113 and the node 12 are in a conductive state. Therefore, the potential of the wiring 113 is the node 1 Supplied to 2. Since the potential of wiring 113 is V2, the potential of node 12 is V2 (Fig. 7). See (B)).

0060In period C, the potential of wiring 111 becomes V2. At this time, the transistor 202 is in the ON state. Since it remains, the wiring 113 and the node 12 remain in a conductive state. Therefore, wiring Since the potential of 113 remains supplied to node 12, the potential of node 12 remains V2. become. The capacitance element 201 retains the difference between the potential of the wiring 111 and the potential of the node 12 at this time. To have. After that, the potential of node 11 becomes V2. As a result, the transistor 202 is Since the state is changed, the wiring 113 and the node 12 are in a non-conducting state. Therefore, node 1 2 becomes a floating state. However, the potential of node 12 is maintained at V2 by the capacitive element 201. (See Figure 7 (C)).

0061During period D, the potential of node 11 remains at V2. As a result, the transistor 202 becomes Since it remains in the off state, the wiring 113 and the node 12 remain in the non-conducting state. this Then, the potential of the wiring 111 becomes V1. As a result, the potential of the node 12 becomes the capacitance element 20. It rises due to the capacitive coupling of 1 (see Fig. 7 (D)). In period E, the potential of node 11 is V2 Will remain. This leaves the transistor 202 in the off state, so wiring 11 3 and node 12 remain non-conducting. At this time, the potential of the wiring 111 becomes V2. .. As a result, the potential of the node 12 is reduced by the capacitive coupling of the capacitive element 201 (FIG. 7 (Fig. 7). See E)).

0062As described above, a circuit capable of controlling the potential of the node 12 with a small number of elements is constructed. Can be done.

0063As shown in FIG. 7 (F), in FIG. 7 (A), the first terminal is connected to the wiring 113. A transistor whose second terminal is connected to node 12 and whose gate is connected to wiring 114. It is possible to provide 203. Transistor 203 is turned on during period A Therefore, it turns off in period B to period E. Therefore, in the period A, the electric power of the wiring 113 Since the place is supplied to the node 12, the fall time of the potential of the node 12 in the period A is set. Can be shortened. Also, if the gate of the transistor 203 is connected to the wiring 115, Transistor 203 is turned on in period C, period A, period B, period D and period. Turns off during E. Therefore, in period C, the potential of the wiring 113 is the node 12 Since it is supplied to the capacitor element 201, the voltage required for operation can be reliably held. .. Alternatively, in period C, the time for the capacitive element 201 to hold the voltage is lengthened. Therefore, the capacitance value of the capacitance element 201 can be increased. Capacitive element 201 If the capacitance value is large, the potential of the node 12 in the period D can be increased.

0064In the present embodiment, for example, the off-current of the transistor 202 is small, so that the capacitance element The amount of charge lost from child 201 can be reduced. Therefore, the H side of node 12 It is possible to suppress a decrease in the potential of. Suppressing the rise in potential on the L side of node 12 it can. As a result, the time from the start time of period A to the start time of the next period A is lengthened. can do. That is, the drive frequency can be lowered. Therefore, it works The range of drive frequencies that can be used can be widened.

0065The circuit described in this embodiment includes the following configuration as one aspect of the present invention. Tran A semiconductor device having a Gista 101, a transistor 103, and a transistor 104 (FIG. 6 (Fig. 6). See A)). It has a transistor 101, a transistor 102 and a transistor 104. Semiconductor device (see Fig. 6 (B)). Transistor 101, transistor 102, transistor A semiconductor device having a data 103 and a transistor 104 (see FIGS. 6C and 6D). To Has Langista 101, Transistor 102, Transistor 104, Transistor 105 Semiconductor device (see Fig. 6 (E)). Transistor 101, transistor 102, transistor A semiconductor device having a Gista 103, a transistor 104, and a transistor 105 (Fig. 6 (F) )reference).

0066(Embodiment 2) In the present embodiment, the shift register circuit related to the display device, which is one aspect of the present invention, is used. explain. The shift register circuit of the present embodiment includes the circuit described in the first embodiment. be able to. Further, the shift register circuit of this embodiment includes a gate driver circuit and /. Alternatively, it can be used as a drive circuit of a display device such as a source driver circuit.

0067FIG. 8 shows a shift register having N circuits 301 (denoted as circuits 301_1 to 301_N). This is a configuration example of a star circuit. As the circuit 301, the circuit of the first embodiment can be used. To. FIG. 8 shows an example in which the circuit shown in FIG. 1 (A) is used as the circuit 301.

0068The connection relationship of the shift register circuit shown in FIG. 8 will be described. Circuit 301_i (i is 2) The connection relationship of any one) of N-1) will be described as an example. Circuit 301_i is wiring 311 _i, wiring 311_i-1, wiring 311_i + 1, one of wiring 312 and wiring 313, and And is connected to wiring 314. Specifically, in the circuit 301_i, the wiring 112 is the wiring 3 Connected to 11_i, wiring 114 is wiring 311_i-1, wiring 115 is wiring 311_i + Connected to 1, wire 111 is connected to one of wire 312 and wire 313, wire 113 Connected to wiring 314. In circuit 301_i, wiring 111 is in contact with wiring 312. If continued, in circuit 301_i + 1 and circuit 301_i-1, wiring 111 is wiring. It should be connected with 313. In circuit 301_1, wiring 114 is connected to wiring 315. However, it is different from the circuit 301_i. Also, in circuit 301_N, wiring 115 is a dummy. Output terminal of circuit (not shown), wiring (not shown) to which reset signal is input, or wiring 3 It differs from circuit 301_i in that it is connected to 15 mag.

0069Next, regarding the operation of the shift register circuit shown in FIG. 8, the timing chart shown in FIG. 9 is shown. It will be explained with reference to.

0070The operation of the circuit 301_i will be described as an example. First, the potential of wiring 311_i-1 (potential V3) (Shown as 11_i-1) becomes V1. Then, the circuit 301_i operates in the period A. Then, the potential of the wiring 311_i (indicated as the potential V311_i) becomes V2. Then wiring 3 The potential of 12 (indicated as potential V312) and the potential of wiring 313 (indicated as potential V313) are inverted. To do. Then, the circuit 301_i operates in the period B, and the potential of the wiring 311_i is changed. Become V1. After that, the potential of the wiring 312 and the potential of the wiring 313 are reversed, and the wiring 311_i The potential of +1 (indicated as potential V311_i + 1) becomes V1. Then, the circuit 301_i The operation is performed in the period C, and the potential of the wiring 311_i becomes V2. Then circuit 301_ i is the operation in the period D and the period E until the potential of the wiring 311_i-1 becomes V1 again. The operation in 311_i is repeated in order, and the potential of the wiring 311_i remains V2. It should be noted that , Circuit 301_1 shows period A when the potential of wiring 315 (denoted as potential V315) reaches V1. It differs from the circuit 301_i in that it operates in.

0071As described above, from the potential of wiring 311_1 (indicated as potential V311_1) to wiring 311_N The potential (denoted as potential V311_N) can be set to V1 in order.

0072The output signal of the shift register circuit is supplied to the wiring 311. The wiring 312 has a black A signal is input. The phase of the wiring 313 is different from that of the clock signal input to the wiring 312. A different clock signal or an inverted signal of the clock signal input to the wiring 312 is input. .. The voltage V2 is supplied to the wiring 314. A start signal is input to the wiring 315. ..

0073Wiring 311 is an output signal of the shift register circuit to a circuit such as a pixel circuit or a demultiplexer. It is a wiring for transmitting the above, and has a function as a signal line or a gate signal line. Wiring 31 2 and wiring 313 are the shift register circuit of the present embodiment from an external circuit such as a controller. It is a wiring for transmitting a signal such as a clock signal, and is used as a signal line or a clock signal line. Has all the functions. Wiring 314 is a shift register of the present embodiment from an external circuit such as a power supply circuit. Wiring for supplying a power supply voltage such as voltage V2 to the star circuit, such as a power supply line, a negative power supply line, or It has a function as a ground wire. Wiring 315 is actually implemented from an external circuit such as a controller. It is a wiring for transmitting the start signal to the shift register circuit of the form of, and is used as a signal line. Has all the functions.

0074The scanning direction is switched by providing a transistor in the shift register circuit shown in FIG. It is possible to have a function to obtain. That is, the electricity from wiring 311_1 to wiring 311_N Drive to change the position to V1 in order, and change the potential from wiring 311_N to wiring 311_1 to V1 in order. It is possible to switch between driving and driving. Figure 10 shows a switch for switching the scanning direction. An example of a shift register circuit provided with is shown. In FIG. 10, circuits 301_i-1 to circuit 3 are shown. 01_i + 1 is illustrated. The shift register circuit shown in FIG. 10 is in addition to the N circuits 301. , N transistors 302 (denoted as transistors 302_1 to 302_N), N Transistors 303 (denoted as transistors 303_1 to 303_N), N transitions Star 304 (denoted as transistors 304_1 to 304_N) and N transistors 3 It has 05 (indicated as transistors 305_1 to 305_N). For example, a transistor The first terminal of 302_i is connected to the wiring 311_i-1 and of the transistor 302_i. The second terminal is connected to the wiring 114 of the circuit 301_i and is the game of the transistor 302_i. Is connected to the wiring 315. The first terminal of transistor 303_i is wiring 311_ Connected to i-1, the second terminal of transistor 303_i is the wiring 11 of circuit 301_i. Connected to 5, the gate of transistor 303_i is connected to wire 316. Transi The first terminal of the star 304_i is connected to the wiring 311_i + 1, and the transistor 304_i The second terminal of i is connected to the wiring 114 of circuit 301_i and of transistor 304_i. The gate is connected to wiring 316. The first terminal of transistor 305_i is wiring 31 Connected to 1_i + 1, the second terminal of transistor 305_i is the wiring of circuit 301_i Connected to 115, the gate of transistor 305_i is connected to wire 315.

0075An example of the operation of the shift register circuit shown in FIG. 10 will be described. Arranged from wiring 311_1 In the case of driving to set the potential up to line 311_N to V1 in order, input the H signal to the wiring 315 and distribute it. It is advisable to input the L signal to line 316. Therefore, the transistor 302_i is turned on. Then, the transistor 303_i is turned off, and the transistor 304_i is turned off. Then, the transistor 305_i is turned on. This outputs from wiring 311_i The signal is sent to the wiring 114 of the circuit 301_i + 1 and the wiring 115 of the circuit 301_i-1. Be supplied. On the other hand, the drive to change the potential from wiring 311_N to wiring 311_1 to V1 in order. In the case of operation, it is advisable to input the L signal to the wiring 315 and the H signal to the wiring 316. Et cetera Therefore, the transistor 302_i is turned off and the transistor 303_i is turned on. Then, the transistor 304_i is turned on and the transistor 305_i is turned off. To. As a result, the signal output from the wiring 311_i is the wiring 11 of the circuit 301_i + 1. It is supplied to 5 and the wiring 114 of the circuit 301_i-1.

0076The amplitude voltage of the signal input to one or both of the wiring 315 and the wiring 316 is N. The amplitude voltage of the signal input to at least one of the wiring 311, the wiring 312, and the wiring 313. It is preferable that it is also large.

0077(Embodiment 3) In this embodiment, an example of transistors constituting the circuit described in the first or second embodiment. Will be described. Specifically, at least the channel region is formed by oxide semiconductors. An example of the structure of the transistor and the manufacturing process will be described.

0078As an oxide semiconductor, an In-Sn-Ga-Zn-O oxide half, which is a quaternary metal oxide. Conductor, In-Ga-Zn-O oxide semiconductor, which is a ternary metal oxide, In-Sn-Zn -O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based acid Compound semiconductors, Al-Ga-Zn-O oxide semiconductors, or Sn-Al-Zn-O acids Compound semiconductors, or In-Zn-O oxide semiconductors, which are binary metal oxides, Sn-Zn- O-based oxide semiconductor, Al-Zn-O-based oxide semiconductor, Zn-Mg-O-based oxide semiconductor, S n-Mg-O oxide semiconductor, In-Mg-O oxide semiconductor, In-O oxide semiconductor , Sn-O-based oxide semiconductors, or Zn-O-based oxide semiconductors and other oxide semiconductors are used. Can be In addition, SiO is added to the oxide semiconductor.₂It may be an oxide semiconductor to which.

0079In addition, oxide semiconductors are InMO.₃(ZnO)_mTable with (m&gt; 0 and m is not a natural number) The listed substances can be used. Here, M is selected from Ga, Al, Mn and Co. Indicates one or more metal elements that have been exposed. For example, as M, Ga, Ga and Al, Ga and There are Mn, or Ga and Co. InMO₃(ZnO)_m(m&gt; 0 and m is natural Of the oxide semiconductors with a structure represented by (not a number), half an oxide with a structure containing Ga as M The conductor is called the above-mentioned In-Ga-Zn-O oxide semiconductor, and its thin film is called In-Ga-Z. It is also called nO-based membrane. In addition, it is expressed as In-Ga-Zn-O referred to in this specification. Oxide semiconductor material is InGaO₃(ZnO)_m(m&gt; 0, and m is not a natural number) Yes, it should be confirmed by ICP-MS analysis or RBS analysis that m is not a natural number. Can be done.

0080A form of a method for manufacturing a transistor whose channel region is formed of an oxide semiconductor is shown in the figure. This will be explained with reference to 11.

008111 (A) to 11 (D) are views showing an example of the cross-sectional structure of the transistor. Figure 11 (A ) To (D), the transistor 410 is a bottom gate structure called a channel etch type. It is one of the structures.

0082In addition, FIGS. 11 (A) to 11 (D) show transistors having a single gate structure, but they are necessary. It can be a transistor having a multi-gate structure having a plurality of channel regions according to the above. To.

0083Hereinafter, using FIGS. 11A to 11D, the transistor 410 is manufactured on the substrate 400. I will explain the process.

0084First, after forming a conductive film on the substrate 400 having an insulating surface, the first photolithography The gate electrode layer 411 is formed by the process.

0085There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, but there are few. In both cases, it is necessary to have heat resistance sufficient to withstand the subsequent heat treatment. For example, By using a glass substrate such as lithium borosilicate glass or aluminoborosilicate glass, Wear. If the temperature of the subsequent heat treatment is high, use a glass substrate with a distortion point of 730 ° C or higher. Good to use.

0086An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 411. The base film is It has a function to prevent the diffusion of impurity elements from the substrate 400, and has a silicon nitride film and silicon oxide. With one or more membranes selected from membranes, silicon nitride films, or silicon oxide films It can be formed by a laminated structure.

0087The material of the gate electrode layer 411 is molybdenum, titanium, chromium, tantalum, and tongue. Metallic materials such as ten, aluminum, copper, neodymium, scandium or these as the main components It can be formed in a single layer or in a laminated manner by using an alloy material.

0088Next, the gate insulating layer 402 is formed on the gate electrode layer 411.

0089The gate insulating layer 402 is made of silicon oxide by using a plasma CVD method, a sputtering method, or the like. Layer, silicon nitride layer, silicon oxide nitride layer, silicon nitride oxide layer, or aluminum oxide The nium layer can be formed as a single layer or laminated. In addition, it is oxidized as a gate insulating layer. High-k materials such as funium (HfOx) and tantalum oxide (TaOx) can also be used. it can. The film thickness of the gate insulating layer 402 is 100 nm or more and 500 nm or less, and in the case of lamination. For example, the first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and the first gate breaking A second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less is laminated on the edge layer.

0090In the present embodiment, the gate insulating layer 402 has a film thickness of 100 nm or more by the plasma CVD method. The lower silicon oxide nitride layer is formed.

0091Further, as the gate insulating layer 402, a high-density plasma device is used to form a silicon oxide film. You may go. Here, the high-density plasma device is 1 x 10¹¹/cm³Plasma density above Refers to a device that can achieve. For example, apply microwave power of 3kW to 6kW. Razuma is generated to form an insulating film. The insulating film obtained by the high-density plasma device Since a film with a constant thickness can be formed, it has excellent step coverage. In addition, high-density plasma equipment The thickness of the thin film of the insulating film obtained by the placement can be precisely controlled.

0092The insulating film obtained by the high-density plasma device is obtained by the conventional parallel plate type PCVD device. The etching rates were compared using the same etchant, which is very different from the insulating film. In some cases, 10% or more or 20% or more of the insulating film obtained by the parallel plate type PCVD equipment. It can be said that the insulating film obtained by the high-density plasma device is a dense film.

0093Oxide semiconductors (highly purified oxides) that are i-shaped or substantially i-shaped in a later process. Since semiconductors) are extremely sensitive to interface states and interfacial charges, the interface with the gate insulating layer is is important. Therefore, the gate insulating layer (GI) in contact with the highly purified oxide semiconductor is high. Quality improvement is required. Therefore, high-density plasma CVD using microwaves (2.45 GHz) is not possible. It is preferable because it can form a high-quality insulating film that is dense and has a high dielectric strength. Highly purified oxide The close contact between the semiconductor and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can be made. It is unfortunate that the film quality as the gate insulating layer is good. In theory, it is important to be able to reduce the interface state density with oxide semiconductors and form a good interface. Is.

0094Next, an oxide semiconductor film 43 having a film thickness of 2 nm or more and 200 nm or less is placed on the gate insulating layer 402. Form 0. The oxide semiconductor film 430 is an In-Ga-Zn-O type or an In-Zn-O type. Which oxide semiconductor film is used. In the present embodiment, the oxide semiconductor film 430 is an In- A Ga-Zn-O oxide semiconductor target is used to form a film by a sputtering method. This stage The cross-sectional view in is corresponding to FIG. 11 (A). The oxide semiconductor film 430 is a rare gas (typical). In an argon atmosphere, in an oxygen atmosphere, or in a noble gas (typically argon) and oxygen It can be formed by a sputtering method in a mixed atmosphere.

0095Here, metal oxide targets containing In, Ga, and Zn (In)₂O₃: Ga₂O₃: ZnO = 1: 1: 1 [mol number ratio]) to set the distance between the substrate and the target to 10 0mm, pressure 0.2Pa, direct current (DC) power supply 0.5kW, argon and oxygen (argon: Oxygen = 30sccm: 20sccm, oxygen flow rate ratio 40%) Film formation in an atmosphere. In addition, it should be noted. By using a pulsed direct current (DC) power supply, powdery substances generated during film formation can be reduced and the film thickness distribution can be improved. It is preferable because it becomes uniform. The film thickness of the In-Ga-Zn-O film is 5 nm or more and 200 nm. It is as follows. In the present embodiment, the oxide semiconductor film is an In-Ga-Zn-O-based metallic acid. An In-Ga-Zn-O film with a film thickness of 20 nm is formed by a sputtering method using a compound target. Membrane. Next, the oxide semiconductor film 430 is subjected to a second photolithography step to form an island-shaped acid. Process into a compound semiconductor layer.

0096Next, the oxide semiconductor layer is dehydrated or dehydrogenated. Dehydration or dehydrogenation The temperature of the heat treatment of 1 is 400 ° C or more and 750 ° C or less, preferably 400 ° C or more and distortion of the substrate. Less than a point. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconducting is carried out. After heat-treating the body layer at 450 ° C for 1 hour under a nitrogen atmosphere, it comes into contact with the atmosphere. Prevents water and hydrogen from being remixed into the oxide semiconductor layer, and obtains the oxide semiconductor layer 431 ( See Figure 11 (B)).

0097The heat treatment device is not limited to an electric furnace, and heat conduction or heat from a heating element such as a resistance heating element is used. A device for heating the object to be processed by radiation may be provided. For example, GRTA (Gas) Rapid Thermal Anneal) device, LRTA (Lamp Rapid) RTA (Rapid Thermal An) for Thermal Anneal equipment, etc. neal) Equipment can be used. LRTA equipment is halogen lamp, metal halo Drump, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats an object to be processed by the radiation of light (electromagnetic waves) emitted from a lamp such as a mercury lamp. Is. The GRTA device is a device that performs heat treatment using high-temperature gas. For gas, a Noble gas such as Lugon, or inactive such as nitrogen that does not react with the object to be treated by heat treatment Sexual gas is used.

0098For example, as the first heat treatment, it is based in an inert gas heated to a high temperature of 650 ° C to 700 ° C. The plate is moved and put in, heated for several minutes, and then the substrate is moved and heated to a high temperature in an inert gas. You may perform GRTA from. With GRTA, high temperature heat treatment can be performed in a short time. Become.

0099In the atmosphere of the first heat treatment, nitrogen, helium, neon, argon, etc. It is preferable that the noble gas and dry air do not contain water, hydrogen, or the like. For example, heat treatment equipment The purity of nitrogen to be introduced into the table or a rare gas such as helium, neon, or argon is 6N (99). .9999%) or higher, preferably 7N (99.99999%) or higher (ie, impurity concentration It is preferably 1 ppm or less, preferably 0.1 ppm or less).

0100Further, the first heat treatment of the oxide semiconductor layer is the oxide before processing into the island-shaped oxide semiconductor layer. It can also be applied to the semiconductor film 430. In that case, after the first heat treatment, heat equipment The substrate is removed from the table and a second photolithography step is performed.

0101When forming an opening in the gate insulating layer 402, the process is performed on the oxide semiconductor film 430. It may be performed before or after the dehydration or dehydrogenation treatment.

0102The etching of the oxide semiconductor film 430 here is not limited to wet etching. Dry etching may be used.

0103Chlorine is contained as the etching gas of the oxide semiconductor film 430 used for dry etching. Gas (eg chlorine (Cl)₂), Boron chloride (BCl)₃) Etc.) are preferable.

0104Phosphoric acid and acetic acid are the etching solutions for the oxide semiconductor film 430 used for wet etching. And nitric acid mixed solution, ammonia overwater (31 wt% hydrogen peroxide solution: 28 wt% ammonia Water: water = 5: 2: 2) etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) May be used.

0105Next, a metal conductive film is formed on the gate insulating layer 402 and the oxide semiconductor layer 431. The metal conductive film may be formed by a sputtering method or a vacuum vapor deposition method. As a material for the metal conductive film, a Luminium (Al), Chromium (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti) , Molybdenum (Mo), Tungsten (W), Neodymium (Nd), Scandium (Sc) Elements selected from, alloys containing the above-mentioned elements as components, or combinations of the above-mentioned elements Money etc. can be mentioned. Further, the above-mentioned elemental nitride film may be used. Also, manganese (Mn) ), Magnesium (Mg), Zirconium (Zr), Beryllium (Be), Yttrium A material selected from any one or more of (Y) may be used. Also, the metal conductive film , A single-layer structure or a laminated structure of two or more layers may be used. For example, aluminum containing silicon Single-layer structure of aluminum film, two-layer structure in which a titanium film is laminated on an aluminum film, aluminum on a titanium film A three-layer structure in which a nium film is laminated and a titanium film is further laminated on an aluminum film is mentioned. Is done.

0106When heat treatment is performed after the metal conductive film, the metal conductive film has heat resistance to withstand this heat treatment. It is preferable to add it.

0107A resist mask is formed on the metal conductive film by the third photolithography step, and selectively After etching to form the source electrode layer 415a and the drain electrode layer 415b, the register Remove the strike mask (see Figure 11 (C)).

0108In the present embodiment, a titanium film is used as the metal conductive film, and the oxide semiconductor layer 431 is made of In. -Using Ga-Zn-O oxide, hydrogen peroxide water (ammonia) as an etchant , Water, hydrogen peroxide solution).

0109In the third photolithography process, only a part of the oxide semiconductor layer 431 is etched. It may be formed into an oxide semiconductor layer having grooves (recesses).

0110In addition, in order to reduce the number of photomasks and the number of steps used in the photolithography process, transmission is performed. Registrar formed by a multi-tone mask, which is an exposure mask in which the emitted light has multiple intensities. The etching step may be performed using a desk. Registrar formed using a multi-tone mask The desk has a shape with multiple film thicknesses, and the shape can be further deformed by performing ashing. It can be used in multiple etching processes to process different patterns. .. Therefore, one multi-tone mask can handle at least two different patterns. A resist mask can be formed. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can be reduced, the process can be simplified.

0111Then nitrous oxide (N₂O), nitrogen (N)₂), Or a gas such as argon (Ar) Perform the plasma treatment that was used. The surface of the oxide semiconductor layer exposed by this plasma treatment Remove the adsorbed water etc. adhering to. In addition, plasma processing using a mixed gas of oxygen and argon You may make sense.

0112After plasma treatment, it comes into contact with a part of the oxide semiconductor layer 431 without touching the atmosphere. An oxide insulating layer 416 serving as a protective insulating film is formed.

0113The oxide insulating layer 416 has a film thickness of at least 1 nm or more, and is oxide-insulated by a sputtering method or the like. The layer 416 can be formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed. When hydrogen is contained in the oxide insulating layer 416, the hydrogen invades the oxide semiconductor layer and is oxidized. The back channel of the semiconductor layer 431 is reduced in resistance (N-type), and the parasitic channel is formed. Made. Therefore, the oxide insulating layer 416 is formed so as to be a film containing as little hydrogen as possible. It is important not to use hydrogen in the membrane method.

0114In the present embodiment, a silicon oxide film having a film thickness of 200 nm is spattered as the oxide insulating layer 416. A film is formed using the T-method. The substrate temperature at the time of film formation may be room temperature or higher and 300 ° C or lower. In the form of application, the temperature is 100 ° C. The film formation of the silicon oxide film by the sputtering method is a rare gas (typically). Is in an argon atmosphere, in an oxygen atmosphere, or in a noble gas (typically argon) and oxygen atmosphere It can be done in an atmosphere. Also, as a target, a silicon oxide target or Can use a silicon target. For example, using a silicon target, acid A silicon oxide film can be formed by a sputtering method in a raw and nitrogen atmosphere.

0115The second heating is then performed under an inert gas atmosphere, a dry air atmosphere, or an oxygen gas atmosphere. Perform processing (preferably 200 ° C or more and 400 ° C or less, for example, 250 ° C or more and 350 ° C or less) .. For example, a second heat treatment is performed at 250 ° C. for 1 hour in a nitrogen atmosphere. Second heat treatment When this is done, a part of the oxide semiconductor layer (channel region) is added in contact with the oxide insulating layer 416. Be heated. As a result, oxygen is supplied to a part (channel region) of the oxide semiconductor layer.

0116By going through the above steps, the oxide semiconductor layer can be dehydrated or dehydrogenated. After heat treatment, a part (channel region) of the oxide semiconductor layer is selectively in a state of excess oxygen. And. The transistor 410 is formed by the above steps.

0117Furthermore, heat treatment is performed in the atmosphere at 100 ° C or more and 200 ° C or less, for 1 hour or more and 30 hours or less. You may. In this embodiment, heat treatment is performed at 150 ° C. for 10 hours. This heat treatment is constant It may be heated while maintaining the heating temperature, or from room temperature to a heating temperature of 100 ° C or higher and 200 ° C. The temperature rise and the temperature decrease from the heating temperature to room temperature may be repeated a plurality of times.

0118A protective insulating layer may be further formed on the oxide insulating layer 416. For example, the RF sputtering method It is used to form a silicon nitride film. Since the RF sputtering method has good mass productivity, a protective insulating layer is formed. Preferred as a method. The protective insulating layer contains moisture, hydrogen ions, and OH.^-Contains impurities such as Instead, a silicon nitride film and nitriding are used using an inorganic insulating film that blocks these from entering from the outside. An aluminum film, a silicon nitride film, aluminum nitride, etc. are used. In this embodiment Formes a protective insulating layer 403 as a protective insulating layer using a silicon nitride film (FIG. 11 (D)). reference).

0119In the present embodiment, the oxide semiconductor layer of the transistor 410 contains hydrogen, which is an n-type impurity. Removed from oxide semiconductors and high so that impurities other than the main components of oxide semiconductors are not included as much as possible. It is made into a true type (i type) by purifying it, or it is made into a substantially genuine type. That's right By removing impurities such as hydrogen and water as much as possible, instead of adding impurities to form i-type. It is characterized by being highly purified i-type (intrinsic semiconductor) or close to it. so By doing so, the Fermi level (Ef) is brought to the same level as the true Fermi level (Ei). can do.

0120The band gap (Eg) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is 4. It is said to be 3eV. Titanium (Ti) constituting the source electrode layer and drain electrode layer The work function of) is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, metal-oxidation A Schottky type barrier is not formed for electrons at the object semiconductor interface.

0121For example, the channel width W of the transistor is 1 × 10.⁴An element with μm and a channel length of 3 μm Even at room temperature, the off current is 10^-13A or less and S value is 0.1V / deca It can be de (gate insulating layer film thickness 100 nm).

0122In this way, purification should be performed so that impurities other than the main components of the oxide semiconductor are not contained as much as possible. Therefore, the operation of the transistor 410 can be improved.

0123In order to suppress fluctuations in electrical characteristics, the above-mentioned oxide semiconductors have hydrogen, moisture, and other factors that cause fluctuations. Impurities such as hydroxyl groups or hydrides (also called hydrides) are intentionally eliminated and impurities Oxygen, which is the main component material of oxide semiconductors, is reduced at the same time by the elimination process. It is an oxide semiconductor that has been made highly purified and electrically type I (intrinsic).

0124Therefore, the smaller the amount of hydrogen in the oxide semiconductor, the better. In addition, highly purified oxides There are very few carriers in the semiconductor (close to zero), and the carrier density is 1 × 10.¹²/ c m³Less than, preferably 1x10¹¹/cm³Is less than. That is, the carry of the oxide semiconductor layer A density is as close to zero as possible. Since there are very few carriers in the oxide semiconductor layer, The reverse characteristic of the transistor can reduce the off-current. Off current is small The smaller the number, the better. The transistor has a current value of 1 per 1 μm of channel width (w). 00aA / μm or less, preferably 10zA (zeptampere) or less, more preferably 1z A or less. Furthermore, since there is no pn junction and there is no hot carrier deterioration, these are tigers. The electrical characteristics of the engineer are not affected.

0125High purity was achieved by thoroughly removing hydrogen contained in the oxide semiconductor layer in this way. Transistors that use oxide semiconductors in the channel region should have extremely low off-current. Can be done. That is, the oxide semiconductor layer is regarded as an insulator in the non-conducting state of the transistor. You can design the circuit. On the other hand, the oxide semiconductor layer is in the conductive state of the transistor. In, expect a higher current supply capacity than the semiconductor layer formed of amorphous silicon. Can be done.

0126In addition, thin film transistors equipped with low-temperature polysilicon are manufactured using oxide semiconductors. It is estimated that the off-current is about 10,000 times larger than that of the transistor. I'm counting. Therefore, low-temperature polysilicon is used in transistors with oxide semiconductors. When the holding capacity is the same (about 0.1pF) as compared to the thin film transistor provided with The pressure retention period can be extended by about 10,000 times. As an example, every video display When performing at 60 frames per second, the retention period for one signal write is increased by 10000 times to 160. It can be about seconds. And even if the number of times the image signal is written is small, the display unit is static. A still image can be displayed.

0127(Embodiment 4) In the present embodiment, an example of the display device according to one aspect of the present invention will be described.

0128FIG. 12A shows an example of a display device in which the shift register circuit of the second embodiment is used. The display devices shown in Fig. 12 (A) are the timing controller 5360 and the source driver times. Has road 5362, gate driver circuit 5363_1 and gate driver circuit 5363_2 It has a drive circuit 5361 and a pixel unit 5364. Pixel part 5364 has a source dora Multiple source signal lines 5371 are extended from the Eva circuit 5362 and arranged, and the gate driver Multiple gate signal lines 5372 from circuit 5363_1 and gate driver circuit 5363_2 Is stretched and arranged. Multiple source signal lines 5371 and multiple gate signal lines 5372 Pixels 5367 are arranged in a matrix in each of the intersections with and.

0129The display device may include a lighting device and a control circuit thereof. In this case, the pixel The 5367 may have a liquid crystal element.

0130One of the gate driver circuit 5363_1 and the gate driver circuit 5363_2 is omitted. Can be abbreviated.

0131The timing controller 5360 supplies a control signal to the drive circuit 5361. , A circuit having a function of controlling the operation of the drive circuit 5361. For example, timing control The troller 5360 has a source driver circuit 5362, a start signal SSP, and a clock signal. Control signals for SCK, inverted clock signal SCKB, video signal DATA, latch signal LAT, etc. Supply the issue. In addition, the timing controller 5360 has a gate driver circuit 5363. Start signal GSP, clock signal GCK to _1 and gate driver circuit 5363_2 , Clock signal GCKB and other control signals are supplied.

0132The source driver circuit 5362 outputs a video signal to each of a plurality of source signal lines 5371. It is a circuit having a function of performing, and can be called a drive circuit, a signal line drive circuit, or the like. Project The image signal is input to pixel 5367, and the display element constituting pixel 5367 responds to the video signal. The gradation becomes similar.

0133The gate driver circuit 5363_1 and the gate driver circuit 5363_2 have pixels 5 in each row. It is a circuit that has a function to select 367 in order, and is called a drive circuit or a scanning line drive circuit. Can be done. The gate driver circuit 5363 controls the timing of selecting pixel 5367. _1 and gate driver circuit 5363_2 output gate signal to gate signal line 5372 It is done by.

0134In the display device shown in FIG. 12 (A), the gate driver circuit 5363_1 and the game The driver circuit 5363_2 can be formed on the same substrate as the pixel portion 5364. Figure 12 (B) shows the gate driver on the same board (shown as board 5380) as the pixel section 5364. An example of the case where the circuit 5363_1 and the gate driver circuit 5363_2 are formed is shown. Na Oh, the board 5380 and the external circuit are connected via the terminal 5381.

0135In the display device shown in FIG. 12 (A), a part of the source driver circuit 5362 (for example). Switch, multiplexer, shift register circuit, decoder circuit, inverter circuit, switch The buffer circuit and / or the level shifter circuit, etc.) are formed on the same board as the pixel part 5364. Can be FIG. 12 (C) shows the same substrate as the pixel portion 5364 (indicated as substrate 5380). In addition, the gate driver circuit 5363_1 and the gate driver circuit 5363_2 and the source driver A part of the Iba circuit 5362 (denoted as 5362a) is formed and the source driver circuit 5362 Another part of (indicated as 5362b) is an example where it is formed on a different substrate than the substrate 5380. Shown.

0136The shift register described in the second embodiment as a drive circuit of a display device or a part of the drive circuit. A circuit can be used. In particular, the drive circuit of the display device will be described in Embodiment 3. By being composed of a ranger, it is possible to improve the drive capacity of the drive circuit. .. Therefore, the display device can be made large. Or, improve the resolution of the display device. Can be Alternatively, the layout area of the drive circuit can be reduced, so the table The frame of the indicator can be made smaller.

0137(Embodiment 5) In this embodiment, an example of an electronic device will be described.

013813 (A) to 13 (H) and 14 (A) to 14 (D) are diagrams showing electronic devices. is there. These electronic devices include housing 5000, display 5001, speaker 5003, and LED. Lamp 5004, operation key 5005 (including power switch or operation switch), connection end Child 5006, sensor 5007 (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, Light, liquid, magnetism, temperature, chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, Has the ability to measure flow rate, humidity, gradient, vibration, odor or infrared rays), microphone Can have 5008, etc.

0139Figure 13 (A) shows a mobile computer, in addition to the ones mentioned above, Switch 5009, It can have infrared port 5010, etc. Figure 13 (B) shows a mobile phone equipped with a recording medium. A type of image player (for example, a DVD player), in addition to the ones mentioned above, a second display It can have a unit 5002, a recording medium reading unit 5011, and the like. Figure 13 (C) is a gog It is a type display, and in addition to the ones described above, the second display unit 5002, the support unit 5012, You can have earphones 5013, etc. FIG. 13 (D) shows a portable game machine, which is described above. In addition to the above, it may have a recording medium reading unit 5011, etc. Figure 13 (E) shows It is a projector and has a light source 5033, a projection lens 5034, etc. in addition to those described above. Can be FIG. 13 (F) shows a portable gaming machine, and in addition to the above-mentioned one, the second display unit It can have 5002, a recording medium reading unit 5011, and the like. Figure 13 (G) shows the TV receiver It is an image machine, and in addition to the above-mentioned one, it can have a tuner, an image processing unit, and the like. Figure 13 (H) is a portable TV receiver that can send and receive signals in addition to the ones mentioned above. Can have a charger 5017, etc. FIG. 14 (A) is a display, described above. In addition to the above, it is possible to have a support base 5018, etc. Figure 14 (B) shows the camera In addition to the above, external connection port 5019, shutter button 5015, image receiver Can have 5016, etc. Figure 14 (C) is a computer, as described above. Besides, pointing device 5020, external connection port 5019, reader / writer 5 It can have 021, etc. Figure 14 (D) shows a mobile phone, in addition to the ones mentioned above. For antennas and 1Seg (1 segment partial reception service for mobile phones and mobile terminals) You can have a tuner, etc.

0140The electronic devices shown in FIGS. 13 (A) to 13 (H) and 14 (A) to 14 (D) are various. Can have various functions. For example, various information (still images, videos, text images, etc.) Display on the display, touch panel function, calendar, date or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, A function to connect to various computer networks using the wireless communication function, a wireless communication function A function to transmit or receive various data using it, a program recorded on a recording medium, or Can have a function of reading data and displaying it on a display unit, and the like. In addition, multiple In an electronic device having a display unit, one display unit mainly displays image information, and another display unit displays image information. A function that mainly displays character information on one display unit, or consideration of parallax on multiple display units By displaying an image, it is possible to have a function of displaying a three-dimensional image, and the like. further, In an electronic device that has an image receiving unit, a function for shooting a still image, a function for shooting a moving image, and shooting A function to automatically or manually correct the captured image, and the captured image as a recording medium (external or to the camera) It can have a function to save in (built-in), a function to display the captured image on the display unit, etc. .. The electronic devices shown in FIGS. 13 (A) to 13 (H) and 14 (A) to 14 (D). The functions that can be possessed are not limited to these, and can have various functions.

0141FIG. 14 (E) shows an example in which the display device is provided integrally with the building. Figure 14 (E) Is a housing 5022, a display unit 5023, a remote control device 5024 which is an operation unit, and a speaker 50. Including 25 mag. The display device is a wall-mounted type that is integrated with the building and has a large installation space. It can be installed without the need for.

0142FIG. 14 (F) shows another example in which a display device is provided integrally with the building in the building. .. The display panel 5026 is installed integrally with the unit bath 5027, and bathers can use it. The display panel 5026 can be viewed.

0143In addition, in this embodiment, a wall and a unit bath are taken as an example of a building, but the form of this embodiment The state is not limited to this, and display devices can be installed in various buildings.

0144Next, an example in which the display device is provided integrally with the moving body will be described.

0145FIG. 14 (G) is a diagram showing an example in which a display device is provided in an automobile. Display panel 5 The 028 is attached to the car body 5029 and enters from the movement of the car body or from inside and outside the car body. Powered information can be displayed on demand. In addition, it has a navigation function You may be.

0146FIG. 14 (H) is a diagram showing an example in which the display device is provided integrally with the passenger airplane. To. Figure 14 (H) shows the display panel 5031 installed on the ceiling 5030 above the seats of a passenger airplane. It is a figure which showed the shape at the time of use at the time of a digit. The display panel 5031 is the ceiling 503 It is attached integrally via 0 and the hinge part 5032, and it depends on the expansion and contraction of the hinge part 5032. Passengers will be able to view the display panel 5031. The display panel 5031 is operated by passengers It has a function to display information.

0147In the present embodiment, an automobile body and an airplane body are exemplified as the moving body. However, it is not limited to this, and motorcycles, motorcycles (including automobiles, buses, etc.), trains (monore) It can be installed on various things such as railroads, railroads, etc.), ships, etc.

0148It is preferable to mount the shift register circuit of the second embodiment on the electronic device shown in the present embodiment. Good. In particular, as a circuit for driving a display unit of an electronic device, the shift gear of the second embodiment It is preferable to mount a gista circuit. The shift register circuit of the second embodiment is used in an electronic device. By mounting it as a circuit to drive the display unit, the area of the drive circuit can be reduced. Therefore, the display unit can be enlarged. In addition, the resolution of the display unit can be improved. ..

0149101 transistor 102 transistor 103 transistor 104 transistor 105 transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 121 transistor 122 transistor 123 transistor 124 transistor 125 transistors 126 Capacitive element 200 circuits 201 Capacitive element 202 transistor 203 transistor 301 circuit 302 transistor 303 transistor 304 transistor 305 transistor 311 Wiring 312 Wiring 313 wiring 314 wiring 315 wiring 316 wiring 400 board 402 Gate insulating layer 403 Protective insulation layer 410 transistor 411 Gate electrode layer 415a Source electrode layer 415b Drain electrode layer 416 Oxide insulation layer 430 Oxide semiconductor film 431 Oxide semiconductor layer 5000 chassis 5001 Display 5002 2nd display 5003 speaker 5004 LED lamp 5005 Operation key 5006 connection terminal 5007 sensor 5008 microphone 5009 switch 5010 infrared port 5011 Recording medium reading unit 5012 Support 5013 earphones 5015 Shutter button 5016 Image receiver 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing device 5021 Reader / Writer 5022 housing 5023 Display 5024 remote control device 5025 speaker 5026 Display panel 5027 Unit bath 5028 Display panel 5029 Body 5030 Ceiling 5031 Display panel 5032 Hinge 5360 Timing Controller 5361 circuit 5362 circuit 5362a circuit 5362b circuit 5363_1 circuit 5363_2 circuit 5364 Pixel part 5367 pixels 5371 Source signal line 5372 Gate signal line 5380 board 5381 terminal