Semiconductor device and semiconductor device manufacturing method

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

For example, in a semiconductor device having an external terminal on the back surface of the package substrate such as a BGA (Ball Grid Array) type semiconductor device, the heat generated by the semiconductor chip mounted on the package substrate is mainly released from the cap covering the package substrate. To.

In such a semiconductor device, a heat conductive material is filled between the cap and the semiconductor chip, and the heat generated by the semiconductor chip is released from the cap through the heat conductive material.

<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2001-267473</text></patcit></p>

<p num="0005"> The cap covering the semiconductor chip is fixed to the package substrate with an adhesive. Due to the insufficient strength of this adhesive, the cap may come off from the package substrate.</p><p num="0006"> Such cap peeling becomes more remarkable as the size of the package substrate increases.</p>

<p num="0007"> In order to solve the above problem, according to one viewpoint of the present manufacturing apparatus, the substrate in which the bonding pad is arranged around the chip mounting region and the chip mounting region with the first surface facing the substrate The mounted semiconductor chip, a heat radiating plate connected to a second surface of the semiconductor chip opposite to the first surface and covering the semiconductor chip and the bonding pad in a plan view, and the heat radiating plate and the bonding pad Provided is a semiconductor device having a joint portion to be solder-bonded and a mold resin arranged between the substrate and the heat sink and sealing the semiconductor chip. </p>

<p num="0008"> According to the disclosed device, the heat sink is less likely to come off the package substrate.</p>

<figref num="1">FIG. 1 is a cross-sectional view of the semiconductor device of the first embodiment.</figref><figref num="2">FIG. 2 is a plan view of the surface of the substrate.</figref><figref num="3">FIG. 3 is a cross-sectional view of the semiconductor chip.</figref><figref num="4">FIG. 4 is a cross-sectional view of a semiconductor device in which a heat radiating member is fixed by an adhesive.</figref><figref num="5">FIG. 5 is a flowchart of the method for manufacturing the semiconductor device according to the first embodiment.</figref><figref num="6">FIG. 6 is a process cross-sectional view of the method for manufacturing the semiconductor device according to the first embodiment.</figref><figref num="7">FIG. 7 is a process cross-sectional view of the method for manufacturing the semiconductor device according to the first embodiment.</figref><figref num="8">FIG. 8 is a process cross-sectional view of the method for manufacturing the semiconductor device shown in FIG.</figref><figref num="9">FIG. 9 is an example of a cross-sectional view of a semiconductor device that has failed to adjust the weight or the like.</figref><figref num="10">FIG. 10 is a plan view of the substrate included in the modified example of the semiconductor device of the first embodiment.</figref><figref num="11">FIG. 11 is a cross-sectional view of the semiconductor device of the second embodiment.</figref><figref num="12">FIG. 12 is a plan view of the surface of the substrate.</figref><figref num="13">FIG. 13 is a flowchart of a method for manufacturing a semiconductor device according to the second embodiment.</figref><figref num="14">FIG. 14 is a process cross-sectional view of the method for manufacturing the semiconductor device according to the second embodiment.</figref><figref num="15">FIG. 15 is a process cross-sectional view of the method for manufacturing the semiconductor device according to the second embodiment.</figref><figref num="16">FIG. 16 is an example of a plan view of a mold for forming a mold resin.</figref><figref num="17">FIG. 17 is a cross-sectional view taken along the line XVII-XVII of FIG.</figref><figref num="18">FIG. 18 is a process cross-sectional view illustrating a method for forming a mold resin using the molds of FIGS. 16 and 17.</figref><figref num="19">FIG. 19 is a process cross-sectional view illustrating a method of forming a mold resin using the molds of FIGS. 16 and 17.</figref><figref num="20">FIG. 20 is a plan view of the substrate included in the first modification of the semiconductor device of the second embodiment.</figref><figref num="21">FIG. 21 is a cross-sectional view illustrating the modified example 2.</figref><figref num="22">FIG. 22 is a cross-sectional view illustrating the modified examples 3 to 5.</figref>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and their equivalents. Even if the drawings are different, the same reference numerals are given to the corresponding parts, and the description thereof will be omitted.

(Embodiment 1) (1) Structure FIG. 1 is a cross-sectional view of the semiconductor device 2 of the first embodiment.

As shown in FIG. 1, the semiconductor device 2 includes a substrate (package substrate) 4 and a semiconductor chip 6 mounted on the substrate 4.

The semiconductor device 2 further includes a heat radiating plate 8 connected to the back surface of the semiconductor chip 6, and a joint portion 10 for solder-bonding the heat radiating plate 8 and the substrate 4. By this solder joining, the heat sink 8 is fixed to the substrate 4.

Soldering is a type of brazing and soldering. Brazing is a general term for a method of joining without melting a base metal using a brazing filler metal (for example, an alloy) having a melting point lower than that of a member (for example, metal) to be joined. Brazing using "wax" with a melting point of less than 450 ° C is called solder bonding. The "wax" used for solder bonding is called solder.

The semiconductor device 2 further includes a mold resin 12 that seals the semiconductor chip 6.

The semiconductor device 2 further has an underfill resin 14 filled between the semiconductor chip 6 and the substrate 4. The semiconductor device 2 further has a passive element 16 mounted on the substrate 4.

-substrate- FIG. 2 is a plan view of the surface of the substrate 4. FIG. 1 is a cross-sectional view of the semiconductor device 2 along line II of FIG.

As shown in FIG. 2, a bonding pad 20 is formed (arranged) around the chip mounting region 18 of the substrate 4. The joining pad 20 is preferably arranged so as to surround the chip mounting region 18.

Wiring such as signal wiring, power supply wiring, and ground wiring (hereinafter referred to as board wiring) is formed inside the board 4. The substrate 4 is a build-up substrate made of, for example, ceramic and / or resin. FIG. 1 shows a part of the ground wiring 22.

On the back surface of the substrate 4, a plurality of electrode pads 23 connected to the substrate wiring are formed. The electrode pad 23 is an external terminal of the semiconductor device 2. On the surface of the substrate 4, a plurality of electrode pads (not shown, for example, a C4 (Controlled Collapse Chip Connection) pattern) connected to the substrate wiring are formed.

The joining pad 20 shown in FIG. 2 is, for example, as shown in FIG. 1, a ground pad connected to the ground terminal 25 via the ground wire 22. The ground terminal 25 is a terminal connected to the ground wire of the printed circuit board (wiring board) among the plurality of electrode pads 23 formed on the back surface of the board.

The material of the substrate wiring, the electrode pad, and the bonding pad is a metal such as W (tungsten) or Cu (copper). The surface of the electrode pad is plated with, for example, Ni (nickel) or Au (gold).

Each electrode pad 23 on the back surface side of the substrate 4 is connected to the printed circuit board by, for example, solder (for example, a solder bump). The solder may be formed on each electrode pad 23, or may be formed on the electrode pad of the printed circuit board. That is, the semiconductor device 2 may be a BGA (Ball Grid Array) type semiconductor device or an LGA (Land Grid Array) type semiconductor device.

A passive element 16 is arranged between the chip mounting region 18 and the bonding pad 20. The passive element 16 is, for example, a chip capacitor connected between the power supply wiring and the gran wiring of the substrate 4 to reduce the noise generated by the semiconductor chip 6.

-Semiconductor chip- FIG. 3 is a cross-sectional view of the semiconductor chip 6. The semiconductor chip 6 has a semiconductor substrate 24 and an integrated circuit 26 formed on the surface of the semiconductor substrate 24. The integrated circuit (for example, CPU (Central Processing Unit)) 26 has a semiconductor element (not shown) formed on the surface of the semiconductor substrate 24 and a multilayer wiring layer 27 formed on the surface of the semiconductor substrate 24. ing. A plurality of pad-shaped external terminals 28 are provided on the surface of the integrated circuit 26.

As shown in FIG. 1, the semiconductor chip 6 is mounted in the chip mounting area 18 (see FIG. 2) of the substrate 4 with the surface on which the integrated circuit 26 is formed facing the substrate 4. The semiconductor chip 6 is connected to an electrode pad (not shown) in the chip mounting region 18 by, for example, a solder bump 30 (see FIG. 1) connected to its external terminal 28 (see FIG. 3). That is, the semiconductor chip 6 is flip-chip mounted on the substrate 4.

An underfill resin 14 that protects the solder bumps 30 is filled between the semiconductor chip 6 and the substrate 4. The underfill resin 14 is, for example, an insulating resin (for example, an epoxy resin or a silicone resin) filled with a filler (for example, silicon particles).

-Mold resin- As shown in FIG. 1, the mold resin 12 is arranged between the substrate 4 and the heat radiating plate 8 and seals the semiconductor chip 6 and the passive element 16.

The mold resin 12 preferably has an inner wall portion 32 that surrounds the semiconductor chip 6, and an outer wall portion 34 that surrounds the inner wall portion 32 and the joint portion 10, as shown in FIG. The passive element 16 is embedded in, for example, the inner wall portion 32.

The mold resin 12 is, for example, a thermosetting resin (for example, an epoxy resin or a silicone resin) filled with a filler (for example, silicon particles). The mold resin 12 is insulating.

The filler density of the mold resin 12 is preferably higher than the filler density of the underfill resin 14. Due to its high filler density, the mold resin 12 has a coefficient of thermal expansion as low as that of the semiconductor chip 6. Therefore, the semiconductor chip 6 is less susceptible to stress based on the difference in the coefficient of thermal expansion.

On the other hand, the underfill resin 14 before curing has high fluidity due to its low filler density. Therefore, the underfill resin 14 is easily filled between the semiconductor chip 6 and the substrate 4.

-Heat sink- The heat radiating plate 8 (see FIG. 1) covers the semiconductor chip 6 and the bonding pad 20 in a plan view. The heat radiating plate 8 has a through hole 47 (see FIG. 6 (c) described later) above the heat radiating pad 20. The area occupied by the through hole 47 is a part of the joining pad 20 in a plan view, and the remaining part is covered with the heat sink 8.

The heat sink 8 is a good conductor of heat. The heat radiating plate 8 is, for example, a Cu (copper) plate or an Al (aluminum) plate. Alternatively, the heat radiating plate 8 is an Al-SiC composite plate in which an Al layer is formed on one surface of a SiC (silicon carbide) plate. The heat radiating plate 8 is preferably flat.

The heat radiating plate 8 is connected to the semiconductor chip 6 by, for example, the heat conductive portion 36. The material of the heat conductive portion 36 is, for example, solder.

-Joint part- The joint portion 10 solder-bonds the heat sink 8 and the joint pad 20 (see FIGS. 1 and 2).

The joint portion 10 is preferably conductive and is arranged so as to surround the side of the semiconductor chip 6 as shown in FIG.

The material of the joint portion 10 is, for example, a solder containing a low melting point metal such as SnPb, SnAg, In, InAg, SnSb, and SnBi as a main component.

(2) Semiconductor device in which the heat radiating member is fixed by an adhesive FIG. 4 is a cross-sectional view of the semiconductor device 38 in which the heat radiating member is fixed by the adhesive.

In the semiconductor device 38 of FIG. 4, the heat generated by the semiconductor chip 6 is released from the lid-shaped heat radiating member 40 (hereinafter, referred to as a cap) that covers the semiconductor chip 6. The cap 40 is made of, for example, ceramic. The semiconductor chip 6 is connected to the cap 40 by a heat conductive portion 36.

The cap 40 is fixed to the substrate 4 by an adhesive 42 arranged on the bottom surface of the side portion thereof. The adhesive 42 is, for example, an adhesive containing an epoxy resin or a silicone resin as a main component. The adhesive strength of such an adhesive 42 is not necessarily high. Therefore, the cap 40 may be peeled off from the substrate 4 due to a change with time.

The bonding area between the cap 40 and the substrate 4 is approximately proportional to the length of the outer circumference of the substrate 4. On the other hand, the area of the substrate 4 is proportional to the square of the outer circumference of the substrate 4. Therefore, the larger the size of the substrate 4, the easier it is for the cap 40 to be peeled off from the substrate 4.

On the other hand, in the semiconductor device 2 (see FIG. 1) of the first embodiment, since the heat radiating plate 8 is firmly fixed to the substrate 4 by solder bonding, it is difficult to peel off from the substrate 4. Solder bonding connects two objects more firmly than adhesive. Therefore, even if the substrate 4 is enlarged (for example, one side is 50 mm or more), the heat sink 8 is not easily peeled off from the substrate 4.

A ground pad is often formed on the surface of the substrate 4 so as to surround the semiconductor chip 6. This ground pad can be used as the joining pad 20. In this case, it is not necessary to provide a pad dedicated to the joint portion 10.

The heat radiating member, that is, the cap 40 in FIG. 4 has a complicated shape. Manufacture of such a cap 40 is not easy. On the other hand, the heat sink 8 (see FIG. 1) of the first embodiment has a flat plate shape. Manufacture of such a heat sink 2 is easy.

The cap 40 in FIG. 4 is made of ceramic. Therefore, the semiconductor chip 6 of FIG. 4 is liable to malfunction due to electromagnetic noise generated by another semiconductor device. On the other hand, the joint portion 10 (see FIG. 1) of the semiconductor device 2 of the first embodiment is conductive and surrounds the side of the semiconductor chip 6. Due to the shielding effect of the joint portion 10, the semiconductor chip 6 of the first embodiment is unlikely to malfunction due to electromagnetic noise. In order to ensure this shielding effect, it is preferable that the heat sink 8 is also conductive.

On the substrate 4 of FIG. 4, undulations occur between the semiconductor chip 6 and the cap 40 due to the heat treatment (reflow treatment of the solder bumps 30 and thermosetting treatment of the underfill resin 14) applied in the process of forming the semiconductor device 38. .. Therefore, the underfill resin 14 and the solder bump 30 may be peeled off from the substrate 4 due to aging.

Therefore, the reliability of the semiconductor device 38 is not always high. This tendency becomes more remarkable as the size of the substrate 4 increases.

On the other hand, in the semiconductor device 2 of the first embodiment (see FIG. 1), the surface of the substrate 4 is covered with the underfill resin 14, the mold resin 12, and the joint portion 10 without gaps. Therefore, in the semiconductor device 2 of the first embodiment, the substrate 4 is unlikely to be wavy. Therefore, the reliability of the semiconductor device 2 of the first embodiment is high.

(3) Manufacturing method FIG. 5 is a flowchart of the manufacturing method of the semiconductor device 2 of the first embodiment. 6 and 7 are process cross-sectional views of the manufacturing method of the semiconductor device 2 of the first embodiment.

-Mounting of semiconductor chip 6 (S2)- As shown in FIG. 6A, the surface of the semiconductor chip 6 is directed toward the surface of the substrate 4, and the semiconductor chip 6 is mounted in the chip mounting area 18 (see FIG. 2) as it is.

Specifically, for example, first, the solder bump 30 (see FIG. 1) is connected to the external terminal 28 (see FIG. 3) on the surface of the semiconductor chip 6. After the solder bump 30 is brought into contact with an electrode pad (not shown, for example, a C4 pad) on the surface side of the substrate 4, the semiconductor chip 6 is connected to the electrode pad by a reflow process. Further, a solder paste is applied to another electrode pad on the surface side of the substrate 4, and the passive element 16 is connected to the electrode pad by a reflow process.

Next, for example, a liquid underfill resin is supplied along one side of the semiconductor chip 6, and a liquid underfill resin is filled between the semiconductor chip 6 and the substrate 4 by a capillary phenomenon. Then, this underfill resin is baked at, for example, 170 to 180 ° C. and thermosetting.

-Formation of mold resin (S4)- Next, as shown in FIG. 6B, the semiconductor chip 6 and the bonding pad 20 are surrounded to form a mold resin 12 having an outer wall portion 34 having an upper surface at a position far from the substrate 4 from the back surface of the semiconductor chip 6.

Specifically, for example, the surface of the substrate 4 is covered with a mold having recesses corresponding to the semiconductor chip 6, the inner wall portion 32, and the outer wall portion 34. The inside of this recess is filled with a heated and fluidized resin. After that, the heat treatment is continued to cure the filled resin. Finally, the substrate 4 on which the mold resin 12 is formed is removed from the mold. By this step, the passive element 16 is embedded in the inner wall portion 32.

The heights (distance from the substrate) of the outer wall portion 34 and the inner wall portion 32 are substantially the same. The mold resin 12 is a thermosetting resin such as an epoxy resin or a silicone resin. The heating temperature is, for example, 170 to 180 ° C.

-Weight of heat conductive material (S6)- Next, as shown in FIG. 6C, the heat radiating plate 8 is pressed against the heat conductive material (heat conductive material) 37 arranged between the heat radiating plate 8 covering the semiconductor chip 6 and the mold resin 12 and the semiconductor chip 6. ..

Specifically, for example, a heat radiating plate 8 to which the heat conductive material 37 is temporarily connected to the back surface is arranged on the mold resin 12. At this time, the heat conductive material 37 is brought into contact with the back surface of the semiconductor chip 6.

The thickness of the heat conductive material 37 (for example, about 0.350 mm) is larger than the height difference (for example, about 0.280 mm) between the upper surfaces of the inner wall portion 32 and the outer wall portion 34 and the back surface of the semiconductor chip 6. The height of the inner wall portion 32 and the outer wall portion 34 is, for example, about 0.890 mm.

After that, the substrate 4 and the heat radiating plate 8 are sandwiched between solder clips (not shown), and a clip load is applied to the heat conductive material 37.

The heat conductive material 37 is, for example, a solder sheet that is thermocompression bonded to the heat radiating plate 8 or a solder paste printed on the heat radiating plate 8. It is preferable that the back surface of the semiconductor chip 6 and the back surface of the heat radiating plate 8 (the surface on the substrate 4 side) are covered with a material (for example, Au) that is well wetted with solder.

-Heating / melting of heat conductive material (S8)- The heat conductive material 37 is melted in a state where the heat radiating plate 8 is pressed against the heat conductive material 37. As a result, the heat conductive material 37 spreads inside the inner wall portion 32 of the mold resin 12, and also connects the heat radiating plate 8 and the semiconductor chip 6.

Specifically, for example, the heat conductive material 37 in a clip-weighted state is heated to a temperature equal to or higher than the melting point of the heat conductive material 37 in, for example, a reflow furnace to melt the heat conductive material 37. Then, the molten heat conductive material 37 spreads inside the inner wall portion 32, and connects the heat radiating plate 8 and the semiconductor chip 6. The heat conductive material spread inside the inner wall portion 32 becomes the heat conductive portion 36.

-Soldering of heat sink and joining pad (S10)- As shown in FIGS. 7A and 7B, the heat sink 8 and the bonding pad 20 are solder-bonded.

Specifically, for example, first, as shown in FIG. 7A, paste-like solder 46 is applied from the through hole 47 (see FIG. 6C) formed in the heat sink 8 to the bonding pad 20 and the heat sink 8. Fill between. Instead of the solder paste, a fine solder ball may be filled.

Next, the solder 46 is melted, for example, in a reflow oven. When the molten solder 46 cools and solidifies, it becomes a joint portion 10 for solder-bonding the heat sink 8 and the joint pad 20 as shown in FIG. 7 (b). The joint portion 10 is solder-bonded to the heat sink 8 in a region other than the through hole 47 (not shown) on the back surface of the heat sink 8 above the joint pad 20.

When the semiconductor device 2 is a BGA type semiconductor device, for example, a solder ball (solder bump) is connected to the electrode pad 23 on the back surface side of the substrate 104.

From the above, the semiconductor device 2 is completed.

FIG. 8 is a process cross-sectional view of the manufacturing method of the semiconductor device 38 shown in FIG.

First, as shown in FIG. 8A, the semiconductor chip 6 and the passive element 16 are mounted on the substrate 4 in substantially the same procedure as in step S2 of FIG.

Next, the cap 40 and the substrate 4 are sandwiched between solder clips (not shown), and the heat conductive material 37 temporarily connected to the cap 40 is pressed against the semiconductor chip 6 as shown in FIG. 8 (b). For example, a film-like adhesive 48 is attached to the bottom surface of the side portion of the cap 40.

In this state, the heat conductive material 37 is melted by a reflow furnace, and the cap 40 and the semiconductor chip 6 are solder-connected as shown in FIG. 8 (c). By the heat treatment at this time, the adhesive 48 is cured to connect the cap 40 and the substrate 4.

When the heat conductive material 37 is melted in a pressurized state, the heat conductive material 37 protrudes from between the cap 40 and the semiconductor chip 6 as shown in FIG. 8 (c). The thickness of the heat conductive material 37, the thickness of the adhesive 48, and the size of the clip load are adjusted so that the heat conductive material 37 does not excessively squeeze out.

FIG. 9 is an example of a cross-sectional view of the semiconductor device 38 that has failed to adjust the load or the like. For example, if the heat conductive material 37 is too thick, as shown in FIG. 9, a large amount of the heat conductive material 37 may squeeze out from between the cap 40 and the semiconductor chip 6 and come into contact with the passive element 16. Alternatively, the heat conductive material 37 may scatter from between the cap 40 and the semiconductor chip 6 and come into contact with the passive element 16. In such a case, for example, the power supply line connected to the passive element 16 is short-circuited, and the semiconductor device 38 fails.

On the other hand, in the semiconductor device 2 (see FIG. 1) of the first embodiment, since the passive element 16 is embedded in the mold resin 12, such a failure is unlikely to occur.

Further, in the semiconductor device 2 of the first embodiment, since the distance between the semiconductor chip 6 and the heat radiating plate 8 is determined by the thickness of the mold resin 12, the thickness of the heat conductive material 37 and the size of the clip load can be easily adjusted. ..

(4) Modification example FIG. 10 is a plan view of the substrate 50 included in the modified example of the semiconductor device of the first embodiment.

In the semiconductor device 2 shown in FIG. 1, as shown in FIG. 2, a single bonding pad 20 surrounds the chip mounting region 18. However, in the modified example described with reference to FIG. 10, a plurality of isolated joining pads 52 are arranged around the chip mounting region 18.

Therefore, in the modified example, the mold resin 12 that seals the semiconductor chip 6 is not separated into the inner wall portion and the outer wall portion. Except for this point, the semiconductor device of the modified example has substantially the same structure as the semiconductor device 2 described with reference to FIGS. 1 and 2.

In the above example, the heat sink 8 is in direct contact with the mold resin 12. However, an adhesive layer may be arranged between the mold resin 12 and the heat radiating plate 8 to adhere the mold resin 12 heat radiating plate 8. The adhesive layer reinforces the bond between the heat sink 8 and the substrate 4.

(Embodiment 2) The description of the parts common to the first embodiment will be omitted or simplified.

(1) Structure FIG. 11 is a cross-sectional view of the semiconductor device 102 of the second embodiment. FIG. 12 is a plan view of the surface of the substrate 104. FIG. 11 is a cross-sectional view of the semiconductor device 102 along the line XI-XI of FIG. The substrate 104 is a package substrate.

As shown in FIGS. 11 and 12, the semiconductor device 102 of the second embodiment is similar to the semiconductor device 2 of the first embodiment (see FIG. 1).

However, of the mold resin 112, the inner wall portion 132 (see FIG. 11) sandwiched between the chip mounting area 18 (see FIG. 12) and the connection pad 120 has an upper surface closer to the substrate 104 than the upper surface of the outer wall portion 134. doing.

Further, a joint portion 110 for solder-bonding the heat radiating plate 108 and the connection pad 120 extends between the semiconductor chip 6 and the heat radiating plate 108 to connect the heat radiating plate 108 to the back surface of the semiconductor chip 6.

Further, the mold resin 112 seals the semiconductor chip 6 and the joint portion 110.

Further, for example, an Au layer 72 is formed by plating on the back surface of the heat radiating plate 108. As a result, the adhesion between the joint portion 110 and the heat radiating plate 108 is improved.

Further, on the back surface of the semiconductor chip 6, for example, an Au layer (not shown) is formed by plating. As a result, the adhesion between the joint portion 110 and the semiconductor chip 6 is improved. However, the Au layer 72 of the heat sink 108 and the Au layer of the semiconductor chip 6 may be omitted.

As is clear from FIGS. 1 and 11, the substrate 104 corresponds to the substrate 4 of the first embodiment. The heat sink 108 corresponds to the heat sink 8 of the first embodiment. The joint 110 corresponds to the joint 10 of the first embodiment. The mold resin 112 corresponds to the mold resin 12 of the first embodiment. The joining pad 120 corresponds to the joining pad 20 of the first embodiment. Further, as is clear from FIGS. 2 and 12, the inner wall portion 132 corresponds to the inner wall portion 32 of the first embodiment. The outer wall portion 134 corresponds to the outer wall portion 34 of the first embodiment.

(2) Manufacturing method FIG. 13 is a flowchart of the manufacturing method of the semiconductor device 102 of the second embodiment. 14 and 15 are process cross-sectional views of the method of manufacturing the semiconductor device 102 of the second embodiment.

-Mounting of semiconductor chip (S12)- As shown in FIG. 14A, the surface of the semiconductor chip 6 is directed toward the substrate 104 in substantially the same procedure as step S2 of the first embodiment, and the semiconductor chip 6 is mounted in the chip mounting region 18 as it is.

-Formation of mold resin (S14)- Next, as shown in FIG. 14B, a mold resin 112 having an outer wall portion 134 and an inner wall portion 132 is formed. The outer wall portion 134 surrounds the semiconductor chip 6 and the bonding pad 120, and has an upper surface (one surface) at a position farther from the substrate 104 than the back surface of the semiconductor chip 6. The inner wall portion 132 surrounds the semiconductor chip 6 inside the joining pad 120 and has an upper surface at a position closer to the substrate 104 than the outer wall portion 134.

FIG. 16 is an example of a plan view of the mold 54 for forming the mold resin 112. FIG. 17 is an exploded cross-sectional view taken along the line XVII-XVII of FIG. In FIG. 16, the internal structure of the mold 54 is shown by a broken line.

As shown in FIG. 17, the mold 54 has an upper mold 56 and a lower mold 58.

As shown in FIGS. 16 and 17, the upper die 56 has a first recess 60a (cavity) corresponding to the semiconductor chip 6 and the inner wall portion 132, and a second recess 60b (cavity) corresponding to the outer wall portion 134. ..

The upper mold 56 further has an injection chamber 62 (pot) in which the molded resin tablet is loaded. The upper mold 56 further has a resin injection flow path 64 provided between the injection chamber 62 and the first recess 60a and between the injection chamber 62 and the second recess 60b.

As shown in FIG. 17, the lower mold 56 has a third recess 60c (cavity) corresponding to the substrate 104.

18 and 19 are process cross-sectional views illustrating a method of forming the mold resin 112 using the mold 54.

First, as shown in FIG. 18A, the substrate 104 on which the semiconductor chip 6 and the passive element 16 are mounted is mounted between the upper die 56 and the lower die 58. At this time, the substrate 104 is fitted into the third recess 60c of the lower mold 58. The surface of the substrate 104 is covered with the upper mold 56.

Next, the molded resin tablet (for example, epoxy resin) 66 is loaded into the injection chamber 62.

Next, while heating the mold resin tablet 66 and the mold 54 to, for example, 170 to 180 ° C., as shown in FIG. 18B, pressure is applied to the mold resin 67 liquefied by the mold resin tablet 66 with the piston 68. Then, the liquefied mold resin 67 is injected into the first recess 60a and the second recess 60b through the resin injection flow path 64 (see FIG. 17). After that, heating of the mold 54 is continued until the injected mold resin 67 is thermoset.

After thermosetting the mold resin 67, as shown in FIG. 19, the substrate 104 on which the inner wall portion 132 and the outer wall portion 134 are formed is removed from the mold 54. Then, the substrate 104 on which the mold resin 112 is formed appears.

-Weight of joint material (S16)- Next, as shown in FIG. 15A, the heat radiating plate 108 is pressed against the bonding material 70 arranged between the heat radiating plate 108 covering the semiconductor chip 6 and the mold resin 112 and the semiconductor chip 6.

Specifically, for example, a heat radiating plate 108 to which the joining material 70 is temporarily connected to the back surface is arranged on the mold resin 112.

The thickness of the bonding material 70 (for example, about 0.350 mm) is larger than the height difference (for example, about 0.280 mm) between the upper surface of the outer wall portion 134 of the mold resin 112 and the back surface of the semiconductor chip 6. The height of the inner wall portion 132 is, for example, about 0.610 mm. The height of the outer wall portion 134 is, for example, about 0.890 mm.

After that, the substrate 104 and the heat radiating plate 108 are sandwiched between solder clips (not shown), and a clip load is applied to the joining material 70.

The joining material 70 is, for example, a solder paste printed on the heat radiating plate 108 or a solder sheet thermocompression bonded to the heat radiating plate 108. The solder material is, for example, a solder containing a low melting point metal such as SnPb, SnAg, In, InAg, SnSb, and SnBi as a main component. The melting point of the bonding material 70 is preferably, for example, 140 ° C. or higher and 250 ° C. or lower. Further, preferably, the melting point of the bonding material 70 is 160 ° C. or higher and 230 ° C. or lower.

-Heating and melting of joint material (S18)- Next, as shown in FIG. 15B, the joining material 70 is melted in a state where the heat radiating plate 108 is pressed against the joining material 70. At this time, the heat radiating plate 108 and the joining pad 120 are solder-bonded by the joining material 70 spreading inside the mold resin 112. Further, the heat sink 108 and the semiconductor chip 6 are connected.

Specifically, for example, the clip-weighted bonding material 70 is heated to a temperature equal to or higher than the melting point of the bonding material 70 in a reflow oven, for example, to melt the bonding material 70. Then, the molten bonding material 70 spreads beyond the inner wall portion 132 and inside the outer wall portion 134.

When the molten joint material 70 cools and solidifies, it becomes a joint portion 110 that solders the heat radiating plate 108 and the joint pad 120. The joint 110 connects the heat sink 108 and the semiconductor chip 6.

When the semiconductor device 102 is a BGA type semiconductor device, for example, a solder ball (solder bump) is connected to the electrode pad 23 on the back surface side of the substrate 104.

From the above, the semiconductor device 102 is completed.

According to the second embodiment, the heat sink 108 and the substrate 104 are connected at the same time as the solder bonding of the heat sink 108 and the substrate 104.

(3) Modification example 1 FIG. 20 is a plan view of the substrate 150 included in the first modification of the semiconductor device of the second embodiment.

In the semiconductor device 102 shown in FIG. 11, as shown in FIG. 12, a single bonding pad 120 surrounds the chip mounting region 18. However, in the first modification, as shown in FIG. 20, a plurality of isolated joining pads 152 are arranged around the chip mounting region 18.

The mold resin 112 of the first modification is a continuous body, and is not separated into an inner wall portion and an outer wall portion.

However, the mold resin 112 on the inner region 136 inside the bonding pad 152 (see FIG. 20) has an upper surface closer to the substrate 150 than the upper surface of the mold resin 112 on the outer region 138 outside the inner region 136.

A joint portion 110 for solder-bonding the heat sink 108 and the joint pad 152 extends over the semiconductor chip 6 beyond the portion where the mold resin 112 approaches the substrate 150 (mold resin 112 on the internal region 136).

(4) Modifications 2 to 5 FIG. 21 is a cross-sectional view illustrating the modified example 2. FIG. 21A is a cross-sectional view of the modified example 2 before the joint portion 110 is formed. FIG. 21B is a cross-sectional view of Modification 2.

In the semiconductor device 102 shown in FIG. 11, the mold resin 112 is in direct contact with the joint portion 110. However, in the second modification, as shown in FIG. 21A, the surface of the mold resin 112 is covered with the plating layer 74 (for example, the Au layer). The plating layer 74 is formed by, for example, electroless plating.

As shown in FIG. 21B, since the joint portion 110 is solder-bonded to the plating layer 74, the adhesion between the joint portion 110 and the mold resin 112 is improved.

FIG. 22 is a cross-sectional view illustrating the modified examples 3 to 5.

FIG. 22A is a cross-sectional view of the modified example 3 before the joint portion 110 is formed.

In the third modification, as shown in FIG. 22A, the adhesive 76 is further applied to the plating layer 74 on the outer wall portion 134 in the second modification. According to the third modification, the bonding strength between the heat sink (not shown) and the substrate 104 is further increased. Instead of the adhesive 76, an adhesive film may be adhered to the outer wall portion 134.

FIG. 22B is a cross-sectional view of the modified example 4 before the joint portion 110 is formed.

In the modified example 4, as shown in FIG. 22B, the adhesive 76 is applied directly on the outer wall portion 134. Also in the modified example 4, the bonding strength between the heat sink (not shown) and the substrate 104 is increased. Instead of the adhesive 76, an adhesive film may be adhered to the outer wall portion 134.

FIG. 22 (c) is a cross-sectional view of the modified example 5 before the joint portion 110 is formed.

In the modified example 5, as shown in FIG. 22 (c), the passive element 16 is not mounted on the substrate 104. Since the passive element 16 is not mounted, the distance between the semiconductor chip 6 and the bonding material 110 is narrowed, and the shielding effect of the bonding material 110 is enhanced.

Further, since the side surface of the underfill resin 14 is covered by the inner wall portion 132 of the mold resin, the underfill resin 14 does not deteriorate even if the molten bonding material spreads inside the mold resin.

Although not mentioned in the above examples, the bonding material 70 and the heat conductive material 37 may contain flux.

In the above example, the side surfaces of the semiconductor chip 6 and the underfill resin 14 are in contact with the mold resins 12 and 112. However, the side surfaces of the semiconductor chip 6 and the underfill resin 14 may be in contact with the joints 10, 110. That is, the mold resins 12 and 112 do not have to have the inner wall portions 32 and 132.

In the above example, the joining pad is connected to the ground wiring. However, the junction pad does not have to be connected to the ground wiring.

The following additional notes will be further disclosed with respect to the above embodiments 1 and 2.

(Appendix 1) A board with bonding pads placed around the chip mounting area, With the first surface facing the substrate, the semiconductor chip mounted in the chip mounting area and the semiconductor chip A heat sink connected to a second surface of the semiconductor chip opposite to the first surface and covering the semiconductor chip and the bonding pad in a plan view, A joint portion for soldering the heat sink and the joint pad, A mold resin that is arranged between the substrate and the heat sink and that seals the semiconductor chip is used. Semiconductor device to have.

(Appendix 2) In the semiconductor device described in Appendix 1, The joint portion extends between the second surface of the semiconductor chip and the heat sink to connect the heat sink to the second surface of the semiconductor chip. A featured semiconductor device.

(Appendix 3) In the semiconductor device according to Appendix 1 or 2, The mold resin has an inner wall portion that surrounds the semiconductor chip, and an outer wall portion that surrounds the inner wall portion and the joint portion. A featured semiconductor device.

(Appendix 4) In the semiconductor device described in Appendix 3, The inner wall portion has an upper surface closer to the substrate than the upper surface of the outer wall portion. A featured semiconductor device.

(Appendix 5) In the semiconductor device according to Appendix 3 or 4, further It has a passive element embedded in the inner wall portion. A semiconductor device characterized by this.

(Appendix 6) In the semiconductor device according to any one of Appendix 1 to 5. That the conductive joint is arranged so as to surround the semiconductor chip. A featured semiconductor device.

(Appendix 7) In the semiconductor device according to any one of Supplementary notes 1 to 6, further It has an underfill resin filled between the semiconductor chip and the substrate, and has That the surface of the substrate is covered with the underfill resin, the mold resin, and the joint portion. A featured semiconductor device.

(Appendix 8) In the semiconductor device according to any one of Appendix 1 to 7. The heat sink should be flat. A featured semiconductor device.

(Appendix 9) In the semiconductor device according to any one of Appendix 1 to 8, The bonding pad is electrically connected to the ground terminal of the substrate. A featured semiconductor device.

(Appendix 10) A process of mounting a semiconductor chip with the first surface facing the substrate in a chip mounting area on the surface of the substrate in which a bonding pad is arranged around the surface of the substrate. A step of forming a mold resin including an outer wall portion that surrounds the semiconductor chip and the bonding pad and has an upper surface at a position far from the substrate from the second surface opposite to the first surface of the semiconductor chip. The bonding material is melted in a state where the heat sink is pressed against the bonding material arranged between the semiconductor chip and the heat sink covering the mold resin and the semiconductor chip, and the bonding spreads inside the mold resin. It has a step of solder-joining the heat sink and the joining pad with a material. Manufacturing method of semiconductor devices.

(Appendix 11) In the method for manufacturing a semiconductor device according to Appendix 10, The step of forming the mold resin is On the substrate between the outer wall portion and the semiconductor chip), the position is the same as or far from the second surface of the semiconductor chip, and is closer to the substrate than the upper surface of the outer wall portion. To have a step of forming an inner wall portion having an upper surface A characteristic method for manufacturing a semiconductor device.

(Appendix 12) In the method for manufacturing a semiconductor device according to Appendix 11, Prior to the step of forming the inner wall portion, there is a step of forming a passive element on the substrate. The inner wall portion covers the passive element. Manufacturing method of semiconductor devices.

2 ... Semiconductor device 4 ... Substrate 6 ... Semiconductor chip 8 ... Heat sink 10 ... Joint 12 ... Mold resin 14 ... Underfill resin 18 ... Chip mounting area 20 ... Joining pad 26 ... Integrated circuit 32 ... Inner wall 34 ... Outer wall 36 ... Heat conduction part 50 ... Substrate 52 . . . Joining pad 70 . . . Joining material 102 ... Semiconductor device 104 ... Substrate 108 . . . Heat sink 110 . . . Joint 112 . . . Mold resin 120 . . . Joining pad 132 . . . Inner wall 134 . . . Outer wall 150 . . . Substrate 152 . . . Joining pad