3d ic method and device

Related application

This application relates to U.S. Pat. No. 6,500,794, Application No. 09 / 532,886, Application No. 10 / 011,432, Application No. 10 / 359,608, and U.S. Patent No. 6,867,073, Application No. 10 / 688,910, Application No. 10 / 440,099. All of these contents are incorporated herein by reference.

The present invention relates to the field of three-dimensional integrated circuits, and more particularly to three-dimensional integrated circuit devices using direct wafer bonding and methods for manufacturing the same.

Semiconductor integrated circuits (ICs) are typically formed in and on silicon wafers, so that the IC area should increase as the IC grows. The constant improvement of smaller transistors in the IC, commonly referred to as Moore's Law, has substantially increased the number of transistors in a given IC area. However, in spite of the increase in the density of transistors, it is desired to increase the total IC area in many application examples. The reason is that more transistors are needed and more horizontal connections between transistors to achieve a particular function. Realizing these applications with one large IC die typically results in a decrease in chip yield and thus an increase in IC cost.

Another trend in IC manufacturing is to increase the number of different types of circuits within an IC. This is more commonly referred to as system-on-chip (SoC). Such manufacturing typically requires an increase in the number of mask layers to produce circuits of different types. Increasing the number of mask layers also typically results in lower yields and thus higher IC costs. The solution to avoid this unwanted yield reduction and cost increase is to stack or connect the ICs vertically. These ICs may be of different sizes, may be made from wafers of different sizes, may have different functions (ie, analog, digital, optical), or be different. It may be made from the material to be used (ie, silicon, GaAs, InP). ICs can be inspected before stacking and combined with Known Good Dies (KGDs) to improve yield. Thus, the economic success of vertical stacking and routing techniques depends on the yield and cost of stacking and connectivity, which is more advantageous than the yield and cost associated with increasing IC and SoC areas. Manufacturable methods to achieve this approach include stacking ICs vertically using direct bonding, thinning wafers, photolithography masking, etching vias, and metallizing wiring. A vertical wiring structure is formed using wafer manufacturing technology. Vertical electrical interconnects between stacked ICs can be formed as a result of stacking with direct bonding, or as a result of a series of wafer manufacturing techniques after stacking with direct bonding. It is possible.

The cost of the vertical interconnects of this technique is directly related to the number of photolithography masking layers required to etch vias and form electrical wiring. Therefore, it is desirable to minimize the number of photolithography masking layers required to form vertical wiring.

One form of vertical stacking and vertical interconnection is that the ICs (on the board) are connected face-to-face, that is, with the ICs facing each other. This form can be in the form of wafer-to-wafer, but is typically done in the form of die-to-wafer. In the die-to-wafer format, the die is bonded to the wafer with the IC side facing down and the IC side facing up. This enables the accumulation of known good dies and improves the yield. Vertical interconnects can be formed as a result of stacking, either directly as a result of stacking, or as a result of a series of wafer manufacturing techniques after stacking by direct bonding, as described, for example, in application 10 / 359,608. This series of wafer manufacturing techniques after stacking by direct bonding typically includes: The die is typically thinned substantially by removing most of the die substrate. Die substrates are generally not allowed to be completely removed due to the presence of transistors within the substrate. This is, for example, bulk CMOS This is the case with ICs. Thus, the substrate is typically removed as far as practicable as possible, leaving sufficient substrate residue to avoid damage to the transistors. Next, the wiring to the die IC is formed by etching the vias that penetrate the remaining substrate and reach the position of the wiring in the die IC so that there are no necessary transistors near the vias. Further, in order to achieve the highest wiring density, it is preferable that this via penetrates the entire die IC, reaches the inside of the wafer IC, and continues to the connection position in the wafer IC. This via typically extends through an insulating material that provides the desired electrical insulation from the connection position within the die and wafer ICs and also within the die and wafer ICs. To expose. After the formation of this via, vertical wiring to the exposed desired electrical connection positions within the die IC and wafer IC can be formed by the conductive material. An insulating layer between the conductive material and the exposed substrate on the via sidewall can be used to avoid unwanted electrical conduction between the conductive material and the substrate.

Manufacture of this structure typically requires the formation of four photolithography masking layers. These layers are 1) etching of vias through the substrate, 2) etching of vias penetrating the insulating material in the die IC and wafer IC to expose the desired conductive material in the die IC and wafer IC, 3) die. Electrically insulate the conductive material that connects the connection position in the IC to the connection position in the wafer IC. Exposure that exposes the desired conductive material in the die IC and wafer IC through the continuously deposited insulating layer. Etching of vias on the side wall of the substrate via, 4) connection using a conductive material between the exposed wiring position in the die IC and the exposed wiring position in the wafer IC.

The pattern defining the etching of vias penetrating the insulating material is typically smaller than the pattern defining the etching of vias penetrating the substrate. This is to properly expose the wiring points in the die IC and the wafer IC and to avoid removing the insulating material on the side wall of the substrate via. These patterns are formed after the formation of vias in the substrate, and this patterning is typically performed in a hierarchy below the patterning of the substrate vias. This results in patterning on a non-flat structure. This limits the desired structural scaling to very small to achieve the highest wire density and scrapes the least likely silicon substrate. A functional transistor could have been located on this scraped substrate if it had not been scraped.

Therefore, it is possible to have a device comprising a structure and a method of manufacturing the structure that requires fewer masking steps and a feasible masking step on a flat surface at or one of the positionally highest layers within the structure. desirable.

The present invention is directed to three-dimensional device integration methods and three-dimensionally integrated devices.

In one example of this method, the first element having the first contact structure is integrated with the second element having the second contact structure. In this method, vias exposed to at least the first contact structure are formed in the first element, and at least a conductive material connected to the first contact structure is formed in the vias. It may include the step of adhering the first element to the second element such that one of the one contact structure and the conductive material is directly connected to the second contact structure.

In the second example, in the present method, a via is formed in the first element, a first conductive material is formed in the via, the first conductive material is connected to the first contact structure, and the first is described. One element may include the step of adhering one element to the second element such that one of the first contact structure and the first conductive material is directly connected to the second contact structure.

In the third example, in the present method, a via is formed in the first element having the first substrate, a conductive material is formed in the via, and after the via and the conductive material are formed, the conductive material is formed. To form a contact structure electrically connected to, a second element having at least one second contact structure is formed, and a part of the first substrate is removed to expose the via and the conductive material. As part of the process of adhering the first substrate to the second substrate and adhering the first substrate, between the second contact structure and one of the first contact structure and the conductive material. May include steps to connect.

In an example of the integrated structure according to the present invention, the first element has a first contact structure, the second element has a second contact structure, the first via is formed in the first element, and the first conductivity is formed. The sex material is formed in the first via and is connected to the first contact structure so that the first conductive material and one of the first contact structures are directly connected to the second contact structure. The first element is adhered to the second element.

<figref num="1">It is a figure which shows the die which is bonded face-down to a face-up wafer.</figref><figref num="2A">It is a figure of a die bonded to a substrate.</figref><figref num="2B">It is the figure of the die adhered to the substrate in the form which a part of the substrate of the die was removed.</figref><figref num="2C">It is a figure of the substrate bonded to another substrate.</figref><figref num="3A">It is a figure which shows that the insulating film and the mask layer are formed so as to cover the structure of FIG. 2A.</figref><figref num="3B">It is a figure which shows that the insulating film and the mask layer are formed after the flattening material formation.</figref><figref num="4">It is a figure which shows the opening formed in the insulating film and a mask layer of FIG. 3A and FIG.</figref><figref num="5">It is a figure which shows that the die is etched using the opening formed as shown in FIG.</figref><figref num="6A">It is a figure which shows that the contact structure in a die and a wafer is exposed by further etching.</figref><figref num="6B">FIG. 5 is a diagram of a variant of the process, including the formation of a hard mask.</figref><figref num="7A">It is a figure which shows a part of the structure of FIG. 6A after forming a conformal insulating side wall layer.</figref><figref num="7B">A variant of the embodiment in which the hard mask has been removed.</figref><figref num="8A">It is a figure which shows that the conformal insulating side wall layer is anisotropically etched.</figref><figref num="8B">A variant of the embodiment in which the hard mask has been removed.</figref><figref num="8C">It shows a variant in forming a conformal film in the bonded structure.</figref><figref num="8D">It shows a variant in forming a conformal film in the bonded structure.</figref><figref num="8E">It shows a variant in forming a conformal film in the bonded structure.</figref><figref num="8F">It shows a variant in forming a conformal film in the bonded structure.</figref><figref num="8G">The structure in FIG. 8C after etching the conformal film is shown.</figref><figref num="8H">The structure in FIG. 8D after etching the conformal film is shown.</figref><figref num="8I">The structure in FIG. 8E after etching the conformal film is shown.</figref><figref num="8J">The structure in FIG. 8F after etching the conformal film is shown.</figref><figref num="8K">It shows an alternative way to form a sidewall film within the glued structure.</figref><figref num="9A">It is a figure which shows that the metal contact which comprises a metal seed layer and a metal embedding material is formed.</figref><figref num="9B">A variant of the embodiment in which the hard mask has been removed.</figref><figref num="9C">It is a variant of the embodiment in which a seed layer is not formed.</figref><figref num="10A">It is a figure of the structure of FIG. 9A and FIG. 9B after chemical mechanical polishing.</figref><figref num="10B">It is a figure of the structure of FIG. 9C after chemical mechanical polishing.</figref><figref num="10C">FIG. 5 illustrates an alternative method of filling cavities in a glued structure.</figref><figref num="10D">FIG. 5 illustrates an alternative method of filling cavities in a glued structure.</figref><figref num="10E">FIG. 5 illustrates an alternative method of filling cavities in a glued structure.</figref><figref num="10F">FIG. 5 illustrates an alternative method of filling cavities in a glued structure.</figref><figref num="11">It is a figure which shows the metal coating of the structure of FIG. 10A.</figref><figref num="12">It is a figure of the 2nd Embodiment which uses a mask layer without an intervening insulating layer.</figref><figref num="13">It is a figure which shows that the metal contact is formed in 2nd Embodiment.</figref><figref num="14">It is a figure which shows the structure of FIG. 13 after chemical mechanical polishing.</figref><figref num="15">It is a figure which shows another embodiment of this invention.</figref><figref num="16A">It is a figure which shows the embodiment which a contact structure is located on one surface of an apparatus.</figref><figref num="16B">It is a figure of the structure of FIG. 16A after further processing.</figref><figref num="17">It is a figure which shows the device manufactured by the method according to this invention using the structure shown in FIG. 16A and FIG. 16B.</figref><figref num="18">It is a figure of another embodiment of this invention.</figref><figref num="19A">It is a figure which shows the device manufactured by the method according to this invention using the structure shown in FIG.</figref><figref num="19B">A structure with flattening material and contacts formed on the structure of FIG. 19A is shown.</figref><figref num="19C">A direct glued contact similar to FIG. 19A but without an opening is shown.</figref><figref num="20A">A fifth embodiment with a side wall membrane is shown.</figref><figref num="20B">A fifth embodiment with a side wall membrane is shown.</figref><figref num="20C">A fifth embodiment with a side wall membrane is shown.</figref><figref num="20D">A fifth embodiment with a side wall membrane is shown.</figref><figref num="20E">A fifth embodiment with a side wall membrane is shown.</figref><figref num="20F">A fifth embodiment with a side wall membrane is shown.</figref><figref num="20G">A fifth embodiment with a side wall membrane is shown.</figref><figref num="20H">A fifth embodiment with a side wall membrane is shown.</figref><figref num="21A">It shows a sixth embodiment in which the substrate is substantially completely removed.</figref><figref num="21B">It shows a sixth embodiment in which the substrate is substantially completely removed.</figref><figref num="21C">It shows a sixth embodiment in which the substrate is substantially completely removed.</figref><figref num="21D">It shows a sixth embodiment in which the substrate is substantially completely removed.</figref><figref num="21E">It shows a sixth embodiment in which the substrate is substantially completely removed.</figref><figref num="22A">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22B">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22C">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22D">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22E">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22F">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22G">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22H">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22I">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22J">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22K">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="22L">It shows a seventh embodiment in which vias are formed prior to die carving.</figref><figref num="23A">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23B">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23C">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23D">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23E">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23F">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23G">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23H">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23I">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23J">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23K">It shows the eighth embodiment in which the die is mounted top-down.</figref><figref num="23L">It shows bonding structures with embedded vias in top-down and top-up configurations.</figref><figref num="23M">It shows that the second layer is glued.</figref><figref num="23N">It shows that the second layer is glued.</figref><figref num="23O">Shows wafer-to-wafer adhesion.</figref><figref num="24A">It shows a variant of the eighth embodiment in which the die is mounted top-up.</figref><figref num="24B">It shows a variant of the eighth embodiment in which the die is mounted top-up.</figref><figref num="25A">A ninth embodiment in which a via is embedded prior to bonding is shown.</figref><figref num="25B">A ninth embodiment in which a via is embedded prior to bonding is shown.</figref><figref num="25C">A ninth embodiment in which a via is embedded prior to bonding is shown.</figref><figref num="25D">A ninth embodiment in which a via is embedded prior to bonding is shown.</figref><figref num="25E">A ninth embodiment in which a via is embedded prior to bonding is shown.</figref><figref num="25F">A ninth embodiment in which a via is embedded prior to bonding is shown.</figref><figref num="26A">A tenth embodiment with embedded vias and surface contacts is shown.</figref><figref num="26B">A tenth embodiment with embedded vias and surface contacts is shown.</figref>

A more complete understanding of the present invention and the many advantages associated with it will be readily available as they are better understood by reference to the following detailed description, as reviewed with the accompanying drawings. ..

A first embodiment according to the present invention will be described with reference to the drawings, in particular FIG. It should be noted that the drawings are not drawn in actual proportions, but are drawn to show the concepts of the invention.

The substrate 10 includes a device region 11 having a contact region 12. The substrate 10 can be made up of a number of materials, such as semiconductor materials or insulating materials, depending on the desired application. Typically, the substrate 10 is composed of silicon or III-V material. The contact structure 12 is typically a metal pad or wiring structure that forms a contact to a device or circuit structure (not shown) formed within the substrate 10. The substrate 10 also includes an integrated circuit connected to the contact structure 12, and the substrate 10 may be a module containing only the contact structure. For example, the substrate 10 can be a module for connecting structures bonded to the substrate 10, or a module that provides a package or connection for integration with another module or, for example, a circuit structure on a printed circuit board. ..

Three separate dies 14 to 16 are arranged on the surface 13 to be adhered to the substrate 10. Each die has a substrate portion 19, a device region 18, and a contact structure 17. The die can be divided in advance by dicing or the like. The dies 14 to 16 can be composed of a large number of materials, eg, semiconductor materials, depending on the desired application. Typically, the substrate is composed of silicon or III-V material. The contact structure 17 is typically a metal pad or wiring structure that forms a contact to the device or circuit structure formed within the device region 18. The sizes of the contact structures 12 and 17 can be different from each other. The typical range of contact structure sizes is 1 to 20 microns, but size and relative size are outside this range depending on alignment tolerances, circuit design parameters, and other factors. You may. The size of the contact structure is intended to explain the concept of the invention and is not meant to be limiting. The device region 18 may also include an integrated circuit connected to the contact structure 17. Virtually all board portions 19 can be removed, leaving device layers, circuits, and circuit layers. Further, the substrates of the dies 14 to 16 are thinned to a desired thickness after bonding.

The dies 14 to 16 may be made by the same technique as the wafer 10 or may be made by another technique. Dies 14-16 can be the same or different devices or materials, respectively. Each of the dies 14 to 16 has a contact structure 17 formed in the device region 18. The conductive structures 17 are separated from each other to form a gap. Alternatively, it may be a single structure having openings at both ends of the contact structure. In other words, the opening can be a hole located within the contact structure, or the contact structure can be split in two. The size of the spacing or opening can be determined by the photolithographic design rules for the specific technique during bonding. For example, a minimum horizontal width of the contact structures 12 and 17 is required to later form a reliable low resistance electrical connection with the wiring metal.

A further factor in determining the optimum spacing or opening size is the ratio of the vertical distance between the contact structures 17, 12 plus the thickness of the contact structure 17 to the size of the spacing or opening. This defines the aspect ratio of the vias that will be formed later between the contact structures 17 and 12, which allow for an electrical connection between the contact structures 17 and 12. This vertical distance is 1 to 50, for direct oxide-to-oxide adhesion, as described in US Application No. 09 / 505,283, which is incorporated herein by reference. It is 5 microns or less, and for direct metal bonding is near zero, as described in US Application No. 10 / 359,608, which is incorporated herein by reference. In addition, the thickness of the contact structure 17 is typically 0.5-5 microns. For a typical desired via aspect ratio of 0.5 to 5 depending on the processing technique used, the typical range of spacing magnitudes is 0.3 to 20 microns for oxide-to-oxide adhesion and metal direct. Adhesion is 0.1 to 10 microns. The case of direct metal bonding will be described later in the fourth embodiment.

The dies 14-16 are generally aligned with the contact 12 such that the contact structure 17 and the spacing or opening are above the corresponding contact structure 12. The size of the contact structure 12 is chosen so that the dies 14-16 can simply be aligned with each other in the spacing between the contact structures 17. This size depends on the alignment accuracy of the method used to place the dies 14-16 on the substrate 10. Alignment accuracy can range from 1 to 10 microns according to typical methods using commercially available manufacturing tools. However, future improvements in these tools will result in lower alignment accuracy. The extent of the contact structure 17 beyond the horizontal spacing or aperture is preferably at least the distance given by this alignment accuracy.

Only one set of contact structures 17 is shown for each die 14-16, but the lateral spread of the contact structure 17 is typically much smaller than the horizontal spread of the dies 14-16. As a result, each die can have a number or a large number of contact structures 17. For example, the contact structure 17 has a horizontal spread in the range of 1 to 100 microns, and the dies 14 to 16 have a horizontal spread in the range of 1 to 100 mm. Thus, 10 in dies 14-16⁴The number of contact structures 17 having the above order is practically feasible.

As shown in FIG. 2A, the surface 20 of the die 14 is adhered to the surface 13 of the substrate 10. Although this can be achieved by many methods, it is preferred that they be adhered at room temperature using an adhesion method such as that described in US Application No. 09 / 505,283. In this application, 500 to 2000 mJ / m²Strong adhesion within the range of, i.e. chemical bonds are formed. Adhesion of dies 14 to 16 to substrate 10 is shown in FIG. After bonding, the substrates of dies 14 to 16 are thinned. Thinning is achieved by polishing, grinding, etching, or a combination of these three techniques, leaving the thinned substrate 21 or completely removing the substrate portion 19. FIG. 2B shows an example in which the substrate portion 19 is completely or substantially completely removed. The substrate of dies 14 to 16 may be thinned prior to bonding.

In one example, the material into which the contacts 12 and 17 are formed is SiO formed by chemical vapor deposition (CVD) or plasma CVD (PECVD), sputtering, evaporation.₂It is a deposited oxide such as. Other materials such as silicon nitride, amorphous silicon, polymers, semiconductors, and sintered materials may be used. Also, a layer of deposited oxide can be formed on the die.

Next, the surfaces are directly bonded to each other by a direct bonding technique. Preferably, any type of oxidative adhesion can be used, especially low temperature or room temperature oxidative adhesion. Adhesion techniques may include flattening and smoothing surfaces 13, 20 (surface 20 may be prepared prior to die cutting). This step can be accomplished using chemical mechanical polishing. The surface is preferably polished to a roughness of about 0.5 to 1.5 nm or less, preferably 0.5 nm or less, and is substantially flat. The surface roughness value is typically given by the root mean square (RMS) value. The surface roughness may also be given as an average value, which is approximately the same as the RMS value. After polishing, the surface is cleaned and dried to remove any residue from the polishing process. The polished surface is then preferably washed with a solution.

The bonded surface may be etched prior to polishing to improve flatness and / or surface roughness. This etching can be effective in removing particularly high portions on the adhesive surface, for example by selectively etching the high portions using standard photolithography techniques.

Adhesion techniques can include activation treatments. This activation process may include an etching process, preferably a very slite etch (VSE) process. The term VSE means that the micro-roughness (RMS) of the square root of the very slightly etched surface remains approximately unetched, typically &lt;0.5 nm, and preferably 0.5 nm. It means that it is in the range of ~ 1.5 nm. The optimum total amount of material removed depends on the material and the method used for removal. Typical amounts removed range from angstroms to several nanometers. It is also possible to remove a larger amount of material.

The term VSE can also refer to the removal of unwanted organic contaminants from the surface without removing the material, eg silicon oxide, which was intentionally deposited on the surface. Therefore, removing unwanted organic contaminants can reduce RMS.

The activation process can be a plasma process performed in different modes. For example, Ar or O plasma. Reactive ion etching (RIE) and plasma modes can be used, as can inductively coupled plasma modes (ICPs). Sputtering can also be used. Examples are presented below in RIE and plasma modes.

Alternatively, a post-VSE treatment that activates during that time and terminates the surface with the desired termination species can be used.

After activation, the surface is preferably terminated by a desired species that forms a temporary bond in the atomic layer of the surface, so that this surface can be combined with a surface terminated by the same or another bond species. Terminate the atomic layer until the next opportunity possible. The desired species on multiple surfaces preferably react with each other when they are sufficiently close to each other, allowing chemical bonding at low or room temperature. This bond can be strengthened by diffusion and dissociation or diffusion from the bonding interface of the desired species that has reacted.

This termination treatment may include immersing the bonded surface in a solution containing a chemical selected to produce a surface reaction that results in termination with the desired species. N-based solutions, eg NH₄OH can be used. This immersion is preferably performed immediately after the activation treatment. The termination treatment can consist of plasma, RIE, or a dry treatment in which a suitable gaseous component is introduced to terminate the surface with the desired species.

The surface is optionally washed and then dried. The two surfaces are bonded by aligning them (if necessary) and combining them to form an adhesive interface. The two surfaces are combined, for example, by initiating a bonding interface using a commercially available bonding device (not shown).

Natural adhesion then typically occurs at several points on the bonding interface and propagates throughout the surface. Once the initial adhesions begin to propagate, if the surfaces are close enough, chemical reactions such as polymerization leading to chemical bonds occur between the species used for surface aggregation. Thus, a strong bond is formed by the binding energy defined as the specific surface energy of one of the two separated surfaces at the partially stripped adhesive interface by inserting the wedge. By-products of this chemical reaction can diffuse from the adhesive interface and can typically be absorbed in the surrounding material. This by-product can also be converted to another by-product, diffused and absorbed. The amount of covalent and / or ionic bonds is increased by removing the converted species, resulting in increased bond strength.

Although FIG. 2A shows that three dies are glued to one substrate 10, more or fewer dies can be glued to substrate 10. Further, another substrate having the same size as the substrate 10 can be bonded. This is shown in FIG. 2C, where the substrate 22 with the device region 23 is glued to the wafer 10 so that the separated conductive structure 24 is generally aligned with the conductive structure 12. The substrate 22 can be thinned or removed prior to bonding to facilitate alignment. The substrate 22 can be thinned after bonding and, if desired, substantially entirely of the substrate 22 can be removed. The procedures described in the drawings below are also applicable to the structures shown in FIGS. 2B and 2C, but separate drawings are omitted for brevity.

As shown in FIG. 3A, a conformal insulating film 30 is formed so as to cover the substrate 10 and the surface 13 of the dies 14 to 16. The film can be formed, for example, by CVD, PVD, PECVD, preferably composed of an oxide film such as a silicon oxide film typically having a thickness of 0.1 to 1.0 micron. Also, implants such as deposited or spin-coated or deposited oxides or polymers 32 such as polyimide or benzocyclobutene may cover dies 14-16, as shown in FIG. 3B. It can also / or be formed between them. Material 32 can be formed at various points in the process. FIG. 3B shows an example in which the material 32 is formed before the formation of the films 30 and 40. In addition, the embedded material is treated after the formation of the structure shown in FIG. 3A, or after the formation of the hard mask 40 (FIG. 4), or based on many factors such as selected material and temperature considerations. It may be formed at various points in. Another technique may be used to form the implant material. For example, an insulating implant of silicon oxide, for example, can be used, for example, by continuous or repeated insulation forming steps and chemical mechanical polishing using the methods described above. Alternatively, a conductive implant of, for example, a metal formed, for example, by electroplating, can be used by continuous or repeated metal forming steps or chemical mechanical polishing. Having a flat surface improves the formation of photoresists and other films on this surface, as well as the formation of openings such as the opening 41 shown in FIG.

Subsequently, a hard mask 40 is formed on the insulating film 30 and patterned so that the openings 41 are generally aligned with the structure 17 (FIG. 4). The hard mask may consist of a material that has high etching selectivity for subsequent etching processes used to etch vias that penetrate the thinned substrate 21 and device regions 18 and 11 to reach the contact structure 12. preferable. Examples of hard masks are aluminum, tungsten, platinum, nickel and molybdenum, and examples of etching are SF.₆The vias are etched through a silicon substrate thinned by reactive ion etching based on, followed by CF.₄By reactive ion etching based on the above, the vias that penetrate the device regions 18 and 11 and reach the contact structure 12 are etched. The typical thickness of the hard mask 40 is 0.1 to 1.0 micron. The width of the aperture 40 depends on many factors, including the thickness of the thinned substrate 21 and the spacing between the contact structures 17, but is typically 1-10 microns.

The openings 41 are formed using standard photolithographic patterning and etching techniques on the hard mask 40 and the insulating film 30. For example, it is possible to form openings in photoresists using photolithography. This opening can be aligned with the alignment marks on the dies 14-16 (or substrate 22), or substrate 10. Optical imaging or IR imaging can be used for alignment. The hard mask 40 can then be etched by a suitable wet chemical solution or dry reactive ion etching process, depending on the material of the hard mask. In this way, the insulating film 30 is exposed in the opening. The insulating film 30 can then be etched by a suitable wet chemical solution or dry reactive ion etching, depending on the material of the insulating film, in the same manner as for the hard mask 40. An example of a wet chemical solution for a hard mask is Aluminum Etchant Type if the hard mask is aluminum. A. An example of reactive ion etching treatment for an insulating film material is CF when the insulating film material is silicon oxide.₄Reactive ion etching based on. Many other wet and dry etchings are possible for these and other hard mask and insulating film materials. The width of the openings 41 is preferably wider than the spacing of the structures 17 if the openings are aligned with dies 14-16 (or substrate 22), or the openings are aligned with the lower substrate 20. If so, it is preferably wider than the spacing of the structure 17 plus the alignment accuracy of the method used to place the dies 14-16 (or the substrate 22) on the substrate 20.

As shown in FIG. 5, the hard mask 40 is used to etch the substrate portions of the dies 14 to 16 to form the via 50. This etching continues through the materials adjacent to the contact structures 12 and 17 (which are typically insulating films), exposing the back and sides of the conductive material 17 and the top surface of the contact structure 12. .. The first set of gases and conditions is used (eg SF₆Etching can be performed through the substrate material of dies 14-16 (based on) and a second set of gases and conditions (eg CF).₄Etching is performed through the insulating layer around the contact structure 17 using). Both etchings can be performed in one chamber by switching the gas and conditions appropriately without breaking the vacuum. The etching that exposes the conductive material 12 is shown in FIG. 6A. This etching produces vias 60 that extend through the spacing or openings of the contact structure 17 to the contact structure 12.

The etching of the vias of the insulating film that exposes the contact structures 12 and 17 preferably has a high etching selectivity for the contact structure 17 so as to avoid an amount of etching that is harmful to the contact structure 17. However, there are some combinations of via etching on the insulating film and the conductive structure that lead to an amount of etching that is detrimental to the contact structure 17. For example, this detrimental effect can occur if the conductive structure 17 is thin enough or if the vertical distance between the contact structures 12, 17 is large enough.

Examples where the amount of etching is detrimental are the aluminum contact structure 17 surrounded by a silicon oxide insulator and some CF.₄In a combination of reactive ion etching based on, the ratio of the etching rate of the aluminum conductive structure to the silicon oxide insulator is the thickness of the contact structure 17 to the thickness of the silicon oxide insulator between the contact structures 12 and 17. Is about the same as or higher than this ratio.

In such situations where a detrimental amount of etching can occur to the contact structure 17, an intermediate treatment is added to thicken the contact structure 17 or protect the contact structure 17 from etching vias into the insulating film. can do. Intermediate treatments can be used to avoid harmful etchings, such as: When the back and sides of the upper contact structure 17 are first exposed by etching the insulator, a hard mask such as a metallic material is harmful to the contact structure 17 by continuing to etch the insulator. It is possible to selectively deposit on the exposed portion of the contact structure 17 before the result of etching. After selective deposition of the hard mask, etching of the insulator can be continued without harmful etching on the contact structure 17. An example of selective deposition of hard masks is the electroless plating method of nickel. This is shown, for example, in FIG. 6B. In FIG. 6B, etching is stopped after exposure of the contact structure 17 before any significant harmful etching occurs. The contact structure 17 is then coated, for example, with a protective hard mask material of nickel, for example using electroless plating. A material such as nickel may remain in the device when the contact structures 12, 17 are later connected. Alternatively, material 61 may be removed prior to making the connections of structures 12 and 17, if desired.

Note that the protective hard mask 61 may be selectively deposited on the hard mask 40. An example is that the hard mask 40 is a conductor and the deposition of the protective hard mask 61 is achieved by electroless plating. This is advantageous in reducing the required thickness of the hard mask 40. A further advantage of depositing the protective hard mask material on the hard mask 40 is that the constraining of the openings in the via 50 protects part of the contact structure 17 from the anisotropic etching of the via 60. possible. FIG. 7A shows one of the dies 14-16 in more detail to show the subsequent steps more clearly. A conformal insulating film 70 is formed so as to cover the side walls of the mask 40 and the contact structures 12, 17, vias 50, 60, and the vias 50, 60 are partially embedded. Examples of suitable insulating films are silicon oxide, silicon nitride and parylene. This insulating film can be formed using many typical deposition methods. This deposition method includes, but is not limited to, physical vapor deposition, chemical vapor deposition, and vapor deposition. An example of physical vapor deposition is sputtering, an example of chemical vapor deposition is plasma chemical vapor deposition, and an example of vapor deposition is solid evaporation followed by thermal decomposition and deposition.

The hard mask 40, or the hard mask 40 and the conformal insulating film 30, can be removed, for example, by etching prior to the formation of the conformal insulating film 70. FIG. 7B shows the case where the hard mask 40 is removed. If the etching to remove the hard mask 40 or the hard mask 40 and the film 30 is selective for the material exposed by the vias 50, 60, this etching can be done without a mask. is there. If this etching is not selective for the materials exposed by the vias 50, 60, these materials to be etched within the vias 50, 60 can be masked with the appropriate material. For example, if the hard mask 40, contact structures 12, 17 are made of aluminum, the vias are partially embedded with an easily removable spin-coated viscous liquid to a depth that covers the contact structures 12, 17. This via is a spin-coated viscous liquid by first selecting the appropriate spin-coated film thickness to properly flatten the surface formed by the hard mask 40 used to form the vias 50, 60. , Can be partially embedded. When this film thickness is applied, the film thickness inside the via is significantly thicker than that outside the via. The entire surface is then properly etched to remove the material from the surface of the hard mask 40, leaving the material within the vias 50, 60 covering the contact structures 12, 17. Examples of easily removable spin coating materials and suitable etchings are photoresist and O, respectively.₂It is plasma etching.

The conformal film 70 is anisotropically etched to expose the contact structures 12, 17 while leaving the film 70 on the sidewalls of the vias 50, 60. It is preferred that the back surface of the structure 17 be exposed to form shelves 27 for increasing the contact surface area. As a result, contact resistance is reduced. A typical shelf 27 over 1 micron wide is preferred to minimize contact resistance, but this distance will vary based on device and process parameters. 8A and 8B show the etched conformal film 70 with and without the mask removed before the formation of the conformal insulating film 70, respectively. Both membranes 30 and 40 may be removed prior to the formation of layer 70. In this case, following the etching of the conformal layer 70, another insulating layer may be formed on the substrate portion 21 (or the portion of the device region 18 where the portion 21 is completely removed), for example by oxidation or deposition.

Instead of the conformal film 70, another conformal film may be formed before the contact structure 12 is exposed. As shown in FIGS. 8C, 8D, 8E, and 8F, for example, a conformal film after etching through the substrate of dies 14 to 16 and before etching into the material adjacent to the contact structure 17. The conformal film 72 is formed before reaching the contact structure 17 after etching into the material adjacent to the contact structure 17 or the via 60 is formed after reaching the contact structure 17. The conformal film 73 is formed before the formation of the via 60, or the conformal film 74 is formed after reaching the conductive structure 17 and after forming a part of the via 60 and before the completion of the via 60 and before reaching the contact structure 12. It is formed. The conformal films 71, 72, 73, 74 are subsequently anisotropically etched to form an insulating side wall on the via 50 of the substrate portion of the dies 14-16. For example, as shown in FIGS. 8G, 8H, 8I, and 8J, the conformal film 71 is subsequently anisotropically etched to provide insulation on the via 50 of the substrate of dies 14-16. The sidewalls of the die 14 to 16 can be formed and the conformal film 72 is subsequently anisotropically etched onto the vias 50 of the substrate of dies 14-16 and the top of the vias 50 made of material adjacent to the contact structure 17. An insulating side wall can be formed, the conformal film 73 can be subsequently etched anisotropically to form an insulating side wall over the entire depth above the via 50, and the conformal film 74 can be subsequently heterogeneous. It can be sexually etched to form an insulating side wall over the entire depth on the via 50 and above the top of the via 60.

Instead of the sidewalls formed by uniformly depositing the films 70, 71, 72, 73, 74 and subsequently anisotropically etching these films, as shown in FIG. 8K, The side wall 75 can be selectively formed on this substrate portion after this portion of the dies 14-16 within the via 50 is formed by the via. The side wall 75 can be formed by a process that preferentially reacts with the substrate portion on the material adjacent to the contact structure 17. For example, when the substrate portion of the dies 14 to 16 is silicon and the material adjacent to the contact structure 17 is silicon oxide, an insulator deposition treatment in which silicon is preferentially nucleated over silicon oxide can be used. Here, the deposition of insulator constitutes the side wall 75. As shown in FIG. 8K, the side wall 75 is structurally similar to the conformal film 71 in the via 50 after the anisotropic etching of the conformal film 71. Here, the side wall 75 is formed after etching through the substrate portion of the dies 14 to 16 and before etching to the material adjacent to the contact structure 17.

During anisotropic etching, the sides of the contact structure 17 can also be exposed to further increase the surface area and reduce the contact resistance. This is also shown in FIGS. 8A and 8B. Vias 50, 60 can then be further or completely embedded by metal. Methods of embedding vias 50 and 60 with metal include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating. Electroplating is typically used to deposit thicker films than PVD or CVD, typically preceded by the deposition of thin PVD or CVD seed layers. Examples of films formed by PVD are sputtered aluminum, palladium, titanium, tungsten, titanium-tungsten, or copper, examples of films formed by CVD are tungsten or copper, electrolytic plating (none). Examples of films formed by (including electrolytic plating) are nickel, gold, palladium and copper.

FIG. 9A shows an example of the mask electroplating method. By the mask electroplating method, the metal seed layer 90 is first deposited so as to cover the structure to form electrical contacts to the contact structures 12 and 17, followed by the formation of the mask 91 using, for example, a photoresist. The seed layer 90 can be deposited by PVD, CVD, or electroplating as described above. Using electrical contacts to the mask 91 and seed layer 90, the metal contacts 92 embed vias 50, 60. In FIG. 9B, the structure in which the mask 40 is removed before the formation of the conformal insulating film 70 is shown, and in FIG. 9C, the structure in which the seed layer is not used is shown. It is then possible to remove the outer excess of vias 50, 60 of the metal contacts 92 using a polishing step, eg chemical mechanical polishing. This polishing step can also remove the seed layer 90 on the exposed flanks of dies 14-16. This polishing step can further remove the hard mask 40 on the exposed sides of the dies 14-16. Removing the hard mask 40, when the hard mask is conductive, such as the aluminum mentioned above, electrically insulates the vias thus formed by the metal from each other. It is preferable for this. This polishing step further removes the conformal insulating film 30. As a result, a substantially flat surface and a flat metal structure 100 are formed on the exposed surfaces of the dies 14 to 16, as shown in FIGS. 10A and 10B. Here, the structure in FIG. 10B differs from the structure in FIG. 10A in that the seed layer is not used prior to embedding the via with metal.

Instead of embedding vias 50, 60 with metal followed by CMP, vias 50, 60 are lined with metal 93, embedded with insulator 94, followed by CMP, as shown in Figure 10C. It is possible. Vias 50, 60 can be lined with metal 93 by depositing using at least one of PVD, electroplating, or CVD as described above. The thickness of the metal 93 is typically 0.01 to 0.2 microns and includes a barrier layer adjacent to the conformal insulating film 70 to prevent contamination of contact structures 12, 17 or device regions 18, 11. You may be. Examples of barrier layers include tantalum nitride, tungsten nitride, titanium nitride, and may be preceded by a titanium adhesive layer typically having a thickness of 0.005 to 0.02 microns. The typical thickness of the barrier layer is 0.005 to 0.05 microns. After the initial thickness of 93 has been deposited, electroplating can be used to uniformly increase the thickness of 93 to the desired thickness. A typical thickness after augmentation is 0.5 to 2.0 microns for the via 50, provided the via 50 is wide enough. An example of insulator 94 is silicon oxide, and an example of an embedding method is by plasma chemical vapor deposition (PECVD). This alternative is to reduce metal deposition and metal CMP, and thermal expansion between the inner lining synthetic metal, the vias embedded by the insulator, and the surrounding substrates of dies 14-16. It has the advantage of having the potential to improve coefficient (CTE) matching.

An alternative to embedding vias 50, 60 with metal and lining vias 50, 60 with metal 93 and then embedding with insulator 94 is to embed vias 60 with metal 97 or wrap the inside with contacts. The electrical wiring between structures 12 and 17 was formed without contacting the thinned substrate 21, then vias 50 and 60 were embedded with insulator 98, followed by the above and as shown in FIG. 10D. Doing CMP. A thin substrate in which metal 97 is formed by electroless plating, which preferentially forms plating on contact structures 12 and 17 by forming plating to a thickness sufficient to connect the contact structures 12 and 17. The contact structures 12 and 17 can be connected to each other without contacting 21. An example of an electroless plating method in which plating is performed to a sufficient thickness is a nickel electroless plating method. This alternative method is to use the side walls 60 on the vias 50 of these remaining boards to electrically insulate the electrical wiring from the remaining board dies 14-16, as shown in FIG. 10D. It has the advantage that 71, 72, 73, 74, 75 are not needed.

The electrical wiring to the interconnected contact structures 12 and 17 is shown in FIG. 10E and etches via 51 through insulator 98 to reach metal 97 and via 51 as described in FIG. 10B. Is formed by embedding the metal 46, or by covering the inside of the via 51 with the conductive material 52 and embedding it with the insulator 53 as shown in FIG. 10F and as described in FIG. 10C. It is possible. The via 51 in FIGS. 10E and 10F is shown to be connected to a portion of the metal 97 on the contact structure 12. Alternatively, the via 51 can be connected to either the portion of the metal 97 on the contact 17 or both the contact structures 12 and 17.

The structures of FIGS. 10A-10F are suitable for subsequent processing including, but not limited to, photolithography-based routing or underbump metal coatings to support wire bonding or flip-chip packaging. ing. This process typically forms an electrically insulating material on the exposed side of the thinned substrate 21 to form electrical insulation for wiring formation or underbump metal coating. Includes.

Insulating material 96, such as deposited or spin-coated oxides or polymers, is formed on dies 14-16 after CMP and wire routing or underbump metal coating 95 that contacts the metal structure 100 on the material 96. An example of the formation of is shown in FIG. As shown in FIG. 3B, another implant material may be used between the dies 14-16 prior to the formation of material 96. The metal coating may include multiple layers separated by an insulating layer (not shown here) to accommodate high via density and / or high routing complexity. Alternatively, if the conformal insulating film 70 is not removed by the flattening step, the conformal insulating film may remain and provide adequate electrical insulation for the metal coating structure.

A second embodiment of the method according to the present invention is shown in FIG. A hard mask 101 is formed on dies 14-16 without any intervening insulating layer. A typical range of thickness for the hard mask 101 is 0.1 to 1.0 micron. The hard mask 101 may have high etching selectivity for subsequent etching steps or steps used to etch vias that penetrate the thinned substrate 21 and device regions 18 and 11 to reach the contact structure 12. preferable. Examples of hard masks are aluminum, tungsten, platinum, nickel and molybdenum, and examples of etching are SF for etching vias through a thin silicon substrate.₆Based on reactive ion etching and CF to then form vias that penetrate device regions 18 and 11 to reach contact structure 12.₄Reactive ion etching based on. An opening 102 is formed in the mask 101 and the structure is processed in the same manner as in the first embodiment and etched through the die substrate and device region to expose structures 12 and 17. At this time, it is preferable that the upper surface of the structure 17 is exposed to form a shelf (as shown in FIGS. 8A and 8B). A metal coating is performed with the mask 103 as shown in FIGS. 7-9 to form the metal 104 to produce the structure shown in FIG. After CMP (Figure 14), the metal 105 is flattened and the structure is based on photolithography to support wire bonding or flip chip packaging, similar to the metal coating structure shown in Figure 11. Suitable for subsequent steps including (but not limited to) wire routing or underbump metal coatings. In this step, an electrically insulating material is formed on the exposed side of dies 14-16 and routed to cover the exposed side of dies 14-16 or underbump metal. It may include providing electrical insulation for the coating. To further assist in routing or underbump metal coatings, flattening materials such as, for example, insulators or metals, or polyimide or benzocyclobutene materials have been formed, eg, as described in the first embodiment. The surface of the structure can be flattened by embedding any space in the die, opening, or groove before or after the CMP process.

The present invention can also be used with other structures. For example, one contact in a die or wafer can be connected to a contact in the substrate to which the die or wafer is bonded without requiring a pair of contacts 17. This is shown in Figure 15. In FIG. 15, the metal structure 107 is in contact with the seed 90 connecting the contact structures 12, 108, while the structure 108 is separated from the structure 12. A portion (left side) of the metal contact 107 extends directly from the top surface of the substrate 109 to the seed 90 on the structure 108. On the other hand, the other side (right side) of the metal contact 107 extends directly from the upper surface of the substrate portion 109 to the seed 90 on the structure 12.

The present invention provides many advantages. One mask is used to connect the die or wafer to the substrate by etching through the back surface of the die or wafer bonded to the substrate. Typically, there is no need for intra-via photolithography, which is complex, problematic, and can limit scaling. This etching proceeds through the bonding interface. In addition, the top surface of the contact to be connected can be exposed to increase the surface area of the contact and reduce the resistance of the contact. Devices of different technologies can be connected. This optimizes device performance and avoids problems with trying to manufacture and use different technologies in one process sequence.

A third embodiment is shown in FIGS. 16A, 16B and 17. The substrate 110 has a device region 111 having a contact structure 112. As shown in FIG. 16A, the dies 114 to 116 each have a device region 118, a substrate portion 121, and a contact structure 117, which are adhered to the substrate 110 on the surface 113. In this embodiment, there is no material covering the contact structure 112. Following one masking process described for the first and second embodiments, the structures shown in FIGS. 16B and 17 are manufactured. The via 50 is etched through the substrate portion 121 and the device region 118 to expose the shelf 26 on the back surface of the contact structure 117. This etching is continued to form the via 60 and expose the top surface of the contact structure 112. The contact 120 is formed in the via with or without the seed layer 90 and the contact structures 112, 117 are connected. The implant material can be used to flatten the device as described above with respect to FIG. 3B. Contact 120 can also be formed by the method shown above in FIGS. 10C-10F. Also, the film 70 can be formed as shown in FIGS. 8C-8K.

A fourth embodiment is shown in FIGS. 18-19. In this embodiment, there is no material covering the contact structures 122, 123. A contact structure 123 made of a conductive material, eg a metal, within the dies 114-116 can spread above the surface of the dies 114-116, and a contact structure 122 made of a conductive material, eg a metal, is an upper surface of the surface 113. Can spread with. The contact structure 123 and the contact structure 122 may be composed of different metals. For example, the contact structure 123 may be composed of one of copper, tungsten, nickel and gold, and the contact structure 122 may be composed of another of copper, tungsten, nickel and gold. The contact structure 123 or contact structure 122 may further be composed of another metal, eg, a combination of nickel, palladium, gold. The contact structure 123 and the contact structure 122 may be further composed of an alloy of copper, tungsten, nickel, gold, or another alloy, such as indium tin oxide. These metals can be formed by a variety of techniques, including PVD, thermal, electron beam, and electroplating.

The parts of the dies 114 to 116 excluding the contact structure 123 and the parts of the surface 113 excluding the contact structure 122 are non-conductive materials, for example, silicon oxide or silicon nitride, or silicon oxynitride, or semiconductor integrated circuit manufacturing. It is preferable that it is another insulating material that is compatible with the above. As described in Application No. 10 / 359,608, dies 114 to 116 with the contact structure 123 exposed are exposed on the surface 123 with the contact structure 122 exposed within the dies 114 to 116 of the contact structure 113. Sufficient to align the exposed portion with the exposed portion within the surface 113 of the contact structure 122 and align the non-conductive material portion of the dies 114-116 with the non-conductive material portion of the surface 113. It is glued with a sufficient system. The adhesion between the non-conductive material portion of the dies 114 to 116 and the non-conductive material portion of the surface 113 is preferably direct adhesion as described in Application No. 10 / 359,608. Alternative examples of direct bonding, eg, those described in Application No. 10 / 440,099, may be used. The bonding energy of direct bonding is preferably 1 J / m.²To generate an internal pressure of the contact structure 122 against the contact structure 123. As a result, the contact structures 122 and 123 are electrically connected. As described above, in order to generate the maximum internal pressure, it is preferable to use direct bonding, which results in high bonding energy at a low temperature as described above, for example. However, direct bonding in which the bonding energy is low at a low temperature or direct bonding in which a high temperature is required to obtain a high bonding energy is also permitted depending on the application form. For example 1J / m²Moderate temperature below 400 ° C, for example, or 10 kg / cm, for example, to obtain high adhesion energy above²Direct gluing may be used that requires a modest pressure of less than.

More specifically, when a wafer surface containing a metal bonding pad comes into contact at room temperature, the contacting non-metal parts of the opposite wafer surface begin to form bonds at the point of contact, increasing the chemical bonds in contact. As a result, the attractive adhesive force between the wafers increases. Without the metal pads, the wafers would adhere to each other over the entire surface of the wafer. According to the present invention, the bonding seams between wafers are hindered, but the presence of metal pads does not hinder chemical wafer-to-wafer bonding. Due to the malleability and ductility of the metal bonding pad, the pressure generated in the non-metal region by chemical wafer-to-wafer bonding becomes a force that deforms the non-flat and / or undulating region on the metal pad. As a result, the flatness and / or unevenness of the metal pads is improved and the bond between the metal pads is strengthened. The pressure generated by the chemical bond is sufficient to eliminate the need for external pressure applied to ensure that these metal pads are in strong contact with each other. Mutual diffusion or self-diffusion of metal atoms at the contact interface allows strong metal bonds to be formed between tightly contacted metal pads, even at room temperature. This diffusion is thermodynamically propelled to reduce surface free energy and is typically enhanced for metals with high interdiffusion and / or self-diffusion coefficients. These high diffusion coefficients are the result of cohesive energy. The cohesive energy is typically determined largely by a mobile free electron gas, which is not hindered by the movement of metal ions during diffusion.

Alternatively, the contact structure 123 in the dies 114 to 116 is substantially flat with the surface of the dies 114 to 116, and the contact structure 122 is substantially flat with the surface 113. This can be achieved by forming a substrate with flat surfaces with vias embedded in metal (such as W, Ni, Au, Cu). Metal-embedded vias are electroplated on a metal seed layer, such as a Cu, Al, Al-Cu (2%), Al-Si (2%) alloy layer, about 0.5 micron thick. Can be formed in, or can be formed by a Cu layer formed on an Al or Al alloy. Pd may be used as a seed layer or may be formed on an Al or Al alloy layer. Ni, W, Au, Cu columns may be formed on the seed layer. After electroplating, the seed layer is removed from the surface between the columns using either the column or a mask and a pattern defined by photolithography as metal etching. Next, an oxide layer is formed so as to cover the surface. This oxide layer is the target of CMP and forms a flat surface with oxide and metal regions.

The contact structures 122, 123 may have a higher surface roughness than the non-metal surface of the dies 114-116 and the non-metal of the surface 113. For example, the surfaces and surfaces 113 of dies 114-116 have a root mean square (RMS) surface roughness of preferably less than 1 nm, more preferably less than 0.5 nm. On the other hand, the contact structures 122 and 123 have an RMS surface roughness of preferably less than 2 nm, more preferably less than 1 nm.

The internal pressure of the contact structure 122 on the contact structure 123, which is derived from the adhesion between the non-contact structure 123 on the surface of the dies 114 to 116 and the non-contact structure 122 on the surface 113, is the surface or surface of the dies 114 to 116. Due to, for example, natural oxidation or other contamination on the exposed metal surface of 113, such as hydrocarbons, it may not be suitable to achieve adhesion or to result in electrical contact with a favorable low resistance. .. Alternatively, improving the adhesion between the contact structures 123, 122 or making the electrical connection a preferable low resistance can be achieved by removing the natural oxides on the contact structures 123 or 122. For example, dilute hydrofluoric acid can be used before the surface 113 comes into contact with the surfaces of dies 114-116. In addition, the surfaces of the surface 113 and dies 114-116 may be exposed to an inert environment, such as nitrogen or argon, until the surface 113 contacts the surface of the dies 114-116 after removal of the natural oxide. .. Alternatively, improving the adhesion between the contact structures 123 and 122 and making the electrical connection a preferable low resistance can be done by other than the contact structure 122 on the surface of the dies 114 to 116 and the contact structure 122 on the surface 113. It can be achieved by raising the temperature of the contact structures 122, 123, eg by heating, after adhering to the portions of. Increasing the temperature can be done by reducing natural oxides or other contaminants, or if, for example, the contact structure 123 or 122 has a higher coefficient of thermal expansion than the non-metallic material surrounding the contact structure 123, 122. Increasing the internal pressure between 123 and 122, or reducing the natural oxides and increasing the internal pressure, can result in a favorable low resistance of the electrical connection. Increasing the temperature increases the diffusion between contact structures such as 122, 123, resulting in a preferred low resistance for electrical connections. Thus, by raising the temperature, the metal adhesion between the contact structures 123, 122, Enhanced metal contacts, metal connections and electrical conductivity. 1Ω / μm²Less than contact resistance was achieved. For example, resistance of less than 50 mΩ was obtained for two contact structures with a diameter of about 5 or 10 μm and both 1 μm in thickness.

If the IC, eg a silicon IC, is in the dies 114-116 or in the layer 111 below the surface 113, the temperature rise is to avoid damage to the IC, or contact structure, or other metal structures. , Preferably less than 400 ° C over 2 hours, more preferably less than 350 ° C over 2 hours. If the contact structure is a material sensitive to thermal expansion or internal pressure or negligible natural oxides, eg gold, then metal adhesion between contact structures 122, 123, or metal contact, or metal wiring, or electrical conductivity. The temperature rise that produces the result of strengthening is very low, for example about 50 ° C over 10 minutes.

If necessary, metal bonding between contact structures 123, 122, or metal contact, or metal connection, or lower to minimize post-bonding temperature rise required to enhance electrical conductivity to the desired degree. It is preferable to use contact structures 123, 122, which produce a result that the internal pressure increases significantly at the post-bonding temperature and can be deformed at low pressure. For example, the internal pressure generated as a result of the post-bonding temperature rise depends on the metals that make up the contact structures 123, 122. For example, metals with a large coefficient of thermal expansion (CTE), such as copper, nickel and gold, result in greater expansion at a given temperature. In addition, metals with high shear modulus, such as tungsten and nickel, generate greater stress at a given temperature. Thus, metals with a large product of CTE and shear modulus, such as copper, tungsten, and nickel, are most effective in increasing the internal pressure as the temperature rises. In addition, preferably very pure metals such as metals with a low yield stress of 99.9%, such as copper, nickel and gold, are easily deformed at lower stresses and thus between contact structures at lower stresses. It is possible to produce results of improved metal adhesion, or metal contact, or metal connection, or electrical conductivity. Therefore, metals with a large product of CTE and shear modulus, or a metal with a high CTE and shear modulus standardized by yield stress, such as copper, nickel, and gold, contact structures 123, 122 have post-bonding temperatures. As a result of the generation of internal pressure with an increase, contact structures 123 and 122 showing improvement in metal adhesion, metal contact, metal connection and electrical conductivity between contact structures are preferable.

Alternatively, the contact structure 123 may be slightly lower than the surface of the dies 114 to 116, or the contact structure 122 may be slightly lower than the surface 113. The distance between the surfaces of dies 114-116 is preferably less than 20 nm, more preferably less than 10 nm. Subsequent bonding and subsequent temperature rise increase the internal pressure between the contact structures 122, 123 as described above, and also metal bonding, or metal contact, or metal connection, or electrical conduction between the contact structures 122, 123. The result is improved sex. The slight distance between the surface 113 of the contact structure 122 and the slight distance between the contact structure 123 and the surface of the dies 114-116 are the average distances of the spread of the contact structure. The morphological features of the contact structure include positions equal to, above, and below the average distance. The total height variability of the contact structure is given by the difference between the maximum height and the minimum height, which can substantially exceed the RMS variability. For example, a contact structure with an RMS of 1 nm can have a total height variation of 10 nm. Therefore, as described above, the contact structure 123 is slightly lower than the surface of the dies 114 to 116 and the contact structure 122 is slightly lower than the surface 113, but a part of the contact structure 122 extends above the surface of the dies 114 to 116. At the same time, a part of the contact structure 123 spreads above the surface 113, and as a result, the contact structure 122 and the contact structure 123 are mechanically connected after the non-metal part of the surface 113 is adhered to the non-metal part of the dies 114 to 116. To. This mechanical connection is adequately electrically connected between the contact structure 122 and the contact structure 123 due to incomplete mechanical connection or due to natural oxide film or other contamination on the contact structure 122 or contact structure 123. It may not result in a targeted connection. Subsequent temperature increases can improve metal adhesion, metal contact, metal connection, and electrical conductivity between the contact structures 122, 123 as described above.

Or, if the highest part of the contact structure 123 is lower than the surface of the dies 114 to 116, or the highest part of the contact structure 122 is lower than the surface 113, and there is no mechanical contact between the contact structures 123, 122 after bonding. The rise in temperature can result in mechanical contact and / or preferably electrical connection between the contact structures 123, 122.

Alternatively, the contact structure 123 may be lower than the surface of the dies 114 to 116 and the contact structure 122 may be higher than the surface 113, or the contact structure 123 may be higher than the surface of the dies 114 to 116 and the contact structure 122 may be lower than the surface 113. The distance between the surface 113 and the lower contact structure 122 and the distance between the surface of the dies 114, 115, 116 and the lower contact structure 123 (or vice versa) are described in Application No. 10 / 359,608. As it is, it is a little positive. Alternatively, the distance between the surface 113 and the lower contact structure 122 and the distance between the surface of the dies 114, 115, 116 and the lower contact structure 123 (or vice versa) is nominally zero. There is or is a slight negative, and as described above, the temperature rise after bonding can improve the metal bonding, metal contact, metal connection, and electrical conductivity between the contact structures 122 and 123.

The height of the contact structure 123 relative to the surface of the dies 114 to 116 and the height of the contact structure 122 relative to the height of the surface 113 are the polishing steps that form the surface or surface 113 of the dies 114 to 116, eg. It can be adjusted by chemical mechanical polishing (CMP). CMP processing typically had many processing variables. This variable includes, but is not limited to, polishing slurry, slurry addition rate, polishing pad, polishing pad rotation rate, and polishing pressure. The CMP treatment further comprises the specific non-metal and metallic materials that make up the surface of the surface 113 and dies 114-116 and the relative polishing rates of the non-metallic and metallic materials (similar polishing rates, eg nickel, Silicon oxide is preferred) and depends on the size, pitch, grain structure of the contact structures 122, 123 and the surface non-flatness of the surface 113 or dies 114-116. By optimizing these process parameters, it is possible to control the height of the contact structure 123 relative to the surface of dies 114-116 and the height of the contact structure 122 relative to the height of the surface 113. Alternative polishing techniques, eg slurry-free polishing, may be used.

The height of the contact structure 123 relative to the dies 114 to 116 and the height of the contact structure 122 relative to the height of the surface 113 are the material around the contact 123 on the surface of the dies 114 to 116 or the material around the contact structure 122 on the surface 113. Can also be controlled by slightly dry etching. This dry etching example preferably results in increased surface roughness for a surface made of an insulating material, such as silicon oxide, or silicon nitride, or silicon oxynitride, CF.₄And O₂Plasma or reactive etching using a mixture of. As the surface roughness increases, the binding energy between the interfaces decreases significantly. Alternatively, the height of the contact structures 123 and 122 can be controlled by forming an ultra-thin metal layer on the contact structures 123, 122. For example, electroless plating of suitable metals, eg gold, can be self-restricted to ultra-thin layers, eg, about 5-50 nm. This method has the additional advantage of facilitating the formation of electrical connections by making the edges of the oxidizing metal ultra-thin non-oxidizing metals, such as metals, nickel.

Further, the contact structure 122 has a contact such that the lateral dimension is included in the contact structure 122 after bonding so that the periphery of the contact structure 123 is included in the contact structure 122, or the periphery of the contact structure 122 is included in the periphery of the contact structure 123. It can be larger or smaller than the lateral dimension of structure 123. The lateral minimum dimension of the larger or smaller portion is typically determined by at least twice the alignment accuracy of the adhesion of dies 114-116 to surface 113. For example, when the alignment accuracy of the dies 114 to 116 when adhering to the surface is 1 micron, the contact structure 122 is more than the contact structure 123 so that the periphery of the contact structure 123 is included in the periphery of the contact structure 122. Is preferably at least 2 microns larger.

The maximum internal pressure of the contact structure 122 against the contact structure 123, which is formed between the peripheral part of the contact structure 123 on the surface of the dies 114 to 116 and the peripheral part of the contact structure 122 on the surface 113, or the temperature after bonding. This internal pressure, which can be provided by ascending, depends on the area of the surface of the dies 114-116 that adheres to the portion of the surface 113 and the area of the contact structure 123 relative to the area of the contact structure 122. The sum of these two areas is the contact structure aligned with the remaining area of the contact structure 123 aligned with the non-contact area 122 portion of the surface 113 and the non-contact structure 123 portion of the surface of dies 114-116. Due to the remaining area of 122, it is typically smaller than the area of the entire area of dies 114-116 relative to surface 113. This is due to the difference in lateral dimensions between the contact structures 123 and 122 and the misalignment of the adhesive between the surfaces of the dies 114 to 116 and the surface 113. The maximum internal pressure generated by bonding or that can be provided by the temperature rise after bonding is the fracture stress of the bond between that part of the surface of dies 114-116 and that part of surface 113 and the contact structure 122. It can be approximated by the ratio of the adhesion area of the contact structure 123 to the portion to the portion. For example, that part of the surface of dies 114-116 and that part of the surface 113 are composed of silicon oxide with a fracture stress of 16,000 psi and the direct adhesion between these aligned parts is half that of silicon oxide. At 8,000 psi, contact structures 123, 122 are circles with a diameter of 4 microns with a pitch of 10 microns, and when perfectly aligned, a maximum internal pressure between contact structures 123, 122 over 60,000 psi is possible. is there. This pressure is typically significantly higher than that produced by the post-bonding temperature rise. For example, contact structures 123, 122 with 17 ppm CTE and 6,400,

The contact structures 123, 122 are typically not perfectly aligned and do not have the same lateral dimensions. As a result, a part of the contact structure 123 comes into contact with the peripheral part of the contact structure 122 of the surface 113, or a part of the contact structure 122 comes into contact with the peripheral part of the surface structure 123 of the dies 114 to 116. It can result in contact lenses. If part of the contact structure 123 is in contact with the portion of the surface 113 and the contact structure 122 is lower than the surface 113, or if the contact structure 122 is in contact with the portion of the surface of the dies 114 to 116 and the contact structure 123 is in contact with the die 114. When lower than the surface of to 116, the temperature rise after bonding preferentially increases the internal pressure between the contact 122 and that part of the surface of the dies 114 to 116 or between the contact structure 123 and that part of the surface 113. The result is that the internal pressure between the contact structures 123, 122 at a given post-bonding temperature rise is reduced (this would not happen otherwise). In order to avoid a decrease in the increase in internal pressure between the contact structures 123 and 122, when the contact structure 123 is lower than the surface of the dies 114 to 116, the periphery of the contact structure 122 is mainly caused by this increase in internal pressure in the contact structure 123 and Positioned within the perimeter of the contact structure 123 by an amount that covers the misalignment and size and shape mismatch of the contact structure 123 and the contact structure 122 so that it occurs between the contact structures 122 (eg, twice the alignment tolerance). It is preferable to do so. Alternatively, if the contact structure 122 is lower than the surface 113, after bonding, the periphery of the contact structure 123 is aligned with the contact structure 123 and the contact structure 122 so that an increase in internal pressure occurs mainly between the contact structure 123 and the contact structure 122. It is preferably located within the perimeter of the contact structure 122 by an amount that covers the misalignment and size and shape discrepancies. In addition, the contact structure 123 is lower than the surface of dies 114-116.

The temperature of the contact structure 123 and the contact structure 122 can be raised before or after thinning the substrates of the dies 114-116 to form the thinned die substrate 121. The temperatures of the contact structure 123 and the contact structure 122 can be raised after bonding by various types of heating methods. Such heating methods include, but are not limited to, thermal, infrared, and inductive. Examples of thermal heating include furnaces, belt furnaces, and hot plates. An example of infrared heating is rapid thermal. Annealing). The infrared heat source can be filtered to preferentially heat the contact structures 123, 122 with photons of the desired energy. For example, when the substrate 110, the dies 114 to 116 substrates, the thinned die substrate 121, the device region 111, and the device region 118 are composed of a semiconductor, for example silicon, the infrared heat source has energy that exceeds the bandgap of the semiconductor. It can be filtered to prevent the photons from being absorbed by the semiconductor. As a result, the temperature rise of the semiconductor is smaller than the temperature rise of the contact structure 123 or the contact structure 122. An example of inductive heating is inductive magnetic resonance when the contact structure 123 or contact structure 122 is composed of a magnet, eg nickel.

As shown in FIG. 18, the plurality of contact structures 123 may come into contact with one contact structure 122 without completely covering the one contact structure 122. Alternatively, one contact structure 123 may be in contact with one contact structure 122 in part or in whole, or one contact structure 122 may be in contact with one contact structure 123 in part or in whole, or One contact structure 123 may come into contact with multiple contact structures 122.

If the plurality of contact structures 123 are in contact with one contact structure 122 without covering the entire contact structure 122, the one masking step described for the preceding embodiment is shown in FIG. 19A. The structure being made can be manufactured. Here, the metal seed layer 90 forms electrical wiring for both the contact structures 122, 123. Alternatively, the metal seed layer 90 may only contact the contact structure 123, especially if the contact structure 123 covers the entire contact structure 122. The structure shown in FIG. 19A is further processed to form a surface similar to surface 113 shown in FIG. 18 as previously described and shown in FIG. 19B in this embodiment. obtain. In FIG. 19B, the contact structure 59 is similar to the contact structure 122, and the flattened material 58 is similar to any portion of the surface 113 other than the contact 122. The exposed contact is then similarly glued by an additional die with the exposed contact structure 123 to the dies 114-116 with the exposed contact structure 123 to the exposed contact structure 122. Adhesive and connected to a surface with 59.

In this fourth embodiment, via etching and subsequent metal interconnection are not required to form an electrical interconnection between the contact structures 123, 122. However, via etching and subsequent metal interconnection as shown in FIG. 19A is desirable to provide electrical access from the exposed side of dies 114-116. An application in which this is desirable is to flip-chip bump bond the exposed side of dies 114-116 to a package, substrate, integrated circuit between the contact structure 123 or 122 and this package, substrate, integrated circuit. Is to form an electrical connection to the. An application in which vias are not required for this purpose, for example, forming certain types of Staring Focal Plane Arrays. For these application examples, the method including (but not limited to) the derivatives described above and the devices manufactured thereby as shown in FIG. 18 will suffice.

A fifth embodiment is shown in FIGS. 20A-20H. In this embodiment, the formation of the via 50 is made except that the contact structures 17, 108, 117, 123 in the die having an edge that overlaps the opening or the via 50 are replaced by a contact structure 87 that does not have an opening or an overlapping edge. It is the same as the previous embodiment. In this embodiment, the contact structure 87 in the dies 84 to 86 having the substrate portion 89 and the device region 88 is adhered to the surface 83 having the device region 81, the substrate 80 and the contact structure 82. The contact structure 87 is located above the contact structure 82, as shown in FIG. 20A. Also, dies 84-86 have a surface 113 with an exposed contact structure 112 similar to that shown in FIGS. 16 and 17, or a contact structure similar to that shown in FIGS. 18 and 19. It can be glued to 122. Note that the contact structure 87 can be adhered in direct contact with the contact structure 82. This is shown in device 86. Dies 84-86 may also have the same contact structure configuration. Figures 20A and 20B are drawn to show two contact structure configurations with a notch between the two configurations for simplicity. Typically, each of the dies bonded to one substrate has the same contact structure configuration. If dies with different contact structures are glued to the same substrate, process changes such as adjusting etching parameters or etching vias separately may be required. This figure is presented to show the present invention in which the same or different structures are present on one substrate and does not necessarily show such variants.

A patterned mask 40 and opening 41 are formed as described in the first embodiment and shown in FIG. 20B. Next, the via 55 anisotropically etches the remaining substrate portion 89 in the dies 84 to 86, and etches a part of the device region 88 in the dies 84 to 86 until it reaches the contact structure 87. The contact structure 87 is etched to form the side surface 79, the remaining portion of the device region 88 is etched to the surface 83 (if necessary), and the device region 81 is etched to the contact structure 12 (if necessary). By that, it is formed. With the exception of etching the contact structure 87, these anisotropic etchings can be performed as described in the first embodiment. For anisotropic etching of the contact structure 87, RIE that selectively etches the structure 87 of the conductor with respect to the hard mask 40 can be used. If the hard mask 40 and the conductor structure 87 have the same etching rate, the hard mask 40 can be formed substantially thicker than the contact structure 87. As a result, the exposed contact structure 87 is etched together with the device area 81 up to the substrate portion 89, the device area 88, the contact structure 87, and the contact structure 82 without completely etching the etching hard mask 40. .. Etching for the contact structure 87 can be substantially different from etching for the remaining substrate portion 89 and device region 88 and device region 81 within the dies 84-86. For example, if the residual substrate portion 89 is made of silicon, the etched parts of the device regions 88 and 81 are made of silicon oxide, and the contact structure 87 is made of Al, the RIE is based on something that is not chlorine. Etching can be used to etch the residual substrate 89 and device regions 88, 81, and chlorine-based RIE etching can be used to etch the contact structure 87.

It is preferable that the side wall 76 is formed before etching the contact structure 87. Specifically, the structure can be anisotropically etched through the substrate 89 and stopped after reaching the device region 88, or the contact structure 87 continues into the device region 88. It is possible to stop in front. Layer 76 is then formed, as shown in FIG. 20C for two cases for separated contact structures and directly bonded contact structures. Layer 76 can be formed by depositing an insulating layer, such as silicon oxide, in the via 55, followed by removing this film from the bottom of the via 55, for example by anisotropic etching. The rest of the device area 88 and the contact structure 87 are etched to expose the contact structure 82 as shown in FIG. 20D (left side), and the rest of the device area 88 in FIG. 20D (right side). Is etched to expose contact 87.

Subsequent steps such as the formation of the sidewalls, the electrical connection between the contact structures 82, 87, the coating and / or embedding inside the via, the electrical connection to the contact structure 87 anisotropically etches the contact structure 87. Continued as in the described embodiments, except primarily limited to the side surface 79 exposed by. The second difference is the formation of the side wall as shown by the side wall 70 in FIGS. 8A, 8B, or the side wall 74 shown in FIG. 8J. In FIG. 8J, the side wall extends below the contact 17 and also obstructs the electrical connection of the contact structure 87 to the side surface 79. FIG. 20D (left side) shows one of the dies 84-86 in detail to more clearly show an example in which the side wall 76 does not block the electrical connection to the side surface 79.

An example of side wall formation in FIG. 20D is similar to that previously shown in FIG. 8H. In FIG. 8H, the side wall 72 extends below the thinned die substrate 21 and above the contact structure 17. The etching of the contact structure 87, or the via 55 penetrating the region between the contact structure 87 and the contact structure 82, can be slightly anisotropic above the contact structure 87. As a result, as shown in Figure 20E, a shelf 28 which is very small self-aligned on the upper surface of the contact structure 87 is formed, the cross-sectional of the via 55 without substantially increasing the surface, formed after The wiring resistance of the electrical connection between the contact structures 82 and 87 is reduced. A selective sidewall 77 similar to the sidewall 75 as shown in FIG. 8K is also formed before etching the contact 87 (FIG. 20F, left or right) or after etching the contact structure 87 (FIG. 20F, left). It is possible to be done. By selectively forming the side wall 77 after etching the contact structure 87, it protrudes above the exposed side surface 79, complicating the formation of an electrical connection between the exposed side surface 79 and the contact structure 82. Become. This complication is achieved by a method similar to forming an electrical wiring 97 that electrically connects the contact structures 12 and 17 but does not contact the thinned substrate 21 as shown in FIG. It can be avoided by forming an electrical wiring 99 between the exposed side surface 79 and the contact structure 87. Wiring 99 can extend above contact 87 and below any conductive material within 88 or 89.

After the formation of the electrical wiring 99, the substrate portion 89 exposed to the via 55 is covered and a side wall 76 similar to the side wall 70 in FIGS. 8A and 8B is formed as shown in FIG. 20G. It is possible to be done. In FIG. 20G, a side wall having a thickness similar to that of the wiring 99 is provided. Alternatively, a selective side wall similar to the side wall 75 shown in FIG. 8K can be formed as shown in FIG. 20H. The rest of the via 55 can then be embedded with metal or, as described in the preceding embodiment, its interior covered with metal and embedded with an insulator.

These resulting structures also include photolithography-based routing or underbump metal coatings that support wire bonding or flip-chip packaging, as described in the preceding embodiments (but these). Suitable for subsequent steps (but not limited to). The structure shown in FIGS. 20C to 20F may also include a contact structure configured as shown in the die 86.

A sixth embodiment is shown in FIGS. 21A-21E. In these figures, similar to 19, 21, 89, 109, 121 in the preceding embodiments, the entire die substrate portion 127, or almost all of the die substrate portion 127, is a layer, a circuit, or a circuit layer of a device. Can be removed leaving behind. In this embodiment, the substrate 130 has a device region 131 having a contact structure 132. The dies 134-136 each have a device area 138, a contact structure 137, and a substrate portion 127 that is not required for proper operation. The contact 137 has been shown to have an opening in the die 134, and the contact 137 is single in the die 135, with an opening formed therein, as shown in the fifth embodiment. Can be done. The dies 134-136 are adhered to the substrate 130 on the surface 133, as shown in FIG. 21A. The die substrate 127 is completely removed, for example by polishing and / or grinding, exposing the device area 138 as shown in FIG. 21B. Prior to this embodiment, the number of subsequent steps required to etch vias to expose the contact structure and to form electrical wiring between the contact structures is not the substrate portion 127. It is substantially reduced and simplified compared to the morphology.

For example, in FIG. 21C showing only one of the dies 134-136, the step of etching the via 129 to expose the contact structures 132, 137 is simplified. This is because there is no substrate portion 127 for etching vias. Thus, the vias 129 are substantially shallower than the vias shown in the previous embodiment, resulting in a substantial reduction in the cross-sectional area of the vias and a corresponding increase in the via density. In another example, in FIG. 21D, where only one of the dies 134-136 is shown, the step of forming electrical wiring 128 between the exposed contact structures 132, 137 is simplified. This is because there is no substrate portion 127 that creates the need to electrically insulate the electrical wiring 128. FIG. 21E shows this embodiment including a contact structure bonded by direct contact. The structure shown in FIG. 21E may include a contact structure 124 similar to the contact structures 124, 122 shown in FIG. 19C as well as being configured as shown within the die 135.

Examples of applications where all substrates can be removed include some silicon-on insulators, and III-V ICs where the die substrate of the IC is not required for the manufacture of active transistors and other IC devices. Is included.

The resulting structure of the sixth embodiment also includes subsequent routing or underbump metal coatings based on photolithography that support wire bonding or flip chip packaging, as described in the preceding embodiments. Suitable for the process of.

Variants to those shown in FIGS. 21A to 21E include, but are not limited to, those described in the previous embodiments. For example, embedding vias as shown in FIGS. 10 and 14, covering and embedding vias inside them, and forming wiring at the edges of the die contact structure as shown in FIG. Adhering the die to the exposed contact structure of the wafer as shown in FIGS. 17 and 18 or to the exposed contact structure of the die and wafer as shown in FIG. It is also possible to contact the exposed sides of the die contact structure as shown in FIG.

A seventh embodiment of the present invention is shown in FIGS. 22A-22L and 23A-23K. Note that the composition of the surface contact structure is indicated by the die 146. All dies can have the same or different contact structures within one substrate, and as mentioned above, if different contact structures are adhered to the same substrate, certain process modifications may be required. Substrate 140 may include dies such as 144-146 (shown by dashed lines) separated by scribe array 38. Each die 144-146 has a contact structure 147 located in the device area. Note that for the sake of brevity, the contact structure is not shown in actual proportions. The contact structure 147 may be a separate member, or may be a single member and an opening may be formed through the contact structure 147.

The contact structure 147 can be formed by conventional methods of metal deposition and removal or metal deposition and etching. Alternatively, the contact structure 147 can be formed by a combination of patterning and etching an existing conductive layer, or patterning within an opening of the conductive layer and depositing a metal. To form the contact structure 147, it is desirable to continue depositing a flattening layer of insulating material 151 that electrically insulates as well as below the contact structure 147 in the device region 148. A typical flattening material is silicon oxide formed by plasma chemical vapor deposition as shown by layer 151 in FIG. 22A. If surface contacts are desired, as in device 146, layer 151 may not be formed, may not be formed in a predetermined area of substrate 140, or may be removed later.

Vias can be formed within the dies 144-146. The etching of the vias is performed prior to cutting the dies 144-146 into separate dies along the scribe line 38 so that all the vias on all the dies on the wafer can be etched at the same time. It is preferable to etch on a wafer scale. Thus, the dies 144-146 can all be etched at the same time, or at different times if the dies 144-146 are from different wafers. The vias are preferably anisotropically etched for minimum consumption of device region 148 and substrate 140.

Contact structures within dies 144-146 can also be formed as previously described in the fifth embodiment. For example, as shown in FIG. 22B, the flattening material 151 is patterned and etched to form vias 152 that penetrate the flattening material 151 and reach the conductive material 154. Subsequently, the vias penetrating the conductive material 154 are etched to form a contact structure 147 (154) with exposed side surfaces 153. Subsequently, as shown in FIG. 22C, the via 155 is formed by further etching through the device region 148 into the substrate 140. This etching is preferably anisotropic in order to minimize the lateral spread of the via 155. The flattening material 151 is also patterned and etched to expose two shelves 156 as shown in FIG. 22D, or one shelf 160 as shown in FIG. 22E. Via 158 is formed that does not expose the shelves as shown in FIG. 22F. The patterning and etching of the flattening material 151 has an area slightly larger than the openings formed by (or within the contact structure 154) the contact structure 147. As a result, the lower position and lateral extent of the contact structure 147 of the via 156 is provided by the contact structure 147 (154), while the upper upper portion of the contact structure 147 (154) of the via 156 is the lower portion of the via 156. It will be slightly wider. The shelves 160 and sides 153 of the contact structure 147 (154) are exposed, as shown in FIG. 22D. Alternatively, the patterning and etching of the flattening material 151 may overlap the edges of the contact structure 147 (154). As a result, the position and lateral extent of the via 157 is provided by the contact structure 147 (154) and the upper portion of the via 157 is slightly wider than the lower portion. One shelf 160 of contact structures 147, 154, and contact structure 147 (15), as shown in Figure 22E. The side surface 153 of 4) is exposed. Instead of FIGS. 22D and 22E, the patterning and etching of the flattening material 151 does not overlap any portion of the contact structure 147 (154). As a result, as shown in FIG. 22F, the position and lateral extent of the via 158 is not provided by the contact structure 147 (154) and the side surface 153 of the contact structure 147 (154) is not exposed. Note that it is not necessary for every contact in Figure 22E and Figure 22F to have an opening. Subsequent dies 144-146 were glued to surface 143 of substrate 140 as shown in FIG. 22G for via 155 formed as shown in FIG. 22C and contact structure 147 (154). The vias 156, or 157, or 158 are exposed so that the vias 156, 157, and / or 158 are exposed by thinning the substrate 140 of the later carved dies 144 to 146 to form the thinned substrate 161. It is preferable to etch to a sufficient depth.

Etching of vias defined by or within the contact structure 154 to the desired degree isotropic to form a self-aligned shelf 162 on the back surface of the contact structure 147 (154). It is possible to form via 159 as shown in FIG. 22H for via 155 of 22C, or to form via 163 as shown in FIG. 22I for via 156 of FIG. 22D. This isotropic etching may include the device area 148 below the contact structure 147 (154) and the substrate 140 to expose the back surface of the contact structure 147 (154) as shown in FIG. 22H or 22I. It is possible. This isotropic etching can be achieved by changing the etching conditions used to etch via 155 or via 156. For example, if each condition used to etch via 155 or via 156 includes reactive ion etching at low pressure, similar reactive ion etching can be used at high pressure. The amount of pressure increase required to expose the back surface of the contact structure 147 by the desired amount and to form the self-aligned shelves 162 is the thickness of the flattening material 151 and the depth of vias 156, or 157, or 158. It depends on and can be determined experimentally. Alternatively, this isotropic etching can include the substrate 140 but not the device region 148. As a result, as shown in FIG. 22J, the remaining portion of the self-aligned shelf 166 and device area 148 is formed on the back surface of the contact structure 147 (154) and above the via 164. Similar to FIGS. 22H and 22I above, the back surface of the back contact 147 (154) and the remaining portion 165 of the device area 148 above the via 164 forming the self-aligned shelf 166 are the contact structure 147 (154). It is obtained by isotropically etching the desired amount below. In this structure, for example, the remaining part 165 is an insulator, for example, an acid.

As shown in FIG. 22K, after the via formation, the non-selective insulating side wall 170 may be formed as described in the first embodiment and the substrate 140 may later be formed within the via. Electrically insulated from wiring metal. FIG. 22K shows an example in which the via 163 is formed to generate the via 171 with the shelf 172 as shown in FIG. 22I. A selective insulating side wall 173 similar to the side wall 77 described in the first embodiment and shown in FIG. 22L may be formed. After etching the vias, dies 144-146 are cut and optionally glued to the surface 143 of the substrate 140 having the contact structure 142 and the device region 141. Alternatively, the dies 144 to 146 are glued together without being cut. For example, a wafer or die can be glued to the substrate in a single arrangement instead of separate dies. As a result, the surface becomes substantially flat instead of the uneven surface due to the spacing between the dies. The substrate 140 may also include a contact structure, but does not include a device or device area. Substrate 140 is then thinned by at least one of backside grinding, chemical mechanical polishing, or etching, leaving the thinned substrate die 161 as described in FIGS. 22C and in FIGS. 23A-23B. If vias are formed as shown, expose vias, eg via 155. The contact structure 142 can be flat with the adhesive surface as shown in FIG. 23A, or can be retracted relative to the adhesive surface as shown in FIG. 23B. Is. As shown in FIG. 23A, the adhesive surface and flat contact structure 142 deposits a conductive material, such as a copper or nickel plating, on the surface of the substrate 140 and then covers the conductive material. It can be formed by depositing an insulating material in such a manner and then forming the contact structure 142 and the surface 143 by chemical mechanical polishing. The polishing rate of this conductive material is similar to the polishing rate of insulating materials. Is preferable. Similar polishing rates for conductive materials include: conductive material, insulating material, size and shape of conductive material, coverage area of conductive material, polishing parameters including slurry and pad as shown in the fourth embodiment. Can be obtained by properly selecting.

Alternatively, the contact structure 142 retracted relative to the adhesive surface, as shown in FIG. 23B, is formed by depositing an insulating material, eg silicon oxide, followed by selective polishing of the elevated areas. It can be formed by chemical mechanical polishing of an insulating material that flattens the surface. As a result, a flattened thin insulating material is formed on the upper surface of the contact structure 142. Alternatively, the contact structure 142 retracted to surface 143 as shown in FIG. 23B first forms a flattened surface 143 as shown in FIG. 23A, followed by that shown in FIG. 23A. It can be formed by depositing or depositing and polishing a thin layer of insulating material on such a surface 143 to form a surface 143 as shown in FIG. 23B. The contact structure 142 retracted relative to the adhesive surface is formed by patterning and etching, for example, a flattened insulating material, exposing the contact structure 142 by vias 63, as shown in FIG. 23C. Can have exposed surfaces. The dies 144-146 are then glued together and thinned to expose the surface of the contact structure 142, as shown in FIG. 23D. Exposing the contact structures 142 and 147 (154), for example as shown in FIGS. 23A and 23D, facilitates subsequent electrical connections between the contact structures 142 and 147 (154) as described below. It is preferable to make it. The lateral extent of the exposed contact structure 142 is lateral to the via 155, depending on the relative size of the via 63 and the lateral extent of the etched via 155 as shown in FIG. 22C. Less than, greater than, or equal to the directional spread. For example, if the lateral spread of via 155 shown in FIG. 22C is less than the lateral spread of via 63 shown in FIG. 23C, then the lateral spread of the exposed contact structure 142 is Greater than the lateral spread of via 155, as shown in Figure 23D. Or as shown in Figure 23E Thus, the spread of the exposed contact structure 142 is glued and thinned, and the exposed device areas 141, 148 are isotropically etched to the contact structure 142 to expose vias, eg via 155. Can be spread afterwards. Alternatively, the exposed contact structure 142 as shown in FIG. 23C can be protected by a thin layer during the bonding process, which can be detrimental to the contact structure 142. For example, if the contact structure 142 is made of aluminum, the contact structure 142 can be damaged by exposure to an ammonia-based solution used to achieve covalent bonds at room temperature. An example of such a thin layer is silicon oxide, which can be formed by PECVD. Chemical mechanical polishing of this thin layer can also be performed to maintain the desired surface 143 without removing the thin layer from the contact structure 142. This thin layer can then be removed after adhering the dies 144 to 146 to the substrate 140 and thinning the substrate 140 to expose the vias and forming the thinned die substrate 161 and also after the vias are exposed. It is thin and preferably in the range of 0.05 to 0.5 micron for ease of removal.

When the thinned die substrate 161 is non-conductive, the exposed contact structure 142 and contact structure 147 (154) form a conductive material that overlaps the contact structure 142 and contact structure 147 (154). , Can be connected. Alternatively, if the thinned substrate 161 is conductive, for example if the thinned substrate 161 is made of silicon, then the thinned substrate 161 is made from a conductive material that connects the contact structure 142 and the contact structure 147 (154). Insulated side walls that are electrically insulated are preferred. As shown in FIG. 23A and instead of forming a side wall prior to bonding as previously shown in FIG. 22K or FIG. 22L for the via 163 formed as shown in FIG. 22I. Similar to the via 159 formed as shown in FIG. 22H, the insulating non-selective side wall as described in the preceding embodiment, eg, the side wall 70 in FIG. 8A or FIG. 8B, It can be formed after gluing dies 144-146 and subsequently thinning dies 144-146. Thus, when the exposed contact structure 142 is flat with respect to the surface 143, a thin die substrate 161 remains, as shown in FIG. 23F for the side wall 62. As described in the first embodiment, an insulating selective side wall formed after bonding, thinning the substrate and exposing the vias may be used. As described in the preceding embodiments, forming the sidewalls is undesirable and electrically between the thinned die substrate and the electrical wiring between the contact structure 142 and the contact structure 147 (154). It is preferable to avoid conduction.

If there is a side wall on the exposed contact structure 147 (154) and contact structure 142, and the thinned die substrate 161 if desired, the electrical wiring between the contact structure 147 (154) and the contact structure 142 , Can be formed by forming a conductive material covering the exposed surface of the contact structures 142, 147 (154). Typical conductive materials are metals, typical metals are aluminum, copper, nickel and gold. These metals can be formed in a variety of ways as described in the previous embodiments. As a result of this formation, the exposed thinned die substrate 161 is covered with the conductive material 52, as shown in FIG. 23G. This coating is self-aligned and the thinned die substrate 161 covered with the conductive material 52 until the conductive material 52 is removed from the thinned die substrate 161 as shown in FIG. 23H. Can be removed by polishing the surface of the surface without the use of photolithographic patterning and etching. If there is a remaining portion 165 of device area 148 with self-aligned shelves 166 as shown in FIG. 22J, then a structure similar to that shown in FIG. 23I is exposed contact structure 142. Is flat with structure 143 as shown in FIG. 23A, the dies 144 to 146 are glued to the substrate 140 and the substrate 140 is thinned to expose the vias 164 and form the thinned substrate 161. Is formed after Next, preferably, the remaining portion 165 is removed by anisotropic etching and the self-aligned shelves are rearranged relative to the back surface of the contact structure 147 (154), resulting in the self-aligned shelves 167. Is shown in Figure 23J.

Then, if desired, a conductive material is formed to form a contact structure 147 without the formation of an electrical connection to the thinned substrate 161 as shown in FIGS. 23F, 23G, and 23H. Is connected to the contact structure 142. As already described, the formation of the wiring metal can be done by one or a combination of electron beam, heat treatment, physical vapor deposition, chemical vapor deposition, electroplating. The wiring metal formed can be one or a combination of titanium, tungsten, gold, copper and aluminum.

After the contact structures 142, 147 (154) are electrically connected to the conductive material, the vias are a combination of metal coating, insulation deposition, and chemical mechanical polishing as described in the previous embodiment. Is embedded and flattened. After the vias have been embedded and flattened, underbump metal coating, bump formation, dicing, and flip-chip packaging can be performed as described in the preceding embodiments. It should be noted that although FIGS. 23F-23J show the surface contact 142, this contact may be retracted as shown in FIG. 23B. Dies with surface contact structures may be glued, configured and / connected as shown in FIGS. 23F-23J. FIG. 23K shows the case of FIG. 23H.

Further, the vias in this embodiment (for example, FIGS. 22C to 22F, 22H to 22L) are prior to cutting so that the conductive material is exposed when the cut portion of the substrate 140 is thinned. Can be embedded by the conductive material 168. Insulating materials for electrical insulation can optionally be formed on the sidewalls of the vias, as described above. The via-embedded die (or wafer) is then placed on the exposed surface of the die (or wafer) device area 148 (ie, die down) as described in the ninth embodiment below. ) Can be glued or glued (ie, die-up) to the opposite surface of the exposed device region 148 as described in the tenth embodiment below. This adhesion is described in the fourth embodiment using the contact structure 147, and the die down is shown on the left side of FIG. 23L and is described in more detail in the ninth embodiment described below. Or as described in the middle structure of FIG. 23L for a die-up in which the conductive material 168 is connected to the contact structure 142 and as described in more detail in a tenth embodiment below, or The die-up in which the contact structure 179 is formed in the same manner as the formation of the contact structure 147 as described in the fourth embodiment is shown on the right side of FIG. 23L and is described in the tenth embodiment described later. It can be performed as described in detail. If desired, the insulating material 169 can be formed on the substrate portion 161 and can be polished as it is necessary for adhesion to the substrate 140. Vias can be embedded with various conductive materials or combinations thereof. Such conductive materials include, but are not limited to, polysilicon or various metals such as tungsten, nickel and copper, which are chemical vapor deposition, physical vapor deposition, electroplating. Accumulated in a variety of ways, including but not limited to .. The conductive material can be selected to promote good electrical contact, low electrical resistance, high thermal conductivity with the contact structure to which the conductive material is bonded, and the barrier layer of the insulating material or via on the via side wall. It can be insulated from the outer substrate. The barrier layer is, for example, titanium nitride or tungsten nitride, which, if necessary, to prevent the conductive material from diffusing into the outer substrate of the via, eg, metal-organic vapor deposition or physical vapor deposition. It is deposited by the phase growth method. For example, if a silicon-based IC is manufactured and the vias are etched into the silicon, copper is preferred due to its low resistance. However, typically copper is a suitable via insulating layer, typically a suitable barrier layer between silicon oxides, typically titanium nitride, to prevent copper from diffusing into the silicon. Or require tungsten nitride. Alternatively, if desired, another metal, such as tungsten, may be used in conjunction with the insulating or barrier layer. Further, if necessary, it is advantageous that a material having excellent polishing properties, for example nickel, is used together with an insulating layer or a barrier layer, as described above. Ten may be used with an insulating layer or a barrier layer. Further, if necessary, it is advantageous that a material having excellent polishing properties, for example nickel, is used together with an insulating layer or a barrier layer, as described above. Ten may be used with an insulating layer or a barrier layer. Further, if necessary, it is advantageous that a material having excellent polishing properties, for example nickel, is used together with an insulating layer or a barrier layer, as described above.

The eighth embodiment is shown in FIGS. 24A to 24B. This embodiment is similar to the seventh embodiment in that the opposite side of the dies 144 to 146, for example a thinned die substrate, 161 is adhered to the surface 143 of the substrate 140 after thinning the die substrate to expose vias. different. As a result, the thinned die substrate 161 was adhered to the surface 143 and for the via 155 formed as shown in FIG. 22C against the surface 143 as shown in FIG. 24A and in FIG. 23A. Via 139 is exposed to the contact structure 142 formed as shown in. Thinned substrate 161, for example, silicon is bonded directly to surface 143 of substrate 140, or insulator, eg silicon oxide, is thinned prior to direct bonding to surface 143 of substrate 140. It can be formed on 161. The formation of the thinned substrate 161 cuts dies 144-146 into separate dies so that all vias on all dies on the wafer, eg, via 155 shown in FIG. 22C, are exposed simultaneously. It is preferable that this is done on a wafer scale prior to the above. Thus, dies 144-146 can be exposed at all vias at the same time, or at different times if dies 144-146 are from different wafers.

By forming a thinned substrate 161 from the substrate 140 in FIG. 22C, for example, mechanical integrity can be compromised if the vias are not deep enough. For example, for a thin substrate of 200 nm in diameter made of silicon, vias with a depth of about 0.1 to less than 0.3 mm are typically sufficient. The depth of vias at which mechanical integrity is compromised is greater for thinner substrates with larger diameters and smaller for thinner substrates with smaller diameters. This loss of mechanical integrity thins the substrate 140, as shown in FIG. 24B for the via 155 and contact structure 147 (154) formed as shown in FIG. 22C. Previously, it can be avoided by attaching the opposite side of the exposed surface of the substrate 140 to the substrate on the handle wafer 44. The handle wafer 44 can be attached by a variety of bonding methods, including direct bonding or adhesive bonding. The opposite side of the exposed surface of the substrate 140 is attached to the handle wafer 44, the substrate 140 is thinned to form a thinned substrate 161 and the via 155 is exposed, and then the thinned substrate 161 is adhered. It can be used as a surface or an insulator, eg silicon oxide, can be deposited as an adhesive layer as described above. After the formation of the preferred bonding surface, the dies 144 to 146 are carved and bonded to the surface 143 of the substrate 140, and the carved portion of the handle wafer 44 is removed. Separation can be done by at least one of dicing or scribing. Removal of the carved portion of the handle wafer 44 can be done by at least one or a combination of grinding, chemical mechanical polishing, or etching.

A contact structure 147 (154) is formed within the dies 144-146 as described in the seventh embodiment prior to forming the substrate 161 thinned by adhering to and thinning the handle wafer 44. It is possible to be done. However, forming a shelf on the contact structure 147 to improve the resistance of the electrical wiring between the conductive material 52 and the contact structure 147 is described in the seventh embodiment and is described in FIGS. 23F and 23G. On the opposite side of the contact structure 147 shown in. Therefore, this shelf etches the device area 148 above the contact structure 147 by more than the opening of the contact structure 147 to produce vias similar to those shown for vias 156 and contact structure 147 in FIG. 22D. It can be formed by forming.

In addition, side walls can be formed within the vias prior to forming the substrate 125, which has been thinned by adhering to and thinning the handle wafer 44. This side wall is either non-selective as shown in FIG. 22K for the non-selective side wall 170 and via 163, or is shown in FIG. 22L for the selective side wall 173 and via 163. It can be as selective as. Alternatively, selective or non-selective sidewalls can be formed after bonding the dies 144-146 as described in the previous embodiment.

Adhesion of dies 144 to 146 to substrate 140 is a layer that is flat with or recessed from the adhesive surface and is exposed or thin, as described in the seventh embodiment. It can be made with the contact structure 142 protected by. After bonding the dies 144 to 146, and after removing the carved portion of the handle wafer 44 if it is used, and after removing it if a thin protective layer is used, the contact structure 142 is 7 Exposed as shown in FIG. 23A or FIG. 23D in the embodiment. Next, a conductive material is formed and the exposed contact structures 142, 147 are electrically connected, for example, as in FIGS. 23G and 23H in the seventh embodiment. By forming this conductive material, the vias can be partially or completely embedded. If the conductive material that electrically connects the exposed contact structures 142, 147 (154) partially embeds the vias, the rest of the vias are metal as described in the previous embodiment. It can be embedded and flattened by a combination of coatings, insulation deposits and chemical mechanical polishing. After the vias have been embedded and flattened, underbump metal coating, bumping, dicing, and flip-chip packaging can be performed as described in the previous embodiments.

The ninth embodiment is similar to the fourth embodiment in terms of bonding and electrical connection, and is similar to the seventh embodiment in that a via is formed through the die prior to bonding and exposure by thinning after bonding. Is also possible. This embodiment begins as described in the seventh embodiment, and as described in the fourth embodiment, an adhesive surface comprising contact structures 123, 122 is prepared, adhered, and electrically. Continue to carving and gluing of dies 114-116 (or wafers), except that they are connected to. After bonding, the dies 114-116 are thinned as described in the seventh embodiment to expose the vias within the dies 114-116 and are embedded with metal as described in the previous embodiment. The appearance of the final structure is similar to FIG. 19A when the vias are embedded and the contact structure has openings.

In the variant of the ninth embodiment, the formation of vias before bonding is reinforced by metal embedding as described in the seventh embodiment. For example, the vias in dies 114-116 are formed prior to bonding, as shown in FIGS. 22D, 22E, 22F for vias 156, 157, 158. If part of the die substrate and the device area of the die is conductive, then on the conductive portion of the etched via sidewalls, an electrically insulating sidewall, eg, substrate 140 as shown in FIG. 22L and It is preferred that a side wall 173 within the via 163 on the device area 148 be formed. This side wall may be formed on the entire side wall, or on the non-contact portion of the side wall as shown in FIG. 22K, or within the bottom of the via. After the vias are properly electrically insulated from the die substrate and device area, the vias can be made of conductive material, such as by metal, as shown in FIG. 10B with a flattened metal structure 100. It is embedded by a combination of conductive and insulating materials as shown in FIG. 10C with a metal inner coating or barrier layer 93 and insulator 94. Embedding vias, for example with metal or metal and insulators, can be done by many techniques as described in the previous embodiments.

Instead of etching and embedding vias that penetrate the device area of the die and part of the die substrate, the vias are only part of the die substrate or the device of the die prior to device formation or completion of the die device area. It is possible to etch or etch and embed part of the area and part of the die substrate. For example, as shown in FIG. 25A, the vias penetrate into the die substrate 140 and through the device region 171 of the die, eg, conductive materials such as metals (not shown) and silicon oxide or other suitable. The device region remaining in the substrate or through the semiconductor portion of the device region consisting of a semiconductor transistor made of an insulator made of various materials and a layer of a multilayer wiring structure is etched. If the device region 171 and die substrate 140 of the die are made of a conductive material, eg a semiconductor material with sufficiently low resistance, eg silicon used in typical CMOS wafer formation, then the sidewalls of this embodiment and earlier It is formed as shown in FIG. 25B for a selective sidewall 173 that is also formed on the bottom of the via 172 as described in the embodiment and as described in the previous embodiment. Is preferable. In addition, if the structure shown in FIG. 25A is composed of silicon, a very thin, eg 5-50 nm high quality selective silicon oxide side wall is thermally grown and beside the via 172. 100,000, per square centimeter, facilitating directional dimensions to be substantially less than 1 micron Allows the formation of vias with very high areal densities in excess of 000. Alternatively, the non-selective side wall can be formed on the side wall of the via 172 without being formed on the bottom of the via 172 as described in the previous embodiment. The via 172 is then lined with a suitable barrier layer, if necessary, and embedded with a conductive material 174 to form a metal-embedded via as described above. The via 172 may be embedded with conductive polysilicon. The contact structure 123 can come into contact with the embedded vias, as shown in FIG. 25D.

Alternatively, prior to the formation of the contact structure 123, further processing was performed on the structure of FIG. 25C to complete the production of the die device area 148 as shown in FIG. 25E, followed by the die device area 148. A contact structure 123 can be formed on top. For example, the multilayer wiring structure can be composed of a conductive material, for example, a metal, and an insulating material, for example, similar to or the same as a typical CMOS wafer manufacturing. Typical metals include copper and aluminum, and typical insulating materials include silicon oxide and low dielectric constant insulators. Contact structures 123 within dies 114-116 can be formed as described in the fourth embodiment and as shown in FIG. 25E. The device region 148 may include forming a conductive material 176 to electrically connect the contact structure 123 to a metal-embedded via 174. The conductive material 176 is shown in FIG. 25E to be perpendicular between the conductive material 174 and the contact structure 123, but is a typical inter-layer metal in the formation of integrated circuits, eg CMOS wafer manufacturing. It may contain a lateral component or may be a completely lateral component, as provided by the routing of the. See FIG. 25F with conductive material 178.

Thus, an electrical connection from the metal-embedded via 174 to the contact structure 123 can be provided using the wiring structure of the integrated circuit, eg, as in typical CMOS wafer manufacturing. Thus, the need to modify the design rules of the wiring structure to achieve electrical connectivity is minimized or eliminated, resulting in improved existing manufacturing capacity scaling and means. It should be noted that while the conductive material 176 may contain or consist primarily of lateral components, the via 172 does not require a lateral component. For example, if the via 172 is within the device region 148 of the die, eg, the device region 171 of the die, and the conductive material 176 is made of an interlayer metal typically used in the manufacture of integrated circuits, the via 172 is conductive. Manufactured according to design rules that are generally independent of the production of the conductive material 176, except that it is placed vertically from the conductive material 176 and that the conductive material 176 is in electrical contact with the metal-embedded vias 174. Can be done. Moreover, the via 172 in this example is substantially shorter than that previously described in this embodiment, for example, where the via 155 extends through the entire device region 148 of the die. Shorter vias 172 allow for smaller lateral dimensions of vias 172, eg, substantially less than 1 micron, and very high areal densities, eg, more than 100,000,000 vias per square centimeter. As a result, scaling is improved. Note that within the device 146, an insulating side wall film 177 and an insulating surface film 180 are included when it is necessary to insulate the conductive material 176 from another surface contact.

In this variant, thinning after bonding exposes metal-embedded vias instead of metal-impregnated vias, for example, as shown on the left side of FIG. 23L. In any variant, the substrate portion of the die can be completely removed as described in the sixth embodiment. Also, any variant can adhere to a substrate that does not have a device area but has a contact structure as described in the fourth embodiment, eg, chip-to-package in a ball grid array IC package. -It can also be used as a substitute for the interposer board.

Moreover, in any variant, the exposed surface may include vias embedded in metal. This surface, if necessary, uses an embedding material for flattening the surface as described in the first embodiment and via exposure and contact structure formation as described in the tenth embodiment. It can be properly prepared for bonding with electrical connections as described in the fourth embodiment. Further dies from the same or different wafers with exposed contact structures are then bonded to a post-bonded thinned surface with exposed contact structures as described in the fourth embodiment. It is possible. Alternatively, an underbump metal coating can be formed so that flip-chip packaging can be implemented as described in the previous embodiment. This is shown in FIGS. 23M and 23N. In these figures, the second die is glued to the first die. Many combinations are possible when connecting conductive materials and / or contacts of one die to another using the configurations described above or below. Figure 23M shows three examples. In FIG. 23M, in the die 181 the conductive material 168 is connected to the conductive material 168 of the lower die using a contact structure 179, and in the die 182 the contact 147 (154) is the contact of the lower die. Connected to the 147 and the conductive material 168, the die 183 has the contact 147 and the conductive material 168 connected to the contact 147 and the conductive material 168 of the lower die.

In FIG. 23N, the structure on the left has two dies glued together in a die-down configuration. The middle structure has a substrate 149 with contact structure 142, eg an interposer, and a die with contact structure 147 (154) bonded to it. The contact structure 147 (154) and the conductive material 168 are connected via a conductive material 187 formed after bonding. The structure on the right has a conductive material 187 that connects the conductive material 168 and the contact structure 154 in the substrate 149.

As described above, the method according to the present invention can be applied to wafer-to-wafer adhesion. In FIG. 23O, an upper substrate 140 having a plurality of contact structures 147 and a conductive material 168, such as the die on the left side of FIG. 23L, is adhered to the lower substrate 140 to form a connection with the contact structure 142, respectively. It shows that it is. A die or another wafer can be glued to wafer 149 using the configurations described above and below. Any number of wafers and dies can be glued and connected.

A tenth embodiment similar to the eighth embodiment is also possible with respect to the bonding and electrical connection as in the ninth embodiment, with respect to the orientation of the bonding surfaces of the dies 144 to 146 and any additional usage of the handle wafer. , Shown in Figure 26A. This embodiment begins as described in a ninth embodiment in which the vias are etched, insulated if necessary, and embedded with a conductive material, eg, as shown in FIG. 25C. As mentioned above, vias can be embedded with a variety of conductive materials. This conductive material includes polysilicon or eg tungsten or copper deposited by various methods including, but not limited to, chemical vapor deposition, with insulating and barrier layers if desired. Various metals are included, not limited to these. The die (or wafer) substrate, eg 140 in FIG. 25F, is then thinned and embedded in a conductive material, optionally using a handle wafer as described in the eighth embodiment. The via, for example, 174 in Fig. 25F is exposed. The exposure of vias can be done by a combination of backside grinding, CMP, and etching. This exposure can preferably result in a flat surface, or the CMP or etching selectivity of the substrate can result in a non-flat surface. For example, silicon is removed during CMP processing at a lower rate than copper, resulting in the retraction of conductive vias as described in the fourth embodiment, or even below the surface of the silicon substrate. It will be dented. Alternatively, the vias are exposed, or the exposed vias are etched by selective etching, which preferentially etches the substrate against the conductive vias so that the conductive vias extend over the surface of the silicon substrate. obtain. For example, silicon is SF₆Reactive ion etching based on can be used to preferentially etch copper or vias with embedded vias. As described in the eighth embodiment, if exposing the vias embedded in the conductor results in a properly adhereable surface as described in the fourth embodiment. The die can be carved and glued together.

If exposing the conductor-embedded vias does not result in a properly adhereable surface as described in the fourth embodiment, contact as described in the fourth embodiment. Structures can be formed to form suitable surfaces. For example, if the embedding of exposed conductive vias is below the adhesive surface, a contact structure 179 is formed on the conductive material 174 in a manner similar to that described in the fourth embodiment. obtain. Such formation involves depositing contact structures and insulators, such as silicon oxide, followed by polishing, resulting in the adhesive surface being adequately flat and electrically insulated except for the contact structure. It becomes. This is shown in FIG. 26B with a contact structure 179 formed in contact with the conductive material 174 and an insulating film 169 such as PECVD silicon oxide.

Alternatively, the process may include depositing and polishing the contacts with or without insulation. As a result, the adhesive surface is properly flattened with the contact structure and is composed of a substrate, for example, the substrate 140 of FIG. 25F. Further, if the exposed conductive embedding is higher than the adhesive surface, a contact structure may be formed on the conductive material 174 in a manner similar to that described in the fourth embodiment. This formation may include depositing and polishing contact structures and insulators, such as silicon oxide. As a result, except for the contact structure 179, the adhesive surface is properly flattened and electrically insulated. The contact structure 179 can be formed to the same extent as, smaller than, or larger than the conductive material 174.

The dies are then cut and glued as shown in the eighth embodiment. Thus, the dies 144 to 146 are bonded to the substrate 140 by pre-bonding vias formed and embedded as described in the ninth embodiment, and if necessary, a bonding surface including a contact structure is provided. Prepared, glued and electrically connected as described in embodiments. After bonding the dies 144 to 146 to the substrate 140, the dies 144 to 146 do not need to be electrically connected to the contact structure 142, and the exposed surface of the dies 1114 to 116 is the earlier embodiment. Available for underbump metal coatings in preparation for flip lip packaging as described in.

In a tenth embodiment, vias can be formed through the entire device region 148 or through the semiconductor portion of the device region 148 as shown in the ninth embodiment. By forming vias within the semiconductor region of device region 148, as in the ninth embodiment, deeper and wider vias due to forming vias prior to completion of the device region are avoided. This improves device density and reduces the portion consumed as a result of semiconductor via formation. As a result, scaling is improved. In addition, the die substrate portion can be completely removed as described in the sixth embodiment. In addition, the exposed surface may have a contact structure. This surface, if necessary, was accompanied by electrical connections as described in the fourth embodiment, using an implant material for flattening the surface as described in the first embodiment. Can be properly prepared for adhesion. An additional die from the same or different wafers with vias embedded in exposed metal is then bonded to a post-bonded surface with a suitable contact structure as described in the fourth embodiment. Is possible. Alternatively, an underbump metal coating may be formed in preparation for the possibility of flip-chip packaging as described in the previous embodiment. The tenth embodiment may also be performed to stack a plurality of dies as in FIG. 23M or in a wafer-to-wafer format as in FIG. 23N.

A desirable feature of the present invention is directed to vertical stacking and connection configurations. For example, the dies can be glued with the IC side down or the IC side up. Further, in the die-to-wafer format and the wafer-to-wafer format, it is possible to bond the upper wafer with the IC side up or down to the lower wafer with the IC side up. In addition, these die-to-wafer and wafer-to-wafer formats can be used with ICs manufactured using substrates that do not require a substrate for IC functionality. For example, ICs manufactured using silicon-on-insulator (SOI) substrates or non-silicon substrates such as III / V materials, SiC, sapphire, etc. do not require the presence of a substrate for IC function. In these cases, all parts not needed for the manufacture of transistors on the substrate can be removed and the etching of vias required to form the vertical electrical wiring can be minimized.

Although it has been shown that the substrate comprises a device region, a substrate having a contact structure without a device region may also be, for example, a chip-to-package interposer substrate in a ball grid array IC package. It is possible as an alternative. Also, it has been shown that the die has a device, but another die or element that does not have a device or has a device but has a contact structure, using the method according to the present invention. , Can be adhered to the substrate.

Many modifications and variants of the present invention are possible in the light of the above techniques. Therefore, it should be understood that, within the scope of the appended claims, it may be practiced in a manner different from that specifically described herein.