Storage device and computing system including the same, and data transfer method thereof

The present invention relates to a storage device, a computing system including the storage device, and the data transfer method.

In recent years, solid state drives (SSDs) are widely used as storage devices for computing systems. SSD uses non-volatile memory such as flash memory to store data, and has better characteristics in terms of durability, size, power consumption, etc. compared to conventional HDD (hard disk drive). There is. SSDs are classified into PCI (peripheral component interconnect) SSDs and SATA (serial advanced technology attachment) SSDs according to the communication method with the host.

<p><patcit num="1"><text>U.S. Pat. No. 8055816</text></patcit></p>

<p> The present invention provides a storage device capable of bidirectional data transfer. The present invention provides a storage device including a host buffer adapter.</p>

<p> In the embodiment of the present invention, the data transfer method of the storage device including the host bus adapter that communicates with the external host via the first interface and internally communicates via the second interface is to the host bus adapter. In response to the write command and the read command, the first interface is used to execute the read direct memory access operation, and the first interface is used in response to the read command. The first interface includes a step of executing a write direct memory access operation and a step of generating a sequence of frame information structures by the second interface in response to the write command and the read command, and the first interface is bidirectional data. The transfer is performed and the second interface performs a unidirectional data transfer.</p><p> A computing system comprising a central processing device, a main memory, and a storage device including a host buffer adapter that communicates with the central processing device via the first interface and internally via the second interface according to an embodiment of the present invention. The data transfer method responds to the information at the stage of transmitting the command queue corresponding to the input / output request to the main memory, the stage of transmitting the information requested for input / output to the main memory to the host buffer adapter, and the stage of transmitting the information. The main memory and the storage device are fetched by transferring the frame information structure corresponding to the input / output request to the main memory, and the main memory and the storage device by the first interface in response to the input / output request. A step of transferring data between the data, a step of generating a sequence of frame information structures by the second interface after the data transfer, a step of generating an interrupt from the storage device, and a step of generating the interrupt from the central processing device. It includes a step of completing the input / output request based on the interrupt.</p><p> The storage device according to the embodiment of the present invention includes a first interface circuit that communicates with the outside according to the first interface, a host bus adapter that communicates with the first interface circuit and the first interface, and the host bus adapter and the first. Output from the second interface emulator, a second interface emulator that communicates by two interfaces, a direct memory access circuit for executing data transfer to an external host memory, at least one non-volatile memory device that stores data, and the second interface emulator. The direct memory access circuit includes a memory controller that controls at least one non-volatile memory device according to the input / output request, so that the direct memory access circuit executes bidirectional data transfer from the first interface circuit at the time of the data transfer. It is configured, and after the data transfer, a sequence of frame information structures by the second interface is generated.</p><p> The computing system according to the embodiment of the present invention includes a host bus, a host processor connected to the host bus via a first interface, a host memory connected to the host processor, and the first host bus. Connected via an interface, RAID (redundant array of independent) A RAID controller for performing a (disks) function and a plurality of storage devices connected to the RAID controller via the first interface, at least one of the plurality of storage devices by the first interface. A first interface circuit that transmits and receives data, a host bus adapter that communicates with the first interface circuit and the first interface, a second interface emulator that communicates with the host bus adapter and the second interface, and the host memory. A direct memory access circuit for executing data transfer, at least one non-volatile memory device for storing data, and the at least one non-volatile memory device in response to an input / output request output from the second interface emulator. The direct memory access circuit is embodied to execute bidirectional data transfer from the first interface circuit at the time of the data transfer, and the frame information structure by the second interface after the data transfer. Sequence is generated.</p>

<p> By providing the driver of the host bus adapter, the storage device according to the embodiment of the present invention can maintain compatibility as compared with the conventional one. Further, the storage device according to the embodiment of the present invention can maximize the efficiency of data transfer by performing bidirectional data transfer.</p>

<figref num="1">The block diagram which shows 1st Embodiment of the computing system by this invention.</figref><figref num="2">The figure which shows schematic the flow of data between a host and a storage device by embodiment of this invention.</figref><figref num="3">The flowchart which illustrates the bidirectional data transfer shown in FIG.</figref><figref num="4">The flowchart which shows exemplary the data transfer method by this invention.</figref><figref num="5">The block diagram which shows the 2nd Embodiment of the computing system by this invention.</figref><figref num="6">The block diagram which shows the 3rd Embodiment of the computing system by this invention.</figref><figref num="7">The block diagram which shows the 4th Embodiment of the computing system by this invention.</figref><figref num="8">The block diagram which shows the 5th Embodiment of the computing system by this invention.</figref><figref num="9">The block diagram which shows the 6th Embodiment of the computing system by this invention.</figref><figref num="10">The figure which shows the computing system from the viewpoint of the input / output request by embodiment of this invention.</figref><figref num="11">The figure which shows the PCI header of the SSD controller including the AHCI controller illustrated in FIG. 10 exemplary.</figref><figref num="12">The figure which shows typically the control information of the host stored in the AHCI engine illustrated in FIG.</figref><figref num="13">The figure which shows the information of the port stored in the AHCI engine illustrated in FIG. 10 exemplary.</figref><figref num="14A">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="14B">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="14C">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="14D">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="14E">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="14F">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="14G">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="14H">The figure which illustrates the regulation of FIS which is transmitted and received between the AHCI engine and the SATA emulator illustrated in FIG.</figref><figref num="15">The figure which shows typically the structure of the host buffer of the main memory illustrated in FIG.</figref><figref num="16">The figure which shows typically the structure of the command list illustrated in FIG.</figref><figref num="17">The figure which shows the command table illustrated in FIG. 16 exemplarily.</figref><figref num="18">The figure which shows the Received FIS structure illustrated in FIG. 15 exemplarily.</figref><figref num="19">The figure which illustrates the process of executing a read command in the computing system illustrated in FIG.</figref>

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that a person having ordinary knowledge in the technical field to which the present invention belongs can easily carry out the technical idea of the present invention. FIG. 1 is a block diagram showing a first embodiment of the computing system 1000 according to the present invention. Referring to FIG. 1, the computing system 1000 comprises a host bus 1001, at least one host processor 1100, at least one host memory 1200 and a storage device 1300. Hereinafter, the host bus 1001, the host processor 1100, and the host memory 1200 will be referred to as a host.

The host bus 1001 can transfer data by the first interface (1st interface) between the components of the computing system 1000 (eg, the processor 1100 and the storage device 1300). Here, the first interface is capable of bidirectional data transfer (full duplex, in other terms, "full duplex"). That is, the first interface provides a transmit channel (Tx) and a receive channel (Rx) that can be used individually. For example, the first interface is FC (fiber channel), USB (universal serial bus) 3.0, SAS (serial attached SCSI), PCIe (peripheral component interconnect express), SPI (serial peripheral interface), Thunderbolt interface (thunderbolt interface). , Lightning bolt interface, etc.

The host processor 1100 controls all operations of the computing system 1000. The host processor 1100 includes a first interface circuit 1110. The first interface circuit 1110 is connected to the host bus 1001 by the first interface. The host processor 1100 is not shown, but includes a memory controller for controlling the host memory 1200. The host memory 1200 is connected to the host processor 1100 and can store necessary data during operation under the control of the host processor 1100. The host memory 1200 can consist of a non-volatile memory device such as DRAM or a non-volatile memory device such as PRAM.

The storage device 1300 is connected to the host bus 1001 by the first interface and stores data. The storage device 1300 communicates with the external host processor 1100 by the first interface, and communicates internally by the second interface. Here, unlike the first interface, the second interface performs unidirectional data transfer (half duplex) without performing bidirectional data transfer (full duplex). For example, the second interface includes an ATA interface and a SATA interface.

Storage 1300 includes first interface circuit 1310 (in other terms, "external interface circuit"), host bus adapter 1320, second interface emulator 1330 (in other terms, "internal interface circuit"), direct memory access (direct). It comprises a memory access (DMA) circuit 1340, at least one non-volatile memory device 1350 and a memory controller 1360.

The first interface circuit 1310 is connected to the host bus 1001 and communicates with the outside by the first interface. The host bus adapter 1320 communicates with the first interface circuit 1310 by the first interface. The host bus adapter 1320 consists of hardware and / or software configured to allow the storage device 1300 to detect at least one command output from the host processor 1100. In the embodiment, the host bus adapter 1320 is composed of AHCI (advanced host controller interface).

The second interface emulator 1330 communicates with the host bus adapter 1320 via the second interface. The second interface emulator 1330 provides a second interface emulation for the storage device 1300. For example, the second interface emulator 1330 is configured to communicate with the host bus adapter 1320 using the frame information structure (FIS) of the second interface. Therefore, FIS is a data packet specified by the second interface. The second interface emulator 1330 can process FIS transactions from / to memory controller 1360, and can process FIS on the host via the host bus adapter 1320.

The DMA circuit 1340 controls the first interface circuit 1310 based on the NCQ (native command queuing) command (write command, read command) input from the host processor 1100, so that the storage device 1300 reads data into the host memory 1200. Or it is configured to be writable.

The DMA circuit 1340 is a transmit DMA circuit (not shown) and a receive DMA for executing bidirectional data transfer using the transmit channel (TX) and the receive channel (RX) of the host bus 1001. It has a circuit (not shown). At least one non-volatile memory device 1350 is a device for storing data as a flash memory (for example, NAND flash memory), PRAM (phase-change RAM), MRAM (magnetic RAM), RRAM (registered trademark) (Resistive RAM) , FRAM (registered trademark) (ferroelectric RAM), VNAND (vertical NAND), etc. The memory controller 1360 controls the non-volatile memory device 1350 by the FIS transaction output from the second interface emulator 1330.

In general, a storage device that supports a second interface (eg, an interface that transfers unidirectional data) cannot transfer data in both directions. However, the computing system 1000 according to the embodiment of the present invention utilizes the host bus adapter 1320 in which the storage device 1300 supports the first interface (for example, the interface for transferring bidirectional data) and the FIS of the second interface. By providing a second interface emulator 1330 that communicates with the adapter, data can be transferred internally by the second interface and bidirectional data can be transferred from the outside by the first interface. That is, the computing system 1000 according to the present invention can satisfy the condition of the second interface and can double the data transfer speed.

Further, the computing system 1000 according to the embodiment of the present invention includes a storage device 1300 having a host bus adapter 1320 that supports the first interface, so that a host driver (host) for the storage device 1300 is provided as compared with the conventional one. There is no need to develop driver) separately. That is, the host processor 1100 according to the embodiment of the present invention can drive the storage device 1300 of the present invention by using a conventional host driver.

FIG. 2 is a diagram schematically showing the flow of data between the host and the storage device according to the embodiment of the present invention. With reference to FIGS. 1 and 2, the data flow is as follows. The host processor 1100 first determines whether it can execute NCQ commands (write or read commands, CMD) for data transfer to storage 1300. To do this, the host processor 1100 reads the registers of the host bus adapter 1320 to verify that the previous command (prior CMD) has completed (S11). If the previous command (prior) is the result of reading the registers of the host bus adapter 1320 When CMD) is complete, the host processor 1100 issues a command (CMD) to host memory 1200 (S12). After this, the host processor 1100 sends a command FIS (CMDFIS) notifying that the command (CMD) of the host memory 1200 has been issued to the host bus adapter 1320 (S13). After that, the second interface emulator 1330 fetches the command (CMD Fetching) by storing the command FIS related information (for example, command type, address, data, etc.) in the host memory 1200 (S14). As a result, the host memory 1200 sets an area in which data can be transferred to the storage device 1300.

After that, a read command or a write command (CMD) is used to transfer data between the host memory 1200 and the storage device 1300 while satisfying the provisions of the second interface. Here, the data transfer is a bidirectional data transfer. That is, bidirectional data transfer is executed by the read command and write command input at the same time, or bidirectional data transfer is executed in a state where the read command and the write command are mixed (S15). When the data transfer is complete, the host bus adapter 1320 sends an interrupt to the host memory 1200 (S16). After that, the host processor 1100 transmits the completion of the operation according to the command (CMD), that is, the information of the command completion to the host memory 1200 (S17). The computing system 1000 according to the present invention can perform bidirectional data transfer by NCQ command (CMD).

FIG. 3 is a flowchart illustrating bidirectional data transfer illustrated in FIG. With reference to Figure 3, bidirectional data transfer is as follows: The transmit DMA circuit of the DMA circuit 1340 receives the write data (Write Data) from the host memory 1200 using the transmit channel (TX) of the host bus 1001 by the write command (Write CMD), and the receive DMA circuit of the DMA circuit 1340. Uses a read command (Read CMD) to transfer read data (Read Data) to host memory 1200 using the receive channel (RX) on host bus 1001 (S21). That is, the transfer of write data (Write Data) and read data (Read Data) is processed in parallel.

When the transmission of write data (Write Data) is completed via the transmission channel (TX) of the host bus 1001, the write data FIS (Write Data FIS:) according to the specifications of the second interface is completed. DMA Setup FIS, Non-Data FIS, SDB (set device bits) FIS) are sent to host memory 1200 (S22, S23, S24). Here, the DMA Setup FIS contains information that configures the DMA circuit 1340 (see Figure 1) to transmit data, the Non-Data FIS contains information that does not have data, and the SDBFIS contains data transmission complete or transmission status. Contains information about. Here, the Non-Data FIS is generated from the host memory 1200 and transmitted to the storage device 1300. Although not shown, the Data FIS contains only the headers generated from the second interface emulator 1330 (see Figure 1) to meet the transfer requirements of the second interface, and the generated Data FIS is the host bus adapter 1320 (see Figure 1). Used for emulation of the second interface (see Figure 1).

When the transfer of read data (Read Data) is completed via the receive channel (RX) of the host bus 1001, the read data FIS (Read Data FIS: DMA Setup FIS, Non-Data FIS, SDBFIS) specified by the second interface is completed. ) Is transferred to the host memory 1200 (S25, S26, S27). Here, the DMA Setup FIS contains information on whether to use the DMA circuit 1340 (see Figure 1) to receive the data, the Non-Data FIS contains the information that no data exists, and the SDBFIS contains the data reception. Contains complete or received status information.

In the embodiment, the write data FIS (Write Data FIS) and the read data (Read Data FIS) are sequentially generated after the transfer of the write data (Write Data) and the read data (Read Data) is completed. In the embodiment, each of the write data FIS (Write Data FIS) and the read data (Read Data FIS) sequentially generates DMA Setup FIS, Non-Data FIS, and SDB FIS.

In the bidirectional data transfer method according to the embodiment of the present invention, after transferring the write data (Write Data) and the read data (Read Data) according to the provisions of the first interface, DATA FIS (Write) according to the provisions of the second interface is executed. FIS, Read FIS) is virtually generated and transferred.

FIG. 4 is a flowchart illustrating an exemplary data transfer method according to the present invention. With reference to FIGS. 1 to 4, the data transfer method is as follows. The host processor 1100 issues NCQ commands (read / write) to storage 1300 (S110). Here, the NCQ command issues a write command and a read command at the same time, or issues them in sequence. Write and read DMA operations are performed in parallel between the host memory 1200 and the storage device 1300 using the first interface in response to NCQ commands (S120). After the write and read DMA operations are complete, the data FIS sequence to satisfy the second interface (eg DMA Setup FIS Non-Data FIS SDB FIS) is transferred from storage 1300 to host memory 1200. (S130).

In the data transfer method according to the embodiment of the present invention, the DMA operation is executed according to the specification of the first interface, and then the Data FIS is transferred according to the specification of the second interface. The computing system 1000 described with reference to FIGS. 1 to 4 is connected to the host bus 1001 from the outside according to the regulation of the first interface, and has a storage device 1300 inside which operates according to the regulation of the second interface. The computing system according to the embodiment of the present invention further includes a storage device that operates by being connected to a host bus according to the provisions of the first interface.

FIG. 5 is a block diagram showing a second embodiment of the computing system according to the present invention. Referring to FIG. 5, the computing system 2000 includes a host bus 2001, at least one host processor 2100, at least one host memory 2200, a first storage device 2300 and a second storage device 2400. Here, the host bus 2001, the host processor 2100, and the host memory 2200 have the same operation and structure as the host bus 1001, the host processor 1100, and the host memory 1200 shown in FIG.

The second storage device 2400 is connected to the host bus 2001 by the first interface. The second storage device 2400 includes a first interface circuit 2410, at least one non-volatile memory device 2450 and a memory controller 2460. The first interface circuit 2410 is configured to perform communication with the host according to the provisions of the first interface. The memory controller 2460 executes commands and data transfers according to the provisions of the first interface, and controls the non-volatile memory device 2450 in response to a request from the host. On the other hand, the second storage device 2400 is called the first interface storage device. At this time, the first storage device 2300 is called a pseudo first interface storage device because the host considers it as the first interface storage device.

The computing system according to the embodiment of the present invention further includes a RAID (redundant array of independent disks) function. Here, the RAID function allows multiple storage devices to operate as a single logical device, thereby expanding the limited capacity of each storage device as much as the user desires or storing it in the storage device. It is used to ensure the reliability of data.

FIG. 6 is a block diagram showing a third embodiment of the computing system according to the present invention. Referring to FIG. 6, the computing system 3000 includes a host bus 3001, at least one host processor 3100, at least one host memory 3200, a RAID controller 3300, a first storage device 3400 and a second storage device 3500. Here, the host bus 3001, the host processor 3100, and the host memory 3200 have the same operation and structure as the host bus 1001, the host processor 1100, and the host memory 1200 shown in FIG.

The RAID controller 3300 is connected to the host bus 3001 by the first interface and controls the first and second storage devices 3400 and 3500 to provide the RAID function. Here, the RAID function includes data mirroring technology. For example, data mirroring technology stores data in the first storage device 3400 and at the same time stores the same data in the second storage device 3500. The RAID controller 3300 is connected to the first and second storage devices 3400 and 3500 by the first interface. The first and second storage devices 3400 and 3500 are configured in the same manner as the storage devices 1300 shown in FIG. 1, respectively. That is, the first and second storage devices 3400 and 3500 become pseudo first interface storage devices.

The computing system 3000 according to the embodiment of the present invention performs the RAID function by using the pseudo first interface storage devices 3400 and 3500. The computing system 3000 illustrated in FIG. 6 has two storage devices, 3400 and 3500. However, the number of storage devices for executing the RAID function of the present invention is not limited to this. The computing system 3000 of the present invention can perform RAID functions using three or more pseudo first interface storage devices.

The storage devices of the computing system 3000 illustrated in FIG. 6 are all pseudo first interface storage devices 3400 and 3500. However, the computing system of the present invention is not limited to this. The computing system of the present invention includes at least one HDD (hard disk drive).

FIG. 7 is a block diagram showing a fourth embodiment of the computing system according to the present invention. Referring to FIG. 7, the computing system 4000 comprises a host bus 4001, at least one host processor 4100, at least one host memory 4200, a RAID controller 4300, a storage device 4400 and an HDD 4500. The host bus 4001, the host processor 4100, and the host memory 4200 have the same operation and structure as the host bus 1001, the host processor 1100, and the host memory 1200 shown in FIG.

The RAID controller 4300 is connected to the host bus 4001 by the first interface and controls the storage device 4400 and the HDD 4500 to provide the RAID function. The RAID controller 4300 saves the write data in the storage device 4400 and also in the HDD 4500 in response to the host write request.

The computing system 4000 according to the embodiment of the present invention executes the RAID function in a hybrid manner by using the pseudo first interface storage device 4400 and the HDD 4500. In the computing system according to the embodiment of the present invention, the first interface is composed of a PCIe interface and the second interface is composed of a SATA interface.

FIG. 8 is a block diagram showing a fifth embodiment of the computing system according to the present invention. Referring to FIG. 8, the computing system 5000 includes a host chipset 5100 and an SSDe storage device 5300. The host chipset 5100 and SSDe storage 5300 are connected via a PCIe interface. The host chipset 5100 includes an AHCI controller 5110, PCIe root port 5120 and PCIe lane 5130. The SSDe storage device 5300 is equipped with an SSD controller 5301. The SSD controller 5301 includes a PCIe physical layer 5310, a PCIe link layer 5320, a PCIe transfer layer 5330, and an AHCI controller 5340.

The PCIe physical layer 5310 is connected to the PCIe root port 5120 of the host chipset 5100 via the PCIe lane 5130. The PCIe physical layer 5310 converts the analog signal received from the host chipset 5100 into digital data and the digital data transmitted to the host chipset 5100 into an analog signal. The PCIe link layer 5320 performs PCIe standard coding / decoding of the digital data of the PCIe physical layer 5310.

The PCIe transfer layer 5330 manages the FIS for transmitting encoded / decrypted data (or data packets) between the host chipset 5100 and the application layer. The AHCI controller 5340 changes the PCIe-specified data packet to the SATAe-specified data packet. The AHCI controller 5340 causes the SSDe storage device 5300 to be considered as a PCIe storage device connected to the host via a PCIe link.

The computing system 5000 according to the embodiment of the present invention sends and receives data packets having a PCIe link layer format between the host chipset 5100 and the SSDe storage device 5300 via the PCIe lane. The computing system according to the embodiment of the present invention may also include both a pseudo first interface storage device and a second interface storage device.

FIG. 9 is a block diagram showing a sixth embodiment of the computing system according to the present invention. Referring to FIG. 9, the computing system 6000 includes a central processing unit 6100 (CPU), DRAM 6200, internal channel controller 6300, AHCI storage 6400, and SATA storage 6500. The central processing unit 6100 and DRAM 6200 correspond to the host processor 1100 and the host memory 1200 shown in FIG. 1, respectively.

The internal channel controller 6300 is connected by a PCIe interface and includes a PCIe route complex 6310, an AHCI controller 6320, and a SATA controller 6330. The AHCI storage device 6400 includes an AHCI controller 6410 that is connected to the internal channel controller 6300 via a PCIe interface and converts PCIe-specified data packets into SATA-specified data packets. The AHCI storage device 6400 is externally regarded as a PCIe storage device, but internally it is a SATA storage device. The AHCI storage device 6400 is configured to operate in the same manner as the storage device 1300 illustrated in FIG.

The SATA storage device 6500 is connected to the internal channel controller 6300 via a SATA interface and includes a SATA controller 6510 that processes SATA-specified data packets. The SATA storage device 6500 sends and receives SATA data packets under the control of the SATA controller 6330 of the internal channel controller 6300. The transmitted / received SATA data packets are converted into PCIe data packets by the AHCI controller 6320 of the internal channel controller 6300, and the converted PCIe data packets are transmitted / received to the central processing device 6100 via the PCIe interface.

The computing system 6000 according to the embodiment of the present invention includes a pseudo PCIe storage device 6400 and a SATA storage device 6500 connected to an internal channel controller 6300 via a PCIe interface. FIG. 10 is a diagram showing a computing system 7000 from the viewpoint of input / output requirements (IO RQ) according to the embodiment of the present invention. Referring to FIG. 10, the computing system 7000 includes a central processing unit 7100, a main memory 7200 and a SATAe storage device 7300.

The SATAe storage device 7300 includes a non-volatile memory device 7350 and a SATA controller 7360 that controls it. The SATA controller 7360 includes a PCIe interface circuit 7361, a SATAe engine 7362, an on-chip SRAM 7363 and a DRAM buffer 7364. The SATAe engine 7362 includes an AHCI engine 7320, a SATA emulator 7330, and a DMA circuit 7340. In particular, the DMA circuit 7340 includes a transmit DMA circuit 7341 (DMA1) for data transfer and a receive DMA circuit 7342 (DMA2) for data reception.

The input / output request (IO RQ) process is as follows: If an input / output request (IO RQ) is possible, the central processing unit 7100 sends an input / output request (IO RQ) to the main memory 7200 ((1)). The command queue corresponding to the input / output request (IO RQ) is the command head (command header; CH) / command FIS (command frame information structure; CFIS), PRDT (physical region descriptor table), host buffer (host). buffer) is included. PRDT is a table that stores the structure of the memory area that stores the data sent to the host and the data sent from the host. The PRD (physical region descriptor) contains the address and size of the corresponding memory region.

The central processing unit 7100 transfers the input / output request (IO RQ) doorbell information to the SATAe storage device 7300 ((2)). The AHCI engine 7320 of the SATAe storage device 7300 is equipped with a host register (for example, PxCI) for storing buzzer information. The SATAe storage device 7300 fetches the I / O request (IO RQ) by transferring the FIS-related information to the main memory 7200 in response to the input / output request (IO RQ) ((3)). In addition, the FIS corresponding to the input / output request (IO RQ) is updated voluntarily ((4)). Data transfer by input / output request (IO RQ) is performed between the main memory 7200 and the SATAe storage device 7300 via the transmission DMA circuit 7341 and the reception DMA circuit 7342, respectively. When the data transfer is complete, the SATAe storage 7300 sends an interrupt to the central processing unit 7100 ((5)). After an interrupt is input to the central processing unit 7100, the central processing unit 7100 transfers the information that the input / output request is completed to the SATAe storage device 7300 ((6)).

The computing system 7000 according to the embodiment of the present invention can perform bidirectional data transfer between the main memory 7200 and the SATAe storage device 7300 based on an input / output request. FIG. 11 is a diagram illustrating an example of a PCI header of a data packet input / output to / from the AHCI engine 7320 illustrated in FIG. Referring to FIG. 11, ABAR is the AHCI base address, the start address of the host control register is the value of ABAR plus 0x0000, and the start address of the port register is the value of ABAR plus 0x0100.

FIG. 12 is a diagram exemplifying the control information of the host stored in the AHCI engine 7320 illustrated in FIG. Referring to FIG. 12, the host control register corresponding to 00h to 03h stores the host capacity information, and the host control register corresponding to 0Ch to 0Fh stores the combined port information.

FIG. 13 is a diagram illustrating exemplary port information stored in the AHCI engine 7320 illustrated in FIG. Referring to FIG. 13, the port register corresponding to 00h to 03h stores the port information for the command list base address, and the port register corresponding to 08h to 0Bh stores the port information for the FIS base address, and corresponds to 28h to 2Bh. The port register to be used stores the port information for the SATA state, and the port register corresponding to 38h to 3Bh stores the port information for the command.

14A-14H are diagrams exemplifying the provisions of FIS transmitted and received between the AHCI engine 7320 and the SATA emulator 7330 illustrated in FIG. With reference to FIGS. 14A-14B, the FIS regulations satisfy the SATA3.0 specification. Figure 14A shows the types of FIS, Figure 14B is the H2DFIS layout, Figure 14C is the D2HFIS layout, Figure 14D is the PIO Setup FIS layout, Figure 14E is the DMA Setup FIS layout, Figure 14F is the DMA Activate FIS layout, and Figure 14G is the Data. FIS layout, FIG. 14H is a diagram showing the SDB FIS layout.

FIG. 15 is a diagram exemplifying the structure of the host buffer of the main memory 7200 shown in FIG. Referring to FIG. 15, the port register PxCLB stores a command list structure (command queue) having multiple commands for identifying the command table (CT), and the port register PxFB stores the input FIS structure. The host buffer base address from main memory 7200 for the command list structure can be identified by the port register PxCLB. The host buffer base address from the main memory 7200 for the FIS structure can be identified by the port register PxFB.

FIG. 16 is a diagram exemplifying the structure of the command list illustrated in FIG. Referring to FIG. 16, each command header stores the command table base address (DW2) and the upper 32 bits (DW3) of the command table base address.

FIG. 17 is a diagram illustrating an example of the command table illustrated in FIG. Referring to FIG. 17, the command table contains a PRDT (physical region descriptor table) having multiple items (Item0 to ItemCHz [PRDTL] -1). Each item (Item0 ~ ItemCHz [PRDTL] -1) contains a database address (DBA). The database address (DBA) is stored in the host buffer in main memory 7200. PRDT is used for prefetching.

FIG. 18 is a diagram illustrating an exemplary Received FIS structure illustrated in FIG. Referring to FIG. 18, the FIS includes a DMA setup FIS, a PIO setup FIS, a D2H register FIS, an unidentified FIS, and a spare area.

FIG. 19 is a diagram exemplifying the process of a read command executed from the computing system 7000 illustrated in FIG. Referring to FIG. 19, register PxCI of AHCI engine 7320 receives NCQ command, AHCI engine 7320 exchanges FIS information by NQQ command with SATAe emulator 7330, and relevant FIS information (CH, H2DFIS, PRD table, etc.) Fetch commands by transferring to the main DRAM 7200. After that, the SATAe engine 7362 transfers the input / output data by the command by accessing the main memory 7200. After that, the DMA setup FIS and SDBFIS according to the SATA regulations are transferred from the SATA e emulator 7330 to the AHCI engine 7320, and the AHCI engine 7320 transfers them to the main memory 7200. The read completion information is then transferred to the AHCI engine 7320.

1000, 2000, 3000, 4000, 5000, 6000, 7000 ... Computing system 1100 ... Host processor 1200 ... Host memory 1001 ... Host bus 1300 ... Storage device 1310 ... First interface Circuit 1320 Host bus adapter 1330 Second interface emulator 1340 Direct memory access circuit 1350 Non-volatile memory device 1360 Memory controller FIS Frame information structure CH Command Header CFIS Command FIS PRDT Physical area descriptor table