Imaging device in which peripheral circuit is arranged and increase in chip area is suppressed, and imaging apparatus

The present invention relates to an image pickup device and an image pickup device, and more particularly to a technique of a circuit constituting the image pickup element.

Conventionally, image pickup devices such as digital cameras and digital video cameras that record captured images by using CMOSAPS (Complementary Metal Oxide Semiconductor Active Pixel Sensor) as an image sensor have been developed. The image sensor has a pixel unit and a peripheral circuit unit. The peripheral circuit section reads the signal from the pixel and outputs it as an image signal to the outside. The pixel portion is photoelectrically converted by a photodiode, and the signal obtained by the photoelectric conversion is read out to a peripheral circuit portion by a pixel circuit formed in the pixel portion.

In recent years, with the miniaturization of pixels, the number of circuits in the pixels has been reduced as much as possible, and the area of the photodiode has been increased to ensure the performance of the image sensor. Further, as the function is improved, the area of the peripheral circuit portion is also increasing. Therefore, a technique for forming a pixel portion and a peripheral circuit portion on different chips is being developed. For example, in Patent Document 1, a method is adopted in which pixels are limited to a photodiode and some switches, and other switches are configured on separate chips.

FIG. 27 is a diagram for explaining a schematic configuration of a conventional image sensor.

The image sensor is predetermined to the signal of the pixel in the row selected by the vertical selection circuit 102'among the pixels in the pixel unit 101', the vertical selection circuit 102'in the pixel unit 101', and the row in the pixel unit 101'. It has a column circuit 103'to be processed. Further, the image sensor has a column memory 104'that holds the signal processed by the column circuit 103'for each column, a horizontal selection circuit 105'that selects a sequence of signals held by the column memory 104', and a horizontal selection circuit 105. It has an output signal line 106'which reads out the signal of the column selected by' to the output circuit 107'. In addition to the components shown in the figure, the image sensor includes, for example, a timing generator, a control circuit, and the like that provide timing signals to the vertical selection circuit 102', the horizontal selection circuit 105', the column circuit 103', and the like.

The vertical selection circuit 102'selects a plurality of rows of the pixel unit 101'in order, and outputs the selected signal to the column memory 104' via the column circuit 103'. The horizontal selection circuit 105'selects the signals held in the column memory 104' in order and outputs the signals to the output circuit 107' via the output signal line 106'. The pixel unit 101'is configured by arranging a plurality of pixels in a two-dimensional array in order to provide a two-dimensional image. These circuits are formed on one semiconductor substrate, and the semiconductor process is miniaturized, the pixel spacing is reduced, and the area of peripheral circuits is reduced.

FIG. 28 is a diagram showing a configuration of one pixel in a conventional image sensor and a configuration of a circuit that reads a signal from the pixel.

As shown in FIG. 28, a pixel array that provides a two-dimensional image is configured by arranging a plurality of pixels in a two-dimensional array. Each pixel 201'is a photodiode (hereinafter also referred to as "PD") 202', a transfer switch 203', a floating diffusion unit (hereinafter also referred to as "FD") 204', a reset switch 207', an amplification MOS amplifier 205', and a selection. It is configured to include switch 206'.

The PD202'functions as a photoelectric conversion element that generates an electric charge by photoelectrically converting the light incident through the optical system. The anode of PD202'is connected to the ground line and the cathode is connected to the source of transfer switch 203'. The transfer switch 203'is driven by the transfer pulse φTX input to the gate terminal, and transfers the electric charge generated by the PD 202' to the FD204'. The FD204'functions as a charge-voltage converter that temporarily stores charges and converts the accumulated charges into voltage signals.

The amplification MOS amplifier 205'functions as a source follower, and the signal converted by the FD204' is input to the gate. Further, the amplification MOS amplifier 205'is connected to the first power supply line VDD1 whose drain supplies the first potential, and its source is connected to the selection switch 206'. The selection switch 206'is driven by the vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205', and its source is connected to the vertical signal line (column signal line) 208'. .. When the vertical selection pulse φSEL becomes the active level (high level), the selection switch 206'of the pixel belonging to the corresponding row of the pixel array becomes conductive, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208'. ..

The reset switch 207'is connected to the second power line VDD2 whose drain supplies the second potential (reset potential), and its source is connected to the FD204'. Further, the reset switch 207'is driven by the reset pulse φRES input to the gate and removes the charge accumulated in the FD204'.

In addition to the FD204'and the amplification MOS amplifier 205', a floating diffusion amplifier is composed of a constant current source 209'that supplies a constant current to the vertical signal line 208'. In each pixel constituting the row selected by the selection switch 206', the electric charge transferred from PD202' to FD204'is converted into a voltage signal by FD204', and a vertical signal line provided for each column through a floating diffusion amplifier. (Column signal line) Output to 208'.

The column circuit 103'connected to each of the vertical signal lines (column signal lines) 208'is composed of a CDS (correlated double sampling) circuit, a gain amplifier, and the like. Further, the column circuit 103'is formed by a circuit having the same configuration for each column. The signals processed by the column circuit 103'are held in the corresponding column memory 104'. The signal held in the column memory 104'is transferred to the output circuit 107' via the output signal line 106'. The output circuit 107'performs amplification, impedance conversion, and the like on the input signal, and outputs the signal to the outside of the image sensor.

<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2008-211220</text></patcit></p>

<p> However, in Patent Document 1, since the chips are connected by floating diffusion (FD), which has a weak signal amount among the pixels, the variation in the manufacturing of the FD becomes the variation in the capacitance value of the FD. As a result, it causes PRNU (Photo Response Non-Uniformity) and DSNU (Dark Signal Non-uniformity). Further, although the arrangement of the read-out circuit is not described in Patent Document 1, since the pixel portion and the peripheral circuit portion are on separate chips, it is desired to arrange the read-out circuit more efficiently than in the past. Further, recently, the chip area of the peripheral circuit is increasing because the circuit that realizes a plurality of functions is introduced into the peripheral circuit, such as the introduction of an AD converter for each column in the column circuit. As a result, the heat generated in the peripheral circuit not only generates a dark current in the PD202'of the pixel, but also the dark current becomes non-uniform within the screen compatible area when the arrangement of the peripheral circuit is biased. The problem arises.</p><p> An object of the present invention is to provide an image pickup device and an image pickup apparatus capable of suppressing an increase in chip area of a peripheral circuit and suppressing an increase in cost without impairing the performance of a pixel portion.</p><p> Further, an object of the present invention is to further suppress an increase in chip area by efficiently arranging peripheral circuits in an image sensor in which a pixel portion and a peripheral circuit portion are formed in different regions without impairing the performance of the pixel portion. Another object of the present invention is to provide an image pickup device and an image pickup device that suppress the non-uniformity of dark current in the screen corresponding region due to heat generation of peripheral circuits.</p>

<p> In order to achieve the above object, the image pickup device according to claim 1 is a first semiconductor substrate, a second semiconductor substrate, a photoelectric conversion element that generates a charge by photoelectric conversion, and one of the photoelectric conversion elements, respectively. A pixel unit having a floating diffusion unit that temporarily stores the charge generated in the above and an amplification unit that outputs a signal corresponding to one potential of the floating diffusion unit, and a pixel unit that outputs the signal for each row from the pixel unit. It has a plurality of row signal lines to be formed, and a plurality of row circuits connected to each of the plurality of row signal lines and subjecting a signal output to the row signal lines to a predetermined process, and the image pickup element is described as described above. The pixel portion is formed in the region of the first semiconductor substrate and the plurality of the pixel portions are formed in the region of the first semiconductor substrate so that the plurality of row circuits are positioned under the pixel portion when viewed from the light incident surface side of the pixel portion. The row circuit is formed in the region of the second semiconductor substrate.</p><p> Further, in order to achieve the above object, the image pickup apparatus according to claim 12 is characterized by including the image pickup device according to any one of claims 1 to 11.</p><p> Further, in order to achieve the above object, the image pickup device according to claim 13 includes a semiconductor substrate having a first surface and a second surface, a photoelectric conversion element that generates an electric charge by photoelectric conversion, and the photoelectric conversion, respectively. A pixel unit having a floating diffusion unit that temporarily stores the electric charge generated by one of the elements and an amplification unit that outputs a signal corresponding to one potential of each of the floating diffusion units, and a row from the pixel unit for each row. It has a plurality of row signal lines from which the signal is output, and a plurality of row circuits connected to each of the plurality of row signal lines and performing predetermined processing on the signal output to the row signal line. When the image sensor is viewed from the light incident surface side of the pixel portion, the pixel portion is placed on the first surface of the semiconductor substrate so that the plurality of row circuits are positioned below the pixel portion. It is characterized in that the plurality of row circuits are formed and the plurality of row circuits are formed on the second surface of the semiconductor substrate.</p><p> Further, in order to achieve the above object, the image pickup apparatus according to claim 17 is characterized by including the image pickup device according to any one of claims 13 to 16.</p>

<p> According to the present invention, it is possible to obtain the effect that the performance of the pixel portion is not impaired and the cost increase due to the increase in the chip area of the peripheral circuit can be suppressed.</p><p> Further, according to the present invention, it is possible to efficiently and efficiently arrange peripheral circuits without impairing the performance of the pixel portion, and to suppress the non-uniformity of dark current in the screen corresponding region due to heat generation of the peripheral circuits. Is possible.</p>

<figref num="1">It is a block diagram for demonstrating the whole structure of the image pickup device which concerns on 1st Embodiment of this invention.</figref><figref num="2">It is a figure which shows the pixel in the image pickup device which concerns on 1st Embodiment, and the circuit structure which reads out the signal from the pixel.</figref><figref num="3">It is a figure which shows the modification of the circuit structure of FIG.</figref><figref num="4">It is a figure which shows the other modification of the circuit structure of FIG.</figref><figref num="5">It is a figure which shows the cross-sectional structure of the image pickup device which concerns on 1st Embodiment.</figref><figref num="6">It is a block diagram which shows the modification of the whole structure of the image pickup device shown in FIG.</figref><figref num="7">It is a block diagram which shows the other modification of the whole structure of the image pickup device shown in FIG.</figref><figref num="8">It is a figure which shows the cross-sectional structure of the image pickup device which concerns on 2nd Embodiment of this invention.</figref><figref num="9">It is a block diagram which shows the further modification of the whole structure of the image pickup device shown in FIG.</figref><figref num="10">It is a figure which shows the schematic structure of the digital camera which is an example of the image pickup apparatus equipped with the image pickup element which concerns on one of the 1st and 2nd Embodiments and a modification thereof.</figref><figref num="11">It is a figure which shows the structure of 1 pixel in the image sensor which concerns on 3rd Embodiment of this invention, and the circuit structure which reads a signal from the pixel.</figref><figref num="12">It is a figure which shows the modification of the circuit structure of the image sensor of FIG.</figref><figref num="13">It is a figure which shows the other modification of the circuit structure of the image sensor of FIG.</figref><figref num="14">It is the figure which took a bird's-eye view of the whole structure of the image sensor of the 3rd Embodiment from the top.</figref><figref num="15">It is sectional drawing of the image sensor of the modification of 3rd Embodiment.</figref><figref num="16">It is the figure which took a bird's-eye view of the whole structure of the image sensor of the 5th Embodiment of this invention.</figref><figref num="17">It is the figure which took a bird's-eye view from the top of the 5th embodiment of the whole configuration modification modification of the image sensor.</figref><figref num="18">It is the figure which took a bird's-eye view from the top of the whole structure of the image sensor of the 5th Embodiment and other modification.</figref><figref num="19">It is the figure which took a bird's-eye view of the whole structure of the image sensor of the 6th Embodiment of this invention.</figref><figref num="20">It is the figure which looked at the modification of the whole structure of the image sensor of 6th Embodiment from the top.</figref><figref num="21">It is the figure which took a bird's-eye view from the other modified example of the whole structure of the image sensor of 6th Embodiment.</figref><figref num="22">It is the figure which took a bird's-eye view of the whole structure of the image sensor of the 7th Embodiment of this invention.</figref><figref num="23">It is the figure which took a bird's-eye view of the whole structure of the image sensor of the 8th Embodiment of this invention.</figref><figref num="24">It is the figure which took a bird's-eye view of the whole structure of the image sensor of the 9th Embodiment of this invention.</figref><figref num="25">It is the figure which looked at the modification of the whole structure of the image sensor of 9th Embodiment from the top.</figref><figref num="26">It is the figure which took a bird's-eye view from the other modified example of the whole structure of the image sensor of 9th Embodiment.</figref><figref num="27">It is a figure for demonstrating the schematic structure of the conventional image pickup device.</figref><figref num="28">It is a figure which shows the structure of one pixel in the conventional image sensor, and the structure of the circuit which reads a signal from the pixel.</figref>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram for explaining a schematic configuration of an image pickup device according to the first embodiment of the present invention. Actually, it is assumed that the illustrated area 1 and the area 2 overlap in the vertical direction.

In FIG. 1, the image sensor reads out the signals of the pixels in the row selected by the vertical selection circuit 102 among the pixels in the pixel unit 101, the vertical selection circuit 102 in the pixel unit 101, and the pixels in the pixel unit 101. It has a column circuit 103 that performs the processing of. Further, the image sensor selects a column memory 104 that holds the signal processed by the column circuit 103 for each column, a horizontal selection circuit 105 that selects the signal held by the column memory 104, and a column selected by the horizontal selection circuit 105. It has an output signal line 106 to be read out to the output circuit 107. In addition to the components shown in the image sensor, the image sensor includes, for example, a timing generator 1007 described later, a control circuit 1009 described later, and DA conversion that provide timing to the vertical selection circuit 102, the horizontal selection circuit 105, the column circuit 103, and the like. Although devices and the like may be incorporated, they do not need to be provided on the same substrate as the image sensor, and the timing generator 1007 and the control circuit 1009 are provided separately from the image sensor as shown in FIG. May be good.

The vertical selection circuit 102 sequentially selects a plurality of rows of the pixel unit 101, and outputs the signal of the selected row to the column memory 104 via the column circuit 103. The horizontal selection circuit 105 sequentially selects the signals held in the column memory 104 and outputs them to the output circuit 107 via the output signal line 106. The pixel unit 101 is configured by arranging a plurality of pixels in a two-dimensional array in order to provide a two-dimensional image.

The pixel portion 101, the vertical selection circuit 102, and the output circuit 107 included in the region 1 are formed on the first semiconductor substrate. On the other hand, the column circuit 103, the column memory 104, the horizontal selection circuit 105, and the output signal line 106 included in the region 2 are formed on the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are formed separately, and are mounted in the same package by connecting and stacking wirings that require electrical connection. That is, when viewed from the upper surface of the image sensor package (the light incident surface side of the pixel portion 101), the region 2 of the second semiconductor substrate is located below the pixel portion 101 formed in the region 1 of the first semiconductor substrate. The formed column circuit 103, column memory 104, horizontal selection circuit 105, and output signal line 106 are located at overlapping positions. Area efficiency is improved by arranging the timing generator 1007, the control circuit 1009, the DA converter, etc. in the area 2 below the vertical selection circuit 102 and the output circuit 107 in the area 1. In the plurality of embodiments described below, the configuration including the first semiconductor substrate and the second semiconductor substrate will be described as an example, but the present invention is not limited to this, and a configuration including another semiconductor substrate may be used. ..

FIG. 2 is a diagram showing a configuration of one pixel in the image sensor according to the first embodiment and a configuration of a circuit for reading a signal from the pixel.

As shown in FIG. 2, a pixel array that provides a two-dimensional image is configured by arranging a plurality of pixels in a two-dimensional array. Each pixel 201 includes a photodiode (hereinafter also referred to as "PD") 202, a transfer switch 203, a floating diffusion unit (hereinafter also referred to as "FD") 204, a reset switch 207, an amplification MOS amplifier 205, and a selection switch 206. It is composed.

The PD202 functions as a photoelectric conversion element that generates electric charges by photoelectrically converting light incident through an optical system. The anode of PD202 is connected to the ground line and the cathode is connected to the source of transfer switch 203. The transfer switch (transfer unit) 203 is driven by the transfer pulse φTX input to its gate terminal, and transfers the electric charge generated by the PD 202 to the FD 204. The FD204 functions as a charge-voltage converter that temporarily stores electric charges and converts the accumulated charges into voltage signals.

The amplifier MOS amplifier (amplification unit) 205 is composed of an amplifier circuit such as a MOSFET and functions as a source follower, and a signal converted by charge voltage by FD204 is input to the gate. Further, the amplification MOS amplifier 205 is connected to the first power supply line VDD1 whose drain supplies the first potential, and its source is connected to the selection switch 206. The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205, and its source is connected to the vertical signal line 208. When the vertical selection pulse φSEL becomes the active level (high level), the selection switch 206 of the pixel belonging to the corresponding row of the pixel array becomes conductive, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208.

The reset switch (reset unit) 207 is connected to the second power supply line VDD2 whose drain supplies the second potential (reset potential) which is a constant potential, and its source is connected to the FD204. Further, the reset switch 207 is driven by the reset pulse φRES input to the gate to remove the electric charge accumulated in the FD204. φTX, φSEL, and φRES are supplied from the vertical selection circuit 102.

In addition to the FD204 and the amplified MOS amplifier 205, a floating diffusion amplifier is composed of a constant current source 209 that supplies a constant current to the vertical signal line 208. In each pixel constituting the row selected by the selection switch 206, the electric charge transferred from PD202 to FD204 is converted into a voltage signal by FD204, and a vertical signal line (column signal line) provided for each column through a floating diffusion amplifier is provided. ) Output to 208.

The column circuit 103 connected to each of the vertical signal lines (column signal lines) 208 is composed of a CDS (correlated double sampling) circuit, a gain amplifier, and the like. The CDS circuit performs a correlation double sampling process on the signal output to the vertical signal line 208. Further, the gain amplifier amplifies the signal output to the vertical signal line 208 at a predetermined amplification factor. Further, the column circuit 103 is formed by a circuit having the same configuration for each column. The signals subjected to the above processing in the column circuit 103 are held in the corresponding column memories 104, respectively. The signal held in the column memory 104 is transferred to the output circuit 107 via the output signal line 106. The output circuit 107 performs amplification, impedance conversion, and the like on the input signal, and outputs the signal to the outside of the image sensor.

The column circuit 103, the column memory 104, and the output circuit 107 may have the circuit configuration as described above, but may be a type in which the column circuit 103 has an AD converter for each column. In that case, the column circuit 103 has an AD converter in addition to the CDS circuit and the gain amplifier. Further, the column memory 104 at that time is a digital memory, and the output circuit 107 also includes components such as an LVDS (Low Voltage Differential Signaling) driver.

The area 1 shown in the figure, that is, the first semiconductor substrate is configured to include a PD202, a transfer switch 203, an FD204, a reset switch 207, an amplification MOS amplifier 205, and a selection switch 206 provided for each pixel, and an output circuit 107. Has been done.

The illustrated region 2, that is, the second semiconductor substrate, is configured to include a vertical signal line 208, a constant current source 209, a row circuit 103, a row memory 104, and an output signal line 106 provided for each row. .. The vertical signal line (column signal line) 208 is a wiring connecting the pixel unit 101 and the column circuit 103, and may be included in either region 1 or region 2. Further, the selection switch 206 may be included in the region 2.

Further, the constant current source 209 may be in the region 1 as in the modified example of the circuit configuration shown in FIG. However, in this case, since the constant current source 209 is arranged on the same substrate as the pixels, the area efficiency is not very good. It is effective only when the constituent area of the column circuit 103, the column memory 104, the output signal line 106, and the like is larger than the area of the pixel portion.

Further, as in the other modification of the circuit configuration shown in FIG. 4, the configuration may not have the selection switch 206. In the configuration without the selection switch 206, the selected line and the non-selected line are set by controlling the potentials of ΦRES and the second power supply line VDD2.

FIG. 5 is a diagram showing a cross-sectional structure of the image pickup device according to the first embodiment of the present invention. The region 1 representing the first semiconductor substrate shows a structure laminated on the region 2 representing the second semiconductor substrate. The same components as those shown in Fig. 2 are given the same sign.

The region 1 representing the first semiconductor substrate is formed on the semiconductor substrate 501. The region 1 includes a first conductive type region 502, a PD region 202, and a first conductive type region 503 for suppressing the dark current of the PD 202. It also includes a transfer switch 203, an FD204, and an amplification MOS amplifier 205. In addition to this, the reset switch 207 is also included.

Further, the element separation region 504, the wiring layer 505 formed in multiple layers, and the interlayer film 506 between the multilayer wiring layers 505 are provided. The through hole 507 electrically connects the wirings. Since region 1 includes a pixel portion, it also includes a color filter 508 that performs color separation and a microlens 509 that collects light.

The region 2 representing the second semiconductor substrate as a semiconductor substrate other than the first semiconductor substrate is formed on the semiconductor substrate 510. Each circuit of the column circuit 103 is formed by a plurality of types of switches of each switch group 511. The area 2 also includes a column memory 104, an output signal line 106, and the like. The connection point 115 of the vertical signal line 208 electrically connects the area 1 and the area 2 with a micro bump or the like. In addition to the connection point 115 of the vertical signal line 208, wirings that supply power and various drive pulses are connected by connection points 512 such as micro bumps. In the present embodiment, the first semiconductor substrate in which the light receiving portion is formed by the back-illuminated type is shown, but the front-illuminated type may be used instead of the back-illuminated type.

In the present embodiment, as shown in FIG. 1, the pixel portion 101, the vertical selection circuit 102, and the output circuit 107 are formed in the area 1, and the other drive circuits are arranged in the area 2, but the present invention is not limited to this. Absent. For example, the output circuit 107 may be arranged in the region 2 as in the modified example of the overall configuration of the image sensor in FIG.

Further, as shown in another modification of the overall configuration of the image pickup device of FIG. 7, a part of the vertical selection circuit 102 may be arranged in the region 1 and the rest of the vertical selection circuit 102 may be arranged in the region 2. Further, in that case, the area efficiency can be improved by arranging them in substantially the same place when viewed from above. That is, in the present invention, if at least the transfer switch 203, the FD204, the reset switch 207, and the amplification MOS amplifier 205 are in the area 1 so that the FD204 is not divided into the area 1 and the area 2 in the pixel unit 101. Good. The other drive circuits may be arranged in the area 1 or the area 2 depending on the area efficiency of the semiconductor substrate.

In the above embodiment, as shown in FIG. 5, region 1 is a first semiconductor substrate and region 2 is a second semiconductor substrate, but the present invention is not limited to this, and as shown in FIG. 8, they are the same. It may be formed on the semiconductor substrate of.

FIG. 8 is a diagram showing a cross-sectional structure of an image pickup device according to a second embodiment of the present invention. The components shown in FIG. 2 and the same components shown in FIG. 5 are given the same symbols, and their description is omitted.

In the second embodiment shown in FIG. 8, regions 1 and 2 are formed on the front surface (first surface or second surface) and the back surface (first surface or second surface) of the semiconductor substrate 501, respectively. .. In the present embodiment, the side on which the region 1 is formed will be described as the front surface, and the side on which the region 2 is formed will be described as the back surface. The protective layer 801 protects the wiring layer 505 on the back surface. The plug 802 electrically connects the front and back surfaces.

Further, in the above embodiment, the description is made as the area 1 and the area 2, but the present invention is not limited to the two areas, and each component may be arranged by dividing into a plurality of areas. For example, as in the modified example shown in FIG. 9, the pixel portion 101 and the vertical selection circuit 102 may be formed in the region 1, and the remaining drive circuit may be divided into the region 2 and the region 3 to be formed. .. In the illustrated example, the rest of the vertical selection circuit 102 and the row circuit 103 are formed in the region 2, and the rest of the row circuit 103 and the other drive circuits are separately formed in the region 3. In this way, by arranging each component separately over a plurality of regions, it is possible to mount an AD converter or the like for each column and effectively arrange the increasing column circuit 103. The region 1, the region 2, and the region 3 may be formed on separate semiconductor substrates.

FIG. 10 is a diagram showing a schematic configuration of a digital camera which is an example of an image pickup device equipped with an image pickup device according to any one of the above-described embodiments and modifications.

In FIG. 10, a lens unit 1001 that forms an optical image of a subject on a solid-state image sensor (an image sensor according to any of the embodiments and modifications) 1005 is subject to zoom control, focus control, and aperture control by a lens drive device 1002. And so on. The mechanical shutter 1003 is controlled by the shutter control unit 1004. The solid-state image sensor 1005 converts the subject image imaged by the lens unit 1001 into an image signal and outputs the image signal. The image pickup signal processing circuit 1006 performs various corrections on the image signal output from the solid-state image sensor 1005 and compresses the data.

The timing generator 1007 is a drive unit that outputs various timing signals to the solid-state image sensor 1005 and the image pickup signal processing circuit 1006. The control circuit 1009 controls various calculations and the entire image pickup apparatus. Memory 1008 temporarily stores image data. The recording medium control interface 1010 records or reads from a removable recording medium 1011 such as a semiconductor memory. The display unit 1012 displays various information and captured images.

Next, the operation at the time of shooting of the digital camera having the above-described configuration will be described.

When the main power supply (not shown) is turned on, the power supply of the control system is turned on, and the power supply of the image pickup system circuit such as the image pickup signal processing circuit 1006 is further turned on. Subsequently, when the release button (not shown) is pressed, the high frequency component is extracted based on the signal output from the distance measuring device 1014, and the distance to the subject is calculated by the control circuit 1009. After that, the lens driving device 1002 drives the lens unit 1001 to determine whether or not the lens is in focus, and if it is determined that the lens is not in focus, the lens unit 1001 is driven again to measure the distance. Then, after the focusing is confirmed, the shooting operation starts.

When the photographing operation is completed, the image signal output from the solid-state image sensor 1005 is image-processed by the image pickup signal processing circuit 1006 and written to the memory 1008 by the control circuit 1009. The data stored in the memory 1008 passes through the recording medium control I / F unit 1010 under the control of the control circuit 1009, and is recorded in the removable recording medium 1011 such as a semiconductor memory. The image may be processed by directly inputting it to a computer or the like through an external I / F section (not shown).

FIG. 11 is a diagram showing a configuration of one pixel in the image sensor according to the third embodiment of the present invention and a circuit configuration for reading a signal from the pixel. Region 1 is a chip having a circuit formed on the first semiconductor substrate, and region 2 is a chip having a circuit formed on the second semiconductor substrate.

The area 1 mainly has pixels 201, and the area 2 mainly has a column circuit that processes signals from pixels 201.

Region 1 is configured by arranging a plurality of pixels 201 in a two-dimensional array as a pixel array that provides a two-dimensional image. Each pixel 201 includes a photodiode (hereinafter, also referred to as PD) 202, a transfer switch 203, a floating diffusion unit (hereinafter, also referred to as FD) 204, an amplification MOS amplifier 205, a selection switch 206, and a reset switch 207. sell.

The PD202 functions as a photoelectric conversion unit that generates electric charges by photoelectrically converting light incident through the optical system. The anode of PD202 is connected to the ground line and the cathode is connected to the source of transfer switch 203. The transfer switch 203 is driven by the transfer pulse φTX input to the gate terminal, and transfers the electric charge generated by the PD 202 to the FD 204. The FD204 functions as a charge-voltage converter that temporarily stores electric charges and converts the accumulated charges into voltage signals.

The amplification MOS amplifier 205 functions as a source follower, and a signal whose charge and voltage are converted by the FD204 is input to the gate. Further, the amplification MOS amplifier 205 is connected to the first power supply line VDD1 whose drain supplies the first potential, and its source is connected to the selection switch 206. The selection switch 206 is driven by a vertical selection pulse φSEL input to its gate, its drain is connected to the amplification MOS amplifier 205, and its source is connected to the vertical signal line 208. When the vertical selection pulse φSEL becomes the active level (high level), the selection switch 206 of the pixel belonging to the corresponding row of the pixel array becomes conductive, and the source of the amplification MOS amplifier 205 is connected to the vertical signal line 208. The vertical signal line 208 is shared by a plurality of pixels 201 that share a column.

The reset switch 207 is connected to the second power line VDD2 whose drain supplies the second potential (reset potential), its source is connected to the FD204, and is driven by the reset pulse φRES input to its gate. , Removes the charge stored in the FD204.

The floating diffusion amplifier is composed of the FD204, the amplification MOS amplifier 205, and the constant current source 209 that supplies a constant current to the vertical signal line 208. In each pixel constituting the row selected by the selection switch 206, the electric charge transferred from PD202 to FD204 is converted into a voltage signal by FD204, and a vertical signal line (column signal line) provided for each column through a floating diffusion amplifier is provided. ) Output to 208. φTX, φSEL, and φRES are supplied from the vertical selection circuit described later.

The column circuit 103 connected to each of the vertical signal lines (column signal lines) 208 is composed of a column amplifier 110 and the like. The column circuit 103 is formed of circuits having the same configuration as each column. The column circuit 103 may have a configuration of only the column amplifier 110 shown in FIG. 11, or may have a configuration including a CDS (correlation double sampling) circuit or the like.

The signals subjected to various processing in the column circuit 103 are held in the corresponding column memory 104. The signal held in the column memory 104 is transferred to the output circuit 107 via the output signal line 106. The output circuit 107 performs amplification, impedance conversion, and the like, and outputs a signal to the outside of the image sensor.

Region 1 and region 2 are electrically connected via the connection point 115 of the vertical signal line (column signal line) 208. By setting the connection point 115 after the amplification MOS amplifier 205 as shown in FIG. 11, it is possible to reduce PRNU and DSNU. The constant current source 209 may be in region 2 or region 1.

FIG. 12 is a diagram showing a modified example of the image sensor circuit of FIG.

In FIG. 12, the row AD111 is mounted after the row amplifier 110. The column AD111 is an AD converter for each column and performs AD conversion. In this case, the column circuit 103 is composed of a column amplifier 110 and a column AD111. Moreover, the above-mentioned CDS circuit and the like may be included. In the case of a configuration having column AD111, the column memory 104 is a digital memory, and the output circuit 107 also includes components such as an LVDS driver.

Further, as in the other modification shown in FIG. 13, a configuration without the selection switch 206 may be used.

FIG. 14 is a bird's-eye view of the outline of the image sensor according to the third embodiment. Regions 1 and 2 are chips formed on different semiconductor substrates, and are mounted in the same package by connecting wirings that need to be electrically connected. That is, when viewed from the top of the package, the area 2 is arranged under the area 1.

In the area 1, pixels 201 are formed on an array in a plurality of rows and a plurality of columns. The above-mentioned φTX, φSEL, and φRES for driving the pixel 201 are supplied from the vertical selection circuit 102 row by row. The vertical signal line 208 that extracts a signal from the pixels is shared by each pixel in the same row. Here, the vertical signal lines 208 in the first to fourth columns are shown as 208_1, 208_2, 208_3, and 208_4, respectively. Regions 1 and 2 have connection points 115 for connecting the vertical signal lines 208 to the column circuit 103. The connection point 115 of the vertical signal line 208_1 is designated as 115_1. Further, the column circuit 103 connected to the vertical signal line 208_1 is indicated by 103_1, and the column memory 104 connected to the column circuit 103_1 is indicated by 104_1. The area 2 includes a horizontal selection circuit 105 for transferring the signal of the column memory 104 to the output circuit 107. The horizontal selection circuit 105 transfers the signal of the column memory 104 to the output circuit 107 in chronological order.

Although not shown, the above-mentioned constant current source 209 is provided in either region 1 or region 2 in addition to the components shown in the illustration. The constant current source 209 may be included in the column circuit 103. In addition, it also has, for example, a timing generator or control circuit that provides timing to the vertical selection circuit 102, the horizontal selection circuit 105, the column circuit 103, and the like, a serial communication interface, a DA converter, and the like.

Since various pulses are supplied to the horizontal selection circuit 105 from a timing generator or the like, it is desirable that the horizontal selection circuit 105 is located near the end of the chip. As shown in FIG. 14, by bringing the connection point 115 near the center in the column direction, the horizontal selection circuit 105 can be arranged in the vertical direction. It is also possible to bring the connection point 115 to the vicinity of the periphery in the column direction.

Since the cross-sectional structure of the image pickup device according to the present embodiment is substantially the same as that of the first embodiment shown in FIG. 5, illustration and description thereof will be omitted.

As shown in FIG. 14, since the connection points 115 are shared by the pixels of each row on each vertical signal line (column signal line), the number of connection points is increased as compared with the case where each pixel has a connection point. Since the number is small, it is possible to solve the problem that the yield is reduced due to the poor formation of the connection point. Of course, the number of connection points may not be one, but may be several in consideration of the yield. In the present embodiment, by sharing the pixels with the vertical signal line on the region 1 side, it is not necessary to connect the region 1 and the region 2 for each pixel.

Although the first semiconductor substrate in which the light receiving portion is formed by the back-illuminated type is shown here, the front-illuminated type may be used instead of the back-illuminated type. FIG. 15 is a diagram showing a cross-sectional structure of a surface irradiation type of a modified example of the present embodiment. The structure in which the region 1 representing the first semiconductor substrate is laminated on the region 2 representing the second semiconductor substrate is shown. The description of the components having the same reference numerals as those in FIG. 5 will be omitted. In the case of the surface irradiation type, the microlens 509 is installed above the wiring 505 with respect to the semiconductor substrate 501. In the case of the surface irradiation type, a through via 601 is formed to connect the connection point 115 and the component of the region 1.

Since the cross-sectional structure of the fourth embodiment of the present invention in which the surface irradiation type region 1 and the region 2 are formed on the same substrate 501 is substantially the same as that of the second embodiment shown in FIG. Although illustration and description are omitted, as described above, in this case, the connection point 115 is a through via 601 for connecting the vertical signal line 208 and the circuit on the back surface side.

FIG. 16 is a bird's-eye view of the overall configuration of the image sensor according to the fifth embodiment of the present invention. 17 and 18 are diagrams showing examples of modifications thereof, respectively.

Unlike the figure shown in FIG. 14, in the overall configuration of the image sensor of the fifth embodiment shown in FIG. 16, the connection points 115, 115_1 and 115_2 are displaced in the direction along the row, so that the row circuits 103_1 and 103_2 are displaced. It is possible to place the connection point 115 in the immediate vicinity of. As a result, the wiring length in the region 2 is shortened, and the column circuit 103 and the like can be arranged more efficiently.

In the modified example of FIG. 17, by shifting the connection points 115_1, 115_2, 115_3, and 115_4, the arrangement of the column circuits 103_1 to 110_4 can be sparsely arranged. As shown in FIG. 14, when the column circuit 103 is unevenly arranged in the screen compatible area, the heat generated by the column circuit 103 is concentrated, and the PD202 that receives the heat from the column circuit 103 causes the captured image to be in the screen compatible area. Non-uniformity of dark current occurs. However, by adopting the configuration as shown in FIG. 17, for example, evenly arranging, it is possible to reduce the non-uniformity of the dark current due to the heat generation of the column circuit 103 in the screen corresponding region. In FIG. 17, the column circuit 103 is distributed by reversing the arrangement of the column circuit 103_1 and the column memory 104_1 and the column circuit 103_3 and the column memory 104_3. Therefore, the output signal line 106 is also arranged in the center in the direction along the row. However, in the case of FIG. 18 in which the column circuit 103 and the column memory 104 can be configured to be sufficiently small, it is not necessary, and the column circuits 103_1 and 103_3 may be arranged in the same direction.

As described above, by shifting the connection points 115 for each row, it is possible to perform an efficient arrangement and an arrangement that reduces the influence of heat generation of the row circuit 103.

FIG. 19 is a bird's-eye view of the overall configuration of the image sensor according to the sixth embodiment of the present invention. 20 and 21 are diagrams showing examples of modifications thereof, respectively.

In FIGS. 14, 16, 17, and 18, the column circuit 103 and the column memory 104 are described as circuits having a width of two columns in the direction along the row, but in the present invention, other configurations can be adopted. , It is not limited to the configuration. For example, as shown in FIG. 19, the circuit may be one column wide in the direction along the row. However, the column circuit 103 and the column memory 104 become circuits whose length increases in the direction along the column, resulting in a further vertical length. Since the column circuit 103 and the column memory 104 are separated from the adjacent column circuit 103 and the column memory 104 in the element separation region, it is more area efficient to form them in an region closer to a square. The modified example of FIG. 20 has a width of four columns in the direction along the row. Although it looks horizontally long on the schematic diagram, such a layout is also possible by shifting the connection points 115 for each column in order to make it closer to a square. As shown in the modified example of FIG. 21, by increasing the width of the column circuit 103 and the column memory 104 in the direction along the row, it is possible to arrange a plurality of output signal lines 106. Since the output signal line 106 does not consume electric power, heat generation can be dispersed by increasing the number of output signal lines 106 and arranging them between the column circuit 103 and the column memory 104.

FIG. 22 is a bird's-eye view of the overall configuration of the image sensor according to the seventh embodiment of the present invention. The layout of FIG. 22 is the same as that of FIG. 17, but if the column circuit 103 and the column memory 114 are small, there will be a gap between the circuits. If the column AD as shown in FIG. 12 is installed, the digital circuit 1401 can be installed. The digital circuit 1401 can also perform various correction processing such as gamma correction processing and image processing such as white balance adjustment on the signal from the column memory 104. Not limited to the arrangement shown in FIGS. 17 and 21, by arranging the column circuits 103 in a distributed manner, the digital circuit 1401 is also arranged in a distributed manner, and the non-uniformity of dark current due to heat generated from the digital circuit 1401 can be reduced. Is possible. Further, when the column AD is installed, the horizontal selection circuit 105 is not always necessary.

FIG. 23 is a bird's-eye view of the overall configuration of the image sensor according to the eighth embodiment of the present invention. In FIG. 23, the connection point 115 is biased up and down. In this case, the non-uniformity of the dark current cannot be reduced, but it is effective for forming the penetrating via as shown in FIGS. 15 and 8. When the characteristics of the pixel 201 in the vicinity of the connection point 115 are poor due to the formation of the penetrating via, the connection points 115 can be moved to the top and bottom, which are relatively inconspicuous on the screen, to make the image inconspicuous.

FIG. 24 is a bird's-eye view of the outline of the image pickup device according to the ninth embodiment of the present invention. 25 and 26 are diagrams showing examples of modifications thereof, respectively.

In the above-described configuration, the vertical selection circuit 102 is configured in the region 1 and the output circuit 107 is configured in the region 2, but the present invention is not limited to this. As shown in FIG. 24, the output circuit 107 may be in region 1. In this case, the output signal line 106 and the output circuit 107 are connected in the area 1 and the area 2. As schematically shown in FIG. 24, the sizes of region 1 and region 2 do not have to be the same. Further, as shown in the modified example of FIG. 25, a part of the vertical selection circuit 102 may be in the area 1 and a part of the vertical selection circuit 102 may be in the area 2. In such a configuration, in the vertical selection circuit 102, the drive buffer for driving the pixel 201 can be brought to the area 1, and the digital part can be brought to the area 2. Further, as shown in FIG. 26, it is possible to bring the output circuit 107 in the vertical direction instead of the horizontal direction. When the column circuit is small in the vertical direction, it is possible to make the sizes of the area 1 and the area 2 almost the same by adopting such a configuration.

The configuration and operation of the digital camera, which is an image pickup device using the image pickup elements of the embodiments and modifications described above, are the same as those described above with reference to FIG. 10, and thus the description thereof will be omitted.

Moreover, the object of this invention is achieved by performing the following processing. That is, a program in which a storage medium in which a program code of software that realizes the functions of the above-described embodiment is recorded is supplied to a system or device, and a computer (or CPU, MPU, etc.) of the system or device is stored in the storage medium. This is the process of reading the code.

In this case, the program code itself read from the storage medium realizes the function of the above-described embodiment, and the program code and the storage medium storing the program code constitute the present invention.

Further, as a storage medium for supplying the program code, the following can be used. For example, floppy (registered trademark) disks, hard disks, optical magnetic disks, CD-ROMs, CD-Rs, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs, DVD + RWs, magnetic tapes, non-volatile memories. Cards, ROMs, etc. Alternatively, the program code may be downloaded over the network.

The present invention also includes a case where the function of the above embodiment is realized by executing the program code read by the computer. In addition, when the OS (operating system) or the like running on the computer performs a part or all of the actual processing based on the instruction of the program code, and the processing realizes the function of the above-described embodiment. Is also included.

Further, the case where the function of the above-described embodiment is realized by the following processing is also included in the present invention. That is, the program code read from the storage medium is written in the memory provided in the function expansion board inserted in the computer or the function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU or the like provided in the function expansion board or the function expansion unit performs a part or all of the actual processing.

1 area 2 areas 101 pixels 102 Vertical selection circuit 103 column read circuit 104 column memory 105 horizontal selection circuit 106 signal line 107 Output circuit