Methods and apparatus for soft data generation for memory devices based on performance factor adjustment
Abstract
Provided are methods and devices for soft data generation of memory devices. By obtaining at least one hard reading for at least one soft data value and generating soft data values associated with at least one hard reading based on statistics for reading the hard reading. Generated for memory devices. Hard readings can include one or more of data bits, voltage levels, current levels, and resistance levels. The soft data values generated are (i) the soft readings used to generate one or more log-likelihood ratios and (ii) one or more of one or more log-likelihood ratios. Can include more than one. Statistics include one or more of bit-based and cell-based statistics. The statistics can optionally include pattern-dependent disturbances of at least one aggressor cell with respect to the target cell as well as position-specific statistics. For at least one soft data value, obtaining a soft reading and generating a soft data value related to the soft reading based on the statistics for reading the soft reading, the statistics are position specific. It can be generated for a memory device by generating, including one or more of statistics and pattern-dependent statistics.

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Projected expiry 30 September 2029.
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46 claims: 5 independent, 41 dependent
- 1メモリ・デバイスの少なくとも1つの軟データ値を生成する方法であって、 少なくとも1つの硬読取値を入手することと、 前記硬読取値を読み取るための統計に基づいて前記少なくとも1つの硬読取値に関連する前記軟データ値を生成することと を含む方法。
- 2前記硬読取値は、データ・ビット、電圧レベル、電流レベル、および抵抗レベルのうちの1つまたは複数を含む、請求項1に記載の方法。
- 3前記硬読取値は、軟データおよび硬データのうちの1つまたは複数を含む、請求項1に記載の方法。
- 4前記軟データ値は、1つまたは複数の対数尤度比を生成するのに使用される軟読取値を含む、請求項1に記載の方法。
- 5前記軟データ値は、1つまたは複数の対数尤度比を含む、請求項1に記載の方法。
- 6前記ステップのうちの1つまたは複数は、コントローラ、読取チャネル、信号処理ユニット、およびデコーダのうちの1つまたは複数によって実施される、請求項1に記載の方法。
- 7前記統計は、少なくとも1つの確率密度関数を含む、請求項1に記載の方法。
- 8前記統計は、複数のワード線にまたがって平均をとられ、前記平均をとられた統計は、前記軟データ値を生成するのに使用される、請求項1に記載の方法。
- 9前記統計は、ビット・ベースの統計、セル・ベースの統計、およびパターン依存統計のうちの1つまたは複数を含む、請求項1に記載の方法。
- 10別々のセル・ベースの統計は、前記メモリ・デバイス内の複数のワード線について維持される、請求項9に記載の方法。
- 111つまたは複数の可能なレベルLVL writ に関する前記セル・ベースの統計は、前記書込レベルLVL writ が書き込まれたか復号された時にレベルLVL read が読み取られた確率に基づく、請求項9に記載の方法。
- 121つまたは複数の可能なレベルLVL read に関する前記セル・ベースの統計は、前記読取レベルLVL read が読み取られた時にレベルLVL writ が書き込まれたか復号された確率に基づく、請求項9に記載の方法。
- 13前記メモリ・デバイス内の少なくとも1つのアグレッサ・セルについて格納されたデータを表す値 を入手するステップをさらに含む、請求項1に記載の方法。
- 14前記値 は、硬データおよび軟データのうちの1つまたは複数を含む、請求項13に記載の方法。
- 15前記入手するステップは、前記少なくとも1つのアグレッサ・セルを読み取るステップをさらに含む、請求項13に記載の方法。
- 16前記入手するステップは、前記少なくとも1つのアグレッサ・セルが配置される1つまたは複数のページまたはワード線を読み取るステップをさらに含む、請求項13に記載の方法。
- 17前記統計は、ターゲット・セルに対する外乱の表示を含む、請求項1に記載の方法。
- 18前記外乱は、バック・パターン依存、セル間干渉、プログラム妨害、読取妨害、および追加の雑音のうちの1つまたは複数を含む、請求項17に記載の方法。
- 19前記統計は、ターゲット・セルに対する少なくとも1つのアグレッサ・セルのパターン依存外乱を含む、請求項1に記載の方法。
- 201つまたは複数の識別されたパターンに関するおよび1つまたは複数の可能な基準レベルLVL ref に関する前記パターン依存統計は、前記基準レベルLVL ref が復号されたか書き込まれた時にレベルLVL read が読み取られた確率に基づく、請求項19に記載の方法。
- 211つまたは複数の識別されたパターンに関するおよび1つまたは複数の可能な読取レベルLVL read に関する前記パターン依存統計は、前記読取レベルLVL read が読み取られた時に基準レベルLVL ref が復号されたか書き込まれた確率に基づく、請求項19に記載の方法。
- 22前記統計は、位置固有統計を含み、前記軟データ値は、前記メモリ・デバイスの所望の位置について生成される、請求項1に記載の方法。
- 23少なくとも1つの所有の位置に関するおよび1つまたは複数の可能な基準レベルLVL ref に関する前記位置固有統計は、前記基準レベルLVL ref が復号されたか書き込まれた時にレベルLVL read が前記所望の位置で読み取られた確率に基づく、請求項22に記載の方法。
- 24少なくとも1つの所有の位置に関するおよび1つまたは複数の可能な読取レベルLVL read に関する前記位置固有統計は、前記読取レベルLVL read が前記所望の位置で読み取られた時に基準レベルLVL ref が復号されたか書き込まれた確率に基づく、請求項22に記載の方法。
- 25前記統計は、格納されたテーブルおよび式のうちの1つまたは複数として表される、請求項1に記載の方法。
- 26前記統計は、ガウス近似を使用して表される、請求項1に記載の方法。
- 27前記軟データ値をデコーダに供給するステップをさらに含む、請求項1に記載の方法。
- 28前記軟データ値は、前記デコーダに反復して供給される、請求項27に記載の方法。
- 29前記軟データ値は、前記デコーダに供給され、前記デコーダは、新しい軟データ値を計算し、前記新しい軟データ値は、前記反復プロセスが収束するまで、反復的な形で処理される、請求項28に記載の方法。
- 30前記メモリ・デバイスは、フラッシュ・メモリ・デバイスである、請求項1に記載の方法。
- 31前記メモリ・デバイスは、セルあたり少なくとも2つのデータ・レベルsを格納することができる、請求項1に記載の方法。
- 32前記入手するステップは、セル内の複数のビットを読み取るステップをさらに含む、請求項1に記載の方法。
- 33前記入手するステップは、ワード線内の1つまたは複数のページを読み取るステップをさらに含む、請求項1に記載の方法。
- 34前記統計は、確率と確率分布の平均または分散とのうちの1つまたは複数を含む、請求項1に記載の方法。
- 35前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含み、ここで、 は、レベルsが前記メモリ・デバイスに書き込まれたという条件で前記硬読取値 が読み取られる確率である、請求項1に記載の方法。
- 36前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含み、ここで、 は、前記硬読取値 が読み取られるという条件でレベルsが前記メモリ・デバイスに書き込まれた確率である、請求項1に記載の方法。
- 37前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含み、ここで、 は、レベルsが前記メモリ・デバイスに書き込まれたという条件で、前記硬読取値 が読み取られ、パターン が1つまたは複数のアグレッサ・セルに格納される確率である、請求項1に記載の方法。
- 38前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含み、ここで、 は、前記硬読取値 が読み取られ、1つまたは複数のアグレッサ・セル内のパターンが、 であるという条件でレベルsが前記メモリ・デバイスに書き込まれた確率である、請求項1に記載の方法。
- 39前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含む、請求項1に記載の方法。
- 40前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含み、ここで、複数の状態の電圧分布は、実質的に類似する標準偏差σ(s)=σを有する、請求項1に記載の方法。
- 41前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含み、ここで、複数の状態の電圧分布は、実質的に類似する標準偏差σ(s)=σを有する、請求項1に記載の方法。
- 42前記軟データ値は、 として計算される1つまたは複数の対数尤度比を含む、請求項1に記載の方法。
- 43メモリ・デバイスの少なくとも1つの軟データ値を生成する方法であって、 軟読取値を入手することと、 前記軟読取値を読み取るための統計に基づいて前記軟読取値に関連する前記軟データ値を生成することであって、前記統計は、位置固有統計およびパターン依存統計のうちの1つまたは複数を含む、生成することと を含む方法。
- 44前記軟読取値は、デコーダから入手される、請求項43に記載の方法。
- 45メモリ・デバイスの少なくとも1つの軟データ値を生成するシステムであって、前記システムは、 メモリと、 前記メモリに結合され、 少なくとも1つの硬読取値を入手し、 前記硬読取値を読み取るための統計に基づいて前記少なくとも1つの硬読取値に関連する前記軟データ値を生成する ように動作可能な少なくとも1つのプロセッサと を含む、システム。
- 46メモリ・デバイスの少なくとも1つの軟データ値を生成するシステムであって、前記システムは、 メモリと、 前記メモリに結合され、 軟読取値を入手し、 前記軟読取値を読み取るための統計に基づいて前記軟読取値に関連する前記軟データ値を生成する ように動作可能な少なくとも1つのプロセッサであって、前記統計は、位置固有統計およびパターン依存統計のうちの1つまたは複数を含む、少なくとも1つのプロセッサと を含む、システム。
Independent claims46
351 paragraphs, as filed
Cross-reference of related applications This application is incorporated herein by reference in US Provisional Application No. 61 / 194,751 filed on September 30, 2008 and International Application No. PCT / US09 / 49333 filed on June 30, 2009, respectively. It claims the priority of the issue and the name "Methods and MFP for Soft Demapping and Intercell Interference Mitigation in Flash Memories".
Each application is filed at the same time as the present application and is incorporated herein by reference in an international application, entitled "Methods and MFP for Soft Data Generation for Memory Devices Based on Performance Factor Adjustment", an international application, in the name "Methods and". Related to "VMware for Soft Data Generation for Memory Devices Using Reference Cells" and the international application, named "Methods and MFP for Soft Data Generation for Memory Devices Using Decoder Performance Feedback".
The present invention relates generally to flash memory devices, and more specifically to cell-to-cell interference, back pattern dependency, noise, and other such flash memory devices. For improved soft demapping and soft data generation techniques to reduce strain.
Multiple memory devices, such as flash memory devices, use analog memory cells to store data. Each memory cell stores an analog value, also called a storage value, such as charge or voltage. The storage value represents the information stored in the cell. For example, in a flash memory device, each analog memory cell typically stores a certain voltage. The range of possible analog values for each cell is divided into threshold regions, each region corresponding to one or more data bit values. The data is written to an analog memory cell by writing a nominal analog value corresponding to one or more desired bits.
For example, a single-level cell (SLC) flash memory device stores one bit per memory cell (ie, two possible memory states). On the other hand, multi-level cell (MLC) flash memory devices store multiple bits per memory cell (ie, each cell has four or more programmable states). For a more detailed discussion of MLC flash memory devices, see, for example, International Application No. PCT / US09 / 36810, filed March 11, 2009, entitled "Methods and," which is incorporated herein by reference. See "VMware for Storing Data in a Multi-Level Cell Flash Memory Device with Cross-Page Sectors, Multi-Page Coding And Per-Page Coding".
For example, in a multi-level NAND flash memory device, a floating gate device is used with a programmable threshold voltage that is divided into multiple intervals, each interval corresponding to a different multi-bit value. To program a given multibit value into a memory cell, program the threshold voltage of the floating gate device in the memory cell to the threshold voltage interval corresponding to that value.
Analog values stored in memory cells are often distorted. Distortion is usually due, for example, back pattern dependence (BPD), noise, and cell-to-cell interference (ICI). For a more detailed discussion of distortion in flash memory devices, see, for example, JDLee et al., "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation," IEEE Electron, which are incorporated herein by reference, respectively. Device Letters, pp. 264-266 (May 2002), or Ki-Tae Park et al., "A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories", IEEE J .of Solid State See Circuits, Vol.43, No.4, pp. 919-928 (April 2008).
Several techniques have been proposed or advocated to mitigate the effects of ICI and other disturbances. For example, Ki-Tae Park et al. Are existing in mitigating ICI, such as even / odd programming, bottom up programming, and multi-stage programming. Explains programming techniques. International Application No. PCT / US09 / 49333, named "Methods and MFP for Soft Demapping and Intercell Interference Mitigation in Flash Memories," filed on June 30, 2009, is for soft demapping and disturbance mitigation in flash memory. The method and device are disclosed.
<p><patcit num="1"><text>US Provisional Application No. 61 / 194,751</text></patcit><patcit num="2"><text>International Application No. PCT / US09 / 49333</text></patcit><patcit num="3"><text>International application, named "Methods and MFP for Soft Data Generation for Memory Devices Based on Performance Factor Adjustment"</text></patcit><patcit num="4"><text>International application, named "Methods and MFP for Soft Data Generation for Memory Devices Using Reference Cells"</text></patcit><patcit num="5"><text>International application, named "Methods and MFP for Soft Data Generation for Memory Devices Using Decoder Performance Feedback"</text></patcit><patcit num="6"><text>International Application No. PCT / US09 / 36810</text></patcit><patcit num="7"><text>U.S. Pat. No. 6,522,580</text></patcit><patcit num="8"><text>International Application No. PCT / US09 / 49326</text></patcit><patcit num="9"><text>International Application No. PCT / US09 / 49327</text></patcit><patcit num="10"><text>International Application No. PCT / US09 / 49328</text></patcit></p>
<p><nplcit num="1"><text>JDLee et al., "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation", IEEE Electron Device Letters, pp. 264-266 (May 2002)</text></nplcit><nplcit num="2"><text>Ki-Tae Park et al., "A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories", IEEE J.of Solid State Circuits, Vol.43, No.4, 919 ~ 928 pages (April 2008)</text></nplcit><nplcit num="3"><text>AJ Blanksby and CJ Howland, "A 690-mW 1-Gb / s 1024-b, Rate-1 / 2 Low-Density Parity-Check Decoder", IEEE J.Solid-State Circuits, Vol.37, pp. 404-412 (2002) March)</text></nplcit><nplcit num="4"><text>DEHocevar, "LDPC Code Construction With Flexible Hardware Implementation", IEEE Int'l Conf.on Comm. (ICC), Anchorage, Alaska, USA, pp. 2708-2712 (May 2003)</text></nplcit><nplcit num="5"><text>RNS Ratnayake, EF Haratsch, and Gu-Yeon Wei, "A Bit-node centric architecture for low-density parity check decoders," IEEE Global Telecommunications Conference (Globecom), Washington, District of Columbia, USA, pp. 265-270 (November 2007)</text></nplcit><nplcit num="6"><text>E.Yeo et al., "VLSI Architectures for Iterative Decoders in Magnetic Recording Channels", IEEE Trans.On Magnetics, Vol.37, No.2, pp. 748-755 (March 2001)</text></nplcit></p>
<p> These existing methods have helped improve the decryption performance of flash memory, but they are subject to multiple constraints, which, if overcome, can further improve the reliability of flash memory. it can. For example, current flash memory typically supplies only hard data to the flash control system for decryption. However, it is well known that soft data can improve the error rate performance of the decoding process. Therefore, there is a need for soft data generation techniques that use hard data from flash memory to estimate or improve the quality of soft data, thereby improving decoding performance.</p>
<p> Generally, a method and an apparatus for generating soft data of a memory device are provided. According to one aspect of the invention, at least one soft data value is associated with at least one hard reading and at least one hard reading based on statistics for reading the hard reading. Generated for a memory device by generating a data value. Hard readings can include soft or hard data (or a combination thereof), such as one or more of data bits, voltage levels, current levels, and resistance levels. The soft data values generated can include (i) soft readings used to generate one or more log-likelihood ratios or (ii) one or more log-likelihood ratios.</p><p> Statistics can include one or more of bit-based statistics, cell-based statistics, and pattern-dependent statistics. One or more possible levels LVL<sub>writ</sub>Cell-based statistics for write level LVL<sub>writ</sub>Level LVL when was written or decrypted<sub>read</sub>Can be based on the probability that is read. Alternatively, one or more possible levels LVL<sub>read</sub>Cell-based statistics on read level LVL<sub>read</sub>Level LVL when is read<sub>write</sub>Can be based on the probability that was written or decrypted.</p><p> Statistics can also include pattern-dependent disturbances in at least one aggressor cell with respect to the target cell. One or more possible reference levels LVL for one or more identified patterns<sub>ref</sub>Pattern-dependent statistics for reference level LVL<sub>ref</sub>Level LVL when was decrypted or written<sub>read</sub>Can be based on the probability that is read. Alternatives are for one or more identified patterns and one or more possible read levels LVL.<sub>read</sub>Pattern-dependent statistics about read level LVL<sub>read</sub>Reference level LVL when<sub>ref</sub>Can be based on the probability that was decrypted or written.</p><p> According to a further aspect, the statistics can include location-specific statistics and soft data values are generated for the desired location of the memory device. For at least one possession position and one or more possible reference levels LVL<sub>ref</sub>Position-specific statistics for reference level LVL<sub>ref</sub>Level LVL when was decrypted or written<sub>read</sub>Can be based on the probability that is read at the desired position. Alternatives are for at least one owned position and one or more possible read levels LVL<sub>read</sub>Position-specific statistics about read level LVL<sub>read</sub>Reference level LVL when is read in the desired position<sub>ref</sub>Can be based on the probability that was decrypted or written.</p><p> According to another aspect of the invention, at least one soft data value obtains a soft reading and generates a soft data value associated with the soft reading based on statistics for reading the soft reading. That is, statistics are generated for memory devices by generating, including one or more of position-specific statistics and pattern-dependent statistics.</p><p> A more complete understanding of the present invention and further features and benefits of the present invention can be obtained by reference to the following detailed description and drawings.</p>
<figref num="1">It is a schematic block diagram which shows the conventional flash memory system.</figref><figref num="2">It is a figure which shows the exemplary threshold voltage distribution of the exemplary flash memory of FIG.</figref><figref num="3">It is a figure which shows the architecture of the exemplary flash cell array in a multi-level cell (MLC) flash memory device.</figref><figref num="4">It is a figure which shows the example 2 stage MLC programming method of the voltage allocation method of FIG.</figref><figref num="5A">It is a figure which collectively shows the alternative MLC programming method which reduces the ICI added to the adjacent cell.</figref><figref num="5B">It is a figure which collectively shows the alternative MLC programming method which reduces the ICI added to the adjacent cell.</figref><figref num="6">It is a figure which shows the example flash cell array in a multi-level cell (MLC) flash memory device in more detail.</figref><figref num="7">FIG. 5 shows the disturbances present for a target cell due to multiple exemplary aggressor cells such as cell-to-cell interference, back pattern dependence, noise, and other distortions.</figref><figref num="8">FIG. 6 is a schematic block diagram showing an exemplary flash memory system incorporating controller-based soft demapping / soft data generation techniques according to the present invention.</figref><figref num="9">FIG. 6 is a schematic block diagram showing an exemplary flash memory system incorporating memory-based soft demapping / soft data generation techniques according to an alternative embodiment of the present invention.</figref><figref num="10">FIG. 5 illustrates an exemplary flash read channel architecture with iterative demapping and decoding as well as optional interleaving.</figref><figref num="11">FIG. 5 illustrates an exemplary flash memory system using soft data generation according to the present invention.</figref><figref num="12A">It is a flow chart explaining an exemplary soft demapping process and an exemplary soft data generation process.</figref><figref num="12B">It is a flow chart explaining an exemplary soft demapping process and an exemplary soft data generation process.</figref><figref num="13">It is a figure which shows the example bipartite graph representation of the LDPC (low-density parity-check) code.</figref><figref num="14">It is a block diagram which shows an exemplary LDPC decoder architecture.</figref><figref num="15">FIG. 5 illustrates an exemplary flash memory system using soft data generation according to an embodiment of the present invention.</figref><figref num="16">A trellis showing the error probabilities p and q of an exemplary binary channel.</figref><figref num="17A">FIG. 5 shows an exemplary cell-based statistical table that records statistics on reading data from flash memory.</figref><figref num="17B">FIG. 5 shows an exemplary cell-based statistical table that records statistics on reading data from flash memory.</figref><figref num="17C">FIG. 5 shows an exemplary cell-based statistical table that records statistics on reading data from flash memory.</figref><figref num="18">FIG. 5 shows an exemplary pattern-dependent cell-based statistical table that records pattern-dependent statistics for reading data from flash memory.</figref><figref num="19">It is a figure which shows the example flash cell array of FIG. 3 in more detail with respect to the reference cell embodiment of this invention.</figref><figref num="20">It is a flow chart explaining the exemplary embodiment of the bit-based statistics generation process concerning the reference cell embodiment of this invention.</figref><figref num="21">It is a flow chart explaining the exemplary embodiment of the cell-based statistics generation process concerning the reference cell embodiment of the present invention.</figref><figref num="22">It is a flow diagram explaining the exemplary embodiment of the bit-based statistic generation process concerning the decoded codeword embodiment of the present invention.</figref><figref num="23">FIG. 5 is a flow chart illustrating an exemplary embodiment of a cell-based statistic generation process for a decoded codeword embodiment of the present invention.</figref><figref num="24">FIG. 5 illustrates a flow diagram illustrating an exemplary bit-based position-specific statistics generation process for calculating error probability statistics for multiple different locations in a memory array.</figref><figref num="25">FIG. 5 illustrates a flow diagram illustrating an exemplary cell-based position-specific statistics generation process for calculating statistics for multiple different locations within a memory array.</figref><figref num="26">FIG. 5 shows a population of probability density functions showing the effects of pattern-dependent disturbances on a given target cell, based on all possible values for each aggressor cell.</figref><figref num="27">A flow diagram illustrating an exemplary bit-based pattern-dependent statistic generation process that estimates error-probability statistics that depend on a given data pattern in one or more aggressor cells associated with at least one target cell. Is.</figref><figref num="28">A flow diagram illustrating an exemplary cell-based pattern-dependent statistic generation process that estimates statistics that depend on a given data pattern in one or more aggressor cells associated with at least one target cell. ..</figref><figref num="29">It is a flow diagram explaining the exemplary asymmetric statistics generation process for estimating the error probability statistics of two possible binary values of the reference cell embodiment of the present invention.</figref><figref num="30">It is a flow diagram explaining an exemplary asymmetric statistics generation process for estimating error probability statistics of two possible binary values of the decoded codeword embodiment of the present invention.</figref><figref num="31">It is a flow diagram explaining an exemplary embodiment of a statistics generation process using an unsatisfied parity check.</figref><figref num="32">It is a flow diagram illustrating an exemplary position-specific statistics generation process that estimates error probability statistics for multiple different locations in a memory array using unsatisfied parity checks.</figref><figref num="33">It is a flow diagram illustrating an exemplary asymmetric statistics generation process that estimates error probability statistics for two possible binary values using unsatisfied parity checks.</figref>
Various aspects of the invention are directed to soft data generation techniques for improved decoding in memory devices such as single-level cell or multi-level cell (MLC) NAND flash memory devices. As used herein, multi-level cell flash memory includes memory in which each memory cell stores multiple bits. Usually, multiple bits stored in one flash cell belong to different pages. Although the present invention is exemplified herein using a memory cell that stores an analog value as a voltage, as will be apparent to those skilled in the art, the present invention can be expressed as a voltage or to represent stored data. It can be used with any storage mechanism of a memory device, such as using electrical current.
FIG. 1 is a schematic block diagram of a conventional flash memory system 100. As shown in FIG. 1, an exemplary flash memory system 100 includes a flash control system 110 and a flash memory block 160. An exemplary flash control system 110 includes a flash controller 120, an encoder / decoder block 140, and one or more buffers 145. In an alternative embodiment, the encoder / decoder block 140 and some buffers 145 can be implemented inside the flash controller 120. Encoder / decoder block 140 and buffer 145 can be implemented using, for example, well-known commercially available techniques and / or products.
An exemplary flash memory block 160 includes a memory array 170 and one or more buffers 180, each of which can be implemented using well-known commercially available techniques and / or products. The memory array 170 can be used as single-level or multi-level cell flash memory, such as NAND flash memory, phase change memory (PCM), MRAM memory, NOR flash memory, or another non-volatile flash memory. Can be carried out. The present invention is illustrated primarily in the context of multi-level cell NAND flash memory, but as will be apparent to those of skill in the art, the present invention applies to single-level cell flash memory and other non-volatile memories. can do.
Multi-level cell flash memory In multi-level cell NAND flash memory, threshold detectors are typically used to convert voltage values associated with a particular cell to a predefined memory state. FIG. 2 shows an exemplary threshold voltage distribution of the exemplary multi-level cell flash memory 170 of FIG. 1, based on the teachings of US Pat. No. 6,522,580 incorporated herein by reference. In general, the threshold voltage of a cell is the voltage that needs to be applied to the cell in order for the cell to carry a certain amount of current. The threshold voltage is a measurement of the data stored in the cell.
In the exemplary embodiment shown in FIG. 2, each storage element uses four possible data states to store two bits of data within each memory cell. FIG. 2 shows four peaks 210 to 213, and each peak corresponds to one state. In multi-level cell flash devices, different peaks 210-213 of the threshold voltage distribution graph 200 are used to store 2 bits in the cell.
Peaks 210-213 of the threshold voltage distribution graph 200 are labeled with the corresponding binary values. Therefore, when a cell is in the first state 210, the cell has a "1" for the lower bit (less significant bit, also referred to as LSB) and a "1" for the upper bit (most significant bit, also referred to as MSB). ". State 210 is generally the initial unprogrammed or erased state of the cell. Similarly, when a cell is in the second state 211, it represents "0" for the lower bit and "1" for the upper bit. When a cell is in the third state 212, the cell represents "0" for the lower bit and "0" for the upper bit. Finally, when a cell is in the fourth state 213, it represents "1" for the lower bit and "0" for the upper bit.
The threshold voltage distribution 210 is the threshold voltage V of cells in the array in the erased state (11 data state) with a negative threshold voltage level of less than 0 volts.<sub>t</sub>Represents the distribution of. Assuming that the threshold voltage distributions 211 and 212 of the memory cells that store the user data "10" and "00", respectively, are between 0 and 1 volts and between 1 and 2 volts, respectively. It is shown. Threshold voltage distribution 213 shows the distribution of cells programmed to be in the "01" data state, with a threshold voltage level set between 2 and 4.5 volts of the read path voltage.
Thus, in the exemplary embodiment of FIG. 2, 0 volt, 1 volt, and 2 volt can be used as voltage level thresholds between each level or state. These voltage level thresholds are used by the flash memory 160 (eg, the sensing circuit in the flash memory 160) to determine the voltage level or state of a given cell. The flash memory 160 allocates one or more bits to each cell based on the comparison of the measured voltage against the voltage level threshold, and this allocation is then sent to the flash control system 110 as a hard decision. In an embodiment in which soft information is used in addition to or instead, the flash memory 160 can send the measured voltage or a quantized version of the measured voltage as soft information to the flash control system 110. Here, more bits than the number of bits stored in the memory cell are used to represent the measured voltage.
Also note that cells are usually programmed using well-known programming / verification techniques. Generally, during a program / verification cycle, the flash memory 160 gradually applies an increasing voltage to store charge in the cell transistor until the minimum target threshold voltage is exceeded. For example, when programming the "10" data state in the example in Figure 2, the flash memory 160 gradually increases the voltage to store charge in the cell transistor until it exceeds the minimum target threshold voltage of 0.4V. Can be applied to.
As further described below, each of the two bits stored in a single memory cell is from a different page. In other words, each of the two bits stored in each memory cell bears a different page address. The right bit shown in Figure 2 is accessed when the lower page address is entered. The left bit is accessed when the top page address is entered.
Figure 3 shows the architecture of an exemplary flash cell array 300 in a multi-level cell (MLC) flash memory device 160, where each exemplary cell typically floats to store 2 bits. Corresponds to gate transistors. In Figure 3, each cell is associated with two numbers on the two pages to which the two bits belong. An exemplary cell array section 300 shows the word lines n to n + 2 and four bit lines. An exemplary flash cell array 300 is divided into even and odd pages, for example, cells with even numbers (such as cells with numbers 0 and 2) correspond to even pages and have odd numbers. (For example, cells with numbers 1 and 3) correspond to odd pages. The word line n stores, for example, even pages 0 and 2 on an even bit line and odd pages 1 and 3 on an odd bit line.
In addition, FIG. 3 shows an exemplary programming sequence in which either even-bit line cells or odd-bit line cells are selected and programmed sequentially (bottom-up) in the order shown. The numbers indicate the order in which the pages are programmed. For example, page 0 is programmed before page 1. For further discussion of even page and outcome page programming, see K.-T.Park et al., A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB, incorporated herein by reference. Please refer to "Program Scheme for MLC NAND Flash Memories", IEEE Journal of Solid-State Circuits, Vol.43, No.4, pp. 919-928 (April 2008).
FIG. 4 shows an exemplary two-stage MLC programming method 400 for the voltage allocation method of FIG. As shown in FIG. 4, during the LSB programming stage, the state of the selected cell in erase state 410 moves to the lowest programmed state 411 when LSB is 0. Therefore, in the LSB programming state, the memory cell is programmed from the erase state "11" to "10". Then, during the MSB program stage, two states, state "00" (412) and state "01" (413), are sequentially formed according to the previous LSB data. Generally, during the MSB programming state, the "10" state is programmed to "00" and the state "11" is programmed to "01".
Note that programming scheme 400 in Figure 4 shows the maximum voltage shift associated with the state change from state 410 to state 413. Multiple programming schemes have been proposed or advocated to reduce the maximum voltage shift associated with changing states, thereby reducing the ICI caused by the voltage shift.
Figures 5A and 5B collectively show alternative MLC programming schemes 500 that reduce the ICI applied to adjacent cells. As shown in Figure 5A, during the LSB programming stage, memory cells are programmed from state "11" to state "x0" as a temporary (or intermediate) state, similar to SLC programming. To. After the adjacent cells within the same word line are also LSB programmed, the distribution is widened, probably due to ICI, as shown by peak 510 in FIG. 5A. Then, at the MSB programming stage shown in Figure 5B, the "x0" state is programmed to either "00" or "10" as the final state corresponding to the input data, or the "11" state is Programmed to the final "01" state. In general, all memory cells except cell "11" are reprogrammed from the temporarily programmed state for LSB data to their final state at the MSB programming stage, resulting in caused by adjacent cells. ICI can be significantly reduced. The cells in the final state have been reprogrammed to the final state and are not damaged by the ICI experienced during the intermediate state. The final state cell is only damaged by the ICI experienced since it was in the final state. As noted above, the multi-step programming sequence of Figures 5A and 5B, using intermediate program states, reduces maximum voltage changes and thus reduces the ICI caused by these voltage changes. It can be seen in Figure 5B that, for example, the maximum voltage shift during the MSB programming stage is associated with the transition from state "11" to "01" and from state "x0" to state "10", respectively. These voltage shifts are significantly smaller than the maximum voltage shift from state "11" to "01" in FIG.
FIG. 6 shows in more detail an exemplary flash cell array 600 in a multi-level cell (MLC) flash memory device 130. As shown in FIG. 6, the flash cell array 600 has three bits c per flash cell.<sub>i</sub>To store. Figure 6 shows a one-block flash cell array architecture, where each exemplary cell typically corresponds to a floating gate transistor that stores 3 bits. An exemplary cell array 600 consists of m word lines and n bit lines. Normally, in current multi-page cell flash memory, the bits in a single cell belong to different pages. In the example of Figure 6, the three bits in each cell correspond to three different pages, and each wordline stores three pages. In the following discussion, pages 0, 1, and 2 are referred to as the lower page level, middle page level, and upper page level in the wordline.
As shown above, the flash cell array can be further subdivided into even and odd pages, for example, cells with even numbers (such as cells 2 and 4 in Figure 6) correspond to even pages. However, cells with odd numbers (such as cells 1 and 3 in FIG. 6) correspond to odd pages. In this case, the page (such as page 0) contains an even page (even page 0) in an even cell and an odd page (odd page 0) in an odd cell.
Cell-to-cell interference and other disturbances FIG. 7 shows the disturbances present for target cell 710 due to multiple exemplary aggressor cells 720, such as cell-to-cell interference, back pattern dependence, noise, and other distortions. It is used in the following notation or in Figure 7. WL word line, BL bit wire, BLo odd bit line, BLe even bit lines, and C capacitance.
For example, ICI is triggered by aggressor cell 720, which is programmed after target cell 710 is programmed. ICI is the voltage V of target cell 710<sub>t</sub>To change. In an exemplary embodiment, a "bottom-up" programming scheme is assumed, where the proximity aggressor cells in word lines i and i + 1 trigger the ICI of target cell 710. Using such bottom-up programming of blocks, ICI from the lower word line i-1 is removed and up to 5 adjacent cells are aggressor cells, as shown in Figure 7. Contribute to ICI as 720. However, it should be noted that, as will be apparent to those of skill in the art, the techniques disclosed herein can be generalized if aggressor cells from other word lines, such as word line i-1, also contribute to ICI. I want to. If the aggressor cells from the word lines i-1, i, and i + 1 contribute to the ICI, then up to eight closest adjacent cells need to be considered. Other cells farther from the target cell can be ignored if their contribution to ICI is negligible. In general, the aggressor cell 720 is identified by analyzing a programming sequence scheme (such as bottom-up or even / odd techniques) to identify the aggressor cell 720 that is programmed after a given target cell 710. Will be done.
Generally, V<sub>t</sub>Is a voltage representing the data stored in the cell and is obtained during the reading operation. V<sub>t</sub>By reading operation, for example, as a soft voltage value with higher accuracy than the number of bits stored per cell, or as a hard voltage level with the same resolution as the number of bits stored per cell (eg, 3 bits / cell). -It can be obtained as a value quantized into (3 bits) for flash.
For a more detailed discussion of ICI mitigation techniques, see, for example, International Application No. PCT / US09 / 49326, entitled "Methods and MFP for Read-Side Intercell Interference Mitigation in Flash Memories," which are incorporated herein by reference, respectively. Or refer to International Application No. PCT / US09 / 49327, name "Methods and MFP for Write-Side Intercell Interference Mitigation in Flash Memories".
Soft data generation The present invention provides a soft demapping technique and a soft data generation technique for flash memory. In one exemplary embodiment, further described below in connection with FIG. 12A, the enhanced soft data is a probability density function, its approximation, a bit-based probability, or a cell-based probability. Generated from soft data allocated by flash memory using statistics. In another exemplary embodiment, further described below in connection with FIG. 12B, soft data uses probability statistics such as probability density functions, their approximations, bit-based probabilities, or cell-based probabilities. Generated from hard data allocated by flash memory. Generally, the data allocated by flash memory is obtained first. The present invention then generates, or enhances, soft information such as probability or reliability information based on data from flash memory. The generated soft information can optionally be used for soft decision decoding. As used herein, the term "probability density function" shall include a probability density function and its approximations such as histograms and Gaussian approximations.
FIG. 8 is a schematic block diagram of an exemplary flash memory system 800 incorporating the controller-based soft data generation technique according to the present invention. As shown in FIG. 8, the exemplary flash memory system 800 includes a flash control system 810 and a flash memory block 860 connected by interface 850. An exemplary flash control system 810 includes a flash controller 820 and a read channel 825, which are typically one or more integrated circuits.
An exemplary read channel 825 includes a signal processing unit 830, an encoder / decoder block 840, and one or more buffers 845. Note that the term "read channel" can also include write channels. In an alternative embodiment, the encoder / decoder block 840 and some buffers 845 can be implemented inside the flash controller 820. Encoder / decoder block 840 and buffer 845 can be implemented using, for example, well-known commercially available techniques and / or products modified herein to provide the features and functionality of the present invention. ..
The exemplary signal processing unit 830 includes one or more soft demappers and / or one or more processors that perform the soft data generation process 835, which are further described below, for example in connection with FIGS. 12A and 12B, respectively. An exemplary flash memory block 860 includes a memory array 870 and one or more buffers 880 that can be implemented using well-known commercially available techniques and / or products, respectively.
In various embodiments of the soft data generation techniques disclosed, the exemplary interface 850 needs to convey additional information related to traditional flash memory systems, such as values representing information related to the aggressor cell. In some cases. Therefore, the interface 850 may need to have a larger capacity or faster rate than the interface in a traditional flash memory system. Interface 850 is optionally incorporated herein by reference, International Application No. PCT / US09 / 49328, filed June 30, 2009, entitled "Methods and MFP for Interfacing Between a Flash Memory Controller and. a Flash Memory It can be carried out according to the teachings of "Array" (Patent Attorney Reference No. 08-0769), and the teachings of this international application No. PCT / US09 / 49328 use, for example, the double data rate (DDR) technique. Increase the information transfer capacity of the interface 850. During the write operation, interface 850 transfers program values stored in the target cell, typically using page-level access techniques or word-line-level access techniques. For a more detailed discussion of exemplary page-level access techniques or word-line level access techniques, see, for example, International Application No. PCT filed March 11, 2009, incorporated herein by reference. / US09 / 36810, name "Methods and MFP for Storing Data in a Multi-Level Cell Flash Memory Device with Cross-Page Sectors, Multi-Page Coding and Per-Page Coding".
During the read operation, the interface 850 transfers hard and / or soft reads obtained from the memory array 870 for the target and aggressor cells. For example, in addition to the readings of the page with the target cell, the readings of one or more adjacent pages in the upper / lower word lines or adjacent even or odd bit lines are sent through the interface bus. Will be transferred. In the embodiment of FIG. 8, the disclosed soft data generation technique is performed outside of flash memory, typically with process technology optimized for logic circuits to achieve a minimum area. However, this comes at the expense of additional aggressor cell data that may be transferred over interface 850.
FIG. 9 is a schematic block diagram of an exemplary flash memory system 900 incorporating a memory-based soft data generation technique according to an alternative embodiment of the present invention. As shown in FIG. 9, an exemplary flash memory system 900 includes a flash control system 910 and a flash memory block 960 connected by interface 950.
An exemplary flash control system 910 includes a flash controller 920 and an optional read channel 925, which are usually one or more integrated circuits. In an alternative embodiment, the encoder / decoder block 940 and some buffers 945 can be implemented inside the flash controller 920. An exemplary flash controller 920 can be implemented using, for example, well-known commercially available techniques and / or products modified herein to support the features and functions of the present invention. An exemplary read channel 925 includes an encoder / decoder block 940 and one or more buffers 945. Encoder / decoder block 940 and buffer 945 can be implemented using well-known commercially available techniques and / or products.
An exemplary flash memory block 960 includes a memory array 970 and one or more buffers 980, each of which can be implemented using well-known commercially available techniques and / or products. In addition, the exemplary flash memory block 960 performs one or more soft demapping and / or soft data generation processes 990, which are further described below in connection with, for example, FIGS. 12A and 12B, respectively. Includes an exemplary signal processing unit 985 that includes the processor of.
In various embodiments of the soft data generation techniques disclosed, the exemplary interface 950 needs to convey additional information related to traditional flash memory systems, such as values representing information related to the aggressor cell. In some cases. Therefore, the interface 950 may need to have a larger capacity or faster rate than the interface in a traditional flash memory system. Interface 950, optionally incorporated herein by reference, International Application No. PCT / US09 / 49328, filed June 30, 2009, entitled "Methods and MFP for Interfacing Between a Flash Memory Controller and It can be carried out according to the teachings of "a Flash Memory Array" (Patent Attorney No. 08-0769), and the teachings of this international application No. PCT / US09 / 49328 use, for example, the double data rate (DDR) technique. Use to increase the information carrying capacity of Interface 950.
During the write operation, interface 950 transfers program data stored in the target and aggressor cells. During the read operation, interface 950 transfers new hard read, hard data, soft read, or soft data in the target cell (s) and optionally the aggressor cell. Usually, the information conveyed for a single read access is one page or one word line of data. Sending only the data in the target cell is soft data inside the memory using the memory process technology used to make flash memory, which is usually optimized for memory rather than logic. Note that it reduces the bandwidth requirement of interface 950 at the expense of performing the generation process.
Figure 10 shows International Application No. PCT / US09 / 49333 filed on June 30, 2009, incorporated herein by reference, in the name "Methods and MFP for Soft Demapping and Intercell Interference Mitigation in Flash." An exemplary flash read channel architecture 1000 with iterative demapping and decoding and optional interleaving according to the teachings of "Memories" is shown. As shown in FIG. 10, exemplary write paths include an encoder 1010, an optional interleaver 1020, a series-parallel converter 1030, and a mapper 1040. The data is written to and read from memory 1050 in a known manner. An exemplary read path includes a soft demapper or soft data generator 1060, a parallel series converter 1070, a deinterleaver 1080, a decoder 1090, and an interleaver 1095. In general, as described further below, a soft demapper or soft data generator 1060 is a decoder that iteratively generates new soft information and feeds it back to the soft demapper until the iterative process converges on the final decision. Generates the soft information further described below, processed by 1090.
The equation used by the soft demapper 1060 to generate soft information (LLR) according to the present invention is described in the section entitled "Calculation of soft data (LLR) using read statistics" below. As shown in FIG. 10, the soft information generated by the soft demapper 1060 can be used for iterative demapping and decoding between the soft demapper 1060, the deinterleaver 1080, the decoder 1090, and the interleaver 1095 in the feedback path. Can be used.
Soft data generation based on data from flash The present invention allows current flash memories 860, 960 to normally supply only hard data to flash control systems 810, 910. However, it is well known that soft data can improve error rate performance in the decoding process. Therefore, according to one aspect of the invention, the hard data from the flash memories 860, 960 is used to estimate the soft data, thereby improving the decoding performance in the flash control systems 810, 910. For example, as will be described later, the statistical properties of hard data can be used to estimate or improve the quality of soft data. The generated soft data can then be used for decoding, such as belief propagation decoding of LDPC codes, to improve error rate performance.
According to another aspect of the invention, the flash memories 860, 960 supply soft data or soft information to the flash control systems 810, 910. Higher quality soft data is generated from the soft data supplied by the flash memories 860, 960, which improves the decoding performance in the flash control systems 810, 910. In an embodiment that uses soft information, the flash memory systems 860, 960 send the measured voltage or a quantized version of the measured voltage as soft information to the flash control systems 810, 910, where they are stored in memory cells. More bits than the number of bits are used to represent the measured voltage.
FIG. 11 shows an exemplary flash memory system 1100 using controller-based soft data generation according to an embodiment of the present invention. As shown in FIG. 11, the exemplary flash memory system 1100 includes a flash memory block 1110 and a flash control system 1120 connected by interface 1115. As will be described later, soft and / or hard data values can be allocated by flash memory block 1110 and transferred to flash control system 1120 via interface 1115 for further decoding and processing. Will be done. An exemplary flash control system 1120 includes a soft demapper / soft data generator 1200, which is further described below in relation to FIGS. 12A and 12B, and a decoder 1400, which is further described below in relation to FIGS. 13-14. The decoder 1400 can be implemented using LDPC decoding algorithms, such as belief propagation, message passing, Sum-Product, or Min-Sum algorithms.
As shown in FIG. 11, the soft information generated by the soft demapper / soft data generator 1200 is optionally iteratively demapped between the soft demapper / soft data generator 1200 and the decoder 1400. It can be used for decryption. In general, as shown in Figure 11, the soft demapper / soft data generator 1200 is in the form of an LLR, as described in the section entitled "Calculating soft data (LLR) using read statistics" below. Soft information L<sub>e</sub>To generate. LLR, L initially calculated by the soft demapper / soft data generator 1200<sub>e</sub>Is based on soft and / or hard reads from flash memory 1100 and the corresponding statistics. LLR, L<sub>e</sub>Is processed by decoder 1400 and new soft information L<sub>a</sub>To generate this soft information L<sub>a</sub>Is iteratively fed back to the soft demapper / soft data generator 1200 until the iterative process converges to the final decision.
Soft demapper / soft data generator 1200 FIG. 12A is a flow diagram illustrating an exemplary soft demapping process 1200 incorporating features of the invention to generate enhanced soft data from soft data supplied by flash memories 860, 960. is there. As shown in Figure 12A, the exemplary soft demapping process 1200 initially obtains the soft data r of the target cell from flash memory 860, 960 during step 1210 and optionally targets the target. · Obtain one or more values h that represent the data stored in the aggressor cell (s) associated with the cell.
The soft demapping process 1200 then obtains r and optionally h-based statistics (or probabilities), such as one or more probability density functions, during step 1220. This statistic is further described in the section entitled "Collecting Statistics" below.
Then, during step 1230, the LLR (s) are calculated using the statistics obtained. The LLR (s) are described in the section entitled "Calculation of Soft Data (LLR) Using Read Statistics" below. Then, during step 1240, the calculated LLR is fed to the decoder 1400 or optionally to the deinterleaver. The calculated LLR can optionally be used to make a final decision on the read data, for example based on the code of the LLR.
FIG. 12B is a flow diagram illustrating an exemplary soft data generation process 1250 incorporating features of the invention to generate soft data from hard data supplied by flash memories 810, 910. As shown in Figure 12B, the exemplary soft data generation process 1250 initially performed the hard data of the target cell during step 1260.
<maths num="1"><img file="JP2012504841A_D0001.tif" /></maths>Is obtained from flash memory 810, 910 and optionally represents one or more values stored in the aggressor cell (s) associated with the target cell.
<maths num="2"><img file="JP2012504841A_D0002.tif" /></maths>To get. Hard data
<maths num="3"><img file="JP2012504841A_D0003.tif" /></maths>Can be, for example, a binary bit or level assigned to each cell by flash memories 810, 910.
The other bits are unavailable to calculate the LLR of one bit in the cell, and the other bits in the cell are read using, for example, page access and wordline access techniques. For a more detailed discussion of exemplary page-level access techniques and word-line level access techniques, see, for example, International Application No. PCT / filed March 11, 2009, incorporated herein by reference. See US09 / 36810, name "Methods and MFP for Storing Data in a Multi-Level Cell Flash Memory Device with Cross-Page Sectors, Multi-Page Coding and Per-Page Coding". Using the page access technique, the page on which the LLR is being calculated is read, and optionally other pages within the same wordline can also be read, resulting in hard data at the cell level.
<maths num="4"><img file="JP2012504841A_D0004.tif" /></maths>You will be able to map to. The wordline access technique can be used to read the entire wordline to obtain all the bits in the cell, from which the hard data level
<maths num="5"><img file="JP2012504841A_D0005.tif" /></maths>Is obtained.
For example, a pattern by reading a bit from the aggressor cell 720 (or the page or word line that contains the aggressor cell 720).
<maths num="6"><img file="JP2012504841A_D0006.tif" /></maths>Is obtained. For a more detailed discussion of techniques for reading aggressor cells, see, for example, International Application No. PCT / US09 / 49326, name "Methods and MFP for Read-Side Intercell Interference Mitigation in Flash," which is incorporated herein by reference. See "Memories".
The soft data generation process 1250 then, during step 1270, includes one or more probability density functions, etc.
<maths num="7"><img file="JP2012504841A_D0007.tif" /></maths>And optionally
<maths num="8"><img file="JP2012504841A_D0008.tif" /></maths>Get statistics (or probabilities) based on. This statistic can also be a bit-based or cell-based probability, as described further in the section entitled "Collecting Statistics" below. When a Gaussian approximation of the distribution of soft readings is used, this statistic is the mean of the distribution or, as described in the section entitled "Calculating Soft Data (LLR) Using Reading Statistics" for the Gaussian approximation formula. Including dispersion. Mean and variance can be pre-calculated and stored in a table during a flash memory chip property test for different performance factors such as program / erase cycle, read cycle, and temperature. Optional mean and variance based on performance factors, pattern stored in aggressor cell 720
<maths num="9"><img file="JP2012504841A_D0009.tif" /></maths>Can also be obtained from the table based on.
The LLR (s) are then calculated using the statistics obtained during step 1280. The LLR (s) are described in the section entitled "Calculation of Soft Data (LLR) Using Read Statistics" below. A priori LLR L supplied by the decoder in addition to or instead of statistics, as described in the section entitled "Calculating Soft Data (LLR) Using Read Statistics".<sub>a</sub>Note that you can optionally use to calculate the LLR. A priori LLR L when the LLR of the bits in a cell is calculated<sub>a</sub>Is used for at least one bit in the cell (optionally all other bits). It has these other bits in the cell read and is a priori LLR L<sub>a</sub>Requires that has been calculated for them by the decoder.
Then, during step 1290, the calculated LLR is fed to the decoder 1400 or optionally to the deinterleaver. The calculated LLR can optionally be used to make a final decision on the read data, for example based on the code of the LLR. International application No. PCT / US09 / 36810, which filed all bits in a cell (or all pages in a word line) on March 11, 2009, named "Methods and MFP for Storing Data in a Multi-Level". Note that it can be jointly encoded and decoded as described in "Cell Flash Memory Device with Cross-Page Sectors, Multi-Page Coding and Per-Page Coding". In another embodiment, the bits in the cell (or all pages in the wordline) can be encoded and decoded separately, also as described in International Application No. PCT / US09 / 36810. ..
Decoder 1400 LDPC Embodiment The following background discussion of LDPC codes and LDPC decoding is incorporated herein by reference by AJ Blanksby and CJ Howland, "A 690-mW 1-Gb / s 1024-b, Rate-1 / 2 Low-Density". Based on the discussion of "Parity-Check Decoder", IEEE J. Solid-State Circuits, Vol.37, pp. 404-412 (March 2002). For a more detailed discussion, readers should refer to the entire Blanksby and Howland treatises.
Graph representation of LDPC code The LDPC code can be represented using a bipartite graph, in which one set of nodes represents a parity check constraint and the other set represents data bits. FIG. 13 is a diagram showing an exemplary bipartite graph representation 1300 of an LDPC code. The parity check matrix is the join matrix of the graph, where the bit node i corresponding to the column i of H is the item h of H.<sub>ji</sub>If is set or non-zero, it is connected to the check node j corresponding to line j of H.
One algorithm used to decode LDPC codes is known as the sum-product algorithm. For good decoding performance using this algorithm, it is important that the cycle length in the graph representation of the LDPC code is as long as possible. The exemplary representation of FIG. 13 illustrates an exemplary short cycle of length 4. Short cycles, such as the 4 cycle shown in Figure 13, degrade the performance of the sum-product algorithm. Another well-known algorithm for decoding LDPC codes is the min-sum algorithm.
Sum-Product algorithm The sum-product algorithm is an iterative algorithm for decoding LDPC codes. The sum-product algorithm is also known as a message passing algorithm or belief propagation. For a more detailed discussion of the sum-product algorithm, see, for example, AJ Blanksby and CJ Howland, "A 690-mW 1-Gb / s 1024-b," which are incorporated herein by reference, respectively. Rate-1 / 2 Low-Density Parity-Check Decoder ", IEEE J.Solid-State Circuits, Vol.37, pp. 404-412 (March 2002), DEHocevar," LDPC Code Construction With Flexible Hardware Implementation ", IEEE Int'l Conf.on Comm. (ICC), Ancollage, Alaska, USA, pp. 2708-2712 (May 2003), and RNS Ratnayake, EF Haratsch, and Gu-Yeon Wei, "A Bit-node centric architecture for low-" See "density parity check decoders", IEEE Global Telecommunications Conference (Globecom), Washington, District of Columbia, USA, pp. 265-270 (November 2007).
Message Q from bit node i to check node j<sub>i, j</sub>Is
<maths num="10"><img file="JP2012504841A_D0010.tif" /></maths>Given by, where L<sub>e, i</sub>Is an outpatient LLR supplied by the bit i soft demapper / soft data generator. Message R from check node j to bit node i<sub>j, i</sub>Is
<maths num="11"><img file="JP2012504841A_D0011.tif" /></maths>Given by, here,
<maths num="12"><img file="JP2012504841A_D0012.tif" /></maths>And
<maths num="13"><img file="JP2012504841A_D0013.tif" /></maths>Is. Inductive information value Λ, also known as the inductive log-likelihood ratio (LLR) of bit i<sub>i</sub>Is
<maths num="14"><img file="JP2012504841A_D0014.tif" /></maths>Given by.
Bit i LLR L fed to the soft demapper / soft data generator for iterative demapping and decoding<sub>a, i</sub>Is
<maths num="15"><img file="JP2012504841A_D0015.tif" /></maths>Given as, here B<sub>i</sub>Is a set of check nodes connected to bit node i, C<sub>j</sub>Is a set of bit nodes connected to check node j.
LDPC Decoder Hardware Shared Decoder Architecture An important issue when implementing a sum-product algorithm that decrypts LDPC codes is managing the passing of messages. Since the functionality of both the check node and the bit node is relatively simple, their respective implementations use only a few gates. The main issue is the implementation of the bandwidth required to pass messages between functional nodes.
FIG. 14 is a block diagram of an exemplary hardware shared LDPC decoder architecture 1400. As shown in Figure 14, the generalized LDPC decoder architecture 1400 sends messages with multiple functional units 1410, 1420, each performing either check node functionality or bit node functionality. Includes memory fabric 1450 to store and provide graph connectivity. Control logic 1430 controls the configuration of memory fabric 1450. For a detailed discussion of the embodiments of the hardware shared LDPC decoder architecture 1400, see, for example, E.Yeo et al., "VLSI Architectures for Iterative Decoders in Magnetic Recording Channels", IEEE Trans.On Magnetics, Vol.37, No.2. , Pp. 748-755 (March 2001).
Such a hardware sharing architecture has been recognized to reduce the area of the decoder.
FIG. 15 shows an exemplary flash memory system 1500 using soft data generation according to an embodiment of the present invention. As shown in FIG. 15, an exemplary flash memory system 1500 includes a flash memory block 1510. As will be described later, hard and / or soft data values are typically allocated by the flash memory block 1510 and transferred to the flash control system 1520 via interface 1515 for further decoding and processing. Will be done. An exemplary flash control system 1520 includes the LLR generator 1550, further described in connection with FIG. 16 below, the statistics generator (s) 1570, further described in the section entitled "Collecting Statistics" below, and the decoder 1530. including. Statistics Generator (s) The statistics generated by the 1570 are optionally recorded in one or more statistics tables 1560, which are further described below, for example in connection with Figures 17A to 17C and 18, or instead. , Can be generated in real time.
Statistics Generator (s) The statistics generated by the 1570 are used by the LLR Generator 1550, for example LLR, L<sub>e</sub>Generates soft data in the form of. Initially, LLR, L<sub>e</sub>Is based on soft and / or hard reads from flash memory 1510 and the corresponding statistics. LLR, L<sub>e</sub>Is processed by the decoder 1530 and the new soft information L<sub>a</sub>To generate this soft information L<sub>a</sub>Is iteratively fed back to the LLR generator 1550 until the iterative process converges on the final decision.
The decoder 1530 can also be implemented using LDPC decoding algorithms such as belief propagation, message passing, Sum-Product, or Min-Sum algorithms. The functions of the statistics generator 1570 and LLR generator 1550 described herein can be performed on one or more of the flash control system 1520, decoder 1530, and read channel 825 (see, eg, FIG. 8). Please note.
Calculation of soft data (LLR) using read statistics Bit c a priori log-likelihood ratio (LLR) L<sub>a</sub>Can be defined as:
<maths num="16"><img file="JP2012504841A_D0016.tif" /></maths>Where P (...) is a probability.
Similarly, the LLR of bit c conditioned on the flash output r is calculated as follows:
<maths num="17"><img file="JP2012504841A_D0017.tif" /></maths>Where L<sub>e</sub>(c) is the foreign LLR or soft information passed to the subsequent decoder, and p (...) is the probability density function (PDF).
FIG. 16 is a trellis 1600 showing the error probabilities p and q of an exemplary binary channel. Note that in the context of binary channels, p represents the probability of error, otherwise p (...) represents the probability density function. If p q, this binary channel is asymmetric. If p = q, this binary channel is symmetric. As shown in FIG. 16, p is the binary 0 error probability (ie, the probability of reading 1 when 0 is written). Similarly, q is the binary 1 error probability (ie, the probability of reading 0 when 1 is written). The probability of reading binary 0 correctly (ie, the probability of reading 0 when 0 is written) can be expressed as 1-p. Similarly, the probability of reading a binary 1 correctly (ie, the probability of reading a 1 when a 1 is written) can be expressed as 1-q.
Outpatient LLR with binary asymmetric channels Foreign LLR, L of bit c of binary asymmetric channel defined by trellis 1600<sub>e</sub>(c) can be expressed as follows.
<maths num="18"><img file="JP2012504841A_D0018.tif" /></maths>
Read bit
<maths num="19"><img file="JP2012504841A_D0019.tif" /></maths>Outpatient LLR, L<sub>e</sub>(c) is
<maths num="20"><img file="JP2012504841A_D0020.tif" /></maths>Is calculated as.
Read bit
<maths num="21"><img file="JP2012504841A_D0021.tif" /></maths>Outpatient LLR, L<sub>e</sub>(c) is
<maths num="22"><img file="JP2012504841A_D0022.tif" /></maths>Is calculated as.
Extraneous LLR of binary symmetric channels (where p = q = p<sub>0</sub>) Read bit
<maths num="23"><img file="JP2012504841A_D0023.tif" /></maths>Outpatient LLR, L<sub>e</sub>(c) is
<maths num="24"><img file="JP2012504841A_D0024.tif" /></maths>Is calculated as.
Read bit
<maths num="25"><img file="JP2012504841A_D0025.tif" /></maths>Outpatient LLR, L<sub>e</sub>(c) is
<maths num="26"><img file="JP2012504841A_D0026.tif" /></maths>Is calculated as.
Outpatient LLR with soft output from flash memory For 2-bit / cell flash memory, the foreign LLR can be calculated for the soft value r received from the flash memories 810, 910 as follows.
<maths num="27"><img file="JP2012504841A_D0027.tif" /></maths>
In general, for any number of bits per cell, bit C<sub>i</sub>Outpatient LLR
<maths num="28"><img file="JP2012504841A_D0028.tif" /></maths>Can be expressed as, here, r Received signal s Stored bits (c<sub>0</sub>, c<sub>1</sub>, ... c<sub>m</sub>) Given the original stored state or level c<sub>i</sub> Encoded bits Number of bits per m cell
<maths num="29"><img file="JP2012504841A_D0029.tif" /></maths> A priori LLR L<sub>e</sub>(C<sub>i</sub>) Outpatient LLR
<maths num="30"><img file="JP2012504841A_D0030.tif" /></maths> Its bit label is position i and value C<sub>i</sub>= c<sub>i</sub>Is a subset of states or levels that have Where L<sub>a</sub>(C<sub>i</sub>) Is supplied by a decoder such as the LDPC decoder 1090 or 1400. In the first iteration, L<sub>a</sub>(C<sub>i</sub>) Can be initialized to 0.
Next equivalence
<maths num="31"><img file="JP2012504841A_D0031.tif" /></maths>You can also use to write the formula for an outpatient LLR as follows:
<maths num="32"><img file="JP2012504841A_D0032.tif" /></maths>
This formula,
<maths num="33"><img file="JP2012504841A_D0033.tif" /></maths>Can be further simplified.
This formula is mathematically equivalent to the above formula when all states or levels are likely to be equivalent.
Pattern-dependent outpatient LLR with soft output from flash memory One or more soft values r in the target cell and one or more values in the aggressor cell (s) received from flash memory 810,910
<maths num="34"><img file="JP2012504841A_D0034.tif" /></maths>about,
<maths num="35"><img file="JP2012504841A_D0035.tif" /></maths>Can be shown here,
<maths num="36"><img file="JP2012504841A_D0036.tif" /></maths>Is a data pattern stored in the surrounding cells (s) or other cells that cause disturbances to the target cell. For example
<maths num="37"><img file="JP2012504841A_D0037.tif" /></maths>Represents all aggressor cells close to the target cell at the position (k, l) where the LLR is being calculated.
pattern
<maths num="38"><img file="JP2012504841A_D0038.tif" /></maths>Can be obtained, for example, by reading hard data from the aggressor cell.
The formula for the outpatient LLR can also be written as:
<maths num="39"><img file="JP2012504841A_D0039.tif" /></maths>
This formula,
<maths num="40"><img file="JP2012504841A_D0040.tif" /></maths>Can be further simplified.
This formula is mathematically equivalent to the above formula if all states are likely to be equivalent.
Outpatient LLR with hard output from flash memory Hard data where soft output is not available from flash memory and the flash memory is the state or level allocated to the data stored by the flash memory.
<maths num="41"><img file="JP2012504841A_D0041.tif" /></maths>When supplying only outpatient LLR,
<maths num="42"><img file="JP2012504841A_D0042.tif" /></maths>Can be calculated as, here,
<maths num="43"><img file="JP2012504841A_D0043.tif" /></maths>Is the expected or hard value of the soft value r (voltage, etc.)
<maths num="44"><img file="JP2012504841A_D0044.tif" /></maths>Is some other estimate for the soft value r that assumes.
<maths num="45"><img file="JP2012504841A_D0045.tif" /></maths>Is a hard value (such as a state or level), assuming that the state or level s was first written and stored.
<maths num="46"><img file="JP2012504841A_D0046.tif" /></maths>Is the probability of being read.
Outpatient LLR instead
<maths num="47"><img file="JP2012504841A_D0047.tif" /></maths>Can be calculated as, here,
<maths num="48"><img file="JP2012504841A_D0048.tif" /></maths>Is the hard value (state or level)
<maths num="49"><img file="JP2012504841A_D0049.tif" /></maths>Is the probability that the state or level s was first written or stored, assuming that is read.
Pattern-dependent outpatient LLR of hard output from flash memory Hard data where soft output is not available from flash memory and the flash memory is the state or level allocated to the data stored by the flash memory.
<maths num="50"><img file="JP2012504841A_D0050.tif" /></maths>When supplying only the outpatient LLR, the pattern stored in the aggressor cell
<maths num="51"><img file="JP2012504841A_D0051.tif" /></maths>Can be calculated based on
<maths num="52"><img file="JP2012504841A_D0052.tif" /></maths>here,
<maths num="53"><img file="JP2012504841A_D0053.tif" /></maths>Is the hard value (state or level), assuming that the state or level s was first written and stored.
<maths num="54"><img file="JP2012504841A_D0054.tif" /></maths>Is read and the pattern in the aggressor cell
<maths num="55"><img file="JP2012504841A_D0055.tif" /></maths>Is the probability of being.
<maths num="56"><img file="JP2012504841A_D0056.tif" /></maths>Is a data pattern stored in the surrounding cells (s) or other cells that cause disturbances to the target cell. For example
<maths num="57"><img file="JP2012504841A_D0057.tif" /></maths>Represents all aggressor cells that are close to the target cell at the position (k, l) at which the LLR is being calculated.
pattern
<maths num="58"><img file="JP2012504841A_D0058.tif" /></maths>Can be obtained, for example, by reading the rigid data from the aggressor cell.
Pattern-dependent LLR instead
<maths num="59"><img file="JP2012504841A_D0059.tif" /></maths>Can be calculated as, here,
<maths num="60"><img file="JP2012504841A_D0060.tif" /></maths>Is a hard value (state or level, etc.)
<maths num="61"><img file="JP2012504841A_D0061.tif" /></maths>Is read and the pattern in the aggressor cell
<maths num="62"><img file="JP2012504841A_D0062.tif" /></maths>Is the probability that the state or level s was first written or stored, assuming that.
Outpatient LLR without soft decoder feedback on soft output from flash The soft output from the decoder is not used in the soft demapper / soft data generator (in other words, L<sub>a</sub>(C<sub>i</sub>When) = 0), the outpatient LLR in the soft demapper / soft data generator can be calculated as follows.
<maths num="63"><img file="JP2012504841A_D0063.tif" /></maths>
These outpatient LLRs are then passed to the decoders shown in Figures 10 and 11. The LDPC can then apply a message-passing decoding algorithm for local iterations inside the decoder, for example until the data bits are decoded. In this case, the global detection / decoding iteration between the soft demapper / soft data generator is not performed to reduce the overall computational complexity.
The pattern-dependent LLR can be calculated in this case as follows.
<maths num="64"><img file="JP2012504841A_D0064.tif" /></maths>
Outpatient LLR without hard output soft decoder feedback from flash If the soft data is not available from flash memory and the soft output from the decoder is used to reduce the complexity of the calculation, the extraneous LLR can be calculated as follows:
<maths num="65"><img file="JP2012504841A_D0065.tif" /></maths>here,
<maths num="66"><img file="JP2012504841A_D0066.tif" /></maths>Is the expected or hard value of the soft value r (voltage, etc.)
<maths num="67"><img file="JP2012504841A_D0067.tif" /></maths>Is another estimate with a soft value r that assumes.
<maths num="68"><img file="JP2012504841A_D0068.tif" /></maths>Is a hard value (such as a state or level), assuming that the state or level s was first written and stored.
<maths num="69"><img file="JP2012504841A_D0069.tif" /></maths>Is the probability of being read.
In an alternative embodiment, the LLR
<maths num="70"><img file="JP2012504841A_D0070.tif" /></maths>Can be calculated as, here,
<maths num="71"><img file="JP2012504841A_D0071.tif" /></maths>Is a hard value (state or level, etc.)
<maths num="72"><img file="JP2012504841A_D0072.tif" /></maths>Is the probability that the state or level s was first written or stored, assuming that is read.
The pattern-dependent LLR can be calculated in this case as follows.
<maths num="73"><img file="JP2012504841A_D0073.tif" /></maths>
Gauss approximation of outpatient LLR with soft power from flash If the soft output from flash memory (such as the read threshold voltage) is modeled with a Gaussian distribution, then the soft output p (r) assuming the first stored or written level s. Condition PDF p (r | s)
<maths num="74"><img file="JP2012504841A_D0074.tif" /></maths>Where σ (s) is the standard deviation and E {r | s} is the mean or expected value of the soft output (threshold voltage, etc.) of the state s.
Then, the outpatient LLR
<maths num="75"><img file="JP2012504841A_D0075.tif" /></maths>Can be calculated as.
If the voltage distributions in all states have the same standard deviation σ (s) = σ, then this equation can be simplified to:
<maths num="76"><img file="JP2012504841A_D0076.tif" /></maths>
This formula,
<maths num="77"><img file="JP2012504841A_D0077.tif" /></maths>Can be further simplified.
Gauss approximation of outpatient LLR with hard power from flash When the soft output from flash memory is not available, the LLR can be calculated as follows, assuming the soft output is Gaussian.
<maths num="78"><img file="JP2012504841A_D0078.tif" /></maths>Here, E {r | s} is the average value or expected value of the soft output r (threshold voltage, etc.) with respect to the state s.
<maths num="79"><img file="JP2012504841A_D0079.tif" /></maths>Is the hard output that is the state or level allocated and supplied by the flash memory.
<maths num="80"><img file="JP2012504841A_D0080.tif" /></maths>The average or expected value of the soft output r (threshold voltage, etc.) for.
If the voltage distributions for all states have the same standard deviation σ (s) = σ, then this equation can be simplified to:
<maths num="81"><img file="JP2012504841A_D0081.tif" /></maths>
This formula is further
<maths num="82"><img file="JP2012504841A_D0082.tif" /></maths>Can be simplified to.
Gauss approximation of pattern-dependent outpatient LLR of hard output from flash memory The pattern-dependent LLR of hard power can be calculated as follows when the distribution of soft power is modeled as Gaussian.
<maths num="83"><img file="JP2012504841A_D0083.tif" /></maths>here,
<maths num="84"><img file="JP2012504841A_D0084.tif" /></maths>Is a pattern stored in the aggressor cell, as defined above,
<maths num="85"><img file="JP2012504841A_D0085.tif" /></maths>State s and pattern
<maths num="86"><img file="JP2012504841A_D0086.tif" /></maths>The standard deviation of the soft power distribution with respect to.
The voltage distribution of all states and patterns has the same standard deviation
<maths num="87"><img file="JP2012504841A_D0087.tif" /></maths>If, this equation can be simplified to the following equation.
<maths num="88"><img file="JP2012504841A_D0088.tif" /></maths>
This formula is further
<maths num="89"><img file="JP2012504841A_D0089.tif" /></maths>Can be simplified to.
Gauss approximation of outpatient LLR without soft decoder feedback of soft output from flash memory When soft decoder feedback is not used, the extraneous LLR can be calculated using a Gaussian approximation of the soft power distribution when soft power from flash memory is available:
<maths num="90"><img file="JP2012504841A_D0090.tif" /></maths>
If the voltage distributions in all states have the same standard deviation σ (s) = σ, then this equation can be simplified to:
<maths num="91"><img file="JP2012504841A_D0091.tif" /></maths>
This formula is further
<maths num="92"><img file="JP2012504841A_D0092.tif" /></maths>Can be simplified to.
Gauss approximation of outpatient LLR without soft decoder feedback of hard output from flash memory When soft decoder feedback is not used, the extraneous LLR can be calculated using a Gaussian approximation of the soft power distribution when only hard power from flash memory is available:
<maths num="93"><img file="JP2012504841A_D0093.tif" /></maths>
If the voltage distributions in all states have the same standard deviation σ (s) = σ, then this equation can be simplified to:
<maths num="94"><img file="JP2012504841A_D0094.tif" /></maths>
This formula is further
<maths num="95"><img file="JP2012504841A_D0095.tif" /></maths>Can be simplified to.
The corresponding pattern-dependent LLR is calculated as follows:
<maths num="96"><img file="JP2012504841A_D0096.tif" /></maths>
Standard deviation with the same voltage distribution for all states and patterns
<maths num="97"><img file="JP2012504841A_D0097.tif" /></maths>If, this equation can be simplified to the following equation.
<maths num="98"><img file="JP2012504841A_D0098.tif" /></maths>
This, further
<maths num="99"><img file="JP2012504841A_D0099.tif" /></maths>Can be simplified to.
Read statistics table Figures 17A-17C are exemplary cell-based statistical tables that record statistics on reading data from flash memory. Figure 17A shows (write level (s) and read level (
<maths num="100"><img file="JP2012504841A_D0100.tif" /></maths>)) For a given pair, when the write level (s) is written Read level (
<maths num="101"><img file="JP2012504841A_D0101.tif" /></maths>) Is an exemplary cell-based statistical count table 1700 showing the number of times read. For example, when the write level (s) is also equal to 00, the read level (
<maths num="102"><img file="JP2012504841A_D0102.tif" /></maths>) Was read 10617 times. Furthermore, when the write level (s) is equal to 01, the read level (
<maths num="103"><img file="JP2012504841A_D0103.tif" /></maths>) Was mistakenly read 148 times. The count table 1700 also optionally shows the sum for each row and column. The values in the count table 1700 are used by multiple cell-based statistical processes, described below in relation to Figures 21, 23, 25, and 28.
Figure 17B shows (write level (s) and read level (
<maths num="104"><img file="JP2012504841A_D0104.tif" /></maths>)) For a given pair of reading levels ()
<maths num="105"><img file="JP2012504841A_D0105.tif" /></maths>Probability that write level (s) was written under the condition that) was read
<maths num="106"><img file="JP2012504841A_D0106.tif" /></maths>Is an exemplary cell-based statistical table showing. Figure 17C shows (write level (s) and read level (
<maths num="107"><img file="JP2012504841A_D0107.tif" /></maths>For a given pair of)), the read level (), provided that the write level (s) was written.
<maths num="108"><img file="JP2012504841A_D0108.tif" /></maths>) Was read
<maths num="109"><img file="JP2012504841A_D0109.tif" /></maths>An exemplary cell-based statistical table 1740.
FIG. 18 is an exemplary pattern-dependent cell-based statistics table 1800 that records pattern-dependent statistics for reading data from flash memory in the presence of a given pattern. An exemplary table 1800 shows the (write level (s) and read level (s) and read level (
<maths num="110"><img file="JP2012504841A_D0110.tif" /></maths>)) For a given pair, a given pattern
<maths num="111"><img file="JP2012504841A_D0111.tif" /></maths>Read level (under the condition that write level (s) was written in the presence of
<maths num="112"><img file="JP2012504841A_D0112.tif" /></maths>) Is the pattern
<maths num="113"><img file="JP2012504841A_D0113.tif" /></maths>Probability read in the presence of
<maths num="114"><img file="JP2012504841A_D0114.tif" /></maths>Is shown.
Collection of statistics Statistics collection using reference cells FIG. 19 shows in more detail the exemplary flash cell array of FIG. As shown in Figure 19, the exemplary flash cell array 1900 has multiple reference cells 1920-ref to provide reliable channel estimates or statistics under all operating conditions.<sub>1</sub>From 1920-ref<sub>N</sub>Includes (collectively referred to herein as reference cell 1920).
An exemplary reference cell 1920 is illustrated in FIG. 19 with a chopped background. The reference cell 1920 can be programmed periodically or intermittently using a known pattern, such as a known bit pattern or a known symbol pattern. Note that the reference cells 1920 can be distributed in any desired form, eg, using a consistent and variable number of cells within each wordline, within the flash cell array 1900. .. The position of the reference cell 1920 can be fixed or changed over time, for example to avoid worn or damaged cells. In one embodiment, the position of the reference cell 1920 is fixed and the performance of the same reference cell 1920 can be observed over time. In this fixed position embodiment, the reference cell 1920 can optionally be written and read only once, or as many times as the other cells in the flash memory array.
In a further variant, the position of the reference cell 1920 is changed over time so that the performance of the reference cell 1920 reflects the performance of the entire array 1900. In yet another variant, statistics can be obtained from reference cells 1920 within a number of different arrays 1900, after which the results are averaged.
As further described below, reference cell 1920 is read and compared to known patterns. For example, the probability of detecting an error p<sub>0</sub>The estimate, input as follows can be hand.
<maths num="115"><img file="JP2012504841A_D0115.tif" /></maths>Reference cell programming and reading can optionally be combined with wear-level algorithms that spread consumption across memory in a known way.
In various embodiments, the reference cell 1920 can store all possible levels, has a periodic pattern (if the levels alternate), and is either written periodically or read over time. You can do it.
As will be described later, various embodiments of the present invention collect and use bit-based statistics, cell-based statistics, or pattern-dependent statistics. For embodiments that use bit-based statistics, bit error performance is measured. For embodiments that use cell-based statistics, read statistics are measured on a cell basis. For pattern-dependent statistics, read statistics also describe the data pattern stored in the aggressor cell.
1. Bit-based statistics using reference cells FIG. 20 is a flow chart illustrating an exemplary embodiment of the bit-based statistics generation process 2000 for a reference cell embodiment of the present invention. In general, the bit-based statistics generation process 2000 has a probability of detecting a bit error p.<sub>0</sub>To calculate. Then the probability of detecting an error p<sub>0</sub>Can be used by the LLR generator 1550 (Fig. 15) to calculate the desired soft data. Initially, the statistics generation process 2000 writes a known pattern to one or more reference cells 1920 during step 2010. As previously indicated, the known pattern can be, for example, a known bit pattern or a known symbol pattern.
Then, during step 2020, read the reference cell. The statistics generation process 2000 then determines during step 2030 an error metric, such as the number of erroneous bits in the reference cell 1920. As shown earlier, the reference cell 1920 read during step 2020 can be compared to a known pattern.
During step 2040, the statistics generation process 2000 calculates error probability statistics as follows:
<maths num="116"><img file="JP2012504841A_D0116.tif" /></maths>
2. Cell-based statistics using the reference cell FIG. 21 is a flow chart illustrating an exemplary embodiment of a cell-based statistic generation process 2100 for a reference cell embodiment of the present invention. As shown in FIG. 21, the cell-based statistics generation process 2100 initially writes one or more known voltage levels to the reference cell 1920 during step 2110.
The cell-based statistics generation process 2100 then reads the voltage level from the reference cell 1920 during step 2120. Possible write levels s or LVL<sub>writ</sub>For each cell-based statistic generation process 2100, during step 2130, this write level s or LVL<sub>writ</sub>Each level when is written
<maths num="117"><img file="JP2012504841A_D0117.tif" /></maths>Or LVL<sub>read</sub>Counts the number of times is read.
During step 2140, the error probability statistics are calculated as follows:
<maths num="118"><img file="JP2012504841A_D0118.tif" /></maths>
In the alternative, during step 2140, the error probability statistics can be calculated as follows (reverse case).
<maths num="119"><img file="JP2012504841A_D0119.tif" /></maths>
Note that alternative normalization terms can be used in the denominator of the formula calculated during step 2140.
Statistics collection using decrypted codewords In the decoded codeword embodiment of the present invention, soft data is generated for memory devices such as flash memory devices 810, 910 using data obtained from the decoded codeword as a reference cell. Generally, hard data from a memory device, such as a flash memory device, is decoded to obtain error metrics such as the number of erroneous decoded bits. For example, the number of erroneous decrypted bits can be obtained by comparing the decrypted bits with the hard data obtained from the memory device. In this way, the decoded codeword can be assumed to be correct, and the decoded codeword can serve as the reference cell described above.
1. Bit-based statistics using decoded codewords FIG. 22 is a flow diagram illustrating an exemplary embodiment of the bit-based statistics generation process 2200 for a decoded codeword embodiment of the present invention. In general, the bit-based statistics generation process 2200 uses decoded codewords to detect errors with a probability p.<sub>0</sub>To calculate. Then the probability of detecting an error p<sub>0</sub>Can be used by the LLR generator 1550 (Fig. 15) to calculate the desired soft data. Initially, the statistics generation process 2200 obtains hard data from flash memory during step 2210.
The bit-based statistics generation process (decoded codeword) 2200 then decodes the hard data during step 2220. Error metrics, such as the number of erroneous bits from flash memory, are determined during step 2230. The number of erroneous bits can be determined, for example, by comparing the decoded bits (assumed to be correct) with the hard data from the flash memory.
The statistics generation process 2200 calculates error probability statistics during step 2240 as follows:
<maths num="120"><img file="JP2012504841A_D0120.tif" /></maths>
2. Cell-based statistics using decoded codewords FIG. 23 is a flow diagram illustrating an exemplary embodiment of a cell-based statistical generation process (decoded codeword) 2300 incorporating features of the present invention. In general, the statistics generation process 2300 uses decoded codewords to calculate cell-based error probabilities. Initially, the cell-based statistics generation process 2300 obtains hard data from flash memory during step 2310.
The cell-based statistics generation process (decoded codeword) 2300 then decodes the hard data during step 2320. Then, during step 2325, the decoded bits are mapped to the corresponding voltage level.
Then possible decoded voltage levels s or LVL<sub>decod</sub>For each cell-based statistic generation process (decrypted codeword) 2300, during step 2330, this decoded level s LVL<sub>decod</sub>Each voltage level when
<maths num="121"><img file="JP2012504841A_D0121.tif" /></maths>Or LVL<sub>read</sub>Counts the number of times is read.
During step 2340, the error probability statistics are calculated as follows:
<maths num="122"><img file="JP2012504841A_D0122.tif" /></maths>
In the alternative, error probability statistics can be calculated during step 2340 as follows (reverse case):
<maths num="123"><img file="JP2012504841A_D0123.tif" /></maths>
Condition-specific error probability As shown earlier, error probability statistics, optionally, for different locations in the memory array, for different patterns of aggressor cells, for different temperatures, for different numbers of program / erase or read cycles, etc. Available for different conditions. Soft data can then be obtained using the correct condition-dependent statistics or probabilities when the same conditions are observed.
As described below in relation to Figures 24 and 25, the exemplary position-specific statistics generation processes 2400, 2500 use bit-based and cell-based statistics, respectively, to use different locations in the memory array. Get error probability statistics about.
Bit-based position-specific statistics FIG. 24 is a flow diagram illustrating an exemplary bit-based position-specific statistics generation process 2400 that estimates the probability of detecting bit errors at multiple different locations in a memory array. For example, the probability of detecting an error p<sub>0, LOC</sub>For different page positions, word line positions, bit line positions (such as even and odd bit lines), and different bits in multilevel cells (such as the most significant bit (MSB) and least significant bit (LSB)). Available for one or more of them. As shown in FIG. 24, the exemplary bit-based position-specific statistics generation process 2400 initially, during step 2430, of the reference cell or decoded codeword based on the desired position-specific statistics. Determine the number of erroneous bits at the desired position. For example, if the position-specific statistics are for the MSB, then during step 2430, the number of erroneous MSB bits is evaluated. Note that when MSB statistics are being obtained, all other bits in each cell can optionally be ignored, for example the LSB bit.
The position-specific statistic generation process 2400 then calculates the position-specific error probability statistics during step 2440 as follows.
<maths num="124"><img file="JP2012504841A_D0124.tif" /></maths>
Cell-based position-specific statistics For cell-based position-specific embodiments, the different locations of interest in the memory array are, for example, one of different word line positions or bit line positions (such as even and odd bit lines). Or it can include more than one.
FIG. 25 is an example of obtaining error probability statistics for several different positions in the memory array 1900, such as one or more of different word line positions or bit line positions (such as even and odd bit lines). It is a flow chart explaining the cell-based position-specific statistics generation process 2500. Possible reference voltage levels s or LVL, as shown in Figure 25<sub>ref</sub>For each example cell-based position-specific statistics generation process 2500 initially, during step 2530, this reference level s or LVL.<sub>ref</sub>Each voltage level when was decoded or written
<maths num="125"><img file="JP2012504841A_D0125.tif" /></maths>LVL<sub>read</sub>Counts the number of times is read at the desired position.
The cell-based position-specific statistic generation process 2500 then calculates the position-specific error probability statistics during step 2540 as follows:
<maths num="126"><img file="JP2012504841A_D0126.tif" /></maths>
In the alternative,
<maths num="127"><img file="JP2012504841A_D0127.tif" /></maths>Can be calculated as described above.
In various embodiments of the invention, separate bit-based, cell-based, or pattern-based statistics are provided page by page, word line, or memory array, or group of pages, word line. Can be collected for groups of, or for groups of memory arrays (for example, for different page levels within a wordline, or for lower, middle, and upper wordlines within a memory array). In addition, statistics can be averaged across multiple pages, wordlines, or memory arrays, and then average statistics can be used for these pages, wordlines, or memory arrays.
Pattern-dependent statistics As previously indicated, various embodiments of the present invention have a target cell and one or more values for one or more soft values r.
<maths num="128"><img file="JP2012504841A_D0128.tif" /></maths>About, about Aggressa cell (s), outpatient LLR, L<sub>e</sub>And here,
<maths num="129"><img file="JP2012504841A_D0129.tif" /></maths>Is a data pattern stored in an aggressor cell (enclosing cell (s), etc.).
Figure 26 shows an exemplary population 2600 of probability density functions 2610 for a given target cell 710 in an exemplary multi-level cell flash memory 600, based on all possible values for each aggressor cell 720. Shown. An exemplary multi-level cell flash memory has four levels (2 bits) per cell, with one aggressor cell 720 being considered for data dependent pdf. The number of probability density functions applicable to each possible level of a given target cell 710 is the number of possible levels of each aggressor cell 720, which affects the given target cell 710. It is the product of the number of. As shown earlier, in an exemplary embodiment, each cell can have one of four possible values, there is one aggressor cell 720 per target cell 710, and each aggressor cell. Cell 720 can have one of four possible levels. Therefore, for illustration purposes, the population density function population 2600 includes four probability density functions 2610-1 to 2610-4 for data or voltage level 0 applicable to the pattern of aggressor cells. There are also four probability density functions for each of the other data levels 1, 2, and 3. As will be apparent to those of skill in the art, the present invention can be extended to a multi-level cell flash memory 600 having any number of levels and any number of aggressor cells 720 per cell.
In general, each probability density function in FIG. 26 represents the effect of ICI on a given target cell 710 for a given value in the corresponding aggressor cell 720, among other noise and disturbance effects. In a further embodiment of the invention, the data-dependent probability density function can represent other data-dependent strains instead of or in addition to the ICI. As will be described later, in various embodiments, the probability density function is either predefined static, adapted based on real-time observation, or an aggressor cell, such as a Gaussian function. It can be expressed as a function of 720 measured or detected values h.
According to one aspect of the invention, a disturbance in a flash memory device obtains one or more probability density functions representing a pattern-dependent disturbance of one or more aggressor cells for at least one target cell. The feature can be expressed by doing. Disturbances can include, for example, back pattern dependence, cell-to-cell interference, program interference, read interference, and / or additional noise. The probability density function can be updated based on one or more data judgments. The probability density function can be expressed as a stored table and / or expression.
Also note that the table entry or function parameters of the probability density function can optionally be updated adaptively, eg, based on the data decisions received. For example, the probability density function, the received aggressor pattern
<maths num="130"><img file="JP2012504841A_D0130.tif" /></maths>Can be selected based on. The selected probability density function is then updated with the latest occurrences (for example, by increasing the corresponding counters) using known techniques based on the received target cell value r. ..
As shown earlier, the number of aggressor cells 720 affecting a given target cell 710 can be reduced or ignored based on multiple factors. In this way, the number of probability density functions that need to be considered can be reduced. For example, in an exemplary embodiment of mitigating ICI, the diagonally coupled coefficient k<sub>xy</sub>However, if it is much smaller than the other combining coefficients (as is often the case), the ICI from the diagonally located cell can be ignored. In addition, the programming sequence affects the number of aggressor cells 720 that need to be considered. For example, if the word lines are always written in a fixed order, such as in the bottom-up method, there may be no disturbance ICI contribution from the cells in the lower word line. Furthermore, if the disturbance ICI is symmetric with respect to the left and right neighbors of the target cell 710, the number of probability density functions that need to be characterized is reduced by half.
As shown previously, in one exemplary embodiment, the probability density function can be approximated using a Gaussian probability density function. In a further variant, improved performance can be obtained at the expense of additional complexity, for example when the probability density function is based on a histogram. When the probability density function is performed using a histogram, the probability density function can be adaptively updated by training the histogram with successfully decoded word lines.
In a further embodiment, the probability density function and its approximations can be used by trellis-based detection algorithms such as the Viterbi algorithm, the Soft Power Viterbi (SOVA) algorithm, and the BCJR algorithm to detect the read data. ..
1. Bit-based pattern-dependent statistics FIG. 27 shows a given pattern of one or more aggressor cells 720 associated with at least one target cell 710 (FIG. 7).
<maths num="131"><img file="JP2012504841A_D0131.tif" /></maths>Or the probability of detecting a bit error related to PATT p<sub>0, PATT</sub>It is a flow diagram explaining an exemplary bit-based pattern-dependent statistic generation process 2700 that estimates. Initially, the bit-based pattern-dependent statistics generation process 2700 reads the reference target cell 710 and potentially related aggressor cells (s) 720 during step 2720. Further, during step 2725, the pattern PATT of the associated aggressor cell 720 is identified for each target bit read. This pattern can be identified during step 2725, for example, by evaluating a known pattern written, or based on the actual reading operation of the reference cell or decoded codeword.
During step 2730, for one or more identified patterns, determine the number of erroneous target bits with the corresponding patterns. Then, during step 2740, the error probability statistics are calculated as follows.
<maths num="132"><img file="JP2012504841A_D0132.tif" /></maths>
It should be noted that the techniques described above can optionally be integrated to obtain position-specific pattern-dependent statistics, as will be apparent to those of skill in the art. Moreover, in a further variant, in addition to or instead, read statistics are available as a function of memory device durability, number of read cycles, retention characteristics, temperature, or other parameters.
2. Cell-based pattern-dependent statistics FIG. 28 illustrates an exemplary cell-based pattern-dependent statistics generation process 2800 that estimates the probability of detecting an error in a given pattern of one or more aggressor cells associated with at least one target cell. It is a flow chart to be done. As shown in Figure 28, the cell-based pattern-dependent statistics generation process 2800 initially reads one or more target cells during step 2820. Then, during step 2825, the pattern of related aggressor cells (s)
<maths num="133"><img file="JP2012504841A_D0133.tif" /></maths>Or identify PATT.
Then, during step 2830, for one or more identified patterns, and possible reference voltage levels s or LVL.<sub>ref</sub>For each cell-based pattern-dependent statistic generation process 2800, this reference level s or LVL<sub>ref</sub>Each voltage level when was decoded or written
<maths num="134"><img file="JP2012504841A_D0134.tif" /></maths>Or LVL<sub>read</sub>Counts the number of times is read.
During step 2840, pattern-dependent error probability statistics are calculated as follows:
<maths num="135"><img file="JP2012504841A_D0135.tif" /></maths>
Asymmetric error probability statistics As shown earlier, certain channels, such as NAND flash memory channels, can have very different probabilities of detecting different possible binary value errors, such as binary 0 and binary 1. .. Therefore, the present invention optionally provides a probability of detecting an asymmetric channel error. Figures 29 and 30 provide exemplary asymmetric statistics generation processes 2900, 3000 that estimate error probabilities p and q for two possible binary values, such as binary 0 and binary 1. As further described below, FIG. 29 uses a reference cell to estimate asymmetry statistics, and FIG. 30 uses decoded codewords to estimate asymmetry statistics. Therefore, the present invention provides an asymmetric LLR for each possible binary value based on hard data from flash memory.
Asymmetric error probability-reference cell As shown earlier, certain channels, such as NAND flash memory channels, can have very different probabilities of detecting different possible binary value errors, such as binary 0 and binary 1. .. Therefore, the present invention optionally provides a probability of detecting an asymmetric channel error. FIG. 29 is a flow diagram illustrating an exemplary asymmetric statistics generation process 2900 for estimating the error probabilities of two possible binary values of the reference cell embodiment of the present invention.
As shown in FIG. 29, the asymmetric statistics generation process 2900 initially writes a known pattern in reference cell 1920 during step 2910 and then reads reference cell 1920 during step 2020. The asymmetric statistics generation process 2900 determines the number of erroneous bits with binary 0s in the reference data during step 2930 and then calculates the binary 0 error probability statistics during step 2940 as follows: To do.
<maths num="136"><img file="JP2012504841A_D0136.tif" /></maths>
The asymmetric statistics generation process 2900 then determines the number of erroneous bits with binary 1 in the reference data during step 2950, and then the binary 1 error probability statistics during step 2960 as follows: To calculate.
<maths num="137"><img file="JP2012504841A_D0137.tif" /></maths>
Asymmetric error probability-decrypted codeword FIG. 30 is a flow diagram illustrating an exemplary asymmetric statistics generation process 3000 for estimating the error probabilities of two possible binary values of the decoded codeword embodiments of the present invention. As shown in FIG. 30, the asymmetric statistics generation process 3000 initially obtains the hard data from the flash memory during step 3010 and decodes the hard data during step 3020.
The asymmetric statistics generation process 3000 then determines the number of erroneous bits from the flash memory with binary 0s in the decrypted data during step 3030. Then, during step 3040, the binary 0 error probability statistics are calculated as follows.
<maths num="138"><img file="JP2012504841A_D0138.tif" /></maths>
Similarly, during step 3050, the number of erroneous bits from the flash memory with binary 1 in the decrypted data is determined. Then, during step 3060, the binary 1 error probability statistics are calculated as follows.
<maths num="139"><img file="JP2012504841A_D0139.tif" /></maths>
In one embodiment, statistics can be collected, calculated, and stored while the NAND flash memory is idle (ie, neither actively reading nor writing user data).
An exemplary embodiment used statistical collection using reference cells or decoder feedback, but using detected or decoded data, for example, using the least mean squared error criterion to obtain statistics. Adaptive methods can also be used to estimate.
In an alternative embodiment, statistics or corresponding LLRs are pre-computed for worst-case operating conditions (eg, with respect to number of program / erase cycles, retention time, and temperature), eg, based on experimental property testing of flash memory. And then these can be used for bad channel conditions. In this way, more accurate statistics or LLRs are available when the probability of error is maximum. In other words, predefined statistics or corresponding LLRs can be pre-computed for predefined operating conditions.
In a further variant, soft data can be iteratively generated based on different statistics (such as error probabilities) until successful decoding. Statistics can be modified over a range, up to the detection or decryption of data success. This variant of the invention provides virtual rereading of data. The data is not actually reread from the flash memory, but the data is successfully decoded with different soft information.
Error performance based on unsatisfied parity check Aspects of the invention acknowledge that unsatisfied parity checks can also be used as performance metrics to obtain soft data. (N, K, J, L) We want to consider LDPC codes, where N is the codeword length and K is the uncoded codeword length (user data length within the codeword), J and L. Are the column weights and row weights of the parity check matrix, respectively. (N, K, J, L) LDPC codeword has an error probability p<sub>0</sub>The probability that a checksum will fail on the first iteration when transmitted or stored in is expressed as:
<maths num="140"><img file="JP2012504841A_D0140.tif" /></maths>This probability can be estimated as follows.
<maths num="141"><img file="JP2012504841A_D0141.tif" /></maths>
Therefore, the error probability p<sub>0</sub>Can be estimated as follows.
<maths num="142"><img file="JP2012504841A_D0142.tif" /></maths>
In the above procedure, the channel and initial LLR values can be estimated before performing iterative decoding. The complexity and latency of channel estimation is less than that of one iteration of soft-determined decoding, with significant performance benefits for hard-determined decoding of LDPC codes. Additional hardware compared to the standard embodiment of soft-decision decoding is a block that performs the following calculations.
<maths num="143"><img file="JP2012504841A_D0143.tif" /></maths>
FIG. 31 is a flow diagram illustrating an exemplary embodiment of a statistics generation process 3100 using an unsatisfied parity check according to one aspect of the invention. In one embodiment, an unsatisfied parity check after the first iteration is used. In general, the statistics generation process 3100 uses an unsatisfied parity check to detect an error with a probability p.<sub>0</sub>To calculate. Then the probability of detecting an error p<sub>0</sub>Can be used by the LLR generator 1550 (Fig. 15) to calculate the desired soft data.
Initially, the statistics generation process 3100 obtains the number of unsatisfied parity checks during step 3110. The statistics generation process 3100 then calculates error probability statistics during step 3120 as follows:
<maths num="144"><img file="JP2012504841A_D0144.tif" /></maths>
Position-specific statistics-unsatisfied parity check FIG. 32 is a flow diagram illustrating an exemplary location-specific statistics generation process 3200 that uses unsatisfied parity checking to obtain error probability statistics for multiple different locations within the memory array 1900. For example, error probability statistics for different page positions, word line positions, bit line positions (such as even and odd bit lines), and different bits in multilevel cells (most significant bit (MSB) and least significant bit (most significant bit)). It can be obtained for one or more of (LSB), etc.). Position-specific statistics are generally obtained by using codewords that position bits at desired positions using unsatisfied parity checks (step 3210).
The exemplary position-specific statistics generation process 3200 then obtains the number of unsatisfactory parity checks for codewords during step 3220, as shown in FIG. Then, during step 3230, the position-specific error probability statistics are calculated as follows.
<maths num="145"><img file="JP2012504841A_D0145.tif" /></maths>
Asymmetric statistics based on unsatisfied parity check FIG. 33 is a flow diagram illustrating an exemplary asymmetric statistics generation process 3300 that estimates the probabilities of detecting two possible binary value errors using unsatisfied parity checks. This aspect of the invention has an average error probability.
<maths num="146"><img file="JP2012504841A_D0146.tif" /></maths>Is allowed to be calculated based on unsatisfied parity checks (provided that
<maths num="147"><img file="JP2012504841A_D0147.tif" /></maths>). Average error probability for p and q values
<maths num="148"><img file="JP2012504841A_D0148.tif" /></maths>And the ratio k of the error probabilities p and q.
The error probabilities p to q ratio k can be obtained using data analysis such as the decrypted codeword technique described above. In the alternative, the ratio k of error probabilities p and q is, for example, an international application, named "Methods and MFP for Soft Data Generation for memory devices Using Reference," which was filed at the same time as the present application and incorporated herein by reference. It can be obtained using the reference cell technique described in Cells. The error probability p to q ratio k should normally be calculated offline and stored in a table, for example. As shown in FIG. 33, the exemplary asymmetric statistics generation process (unsatisfied parity check) 3300 initially obtains the ratio k of error probabilities p and q during step 3310.
Average error probability
<maths num="149"><img file="JP2012504841A_D0149.tif" /></maths>Can be obtained during step 3320 using the technique described above in connection with FIG. Specifically, the average error probability
<maths num="150"><img file="JP2012504841A_D0150.tif" /></maths>Can be estimated as follows.
<maths num="151"><img file="JP2012504841A_D0151.tif" /></maths>
Then, during step 3330, the binary 0 error probability statistic p is calculated as follows.
<maths num="152"><img file="JP2012504841A_D0152.tif" /></maths>
Then, during step 3340, the binary 1 error probability statistic q is calculated as follows.
<maths num="153"><img file="JP2012504841A_D0153.tif" /></maths>
Note that the error probability statistics p and q calculated by the asymmetric statistics generation process (unsatisfied parity check) 3300 can optionally be position-specific and / or pattern-dependent.
Process, system, and product details Although the plurality of flow charts herein illustrate an exemplary sequence of steps, it is also an embodiment of the invention that the sequence can be modified. Various substitutions of the algorithm are contemplated as alternative embodiments of the present invention. An exemplary embodiment of the invention has been described for processing steps within a software program, but as will be apparent to those skilled in the art, various functions, in hardware, as processing steps within a software program in the digital domain. It can be implemented by circuit elements or state machines, or by a combination of both software and hardware. Such software can be used, for example, in digital signal processors, application-specific integrated circuits, microcontrollers, or general purpose computers. Such hardware and software can be implemented within circuits implemented within integrated circuits.
Therefore, the functions of the present invention can be carried out in the form of methods and devices that practice these methods. One or more aspects of the invention, for example, either stored in a storage medium, loaded on a machine and / or executed by a machine, or transmitted via a transmission medium. It can be implemented in the form of program code, where when the program code is loaded into a machine, such as a computer, and executed by that machine, that machine becomes a device that practices the invention. .. When implemented on a general purpose computer, a program code segment is combined with a processor to provide a device that behaves like a particular logic circuit. The present invention can also be implemented in one or more of integrated circuits, digital signal processors, microprocessors, and microcontrollers.
As is known in the art, the methods and devices described herein can be distributed as a product that itself comprises a computer-readable medium on which a computer-readable code means is implemented. Computer-readable program code means, in connection with a computer system, to perform all or part of the steps of performing the methods described herein or to create the equipment described herein. It is operational. Computer-readable media can be recordable media (eg, floppy disks, hard drives, compact disks, memory cards, semiconductor devices, chips, application-specific integrated circuits (ASICs)) or transmission. It can be a medium (eg, a network containing fiber optics, a worldwide web, a cable, or a time division multiple access, a code division multiple access, or a radio channel using another radio frequency channel). Any known or developed medium that can store the appropriate information for use with a computer system can be used. Computer-readable code means are all mechanisms that allow a computer to read instructions and data, such as magnetic fluctuations on a magnetic medium or height fluctuations on the surface of a compact disc.
The computer systems and servers described herein each include memory that constitutes an associated processor to perform the methods, steps, and functions disclosed herein. The memory can be distributed or local, and the processor can be distributed or standalone. The memory can be implemented as electronic memory, magnetic memory, or optical memory, or any combination of the above or other types of storage devices. In addition, the term "memory" must be construed broadly enough to include all information that can be read or written to an address in the address space accessed by the associated processor. Using this definition, information on the network is still stored in memory because the associated processor can retrieve it from the network.
It will be appreciated that the embodiments illustrated and described herein are merely exemplary of the principles of the invention and that various modifications can be practiced by those skilled in the art without departing from the scope and gist of the invention. I want to be understood.
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Numbers
- Publication
- 2012504841
- Publication, DOCDB
- 2012504841
- Publication, EPODOC
- JP2012504841
- Application
- 2011530194
- Application, DOCDB
- 2011530194
- Application, EPODOC
- JP20110530194
Titles2
- Japanese
- メモリ・デバイスの軟データ生成の方法および装置
- English
- Soft data generation methods and equipment for memory devices
Classification
- CPC, 16
- G11C16/26
- G11C16/34
- G11C7/02
- G11C7/04
- G11C11/5642
- G11C16/0483
- G11C16/3418
- G11C2211/5634
- G11C11/16
- G06F11/1012
- G11C7/10
- G06F2212/2022
- G06F2212/1032
- G06F12/0246
- G06F11/1068
- G11C11/5607
- IPC, 10
- G11C29 42
- G11C16 06
- G11C16 02
- H01L27 115
- H01L21 8247
- H01L27 10
- H01L29 788
- H01L29 792
- G06F12 16
- H10B69 00
Designated states4
- Regional, 4
- Zimbabwe
- Turkmenistan
- Türkiye
- Togo