Semiconductor memory device

The present invention relates to a semiconductor memory device.

DRAM, which forms a memory cell using one transistor (cell transistor) and one capacitor, can be highly integrated, can be written indefinitely in principle, and can be written and read at a relatively high speed. Used in electronic devices. Various ideas have been made for DRAM to increase the degree of integration (see Patent Document 1).

The DRAM stores data by accumulating electric charges in the capacitors of each memory cell, and reads out the data by discharging the electric charges to bit lines.

The fluctuation of the bit wire potential with the release of electric charge is determined by the ratio of the capacitance of the capacitor to the parasitic capacitance of the bit wire. Since the parasitic capacitance of a bit wire is almost proportional to the length of the bit wire, a constant value is required for the capacitance of the capacitor if the length of the bit wire does not change. In DRAM, which is widely used at present, a capacitor with a capacity of about 30 fF is required.

The size of memory cells tends to shrink with miniaturization, but as described above, it is necessary to keep the capacity of the capacitor above a certain level, so while the area for forming the capacitor is shrinking, a capacitor with the same capacity as before is used. It has been required to form.

Currently, capacitors are formed by a trench structure for digging deep holes in a silicon wafer or a stack structure in which chimney-shaped protrusions are provided (see Non-Patent Document 1 and Non-Patent Document 2). In each case, the aspect ratio is required to be 50 or more. That is, it is necessary to form extremely elongated structures having a depth and height of 2 μm or more in a limited area, and it is difficult to form these with good yield.

In order to overcome such difficulties, a method has been proposed in which a sub-bit line, which is a branch line of the bit line, is provided, and a flip-flop circuit type sense amplifier is connected to each of the sub-bit lines to reduce the capacitance of the capacitor. (See Patent Document 2).

However, in a DRAM having a conventional structure, it is required to superimpose a bit line and a sub-bit line on a word line. When a stack capacitor is adopted, since many structures are provided on the word line in this way, it becomes difficult to design and manufacture a circuit.

Another problem is that if the capacitance of the capacitor is reduced, the refresh interval is shortened accordingly. For example, when the capacitance is set to 1/10, if the off resistance of the cell transistor does not change, the time for which the electric charge is held in the capacitor is also 1/10, so refresh at 1/10 intervals in the normal case. It needs to be done (ie, refreshed 10 times more often). There are many proposals for a split bit line structure such as Patent Document 2, but there is no example showing a clear solution in this regard.

<p><patcit num="1"><text>U.S. Pat. No. 5302843</text></patcit><patcit num="2"><text>U.S. Pat. No. 4,777,625</text></patcit></p>

<p><nplcit num="1"><text>Kim, "Technology for sub-50nm DRAM and NAND Flash Manufacturing" TECHNICAL DIGEST OF INTERNATIONAL ELECTRON DEVICES MEETING, pp333-336, 2005</text></nplcit><nplcit num="2"><text>Mueller et al., "Challenges for the DRAM Cell Scaling to 40nm" TECHNICAL DIGEST OF INTERNATIONAL ELECTRON DEVICES MEETING, pp347-350, 2005</text></nplcit></p>

<p>One object of the present invention is to provide a memory device that functions sufficiently even if the capacity of the capacitor is equal to or less than the value used in the conventional DRAM, specifically, 1 fF or less, preferably 0.1 fF or less. Another object of the present invention is to provide a memory device having a depth or height required for a capacitor of 1 μm or less, preferably 0.3 μm or less.</p><p>Another object of the present invention is to provide a memory device having a novel structure or a method for driving the memory device. In particular, it is an object of the present invention to provide a memory device capable of reducing power consumption or a method of driving the memory device.</p>

<p>Hereinafter, the present invention will be described, but the terms used in the present specification will be briefly described. First, regarding the source and drain of a transistor, in the present specification, when one is referred to as a drain, the other is referred to as a source. That is, they are not distinguished by the high or low potential. Therefore, in the present specification, the part referred to as the source can be read as the drain.</p><p>Furthermore, in the present specification, even when it is expressed as "connecting", in an actual circuit, the physical connection part is not clear, and it is only when the wiring is extended. is there. For example, in a circuit of an insulated gate type field effect transistor (MISFET), one wiring may also serve as a gate for a plurality of MISFETs. In that case, the circuit diagram may be written so that there are many branches from one wire to the gate. In the present specification, even in such a case, the expression "wiring connects to the gate" may be used.</p><p>In this specification, when dealing with a specific row, column, or position in the matrix, a symbol indicating the coordinates is added to the code, for example, "selection transistor STr_n_m", "bit line MBL_m", and "sub-bit line SBL_n_m". However, in particular, when the rows, columns, and positions are not specified, when they are handled collectively, or when it is clear where they are, "selector transistor STr", "bit line MBL" , "Sub-bit line SBL", or simply "selected transistor", "bit line", "sub-bit line".</p><p>One aspect of the present invention is on a sense amplifier circuit formed on a substrate, a sub-bit line formed on the sense amplifier circuit, an island-shaped semiconductor region formed on the sub-bit line, and an island-shaped semiconductor region. It is a semiconductor memory device characterized by having a formed word wire and a capacitor and a bit wire covering the capacitor.</p><p>Further, one aspect of the present invention is a semiconductor memory device having 1 or more bit lines, 4 or more word lines, 2 or more memory blocks, and 1 or more sense amplifier circuits, and each memory block has 2 or more. Each memory cell has one or more island-shaped semiconductor regions and capacitors, and the first terminal of the sense amplifier circuit is connected to the sub-bit line of the first memory block. , The second terminal of the sense amplifier circuit has a circuit configuration that connects to the sub-bit line of the second memory block, and the sub-bit line of the first memory block and the sub-bit line of the second memory block are below the word line. Yes, the bit line is a semiconductor memory device characterized by being above the word line.</p><p>Here, in addition to the sense amplifier circuit, a circuit (decoder or the like) for sending a signal to the above-mentioned bit line or word line may be provided under the sub-bit line. Further, the island-shaped semiconductor region may be provided in a concave portion or a convex portion in addition to the flat surface. The height or depth of adjacent subbit lines may be different.</p><p>Further, the capacitance of the capacitor may be 0.1 fF or more and 1 fF or less. Further, it is desirable that one memory block has 64 or less memory cells. From the viewpoint of preventing errors, it is desirable that the capacitance of the capacitor is 10 times or more the capacitance of the sense amplifier circuit.</p><p>The off resistance of the cell transistor used in the above semiconductor memory device is 1 × 10.¹⁸Ω or more, preferably 1 × 10²²It should be Ω or more. Further, in order to obtain such a high off resistance, a wide bandgap semiconductor such as an oxide semiconductor may be used as the semiconductor. Alternatively, the thickness of the semiconductor region may be an ultrathin film of 5 nm or less, preferably 1 nm or less.</p>

<p>In the above configuration, the cell transistor is configured by the island-shaped semiconductor region and the word line. As mentioned above, the subbit line is below the cell transistor and the word line and capacitor are above the cell transistor. For this reason, sub-bit lines can be placed regardless of the position of the capacitor, resulting in an extremely efficient layout, and the area of one memory cell is ideally 6F.²(F is the minimum machining size, Featured Size).</p><p>Further, when the island-shaped semiconductor region is provided in the recess, the word wire is mainly formed on the side surface of the recess, but the contact plug for the sub-bit wire may be provided in the contact hole formed on the bottom surface of the recess. The area of the memory cell is ideally 4F²Can be reduced to. The same applies to the case where the island-shaped semiconductor region is provided on the convex portion.</p><p>When a word line is formed on the side surface of the concave portion or the convex portion, the channel length of the transistor using the word line as a gate is roughly about the height or depth of the side surface of the concave portion or the convex portion. Therefore, for example, by appropriately setting such a height and depth, the channel length can be made larger than the minimum machining dimension without impairing the degree of integration, and the short channel effect can be suppressed.</p><p>Further, in the above configuration, since the sub-bit line is located at a position away from the capacitor and the word line, the parasitic capacitance between them can be reduced. If the parasitic capacitance of the sub-bit line becomes smaller, the capacitance of the capacitor provided in the memory cell can be reduced proportionally.</p><p>In particular, in the above configuration, the effect is remarkable when the parasitic capacitance of the sub-bit wire is made smaller than the parasitic capacitance of the bit wire. That is, the parasitic capacitance of the bit line is involved only in the signal delay in the above configuration, whereas the parasitic capacitance of the sub-bit line also determines the capacitance of the capacitor.</p><p>If the above configuration is adopted, the time required for reading is almost the same even if the parasitic capacitance of the bit line is twice that of the DRAM of the conventional structure. In DRAM with the conventional structure, the charge of the capacitor is released to the bit line and the potential fluctuation is observed, but it takes more than twice the signal delay time until the potential of the bit line stabilizes. After that, in order to operate the sense amplifier, it takes several times as long as the signal delay time to read.</p><p>On the other hand, in the above configuration, the charge of the capacitor is released to the sub-bit line, but the parasitic capacitance of the sub-bit line is much smaller than that of the DRAM bit line having the conventional structure. In a DRAM with a conventional structure, about 2,000 memory cells are provided for one bit line, and the parasitic capacitance of the bit line is about 200 fF.</p><p>On the other hand, for example, when there are 64 memory cells in one memory block, the parasitic capacitance of the sub-bit line is about 8fF, so the time until the sense amplifier is operated is 4% of the DRAM of the conventional structure. It is a degree and can be ignored.</p><p>The time required to extract a signal from a sub-bit line to a bit line depends on the parasitic capacitance of the bit line, and even if this is twice the DRAM of the conventional structure, the timing at which the sense amplifier operates in the DRAM of the conventional structure So you can already retrieve the data.</p><p>Further, the small capacity of the capacitor means that a structure having a large aspect ratio such as a conventional DRAM is unnecessary. Therefore, it is possible to easily arrange the bit wire on the capacitor.</p><p>In the above configuration, since the sub-bit line is below the cell transistor and no structure that hinders it is provided, the depth at which the sub-bit line is arranged can be arbitrarily set. Of course, the parasitic capacitance can be further reduced by forming the sub-bit wire away from other wiring. Further, by making the depths of adjacent sub-bit lines different, it is possible to reduce the parasitic capacitance generated between the adjacent sub-bit lines.</p><p>Further, the chip area can be reduced by providing a circuit (drive circuit) for driving a word line, a bit line, a sub bit line, or the like under the sub bit line. Generally, 20% to 50% of the surface of a conventional DRAM chip is a drive circuit including a sense amplifier. The chip area can be reduced by superimposing the drive circuit and the circuit (memory cell array) in which the memory cells are formed, and more memory cells can be formed if the chip area is the same.</p>

<figref num="1">It is a figure explaining an example of the manufacturing method of the semiconductor memory apparatus of this invention.</figref><figref num="2">It is a figure explaining an example of the manufacturing method of the semiconductor memory apparatus of this invention.</figref><figref num="3">It is a figure explaining an example of the manufacturing method of the semiconductor memory apparatus of this invention.</figref><figref num="4">It is a figure explaining the example of the circuit applied to the semiconductor memory apparatus of this invention.</figref><figref num="5">It is a figure explaining the example of the circuit applied to the semiconductor memory apparatus of this invention.</figref><figref num="6">It is a figure explaining the example of the circuit applied to the semiconductor memory apparatus of this invention.</figref><figref num="7">It is a figure explaining an example of the manufacturing method of the semiconductor memory apparatus of this invention.</figref><figref num="8">It is a figure explaining an example of the manufacturing method of the semiconductor memory apparatus of this invention.</figref><figref num="9">It is a figure explaining the example of the structure of the semiconductor memory apparatus of this invention.</figref>

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments, and that the embodiments and details can be variously changed without departing from the spirit and scope thereof. .. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

In addition, the ordinal numbers 1 and 2 are added to avoid confusion of the constituents, and do not necessarily mean the order. For example, another interlayer insulator may be provided under the first interlayer insulator, and another contact plug may be provided in the intermediate layer between the first contact plug and the second contact plug.

(Embodiment 1) 4 (A), 4 (B), 5 and 6 show an example of a DRAM circuit to which this embodiment is applied. FIG. 4 (A) shows the arrangement of one memory block and its associated sense amplifier circuit. As shown in FIG. 4A, the memory block MBK_n_m in the nth row and the mth column has a selection transistor STr_n_m, a sub-bit line SBL_n_m, and a plurality of (four in FIG. 4A) memory cells MC_n_m_1 to MC_n_m_4.

In FIG. 4A, four memory cell MCs are provided in the memory block MBK, but more memory cells may be provided. For example, the number of memory cell MCs contained in one memory block MBK may be 2 to 64. As the number of memory cells increases, the sub-bit line SBL becomes longer, and the parasitic capacitance increases accordingly. If the capacitance of the capacitor of the memory cell MC is constant, the ratio of the sub-bit line SBL to the parasitic capacitance decreases, so that a malfunction when amplifying the signal by the sense amplifier circuit SA is likely to occur.

The gate of the selection transistor STr_n_m is connected to the selection line SL_n, the source is connected to the bit line MBL_m, and the drain is connected to the subbit line SBL_n_m. Further, each memory cell has one cell transistor and one capacitor, and the gate of the cell transistor is connected to the word line WL_n_1 to WL_n_4, the drain is connected to the subbit line SBL_n_m, and the source is connected to one electrode of the capacitor. Note that one memory cell may have two or more cell transistors or two or more capacitors.

Further, the sense amplifier circuit SA_n_m can be configured by, for example, a flip-flop circuit in which two inverters are combined, but the present invention is not limited to this. Further, the first electrode of the sense amplifier circuit SA_n_m is connected to the sub-bit line SBL_n_m, and the second electrode of the sense amplifier circuit SA_n_m is held at the reference potential V_REF. As the reference potential V_REF, another sub-bit line or the like can be used, which will be described later.

Such a memory block MBK is formed in a matrix as shown in FIG. 4 (B). Note that the word line is not shown in Fig. 4 (B).

Various semiconductors can be used for the selection transistor STr, the cell transistor of each memory cell MC, and the transistor used in the sense amplifier circuit SA. For example, all of these may be the same type of semiconductor material. Further, for example, the transistor used in the selection transistor STr and the sense amplifier circuit SA may be manufactured by using a single crystal silicon semiconductor substrate, and the transistor of each memory cell MC may be formed by using a thin film semiconductor layer. In that case, as the semiconductor layer of the thin film, single crystal silicon or polycrystalline silicon may be used, or a semiconductor other than silicon, for example, an oxide semiconductor, a nitride semiconductor, or a sulfide semiconductor may be used.

In particular, among oxide semiconductors, those with a bandgap of 3 electron volts or more have a donor or acceptor concentration of 1 × 10.¹²cm^-3By setting the following, the resistance at the time of off can be made extremely high. That is, by optimizing the potential of the gate, the resistance (off resistance) between the source and drain in the off state is 1 × 10.²⁴It can be Ω or more.

Off resistance of cell transistor is 1 × 10²⁴If it is Ω, for example, the capacity of the capacitor of the memory cell is 1 × 10 which is 1/100 or less of the conventional DRAM.^-16Even if it is F, the time constant is 1 × 10.⁸It is seconds (about 3 years) and can retain data for a period that cannot be expected with conventional DRAM. In other words, refreshing (rewriting data to compensate for the decrease in the charge stored in the capacitor), which was required more than 10 times per second in conventional DRAM, is no longer necessary in normal use. Is.

When writing DRAM data, most of the current flowing through the bit lines is used not only for charging the capacitor of the memory cell but also for charging and discharging the parasitic capacitance between the bit lines. Since the parasitic capacitance between bit lines increases as the wiring width shrinks, in the current state of integration, more than 10 times the current of charging the capacitor of the memory cell is used to charge and discharge the parasitic capacitance between bit lines. It is used.

Needless to say, charging and discharging of parasitic capacitance between bit lines is a phenomenon unrelated to data retention, and refreshing means an increase in power consumption. In that sense, reducing the number of refreshes or eliminating the need for refreshes is effective in suppressing power consumption.

The operation of the semiconductor memory device of FIG. 4 (A) will be described. First, writing will be described. For example, consider the case of writing data to the second memory cell MC_n_m_2 of the memory block of the nth row and the mth column and the case of reading the data from the memory cell MC_n_m_2. Here, the potential of the bit line MBL_m is set to 0V or + 1V depending on the data. The writing potential can be set as appropriate.

Also, when applying potential to them so that the transistors connected to the word line or selection line are turned on, it is expressed as "the potential (of the word line or selection line) is H", and the transistor is turned off. The case where the potential is given to them is expressed as "the potential (of the word line or selection line) is L".

The reference potential V_REF of the sense amplifier circuit SA_n_m is + 0.5V, and if the potential of the sub-bit line SBL_n_m to be amplified is higher than the reference potential V_REF, + 1V is output to the sub-bit line SBL_n_m, and if it is lower, 0V is output. It shall be.

First, writing will be described. Let H be the potential of the selection line SL_n and the word line WL_n_2, and turn on the cell transistor of the selection transistor STr_n_m and the memory cell MC_n_m_2. In addition, it shall correspond to the data to write the bit line MBL_m. As a result, the capacitor of the memory cell MC_n_m_2 is charged to the potential of the bit line MBL_m.

When charging is completed, the potentials of the selection line SL_n and the word line WL_n_2 are set to L, and the cell transistors of the selection transistor STr_n_m and the memory cell MC_n_m_2 are turned off. This completes the data writing.

Next, reading of the memory cell MC_n_m_2 will be described. Here, it is assumed that the capacitance of the capacitor of the memory cell MC_n_m_2 is 1/4 of the sum of the parasitic capacitance of the sub-bit line SBL_n_m and the capacitance of the sense amplifier circuit SA_n_m (including the gate capacitance and the parasitic capacitance). In manufacturing the memory device of the present embodiment, the capacitance of the capacitor of the memory cell MC is 10% or more of the sum of the parasitic capacitance of the sub-bit line SBL and the capacitance of the sense amplifier circuit SA (including the gate capacitance and the parasitic capacitance). Is preferable.

Further, when the capacitance of the capacitor is small, the gate capacitance of the cell transistor cannot be ignored, so care must be taken. However, the gate capacitance can be erased from the circuit by turning off the cell transistor except when necessary. However, in that case, it is necessary to turn off the cell transistor at least twice, and the power consumption increases accordingly.

First, the potential of the bit line MBL_m is set to + 0.5V, the potential of the selection line SL_n is set to H, and the selection transistor STr_n_m is turned on. As a result, the potential of the sub-bit line SBL_n_m becomes + 0.5V.

Next, the potential of the selection line SL_n is set to L, and the selection transistor STr_n_m is turned off. After that, the potential of the word line WL_n_2 is set to H, and the cell transistor of the memory cell MC_n_m_2 is turned on. As a result, the potential of the sub-bit line SBL_n_m fluctuates. Since the selection transistor STr_n_m is off, only the capacitance of the capacitor of the memory cell MC_n_m_2, the parasitic capacitance of the sub-bit line SBL_n_m, and the capacitance of the sense amplifier circuit SA_n_m need to be considered for the fluctuation of the potential.

As described above, the capacitance of the capacitor of the memory cell MC_n_m_2 is 1/4 of the sum of the parasitic capacitance of the sub-bit line SBL_n_m and the capacitance of the sense amplifier circuit SA_n_m, so the potential of the sub-bit line SBL_n_m is + 0.4V or + 0.6V. It becomes one of.

After that, the sense amplifier circuit SA_n_m is operated to amplify the potential difference between the sub-bit line SBL_n_m and the reference potential V_REF. That is, initially, if the potential is + 0.4V lower than the reference potential V_REF, the potential of the sub-bit line SBL_n_m is 0V, and if it is + 0.6V higher than the reference potential V_REF, the potential of the sub-bit line SBL_n_m is + 1V.

Since the cell transistor of the memory cell MC_n_m_2 is on, the capacitor is automatically charged to the potential of the sub-bit line SBL_n_m, but the potential is the same as the potential at the time of writing. After charging the capacitor, the potential of the word line WL_n_2 may be set to L, and the cell transistor of the memory cell MC_n_m_2 may be turned off.

Further, the potential of the selection line SL_n is set to H, the selection transistor STr_n_m is turned on, and the potential of the bit line MBL_m is made equal to the potential of the sub bit line SBL_n_m. Data can be read by reading the potential of this bit line MBL_m.

As the above reference potential V_REF, the potential of another subbit line can be used. For example, FIG. 5 reflects one of the technical ideas of the present invention in an open bit linear DRAM, but here, the memory block MBK_n + 1_m in the (n + 1) th row (m + 1) column. The +1 subbit line SBL_n + 1_m + 1 is used as the reference potential.

Needless to say, in the flip-flop type sense amplifier circuit, the first electrode and the second electrode (that is, the two input / output terminals) are equivalent, so that the potential of the subbit line SBL_n_m is conversely the subbit line SBL_n + 1_m +. It may also be used as a reference potential for 1. That is, as in this example, the flip-flop type sense amplifier circuit is used to amplify the difference between the potential of the sub-bit line SBL_n_m and the potential of the sub-bit line SBL_n + 1_m + 1. Due to such characteristics, the sense amplifier circuit SA_n_m / n + 1_m + 1 is described here.

Similarly, the subbit line SBL_n + 1_m of the memory block MBK_n + 1_m in the (n + 1) th row and mth column and the subbit of the memory block MBK_n + 2_m + 1 in the memory block MBK_n + 2_m + 1 in the (n + 2) th row and mth column. to amplify the difference in potential between the line SBL_n + 2_m + 1, a sense amplifier circuit SA_n + 1_m / n + 2_m + 1 is provided to be connected to them Ru. In addition, the potential of the sub-bit line SBL_n_m + 1 of the memory block MBK_n_m + 1 in the nth row and column (m + 1) is set by the sense amplifier circuit SA_n-1_m / n_m + 1 in the (n-1) row and m column. Compared with the potential of the sub-bit line SBL_n-1_m of the memory block MBK_n-1_m, it is amplified.

The operation of the circuit of FIG. 5 will be described. Since the writing is the same as the case shown in FIG. 4 (A), the writing is omitted, and the reading will be described below. For example, consider the case of reading the data of the memory cell MC_n_m_2.

First, the potentials of the bit line MBL_m and the bit line MBL_m + 1 are set to + 0.5V. Further, the potentials of the selection line SL_n and the selection line SL_n + 1 are set to H, and the selection transistor STr_n_m and the selection transistor STr_n + 1_m + 1 are turned on. After that, the potentials of the selection line SL_n and the selection line SL_n + 1 are set to L, and the selection transistor STr_n_m and the selection transistor STr_n + 1_m + 1 are turned off. As a result, the potentials of the sub-bit line SBL_n_m and the sub-bit line SBL_n + 1_m + 1 become + 0.5V.

Next, the potential of the word line WL_n_2 is set to H, and the cell transistor of the memory cell MC_n_m_2 is turned on. As a result, the potential of the sub-bit line SBL_n_m is either + 0.4V or + 0.6V. On the other hand, since there is no cell transistor to be turned on in the memory cell connected to the sub-bit line SBL_n + 1_m + 1, the potential of the sub-bit line SBL_n + 1_m + 1 remains + 0.5V.

After that, the sense amplifier circuit SA_n_m / n + 1_m + 1 is operated to amplify the potential of the sub-bit line SBL_n_m. That is, if the potential of the sub-bit line SBL_n + 1_m + 1 is + 0.4V, which is lower than the potential of the sub-bit line SBL_n + 1_m + 1, the potential of the sub-bit line SBL_n_m is 0V, which is higher than the potential of the sub-bit line SBL_n + 1_m + 1. If it is 0.6V, the potential of the sub-bit line SBL_n_m is + 1V.

After that, the potential of the selection line SL_n is set to H, the selection transistor STr_n_m is turned on, and the potential of the bit line MBL_m is made equal to the potential of the sub-bit line SBL_n_m. Data can be read by reading the potential of this bit line MBL_m.

In the above process, the cell transistor of another memory cell (for example, memory cell MC_n_m + 1_2) connected to the word line WL_n_2 is also turned on, and the charge stored in the capacitor is released, so that it can be recovered. For example, the sense amplifier circuit SA_n-1_m / n_m + 1 needs to be operated in the same manner.

FIG. 6 reflects one of the technical ideas of the present invention in a folded bit linear DRAM. Here, the potential of the sub-bit line SBL_n_m of the memory block MBK_n_m in the nth row and the mth column and the nth row and the nth th. The potential difference of the sub-bit line SBL_n_m + 1 of the memory block MBK_n_m + 1 in the (m + 1) column is amplified by the sense amplifier circuit SA_n_m / n_m + 1.

Since the folded bit linear DRAM has a structure in which memory cells are provided only at half of the intersections of the word line and the sub bit line, the degree of integration is lower than that of the open bit linear type.

The operation of the circuit of FIG. 6 will be described. Since the writing is the same as the case shown in FIG. 4 (A), the writing is omitted, and the reading will be described below. For example, consider the case of reading the data of the memory cell MC_n_m_3.

First, the potentials of the bit line MBL_m and the bit line MBL_m + 1 are set to + 0.5V. Further, the potential of the selection line SL_n is set to H, and the selection transistor STr_n_m and the selection transistor STr_n_m + 1 are turned on. After that, the potential of the selection line SL_n is set to L, and the selection transistor STr_n_m and the selection transistor STr_n_m + 1 are turned off. As a result, the potentials of the sub-bit line SBL_n_m and the sub-bit line SBL_n_m + 1 become + 0.5V.

Next, the potential of the word line WL_n_3 is set to H, and the cell transistor of the memory cell MC_n_m_3 is turned on. As a result, the potential of the sub-bit line SBL_n_m is either + 0.4V or + 0.6V. On the other hand, since there is no cell transistor to be turned on in the memory cell connected to the sub-bit line SBL_n_m + 1, the potential of the sub-bit line SBL_n + 1_m + 1 remains + 0.5V.

After that, the sense amplifier circuit SA_n_m / n_m + 1 is operated to amplify the potential of the sub-bit line SBL_n_m. After that, the potential of the selection line SL_n is set to H, the selection transistor STr_n_m and the selection transistor STr_n_m + 1 are turned on, and the potential of the bit line MBL_m is made equal to the potential of the sub bit line SBL_n_m. Data can be read by reading the potential of this bit line MBL_m.

An example of the circuit layout of the sense amplifier circuit SA and the selection transistor STr that can be used in FIG. 5 or 6 is shown in FIGS. 7 (A) to 7 (F). 7 (A) to 7 (C) show the layout of the wiring of the sense amplifier that can be used in the circuit of the folded bit linear DRAM of FIG. 6, and FIGS. 7 (D) to 7 (F) show the layout. The layout of the wiring of the sense amplifier that can be used in the open bit linear circuit of Fig. 5 is shown. For details, refer to known semiconductor integrated circuit technology.

FIG. 7A shows an example of an element forming region formed on a semiconductor substrate or the like and a first wiring or the like provided on the element forming region. That is, the element forming region 302n and the element forming region 302p are provided, and the first wirings 301a to 301c are formed on the element forming region 302n. All of these function as the gate of the transistor. For example, the first wiring 301a functions as a selection line SL. Further, the first wirings 301b and 301c serve as gates for the inverter in the sense amplifier circuit SA.

N-type or p-type impurities can be self-consistently doped using the first wirings 301a to 301c. Here, an n-type transistor is formed in the element forming region 302n, and a p-type transistor is formed in the element forming region 302p. Further, as shown in the figure, a first contact plug used for connection to the upper layer is provided in the element forming region 302n and the element forming region 302p.

FIG. 7B shows the layout of the second wiring 303a, 303b, 303n, 303p and the second contact plug to the upper layer formed on the circuit shown in FIG. 7A. The second wires 303a and 303b are provided to connect the drain of the n-type transistor and the drain of the p-type transistor, and the second wires 303n and 303p are connected to the sources of the n-type transistor and the p-type transistor, respectively. It is used to supply power to the sense amplifier.

Further, a second contact plug is provided for connecting the first wiring 301b and the upper layer, the first wiring 301c and the upper layer, the second wiring 303a and the upper layer, and the second wiring 303b and the upper layer.

FIG. 7 (C) shows the layout of the third wires 304a and 304b formed on the circuit shown in FIG. 7 (B) and the third contact plug to the upper layer. The third wirings 304a and 304b are sub-bit wires. Further, the third contact plugs 305a and 305b are for connecting to the bit wire provided in the upper layer. In the upper layer, the bit wire may be provided parallel to the sub bit wire, but may have an angle of less than 45 °.

The third wiring 304a connects the gate of the inverter formed in the upper part of the figure and the output of the inverter formed in the lower part, and the third wiring 304b is formed above the gate of the inverter formed in the lower part of the figure. Connect the output of the inverter.

FIG. 7D shows an example of an element forming region formed on a semiconductor substrate or the like and a first wiring or the like provided on the element forming region. That is, the element forming region 352n and the element forming region 352p are provided, and the first wirings 351a to 351d are formed on the element forming region 352n. The first wiring 351a functions as, for example, the selection line SL_n, and the first wiring 351b functions as the selection line SL_n + 1 in the next line.

Here, an n-type transistor is formed in the element forming region 352n, and a p-type transistor is formed in the element forming region 352p. Further, as shown in the figure, a first contact plug used for connection to the upper layer is provided in the element forming region 352n and the element forming region 352p.

FIG. 7 (E) shows the layout of the second wiring 353a, 353b, 353n, 353p formed on the circuit shown in FIG. 7 (D) and the second contact plug to the upper layer. The second wires 353a and 353b are provided to connect the drain of the n-type transistor and the drain of the p-type transistor, and the second wires 353n and 353p are connected to the sources of the n-type transistor and the p-type transistor, respectively. It is used to supply power to the sense amplifier.

Further, a second contact plug is provided for connection to the first wiring 351c and the upper layer, the first wiring 351d and the upper layer, the second wiring 353a and the upper layer, and the second wiring 353b and the upper layer.

FIG. 7 (F) shows the layout of the third wirings 354a and 354b formed on the circuit shown in FIG. 7 (E) and the third contact plug to the upper layer. The third wirings 354a and 354b are sub-bit wires. Further, the third contact plugs 355a and 355b are for connecting to the bit wire provided in the upper layer.

The third wiring 354a connects the gate of the inverter formed in the upper part of the figure and the output of the inverter formed in the lower part, and the third wiring 354b is formed above the gate of the inverter formed in the lower part of the figure. Connect the output of the inverter.

In the semiconductor memory device of the present embodiment, the memory cell is formed on the circuit such as the sense amplifier described above. The manufacturing process will be described with reference to FIGS. 1 (A), 1 (B), 2 and 3. 1 (A), 1 (B), 2 and 3 show a cross section parallel to the sub-bit line of the semiconductor memory device.

&lt;Fig. 1 (A)&gt; A semiconductor circuit 102 including a transistor is formed on the substrate 101 as described above. Then, the first insulator 103 and the first contact plug 104 having an appropriate thickness are formed. As the substrate 101, it is preferable to use one having a single crystal semiconductor on the surface (for example, a single crystal semiconductor substrate or an SOI substrate). As the single crystal semiconductor, single crystal silicon, single crystal germanium, single crystal silicon germanium, single crystal gallium arsenic, single crystal indium phosphorus, single crystal indium arsenic and the like can be used.

Then, the sub-bit wires 105a and 105c and the connection electrode 105b are formed so as to be in contact with the first contact plug. Further, a second insulator 106 having an appropriate thickness, sub-bit wires 105a and 105c, and a second contact plug 107 to be connected to the connection electrode 105b are formed on the second insulator 106. The thickness of the first insulator 103 and the second insulator 106 is important in determining the parasitic capacitance of the sub-bit wire. It is preferably 100 nm to 1 μm. Further, the first insulator 103 and the second insulator 106 are preferably formed of a material having a relatively low dielectric constant such as silicon oxide.

&lt;Fig. 1 (B)&gt; The island-shaped semiconductor regions 108a and 108b are formed, and the gate insulator 109 is formed by covering the island-shaped semiconductor regions 108a and 108b. The thicknesses of the semiconductor regions 108a and 108b and the gate insulator 109 can be appropriately determined, but when the channel length of the transistor is short, it is preferable to reduce the thickness, for example, 1/50 to 1/5 of the channel length. It is good to say. The thickness of the gate insulator 109 should be thin enough that the tunnel current or the like does not matter. Further, the gate insulator 109 may be formed of a material having a relative permittivity of 10 or more.

There are no restrictions on the types of semiconductors used in the semiconductor regions 108a and 108b, but the mobility is 5 cm.²It is preferably / Vs or more. For example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, indium oxide or oxide obtained by adding other metal elements to indium oxide, gallium nitride or a compound obtained by adding oxygen to gallium nitride, gallium arsenide, indium arsenide. , Zinc sulfide and the like may be used.

The semiconductor regions 108a and 108b constitute cell transistors, but the field effect mobility of the semiconductor does not matter so much, and the product of the on-resistance of the cell transistor of the memory cell and the capacitance of the capacitor should be 1 nsec or less. The material may be selected and the channel length and channel width may be determined. For example, if the capacitance of the capacitor is 1fF, the on-resistance may be 1MΩ or less.

In the semiconductor memory device of the present embodiment, the off resistance is more important than the on resistance. The off-resistance of the cell transistor is determined by comparison with the capacitance of the capacitor of the memory cell. If the refresh period is about the same as that of a conventional DRAM and the capacity of the capacitor of the memory cell is 1/10 of that of the conventional DRAM, the off resistance needs to be 10 times that of the cell transistor of the conventional DRAM.

Further, increasing the off resistance of the cell transistor is preferable because the refresh cycle of the memory cell can be lengthened. For example, if the off resistance is 1 million times that of a conventional cell transistor, it can be practically used without requiring a refresh operation.

In order to obtain such a very high off resistance, it is preferable to use a wide bandgap semiconductor having a bandgap of 2.5 electron volt or more and 4 electron volt or less, preferably 3 electron volt or more and 3.8 electron volt or less. For example, an oxide semiconductor such as indium oxide and zinc oxide, a nitride semiconductor such as gallium nitride, and a sulfide semiconductor such as zinc sulfide may be used.

Off resistance is inversely proportional to the concentration of thermally excited carriers. Even in the state where there are no carriers due to donors or acceptors (intrinsic semiconductor), the bandgap of silicon is 1.1 electron volts, so the concentration of thermally excited carriers at room temperature (300K) is 1 × 10.¹¹cm^-3Degree.

On the other hand, in semiconductors with a bandgap of 3.2 electrons, the concentration of thermally excited carriers is 1 × 10.^-7cm^-3It will be about. When the electron mobility is the same, the resistivity is inversely proportional to the carrier concentration, so the resistivity of a semiconductor with a bandgap of 3.2 electrons is 18 orders of magnitude higher than that of silicon.

The concentration of carriers by donors and acceptors is preferably as low as possible, and the concentration is 1 × 10.¹²cm^-3The following is preferable. These carrier concentrations determine the transistor threshold.

Even if silicon is used, it is possible to increase the off resistance of the cell transistor to about 100 times that of the conventional one. For transistors using silicon, the resistance between the source and drain is determined by the pn junction. In the pn junction, when the impurity concentration of both is high, the depletion layer becomes thin and a tunnel current is generated, so that the insulation property deteriorates. Therefore, the concentration of donors or acceptors at least where the channels are formed is 1 × 10.¹⁴cm^-3The following is preferable.

However, at such a low concentration where the channel is formed, the infiltration of carriers from the source deteriorates the insulation. This can be dealt with by thinning the semiconductor regions 108a and 108b to a thickness of 5 nm or less, preferably 1 nm or less. Alternatively, the channels may be formed in the vertical direction to increase the substantial channel length. These things can also be applied when a wide bandgap semiconductor such as an oxide semiconductor is used.

In addition, materials having a work function of 5 electron volts or more (for example, platinum group elements such as platinum and palladium, indium nitride, zinc nitride, etc.) are placed on the surface where the word wire to be formed later faces the semiconductor region via the gate insulator 109. (Nitride, p-type silicon, etc.) should be used.

After forming the gate insulator 109 with the semiconductor regions 108a and 108b, the word lines 110a to 110d are formed. The word lines 110a to 110d also function as gates for cell transistors in memory cells.

In general, when semiconductor integrated circuits are provided in the lower layer, noise generated by them may hinder the operation of the transistors in the upper layer. To solve this problem, it is advisable to provide some kind of shield layer under the upper transistor, particularly under the sub-bit lines 105a and 105c, to absorb noise.

&lt;Fig. 2&gt; Impurities are implanted into the semiconductor regions 108a and 108b using the word lines 110a to 110d as a mask by an ion implantation method or the like to form an n-type or p-type doped region 111. The distance between the portion where the second contact plug 107 is in contact with the semiconductor regions 108a and 108b and the word lines 110a to 110d, or the portion where the third contact plug and the semiconductor regions 108a and 108b are formed later and 110a to 110d When the distance is 20 nm or less, preferably 10 nm or less, it is not necessary to form the doped region 111.

Further, when the semiconductor regions 108a and 108b have some kind of conductive type in advance, the transistor can be controlled by utilizing the work function difference with the material constituting the word lines 110a to 110d, so that the transistor is particularly doped. It may not be necessary to form the region 111.

For example, polycrystalline silicon on silicon oxide exhibits n-type without special doping of impurities, but the work function of indium nitride, zinc nitride, p-type silicon, etc. on the word lines 110a to 110d is 5 electron volts or more. When a material is used, a region having an extremely high resistance can be formed by eliminating electrons.

Next, the third insulator 112 is formed of a material having a relatively low dielectric constant such as silicon oxide to form the third contact plug 113. Further, the fourth insulator 114 is formed of a material having a low dielectric constant, and a hole for forming a capacitor is provided in the fourth insulator 114. In the present embodiment, since the capacity of the capacitor of the memory cell can be 1/10 or less of the conventional DRAM, the hole depth is also 1/10 or less of the conventional DRAM, that is, 0.3 μm or less, preferably 30 nm or less. Can be done.

The ability to form the holes shallowly in this way is advantageous in forming the electrodes and insulators of the capacitors to be formed thereafter on the inner surface of the holes. That is, it is technically difficult to form these on the inner surface of a deep hole having an aspect ratio of more than 50 times, resulting in a decrease in yield. Further, an insulator having a higher dielectric constant or an electrode material having a higher conductivity may not be formed under such conditions. On the other hand, for example, if the aspect ratio is 10 times or less, the electrode can be formed relatively easily. And insulators can be formed, and more preferred materials can be used.

Then, the first capacitor electrodes 115a to 115d having a thickness of 2 nm to 20 nm are formed on the inner surface of the hole. The upper limit of the thickness of the first capacitor electrodes 115a to 115d may be determined according to the minimum processing dimension F. If F is 20 nm, it is preferably 5 nm or less, and if F is 10 nm, it is preferable. It is preferably 2.5 nm or less.

Further, a fourth contact plug 116 is formed.

&lt;Fig. 3&gt; A capacitor insulator 117 having a thickness of 2 nm to 20 nm is formed. Various high-k materials can be used as the capacitor insulator 117, but hafnium oxide, zirconium oxide, tantalum oxide, barium strontium titanate and the like are preferable.

Further, the second capacitor electrodes 118a and 118b are formed. After that, the fifth insulator 119 and the fifth contact plug 120 are formed, and the bit wire 121 is formed so as to be in contact with the fifth contact plug 120.

(Embodiment 2) 8 (A) to 8 (D) and 9 (A) to 9 (D) show the present embodiment. In the present embodiment as well, the memory cells are formed on the semiconductor circuit such as the sense amplifier as in the first embodiment, but FIGS. 8 (A) to 8 (D) and FIGS. 9 (A) to 9 (A) to FIGS. In 9 (D), such a semiconductor circuit is omitted. Hereinafter, description will be given according to the drawings.

&lt;Fig. 8 (A)&gt; A sub-bit wire 402 is formed on the first insulator 401. At this time, there are several methods for arranging the sub-bit line 402. For example, as shown in FIGS. 9 (A) and 9 (B), the sub bit wires 402 and the adjacent sub bit wires 402a and 402b are all formed at the same depth or in the same layer. FIG. 9 (A) is a schematic cross-section of the surface on which the sub-bit line 402 is formed cut by a plane including the line segment CD of FIG. 8 (A), and FIG. 9 (A) shows a cross section of the line segment EF of FIG. 9 (A). Shown in (B). The cross section of the line segment AB in FIGS. 9 (A) and 9 (C) is shown in FIG.

As shown in FIG. 9B, the sub-bit lines 402a and 402b adjacent to the sub-bit line 402 are also formed at the same depth or in the same layer. This method is characterized by a small number of manufacturing steps.

Another method is to form the sub-bit lines 402a and 402b adjacent to the sub-bit line 402 in different depths or different layers, as shown in FIGS. 9 (C) and 9 (D). 9 (C) is a schematic view of a cross section cut along a plane including the line segment CD of FIG. 8 (A), and FIG. 9 (D) shows a cross section of the line segment EF of FIG. 9 (C).

In FIG. 9 (C), the adjacent sub-bit lines 402a and 402b cannot be seen, but as shown in FIG. 9 (D), the adjacent sub-bit lines 402a and 402b are formed at a depth different from that of the sub-bit line 402. There is. Although this method requires an additional fabrication step, it is possible to reduce the parasitic capacitance between adjacent sub-bit lines as compared with the method of forming sub-bit lines in the same layer. In Fig. 9 (D), the depth of the sub-bit line is set to 2 types, but it can be set to 3 or more types.

In the conventional DRAM, there is a structure such as a capacitor in the part where the sub-bit line is arranged, and the arrangement of the sub-bit line is extremely limited. However, in the present embodiment, the capacitor is formed at a place away from the sub-bit line. Therefore, the degree of freedom in arranging the sub-bit lines is high, and it is possible to form sub-bit lines having different depths as described above. Any method can be adopted in the present embodiment.

As described above, in the uniform state of the present invention, it is more effective to reduce the parasitic capacitance of the sub-bit line than to reduce the parasitic capacitance of the bit line in reducing the capacitance of the capacitor of the memory cell. is there. If the capacitor can be made small by reducing the parasitic capacitance of the sub-bit wire by such a method, an effect commensurate with the increase in the construction constant can be obtained.

Next, the second insulator 403 and the third insulator 404 are formed. The second insulator 403 and the third insulator 404 may be made of different materials or materials having different etching rates. For example, silicon oxide can be used as the second insulator 403, and silicon nitride can be used as the third insulator 404. Then, the first contact plug 405 connected to the sub-bit wire 402 is embedded in the second insulator 403 and the third insulator 404.

Next, an insulator and a conductive layer are formed and etched in a groove shape to form a groove 408 and a fourth insulator 406 and conductive layers 407a and 407b separated by the groove 408. At this time, the etching is stopped at the third insulator. That is, the third insulator serves as an etching stopper.

&lt;Fig. 8 (B)&gt; Next, a semiconductor film is formed on the bottom surface and the side surface of the groove 408, and the semiconductor film and the conductive layers 407a and 407b are etched to form an island-shaped semiconductor region 409. Further, a gate insulator 410 is formed on the semiconductor region 409.

&lt;Fig. 8 (C)&gt; Then, a film of a conductive material is formed, and the film is anisotropically etched to form word lines 411a and 411b in contact with the gate insulator 410 on the side surface of the groove 408. Patent Document 1 may be referred to for a method of forming such word lines 411a and 411b on the side surface of the groove. Further, as disclosed in Patent Document 1, impurities may be doped into the semiconductor region 409 using the word lines 411a and 411b as masks.

In the transistor using the word lines 411a and 411b formed in this way, the channel length can be made larger than the minimum machining dimension. That is, the channel length is approximately the sum of the depth of the groove 408 and the horizontal length of the word line 411a (or word line 411b) (indicated by x in FIG. 8C). When the depth of the groove 408 is made larger than the minimum machining dimension, the channel length becomes larger than the minimum machining dimension, and the short channel effect can be suppressed.

Further, the length x can be set regardless of the minimum machining dimension. For example, the length x can be 1/2 or less, preferably 1/4 or less of the minimum processing dimension, as long as the required conductivity can be secured. Then, the width of the groove 408 can be made to be 2 times or less, preferably 1 times the minimum machined line width. As a result, the area of one memory cell is 5F.², Preferably 4F²Can be done.

For example, when the width of the groove 408 is 2F, if the length x is preferably 0.7F or less, the word lines 411a and 411b formed in the same groove 408 can be separated. As a result, the required length of one memory cell is 2.5F, and the area of one memory cell is the length (subbit line) in the direction perpendicular to the line segment AB (that is, the line segment EF direction in FIG. 9). Interval) 5F, which is the product of 2F²Can be done.

Further, when the width of the groove 408 is F, if the length x is preferably 0.3 F or less, the word lines 411a and 411b formed in the same groove 408 can be separated. As a result, the length required for one memory cell is 2F, and the area of one memory cell is 4F.²Can be done. This is the theoretical lower limit for a matrix-type memory cell array.

It should be noted that such high density and small area are possible because the sub-bit line 402 is below the semiconductor region 409, and when the sub-bit line is above the word line, a word line is formed on the side surface of the groove 408. Even with this method, a larger area is required. This is because it is necessary to provide the groove 408 with a contact with the sub-bit wire in addition to the word wire. Since the contact must not come into contact with the word line, it is essential that the width of the groove 408 is larger than F, and in reality it is larger than 2F.

&lt;Fig. 8 (D)&gt; A fifth insulator 412 is formed, and second contact plugs 413a and 413b are formed to be connected to the conductive layers 407a and 407b. The conductive layers 407a and 407b have a function as an etching stopper, and are particularly effective when the semiconductor region 409 is thin. A capacitor may be formed on the second contact plugs 413a and 413b as shown in the first embodiment, and a bit wire may be further formed on the capacitor.

101 board 102 Semiconductor circuit 103 First insulator 104 1st contact plug 105a subbit line 105b connection electrode 105c subbit line 106 Second insulator 107 2nd contact plug 108a Semiconductor area 108b Semiconductor area 109 Gate insulation 110a word line 110b word line 110c word line 110d word line 111 Doped area 112 Third insulator 113 3rd contact plug 114 4th insulator 115a 1st capacitor electrode 115b 1st capacitor electrode 115c 1st capacitor electrode 115d 1st capacitor electrode 116 4th contact plug 117 Capacitor insulator 118a 2nd capacitor electrode 118b 2nd capacitor electrode 119 Fifth insulator 120 5th contact plug 121 bit line 301a 1st wiring 301b 1st wiring 301c 1st wiring 302n device formation region 302p device formation region 303a 2nd wiring 303b 2nd wiring 303n 2nd wiring 303p 2nd wiring 304a 3rd wiring 304b 3rd wiring 305a 3rd contact plug 305b 3rd contact plug 351a 1st wiring 351b 1st wiring 351c 1st wiring 351d 1st wiring 352n device formation region 352p device formation region 353a 2nd wiring 353b 2nd wiring 353n 2nd wiring 353p 2nd wiring 354a 3rd wiring 354b 3rd wiring 355a 3rd contact plug 355b 3rd contact plug 401 First insulator 402 Subbit line 402a Subbit line 402b Subbit line 403 Second insulator 404 3rd insulator 405 1st contact plug 406 4th insulator 407a Conductive layer 407b Conductive layer 408 groove 409 Semiconductor area 410 Gate insulation 411a word line 411b word line 412 5th insulator 413a 2nd contact plug 413b 2nd contact plug MC memory cell MBK memory block MBL bit line SA sense amplifier circuit SBL subbit line SL selection line STr selection transistor V_REF reference potential WL word line