Manufacturing method for semiconductor device

The present invention relates to a semiconductor storage device, and more particularly to a structure of a semiconductor storage device capable of realizing highly integrated DRAM (Dynamic Random Access Memory) with a small number of steps and a fine cell area, and a method for manufacturing the same.

DRAM is a semiconductor storage device that can be composed of one transistor and one capacitor, and various structures and manufacturing methods for manufacturing a higher density and highly integrated semiconductor storage device have been conventionally studied.

FIG. 59 shows a cross-sectional view of the semiconductor storage device described in JP-A-61-176148.

The source diffusion layer 24 and the drain diffusion layer 26 are independently formed on the semiconductor substrate 10. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. In this way, a memory cell transistor including a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is configured.

On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed is formed. It is formed.

A tubular capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall of the through hole 40, and is connected to the source diffusion layer 24 at the bottom of the through hole 40.

A capacitor dielectric film 48 is formed on the inner wall and upper surface of the capacitor storage electrode 46 and on the upper surface of the source diffusion layer 24 exposed inside the through hole 40.

A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor composed of a capacitor storage electrode 46, a capacitor dielectric film 48, and a capacitor counter electrode 54 is configured.

On the other hand, polycrystalline silicon is embedded in the through hole 38, and is connected to the bit wire 62 formed via the interlayer insulating film 53 formed on the capacitor counter electrode 54.

Further, a metal wiring layer (not shown) is formed on the upper part of the bit wire via an interlayer insulating film (not shown), and a DRAM composed of one transistor and one capacitor is formed.

FIG. 60 shows a cross-sectional view of another semiconductor storage device.

The source diffusion layer 24 and the drain diffusion layer 26 are independently formed on the semiconductor substrate 10. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. In this way, a memory cell transistor including a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is configured.

On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 102 in which a through hole 98 opened on the drain diffusion layer 26 and a through hole 100 opened on the source diffusion layer 100 are formed is formed. Has been done. An insulating film 42 is formed on the gate electrode so as to surround the gate electrode, and the exposed portion of the semiconductor substrate 10 in the through holes 98 and 100 is defined by the insulating film 42.

An interlayer insulating film 36 is further formed on the interlayer insulating film 102, and a capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall and the bottom of the through hole 40 provided in the interlayer insulating film 36. The capacitor storage electrode 46 is connected to the source diffusion layer via a polycrystalline silicon film 104 embedded in the through hole 100.

A capacitor dielectric film 48 is formed on the inner surface and the upper surface of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor composed of a capacitor storage electrode 46, a capacitor dielectric film 48, and a capacitor counter electrode 54 is configured.

On the other hand, a polycrystalline silicon film 106 is embedded in the through hole 98, and is connected to a bit wire 62 formed via an interlayer insulating film 53 formed on the capacitor counter electrode 54.

Further, a metal wiring layer (not shown) is formed on the upper part of the bit wire via an interlayer insulating film (not shown), and a DRAM composed of one transistor and one capacitor is formed.

Normally, in order to configure a DRAM cell, LOCOS separation, gate electrode (ward wire), bit wire contact hole, bit wire, through hole for capacitor storage electrode, capacitor storage electrode, capacitor counter electrode, through hole for metal wiring, At least nine lithography steps are required to form the metal wiring.

Further, in the lithography process, a margin for aligning the gate electrode and the bit wire contact hole, a margin for aligning the gate electrode and the through hole, and a margin for aligning the through hole and the bit wire are required, so that the memory cell area is increased accordingly.

In order to improve these points, in the semiconductor storage device described in JP-A-61-176148, by adopting the above structure, the capacitor storage electrode is formed by self-alignment with respect to the through hole, thereby performing lithography. The number of processes has been reduced by one.

Further, in the semiconductor storage device shown in FIG. 60, in addition to forming the capacitor storage electrode by self-alignment, the through holes 98 and 100 are formed by self-alignment with respect to the gate electrode, so that the gate electrode and the bit are formed. The memory cell area can be reduced because the alignment margin of the through hole for line contact and the alignment margin of the through hole for the gate electrode and the capacitor storage electrode are not required.

In this way, it has been attempted to manufacture a semiconductor storage device capable of high integration with a small alignment margin with a small number of lithography steps.

<p> In the semiconductor storage device described in JP-A-61-176148, the above structure is formed by depositing a polycrystalline silicon film to form a capacitor storage electrode 46 and at the same time embedding polycrystalline silicon in a through hole 38. ing. The reason why the through hole 38 is completely embedded in this way is as follows.</p><p> That is, as disclosed in the above-mentioned publication, the bit wire 62 is made of aluminum (Al), the bit wire 62 is the uppermost wiring layer, and the source / drain of the peripheral circuit or the peripheral circuit. In order for Al to contact the gate electrode, it is necessary to etch an insulating film that is much thicker than the bit wire contact portion, but since there is no evidence of etching on the interlayer insulating film 36 of the bit wire contact portion, the periphery It is considered that the through hole of the circuit is completely embedded with the polycrystalline silicon as well as the through hole 38.</p><p> The reason why the through holes of the peripheral circuit are completely embedded in this way is that the contact resistance in the peripheral circuit greatly affects the performance such as the operating speed of the circuit, and the through holes are completely embedded to reduce the contact resistance as much as possible. This is because it is desirable. Therefore, it is necessary to completely embed the bit wire contact hole to be embedded at the same time as the through hole of the peripheral circuit.</p><p> However, in the semiconductor storage device described in Japanese Patent Application Laid-Open No. 61-176148, the polycrystalline silicon film embedded in the through hole of the peripheral circuit needs to be formed thicker than the radius of the through hole diameter. Since the capacitor storage electrode 46 is also formed at the same time, if the polycrystalline silicon film thickness is too thick, there is a problem that the inner wall area of the through hole 40 is reduced and the cell capacity is reduced.</p><p> Further, when forming the through holes 38 and 40, it is necessary to consider the alignment margin with respect to the gate electrode 20, so that there is a problem that the cell area increases and the capacitor capacity forming portion becomes smaller by that amount.</p><p> Further, in the semiconductor storage device shown in FIG. 60, since the self-aligned contact is formed as described above, it is not necessary to consider the alignment margin with respect to the gate electrode 20 when forming the through holes 98 and 100. Further, since the through hole 40 and the bit wire contact hole 58 are formed separately and the bit wire contact hole 58 is not embedded with a polycrystalline silicon film, a capacitor is used as in the semiconductor storage device described in JP-A-61-176148. The capacity does not decrease.</p><p> However, in the semiconductor storage device of FIG. 60, polycrystalline silicon is embedded in the through holes 98 and 100 in order to connect the source diffusion layer 24 and the capacitor storage electrode 46, the drain diffusion layer 26 and the bit wire 62. , A separate lithography process is required to open through holes 98 and 100 in the embedded portion. Therefore, there is a problem that the lithography process is increased by one step as compared with the semiconductor storage device described in JP-A-61-176148.</p><p> An object of the present invention is to provide a semiconductor storage device and a method for manufacturing the same, which can reduce the memory cell area and the number of lithography steps by reducing the alignment margin in the lithography process.</p><p> Another object of the present invention is to provide a semiconductor storage device and a method for manufacturing the same, which can easily etch a contact hole for a capacitor storage electrode and reduce the number of manufacturing steps.</p>

<p> The above purpose is to form a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer formed on the semiconductor substrate and the source diffusion layer and the drain diffusion layer via a gate insulating film. On the memory cell transistor having the above, the insulating film covering the upper surface and the side surface of the gate electrode, the first through hole covering the memory cell transistor and opening on the source diffusion layer, and the drain diffusion layer. A first interlayer insulating film in which an opened second through hole is formed, a capacitor storage electrode formed on the inner wall and bottom of the first through hole and connected to the source diffusion layer, and the capacitor storage A capacitor having a capacitor dielectric film formed so as to cover the electrodes and a capacitor facing electrode formed so as to cover the capacitor dielectric film, and a drain formed on the inner wall and bottom of the second through hole. A memory cell having a first contact conductive film connected to a diffusion layer, a second interlayer insulating film formed on the memory cell and formed with a bit line contact hole, and the second interlayer insulation. It is achieved by a semiconductor storage device formed on a film and having a bit wire connected to the first contact conductive film of the memory cell via the bit wire contact hole. By configuring the semiconductor storage device in this way, there is a margin for alignment with the gate electrode when forming the first through hole opened on the source diffusion layer and the second through hole opened on the drain diffusion layer. Since it is not necessary to secure the above, a semiconductor storage device having a small memory cell area can be configured. Further, since the first contact conductive film does not need to be completely embedded in the second through hole, it is not necessary to increase the film thickness of the capacitor storage electrode formed at the same time more than necessary, and the capacitor capacity is reduced. Can be prevented.</p><p> Further, a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film are provided. A memory cell conductor having a conductor, an insulating film covering the upper surface and side surfaces of the gate electrode, a first through hole covering the memory cell transistor and opened on the source diffusion layer, and an opening on the drain diffusion layer. A first interlayer insulating film in which a second through hole is formed, a first embedded conductor embedded in the bottom of the first through hole and connected to the source diffusion layer, and the first A second embedded conductor embedded in the bottom of the second through hole and connected to the drain diffusion layer, an inner wall of the first through hole, and an upper surface of the first embedded conductor are formed. A capacitor storage electrode connected to the source diffusion layer via the first embedded conductor, a semiconductor dielectric film formed so as to cover the capacitor storage electrode, and a capacitor dielectric film formed so as to cover the capacitor dielectric film. The drain diffusion layer is formed on the inner wall of the second through hole, the upper surface of the second embedded conductor, and the drain diffusion layer via the second embedded conductor. On a memory cell having a first contact conductive film connected, a second interlayer insulating film formed on the memory cell and having a bit wire contact hole formed, and the second interlayer insulating film. It is also achieved by a semiconductor storage device characterized by having a bit wire formed and connected to the first contact conductive film of the memory cell via the bit wire contact hole. By configuring the semiconductor storage device in this way, when forming a through hole or the like having a large aspect ratio, an embedded conductor having low resistance is formed in advance in a region in contact with the semiconductor substrate to form an ohmic contact. Even when the integration of elements progresses and the aspect ratio of the through hole increases, the contact characteristics at the bottom of the through hole can be ensured.</p><p> Further, a source diffusion layer and a drain diffusion layer formed on the semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film are provided. The memory cell transistor to be provided, the first through hole which covers the memory cell transistor and is opened on the source diffusion layer, and the second through hole which is opened on the drain diffusion layer are separated from the semiconductor substrate. A first interlayer insulating film formed so as to surround the first through hole of the region and having an opening diameter wider than that of the first through hole, an inner wall and a bottom of the opening, and the first A capacitor storage electrode formed on the inner wall and bottom of the through hole 1 and connected to the source diffusion layer, a capacitor dielectric film formed so as to cover the capacitor storage electrode, and a capacitor dielectric film so as to cover the capacitor dielectric film. A memory cell having a capacitor having a capacitor facing electrode formed in the above, a first contact conductive film formed on the inner wall and bottom of the second through hole and connected to the drain diffusion layer, and the memory. A second interlayer insulating film formed on the cell and formed with a bit wire contact hole, and the first interlayer insulating film formed on the second interlayer insulating film and formed through the bit wire contact hole of the memory cell. It is also achieved by a semiconductor storage device characterized by having a bit wire connected to a contact conductive film. By configuring the semiconductor storage device in this way, the opening diameter of the through hole can be made extremely small without reducing the capacitor capacity. This makes it possible to prevent a short circuit between the bit wire and the word wire due to the adhesion of dust or the like.</p><p> Further, in the above-mentioned semiconductor storage device, the capacitor storage electrode has a first columnar conductor formed inside the first through-hole so as to be separated from the inner wall of the first through-hole. It is desirable that the contact conductive film has a second columnar conductor formed inside the second through hole so as to be separated from the inner wall of the second through hole. By doing so, the first columnar conductor also functions as a capacitor storage electrode, so that the capacitor capacity can be significantly increased. Further, since the wiring between the drain diffusion layer and the bit wire can be formed by the first contact conductive film and the second columnar conductor, the wiring resistance between the drain diffusion layer and the bit wire can be reduced. ..</p><p> Further, in the above semiconductor storage device, it is desirable that the first interlayer insulating film in the region in contact with the insulating film is made of a material having etching characteristics different from that of the insulating film. By configuring the semiconductor storage device in this way, the insulating film can be used as an etching stopper when opening the through hole, and the substrate opening can be formed by self-alignment. Therefore, it is not necessary to secure a alignment margin with the gate electrode when forming the through hole, so that a semiconductor storage device having a small memory cell area can be configured.</p><p> Further, in the above semiconductor storage device, it is desirable that the insulating film is a silicon nitride film, and the material having etching characteristics different from that of the insulating film is a silicon oxide film or a silicon oxide film to which impurities are added.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the capacitor storage electrode further has a columnar conductor protruding in a columnar shape from the first through hole into the opening. By doing so, the surface area of the capacitor storage electrode is increased by the amount of the columnar conductor, so that the capacitor capacity can be increased.</p><p> Further, in the above-mentioned semiconductor storage device, the sidewall insulating film formed on the inner wall of the bit wire contact hole is further provided, and the bit wire is insulated from the capacitor counter electrode by the sidewall insulating film. Is desirable. By configuring the semiconductor storage device in this way, the lithography process for forming the capacitor counter electrode and the lithography process for forming the bit line contact hole can be performed at the same time.</p><p> Further, in the above-mentioned semiconductor storage device, the peripheral circuit transistor formed on the semiconductor substrate around the memory cell region in which the memory cell is formed and the bit formed on the first interlayer insulating film. It is desirable that the wire and a wiring layer made of the same conductive layer are further provided, and the wiring layer is directly connected to the gate electrode, the source diffusion layer, or the drain diffusion layer of the peripheral circuit transistor. By configuring the semiconductor storage device in this way, the above-mentioned semiconductor storage device can be configured without sacrificing the operating speed of peripheral circuits.</p><p> Further, in the above-mentioned semiconductor storage device, a peripheral circuit transistor formed on the semiconductor substrate around the memory cell region in which the memory cell is formed, and a third interlayer insulating film formed on the bit wire. Further, the wiring layer is further provided with the wiring layer formed on the third interlayer insulating film, and the wiring layer is directly connected to the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor. desirable. By configuring the semiconductor storage device in this way, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps and without sacrificing the operating speed of peripheral circuits.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the wiring layer is directly connected to the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor, the capacitor counter electrode, or the bit wire. By doing so, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps and without sacrificing the operating speed of peripheral circuits.</p><p> Further, in the above-mentioned semiconductor storage device, the structure is the same as that of the laminated film of the capacitor counter electrode and the second interlayer insulating film directly under the bit wire in the region connecting the bit wire and the wiring layer. It is desirable to further have an etching protection pattern. By doing so, the deep through-holes formed in the peripheral circuit region and the shallow through-holes formed on the bit wire or the capacitor counter electrode can be opened at the same time without causing a short circuit between the bit wire and the semiconductor substrate. it can.</p><p> Further, in the above-mentioned semiconductor storage device, the peripheral circuit transistor formed on the semiconductor substrate around the memory cell region in which the memory cell is formed and the bit formed on the second interlayer insulating film. The wire and the wiring layer made of the same conductive layer are further provided, and the capacitor facing electrode and the second interlayer insulating film are formed so as to extend to the region where the peripheral circuit transistor is formed. It is desirable that the wiring layer is directly connected to the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor. By configuring the semiconductor storage device in this way, it is possible to form the wiring layer of the peripheral circuit without increasing the number of manufacturing steps.</p><p> Further, in the above-mentioned semiconductor storage device, a peripheral circuit transistor formed on the semiconductor substrate around the memory cell region in which the memory cell is formed, and a gate electrode, a source diffusion layer, or a source diffusion layer of the peripheral circuit transistor. It further has a second contact conductive film formed on the inner wall and bottom of the third through hole formed on the first interlayer insulating film on the drain diffusion layer, and is a gate electrode of the peripheral circuit transistor. It is desirable that the source diffusion layer or the drain diffusion layer is connected to the wiring layer formed on the first interlayer insulating film via the second contact conductive film. By configuring the semiconductor storage device in this way, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps.</p><p> Further, in the above-mentioned semiconductor storage device, the third embedded conductor formed at the bottom of the third through hole is further provided, and the second contact conductive film includes the third embedded conductor. It is desirable that the conductor is connected to the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor via the conductor. By configuring the semiconductor storage device in this way, when forming a through hole or the like having a large aspect ratio, an embedded conductor having low resistance is formed in advance in a region in contact with the semiconductor substrate to form an ohmic contact. Even when the integration of elements progresses and the aspect ratio of the through hole increases, the contact characteristics at the bottom of the through hole can be ensured.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the first interlayer insulating film is a laminated film in which a plurality of insulating materials having different etching characteristics are laminated. If the semiconductor storage device is configured in this way, it can be easily performed even when opening a through hole having a large aspect ratio.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the laminated film is laminated by sandwiching a silicon nitride film between silicon oxide films.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the laminated film is a film in which a silicon nitride film is laminated on a silicon oxide film.</p><p> Further, a source diffusion layer and a drain diffusion layer formed on the semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film are provided. A first interlayer insulating film having a memory cell transistor, an insulating film covering the upper surface and the side surface of the gate electrode, and a first through hole covering the memory cell transistor and opening on the source diffusion layer. A contact portion formed on the inner wall and bottom of the first through hole and connected to the source diffusion layer, and a protrusion formed by being connected to the contact portion and projecting onto the first interlayer insulating film. A memory having a capacitor having a capacitor storage electrode having a portion, a capacitor dielectric film formed so as to cover the capacitor storage electrode, and a capacitor counter electrode formed so as to cover the capacitor dielectric film. It is also achieved by a semiconductor storage device characterized by having a cell. By doing so, the capacitor can be configured by using the front and back surfaces of the protruding portion, so that the capacitor capacity can be increased.</p><p> Further, in the above-mentioned semiconductor storage device, a second interlayer insulating film formed on the memory cell and having a bit line contact hole reaching the drain diffusion layer via the first interlayer insulating film and the above-mentioned It is desirable to further have a bit wire formed on the second interlayer insulating film and connected to the drain diffusion layer of the memory cell via the bit wire contact hole.</p><p> Further, in the semiconductor storage device, the first interlayer insulating film is formed with a second through hole opened on the drain diffusion layer, and is formed on the inner wall and the bottom of the second through hole. It is possible to further have a contact conductive film connected to the drain diffusion layer and a bit wire formed on the memory cell via a second interlayer insulating film and connected to the contact conductive film. desirable.</p><p> Further, in the above-mentioned semiconductor storage device, the first interlayer insulating film has a silicon nitride film and a silicon oxide film, and the silicon nitride film is formed on the gate electrode, and the silicon oxide film is formed. Is formed on the silicon nitride film, and it is desirable that the second interlayer insulating film is formed of a silicon oxide film. By doing so, the protrusion can be easily formed. In addition, the variation in capacitor capacity can be reduced.</p><p> Further, in the above semiconductor storage device, it is desirable that the first contact conductive film, the second contact conductive film, or the capacitor storage electrode is a conductive material that contacts N-type silicon and P-type silicon. .. By configuring the semiconductor storage device in this way, the contact characteristics with the silicon substrate can be improved.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the bit wire contact hole has a shape elongated in the extending direction of the bit wire. By configuring the semiconductor storage device in this way, the bit lines and word lines can be arranged with the minimum processing dimensions, so that the memory cell area can be significantly reduced.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the bit wires have a film thickness of half or less of the interval between the bit wires. By configuring the semiconductor storage device in this way, capacitive coupling between bit lines can be suppressed.</p><p> Further, a plurality of bit lines arranged in parallel, a plurality of word lines arranged in parallel in a direction intersecting the plurality of bit lines, and a sense amplifier provided at one end of each of the bit lines, respectively. It has a decoder provided at one end of the word line and a memory cell according to any one of the above provided at each intersection of the bit line and the word line, and the plurality of sense amplifiers have 2 Each set is provided on the opposite side of the memory cell area in which the memory cell is formed, and the plurality of the decoders are divided into two sets, and the other opposite side of the memory cell area is provided. It is also achieved by a semiconductor storage device characterized in that each set is provided on a side portion . By configuring the semiconductor storage device in this way, it is possible to configure a peripheral circuit connected to the bit line and the word line arranged with the minimum processing dimensions.</p><p> Further, a source diffusion layer and a drain diffusion layer formed on the semiconductor substrate, and a gate electrode formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film are provided. A first through hole that covers the memory cell transistor and has a first through hole opened on the source diffusion layer and a second through hole opened on the drain diffusion layer. Capacitor storage formed on the interlayer insulating film, the embedded conductor embedded in the first through hole, and the first interlayer insulating film, and connected to the source diffusion layer via the embedded conductor. A memory cell having an electrode, a capacitor dielectric film formed so as to cover the capacitor storage electrode, and a capacitor having a capacitor facing electrode formed so as to cover the capacitor dielectric film, and the first It has a bit wire formed on an interlayer insulating film and connected to the drain diffusion layer through the second through hole, and the embedded conductor and the bit wire are formed by the same conductive layer. It is also achieved by a semiconductor storage device characterized by being present. By doing so, it is possible to reduce the etching time required to open the through hole for contact of the capacitor storage electrode in the manufacturing process, so that it is possible to prevent the bit wire from being exposed during this etching.</p><p> Further, in the above semiconductor storage device, it is desirable that the embedded conductor is formed on the side wall and the bottom of the first through hole.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the first through-hole and the second through-hole are formed apart from the outside of the gate electrode.</p><p> Further, in the above-mentioned semiconductor storage device, it is desirable that the upper surface and the side surface of the bit wire are covered with an insulating film that functions as an etching stopper for the second interlayer insulating film formed on the bit wire. By doing so, it is possible to reduce the damage given to the bit wire when opening the through hole for contact of the capacitor storage electrode.</p><p> Further, in the semiconductor storage device, the second interlayer insulating film is formed with a third through hole in which the embedded conductor is exposed, and the capacitor dielectric film is formed of the third through hole. It is desirable that it is formed on the side wall and bottom surface of the through hole. By doing so, the height difference between the peripheral circuit area and the memory cell area can be reduced, so that the rules of the wiring layer formed on the peripheral circuit area can be reduced.</p><p> Further, after laminating and depositing the first conductive film and the first insulating film on the semiconductor substrate, the first conductive film and the first insulating film are patterned, and the upper surface is the first insulating film. A gate electrode forming step of forming a gate electrode made of the first conductive film covered with a film, and diffusion using the gate electrode as a mask to introduce impurities into the semiconductor substrate to form a source diffusion layer and a drain diffusion layer. A layer forming step, a first sidewall insulating film forming step of forming a first sidewall insulating film on the side wall of the gate electrode, a first through hole opened on the source diffusion layer, and the drain. The first interlayer insulating film forming step of forming the first interlayer insulating film in which the second through hole opened on the diffusion layer is formed, and the semiconductor substrate on which the first interlayer insulating film is formed. A second conductive film deposition step of depositing a second conductive film on the surface, and the first interlayer so as to leave the second conductive film inside the first through hole and the second through hole. The second conductive film on the insulating film is removed, and a semiconductor storage electrode made of the second conductive film formed in the first through hole and a second through hole formed in the second through hole. A capacitor dielectric material is formed on the semiconductor substrate on which the conductive film removing step of forming the first contact conductive film composed of two conductive films, the capacitor storage electrode, and the first contact conductive film are formed. After depositing the second insulating film to be the film and the third conductive film to be the semiconductor counter electrode, the third conductive film is patterned to form the semiconductor counter electrode. It is also achieved by a method for manufacturing a semiconductor storage device, which is characterized by having. By manufacturing the semiconductor storage device in this way, a semiconductor storage device having a small memory cell area can be formed without increasing the electrical resistance between the bit line-drain diffusion layers and without reducing the capacitor capacity. ..</p><p> Further, in the method for manufacturing a semiconductor storage device, in the capacitor facing electrode forming step, the third insulating film deposited on the third conductive film and the third conductive film are patterned, and the capacitor facing electrode is formed. Then, a bit wire contact hole opened on the second through hole is formed, and after the capacitor counter electrode forming step, a fourth insulating film is deposited and the fourth insulating film is anisotropically etched. A second sidewall insulating film forming step of forming a second sidewall insulating film on the inner wall of the bit wire contact hole and at the same time removing the second insulating film at the bottom of the bit wire contact hole. It is further desirable to have a bit wire forming step of forming a bit wire formed on the third insulating film and connected to the first contact conductive film formed in the bit wire contact hole and exposed in the bit wire contact hole. If the semiconductor storage device is manufactured in this way, the lithography process for forming the capacitor counter electrode and the lithography process for forming the bit line contact hole can be performed at the same time.</p><p> After the transistor hole forming step and the fourth insulating film are deposited on the third insulating film on which the bit wire contact hole is formed, the bit wire is anisotropically etched by etching the fourth insulating film. A second sidewall insulating film forming step of forming the second sidewall insulating film on the inner wall of the contact hole and at the same time removing the second insulating film at the bottom of the bit wire contact hole, and a step of forming the second sidewall insulating film on the capacitor counter electrode. The third through hole opened in the third insulating film and the first interlayer insulating film on the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor. A second through-hole forming step of forming an opened fourth through hole, a bit wire connected to the first contact conductive film exposed in the bit wire contact hole, and the third through hole. Formation of a wiring layer that forms a first wiring layer connected to the capacitor facing electrode via a through hole and a second wiring layer connected to the peripheral circuit transistor via the fourth through hole. It is also achieved by a method of manufacturing a semiconductor storage device, which comprises a process. If the semiconductor storage device is manufactured in this way, the above-mentioned semiconductor storage device can be configured without sacrificing the operating speed of peripheral circuits. The peripheral circuit via the bit wire connected to the contact conductive film 1, the first wiring layer connected to the capacitor counter electrode via the third through hole, and the fourth through hole. It is also achieved by a method for manufacturing a semiconductor storage device, which comprises a wiring layer forming step for forming a second wiring layer connected to a transistor for use. If the semiconductor storage device is manufactured in this way, the above-mentioned semiconductor storage device can be configured without sacrificing the operating speed of peripheral circuits. The peripheral circuit via the bit wire connected to the contact conductive film 1, the first wiring layer connected to the capacitor counter electrode via the third through hole, and the fourth through hole. It is also achieved by a method for manufacturing a semiconductor storage device, which comprises a wiring layer forming step for forming a second wiring layer connected to a transistor for use. If the semiconductor storage device is manufactured in this way, the above-mentioned semiconductor storage device can be configured without sacrificing the operating speed of peripheral circuits.</p><p> Further, in the method for manufacturing a semiconductor storage device, after the second sidewall insulating film forming step, a bit wire forming a bit wire connected to the contact conductive film exposed in the bit wire contact hole. The second through-hole forming step further comprises a forming step and a second interlayer insulating film forming step of forming a second interlayer insulating film on the semiconductor substrate on which the bit wire is formed. A third through hole reaching the capacitor counter electrode is formed in the second interlayer insulating film and the third insulating film, and the second interlayer insulating film and the first interlayer insulating film are formed with the above. A fourth through hole that reaches the source diffusion layer, the drain diffusion layer, or the second gate electrode of the peripheral circuit transistor is formed, and in the wiring layer forming step, the third through hole is formed. It is desirable to form a first wiring layer connected to the capacitor counter electrode and a second wiring layer connected to the peripheral circuit transistor via the fourth through hole. If the semiconductor storage device is manufactured in this way, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps and without sacrificing the operating speed of peripheral circuits.</p><p> Further, in the method for manufacturing a semiconductor storage device, when a fifth through hole connecting the bit wire and the wiring layer is formed in the second through hole forming step, the bit wire contact hole is formed. In the forming step, from the laminated film of the third conductive film and the third insulating film on the first interlayer insulating film of the region forming the contact hole connecting the bit wire and the wiring layer. It is desirable to form an etching protection pattern. By manufacturing the semiconductor storage device in this way, it is possible to prevent the first interlayer insulating film directly under the bit wire from being etched even when a deep through hole formed in the peripheral circuit region is opened. , It is possible to prevent a short circuit with the semiconductor substrate.</p><p> A bit wire contact hole forming step of opening a third through hole opened on the source diffusion layer, the drain diffusion layer, or the second gate electrode of a path transistor up to the second insulating film, and the above-mentioned After selectively forming a photoresist covering the bit wire contact hole, the second insulating film in the third through hole and the first interlayer insulating film are etched to obtain the peripheral circuit transistor. A method for manufacturing a semiconductor storage device, which comprises a second through-hole forming step of forming the source diffusion layer, the drain diffusion layer, or the third through hole reaching onto the second gate electrode. Also achieved by. If the semiconductor storage device is manufactured in this way, it is not necessary to perform fine alignment when opening a through hole in the peripheral circuit portion, so that the lithography process can be simplified.</p><p> Further, in the method for manufacturing a semiconductor storage device, in the bit wire contact hole forming step, the capacitor storage electrode and the second insulating film to be a capacitor dielectric film are formed on the second conductive film. After the third conductive film serving as a capacitor counter electrode, the third insulating film, and the mask film functioning as an etching stopper are continuously deposited, the mask film, the third insulating film, and the third insulating film are deposited. The conductive film of the above is patterned to form the capacitor facing electrode and the bit wire contact hole opened on the second through hole, and the source diffusion layer, the drain diffusion layer, or the drain diffusion layer of the peripheral circuit transistor is formed. The third through hole that opens on the second gate electrode is opened onto the second insulating film, and in the second through hole forming step, a capacitor that covers the bit wire contact hole is selectively selected. Then, using the mask film and the photoresist as an etching mask, the second insulating film in the third through hole and the first interlayer insulating film are etched to form the peripheral circuit transistor. It is desirable to form the third through hole that reaches over the source diffusion layer, the drain diffusion layer, or the second gate electrode. If the semiconductor storage device is manufactured in this way, the lithography process can be simplified.</p><p> Further, in the method for manufacturing a semiconductor storage device, it is desirable that the mask film is a silicon film.</p><p> After depositing a second insulating film to be a capacitor dielectric film, a third conductive film to be a capacitor counter electrode, and a third insulating film on the formed semiconductor substrate, the third insulation is performed. The bit wire contact hole forming step of patterning the film and the third conductive film to form the capacitor counter electrode and the bit wire contact hole opened on the second through hole, and the bit wire contact hole After depositing the fourth insulating film on the formed third insulating film, the fourth insulating film is anisotropically etched to form a second sidewall insulating film on the inner wall of the bit wire contact hole. At the same time as forming the bit wire contact hole, the second sidewall insulating film forming step of removing the second insulating film at the bottom of the bit wire contact hole, and the first contact conductive film exposed in the bit wire contact hole. A semiconductor storage device comprising a connected bit wire and a wiring layer forming step of forming a wiring layer connected to the second contact conductive film formed in the third through hole. It is also achieved by the manufacturing method of. If the semiconductor storage device is manufactured in this way, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps. A semiconductor storage device comprising a continuous bit wire and a wiring layer forming step of forming a wiring layer connected to the second contact conductive film formed in the third through hole. It is also achieved by the manufacturing method of. If the semiconductor storage device is manufactured in this way, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps. A semiconductor storage device comprising a continuous bit wire and a wiring layer forming step of forming a wiring layer connected to the second contact conductive film formed in the third through hole. It is also achieved by the manufacturing method of. If the semiconductor storage device is manufactured in this way, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps.</p><p> Further, in the method for manufacturing a semiconductor storage device, in the capacitor counter electrode forming step, the third conductive film is formed into the first through hole or the first through hole so that the surface of the third conductive film becomes flat. It is desirable to embed it in the through hole of 2. If the semiconductor storage device is manufactured in this way, the lithography process for forming the capacitor counter electrode and the lithography process for forming the bit line contact hole can be performed at the same time.</p><p> Further, in the method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a fifth insulating film is deposited and the fifth insulating film is anisotropically etched to perform the second. A third sidewall insulating film forming step of forming a third sidewall insulating film on the inner walls of the first through hole and the second through hole on which the conductive film is formed, and the third sidewall. After the conductive film removing step, the first through hole in which the insulating film is formed and the fourth conductive film depositing step of depositing the fourth conductive film in which the second through hole is embedded are performed in the third conductive film removing step. By removing the sidewall insulating film, the first columnar conductor made of the fourth conductive film is formed in the first through hole, and the fourth conductive film is formed in the second through hole. It further includes a columnar conductor forming step of forming the second columnar conductor, and in the conductive film removing step, the fourth conductive film, the said, until the third sidewall insulating film is exposed on the surface. It is desirable to remove the second conductive film and the first interlayer insulating film. When the semiconductor storage device is manufactured in this way, the capacitor storage electrode having the first columnar conductor formed so as to be separated from the inner wall of the first through hole and the inner wall of the second through hole are formed so as to be separated from each other. Since the first contact conductive film having the second columnar conductor can be formed, the capacitor capacity can be significantly increased and the wiring resistance between the drain diffusion layer and the bit wire can be reduced. .. Further, in the above-mentioned manufacturing method of the semiconductor storage device, since the inside of the through hole is embedded when the second conductive film is removed, it is possible to prevent the abrasive or the like from entering the through hole. This makes it possible to prevent a decrease in yield due to an abrasive or the like.</p><p> Further, in the method for manufacturing a semiconductor storage device, in the first interlayer insulating film forming step, after the first interlayer insulating film is deposited and before the through hole is formed, the surface of the first interlayer insulating film is formed. It is desirable to flatten by polishing. By manufacturing the semiconductor storage device in this way, the global flatness on the interlayer insulating film is improved, so that the focus depth when opening the through hole can be made shallow, and fine patterning can be performed.</p><p> Further, in the method for manufacturing a semiconductor storage device, it is desirable that the surface of the semiconductor substrate is polished to remove the second conductive film on the first interlayer insulating film in the conductive film removing step. By manufacturing the semiconductor storage device in this way, it is possible to easily form a capacitor storage electrode having a matching through-hole shape and a conductive film for contact.</p><p> Further, in the method for manufacturing a semiconductor storage device, in the first interlayer insulating film forming step, the first interlayer insulating film is formed by a laminated film obtained by laminating a plurality of insulating materials having different etching characteristics, and the insulating film is formed. It is desirable to open the through holes by etching the material layer by layer. If the semiconductor storage device is manufactured in this way, it can be easily performed even when opening a through hole having a large aspect ratio.</p><p> Further, in the method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a photoresist is applied onto the second conductive film, and the first through hole and the second through hole are formed. Or, the photoresist coating step to be embedded in the third through hole is embedded in the first through hole, the second through hole, or the third through hole after the conductive film removing step. Further, the photoresist peeling step of peeling the photoresist is further provided, and in the conductive film removing step, the first through hole, the second through hole, or the second through hole is inside the third through hole. It is desirable to remove the second conductive film and the photoresist on the first interlayer insulating film so that the conductive film and the photoresist remain. When the semiconductor storage device is manufactured in this way, the abrasive or the like does not enter the through hole when the second conductive film is removed by polishing, so that it is possible to prevent a decrease in yield due to this.</p><p> Further, in the method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a sixth insulating film having etching characteristics different from that of the first interlayer insulating film is deposited, and the first through is deposited. The hole, the second through hole, or the insulating film deposition step to be embedded in the third through hole is performed after the conductive film removing step, the first through hole, the second through hole, or the first through hole. It further has a sixth insulating film removing step of removing the sixth insulating film embedded in the through hole of 3, and in the conductive film removing step, the first through hole and the second through hole Or, the second conductive film and the sixth insulating film on the first interlayer insulating film so that the second conductive film and the sixth insulating film remain inside the third through hole. It is desirable to remove the film. When the semiconductor storage device is manufactured in this way, the abrasive or the like does not enter the through hole when the second conductive film is removed by polishing, so that it is possible to prevent a decrease in yield due to this.</p><p> Further, in the method for manufacturing a semiconductor storage device, it is desirable that the first interlayer insulating film is a laminated film having an insulating film having an etching characteristic different from that of the sixth insulating film on its surface. By doing so, only the insulating film embedded in the through hole can be selectively removed after polishing.</p><p> Further, in the method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a sixth insulating film having substantially the same etching characteristics as the first interlayer insulating film is deposited, and the first through is deposited. The hole, the second through hole, or the insulating film deposition step to be embedded in the third through hole is performed after the conductive film removing step, the first through hole, the second through hole, or the first through hole. Further, the insulating film removing step of removing the sixth insulating film and the first interlayer insulating film embedded in the through hole of 3 is provided, and in the conductive film removing step, the first through hole, the said The second conductive film and the second conductive film on the first interlayer insulating film so that the second conductive film and the sixth insulating film remain inside the second through hole or the third through hole. It is desirable to remove the sixth insulating film. When the semiconductor storage device is manufactured in this way, the abrasive or the like does not enter the through hole when the second conductive film is removed by polishing, so that it is possible to prevent a decrease in yield due to this.</p><p> Further, in the method for manufacturing a semiconductor storage device, the first interlayer insulating film has etching characteristics substantially equal to those of the sixth insulating film on an insulating film having etching characteristics different from those of the sixth insulating film. It is a laminated film on which an insulating film is deposited, and in the insulating film removing step, it is desirable to remove the sixth insulating film and the insulating film having substantially the same etching characteristics as the sixth insulating film. By doing so, in the insulating film removing step, the sixth insulating film and the insulating film having substantially the same etching characteristics as the sixth insulating film can be selectively removed.</p><p> A fourth through hole opened on the embedded conductor, a fifth through hole opened on the second embedded conductor, and a sixth through hole opened on the third embedded conductor. A second interlayer insulating film forming step of forming a second interlayer insulating film formed with and a third conductive film is deposited on the semiconductor substrate on which the second interlayer insulating film is formed. The second interlayer insulation so as to leave the second conductive film inside the third through hole, the fourth through hole, the fifth through hole, and the sixth through hole. The third conductive film on the film is removed, and the capacitor storage electrode made of the third conductive film formed in the fourth through hole and the third conductive film formed in the fifth through hole. A conductive film removing step of forming a first contact conductive film made of the third conductive film and a second contact conductive film made of the third conductive film formed in the sixth through hole. It is also achieved by a method for manufacturing a semiconductor storage device, which is characterized by having the above. By manufacturing the semiconductor storage device in this way, it is possible to secure the contact characteristics at the bottom of the through hole even when the integration of the elements progresses and the aspect ratio of the through hole increases. It is also achieved by a method for manufacturing a semiconductor storage device, which comprises a conductive film removing step of forming a second contact conductive film composed of the conductive film of the above. By manufacturing the semiconductor storage device in this way, it is possible to secure the contact characteristics at the bottom of the through hole even when the integration of the elements progresses and the aspect ratio of the through hole increases. It is also achieved by a method for manufacturing a semiconductor storage device, which comprises a conductive film removing step of forming a second contact conductive film composed of the conductive film of the above. By manufacturing the semiconductor storage device in this way, it is possible to secure the contact characteristics at the bottom of the through hole even when the integration of the elements progresses and the aspect ratio of the through hole increases.</p><p> Further, in the method for manufacturing a semiconductor storage device, it is desirable that the surface of the semiconductor substrate is polished to remove the third conductive film on the surface of the second interlayer insulating film in the conductive film removing step. By manufacturing the semiconductor storage device in this way, it is possible to flatten the interlayer insulating film and at the same time form an embedded conductor.</p><p> Further, in the method for manufacturing a semiconductor storage device, the first insulating film and the first sidewall function as an etching stopper when forming the through hole, and the through hole is the first through hole. It is desirable to form the insulating film and the first sidewall insulating film by self-alignment. When the semiconductor storage device is manufactured in this way, the source diffusion layer and the drain diffusion layer can be easily exposed at the bottom of the through hole.</p><p> Further, a gate electrode forming step of depositing and patterning a first conductive film on a semiconductor substrate to form a gate electrode made of the first conductive film, and using the gate electrode as a mask to add impurities to the semiconductor substrate. The diffusion layer forming step of introducing and forming the source diffusion layer and the drain diffusion layer, the first through hole opened on the source diffusion layer, and the second through hole opened on the drain diffusion layer are The interlayer insulating film forming step of forming the formed interlayer insulating film and the interlayer having a larger opening diameter than the first through hole and not reaching the semiconductor substrate are surrounded by the first through hole. The opening forming step of forming the insulating film, the second conductive film deposition step of depositing the second conductive film on the semiconductor substrate on which the interlayer insulating film is formed, and the second through hole and the opening. A capacitor storage electrode made of the second conductive film formed in the opening by removing the second conductive film on the interlayer insulating film so as to leave the second conductive film inside, and the above. The conductive film removing step of forming the first contact conductive film composed of the second conductive film formed in the second through hole, the capacitor storage electrode, and the first contact conductive film After depositing an insulating film to be a capacitor dielectric film and a third conductive film to be a capacitor counter electrode on the formed semiconductor substrate, the third conductive film is patterned to form the capacitor counter electrode. It is also achieved by a method for manufacturing a semiconductor storage device, which comprises a capacitor facing electrode forming step for forming. By manufacturing the semiconductor storage device in this way, the space between the gate electrode and the through hole can be increased, so that it is possible to prevent the bit wire and the word wire from being short-circuited due to the influence of dust generated in the manufacturing process. it can. Further, since the opening for forming the capacitor dielectric film is provided in addition to the through hole having a small opening diameter, the capacitor capacity is not reduced.</p><p> Further, in the method for manufacturing a semiconductor storage device, after the interlayer insulating film forming step, a fourth conductive film is deposited to embed the first through hole and the second through hole. The deposition step is further provided, and in the opening forming step, the columnar conductor made of the fourth conductive film embedded in the first through hole remains in a protruding state in the opening. It is desirable to form an opening. By manufacturing the semiconductor storage device in this way, it is possible to prevent the semiconductor substrate exposed in the first through hole from being damaged when the opening is formed. Further, since the capacitor storage electrode is formed so as to cover the columnar conductor, the capacitor capacity can be increased.</p><p> Further, in the method for manufacturing a semiconductor storage device, it is desirable that the first through hole and the second through hole are formed at the same time in the interlayer insulating film forming step.</p><p> Further, in the method for manufacturing a semiconductor storage device, in the interlayer insulating film forming step, the interlayer insulating film is formed of a laminated film composed of two or more insulating films having different etching characteristics, and in the opening forming step, the interlayer insulating film is formed. It is desirable that the opening is opened to the interface between the insulating films having different etching characteristics. By doing so, the depth of the aperture can be controlled with good reproducibility, so that the variation in the capacitor capacitance can be reduced.</p><p> Further, a gate electrode forming step of depositing and patterning a first conductive film on a semiconductor substrate to form a gate electrode made of the first conductive film, and using the gate electrode as a mask to add impurities to the semiconductor substrate. The diffusion layer forming step of introducing and forming the source diffusion layer and the drain diffusion layer, the first through hole opened on the source diffusion layer, and the second through hole opened on the drain diffusion layer are The interlayer insulating film forming step of forming the formed interlayer insulating film, the second conductive film deposition step of depositing the second conductive film on the semiconductor substrate on which the interlayer insulating film is formed, and the second conductive film deposition step. A second conductive film patterning in which the conductive film is patterned to form a bit wire connected to the drain diffusion layer through the first through hole and an embedded conductor embedded in the second through hole. The step, a capacitor storage electrode connected to the source diffusion layer via the embedded conductor on the interlayer insulating film, a semiconductor dielectric film covering the capacitor storage electrode, and a capacitor covering the capacitor dielectric film. It is also achieved by a method for manufacturing a semiconductor storage device, which comprises a capacitor forming step of forming a capacitor having a counter electrode. When the semiconductor storage device is manufactured in this way, the capacitor storage electrode is embedded in the second through hole formed at the same time as the first through hole for the bit wire contact, and the embedded conductor is embedded at the same time as the bit wire formation. It can be connected to the source diffusion layer via. Therefore, since the etching time for forming the through hole for the capacitor storage electrode contact can be reduced without adding a new process, the insulating film on the bit wire is etched during this etching, and the bit wire is etched. Can be prevented from being exposed.</p><p> Further, in the method for manufacturing a semiconductor storage device, the first insulating film deposition step of depositing the first insulating film on the second conductive film is performed after the second conductive film deposition step. After the conductive film patterning step of 2, a sidewall insulating film forming step of forming a sidewall insulating film on the side wall of the bit wire is further provided, and in the second conductive film patterning step, the first insulating film is formed. It is desirable to process the second conductive film into the same pattern. When the semiconductor storage device is manufactured in this way, the embedded conductor is exposed to the surface at the same time, so that it is not necessary to form through holes for the capacitor storage electrode contacts by using the masking process as in the conventional case. That is, the masking process can be reduced by one process.</p><p> Further, in the method for manufacturing a semiconductor storage device, after the second conductive film patterning step, a second insulating film forming step of forming a second insulating film having an opening formed on the embedded conductor is performed. Further, in the capacitor forming step, it is desirable to selectively form the capacitor accumulating electrode on the side wall and the bottom of the opening. By doing so, the height difference between the memory cell area and the peripheral circuit area becomes small, so that the wiring rules of the wiring layer formed in the upper layer can be strictly designed.</p><p> Further, in the method for manufacturing a semiconductor storage device, the interlayer insulating film forming step includes an interlayer insulating film forming step of depositing an interlayer insulating film on the semiconductor substrate and the first interlayer insulating film on the interlayer insulating film. An etching stopper film forming step in which an opening is formed in the through hole and the region where the second through hole should be formed to form an etching stopper film having different etching characteristics from the interlayer insulating film, and a side wall portion of the etching stopper film. In addition, a sidewall forming step of forming a sidewall having different etching characteristics from the interlayer insulating film, and the second interlayer insulating film being etched using the etching stopper film and the sidewall as masks, and the first through It is desirable to have a hole and a through hole opening step of forming the interlayer insulating film in which the second through hole is formed. By manufacturing the semiconductor storage device in this way, it is possible to open a through hole having an aperture diameter equal to or less than the resolution limit of the exposure device.</p><p> Further, in the method for manufacturing a semiconductor storage device, in the interlayer insulating film forming step, the interlayer insulating film is deposited on the semiconductor substrate and then patterned using an electron beam drawing method as a mask. It is desirable to etch the interlayer insulating film to open the first through hole and the second through hole. By manufacturing the semiconductor storage device in this way, it is possible to open a first through hole and a second through hole having an aperture diameter equal to or less than the resolution limit of a normal exposure device.</p>

<p> As described above, according to the present invention, the source diffusion layer and the drain diffusion layer formed on the semiconductor substrate are formed on the semiconductor substrate between the source diffusion layer and the drain diffusion layer via the gate insulating film. A memory cell transistor having a gate electrode, an insulating film covering the upper surface and side surfaces of the gate electrode, a first through hole covering the memory cell transistor and opened on the source diffusion layer, and an opening on the drain diffusion layer. To cover the first interlayer insulating film on which the second through hole is formed, the capacitor storage electrode formed on the inner wall and bottom of the first through hole and connected to the source diffusion layer, and the capacitor storage electrode. A capacitor having a capacitor dielectric film formed in the above, a capacitor facing electrode formed so as to cover the capacitor dielectric film, and a second through hole formed on the inner wall and bottom of the second through hole and connected to a drain diffusion layer. A memory cell having one contact conductive film, a second interlayer insulating film formed on the memory cell and having a bit wire contact hole formed therein, and a bit wire contact formed on the second interlayer insulating film. Since the semiconductor storage device is composed of the bit wires connected to the first contact conductive film of the memory cell through the holes, the first through hole opened on the source diffusion layer and the opening on the drain diffusion layer. It is not necessary to secure a alignment margin with the gate electrode when forming the second through hole, and the memory cell area can be reduced. Further, since the first contact conductive film does not need to be completely embedded in the second through hole, it is not necessary to increase the film thickness of the capacitor storage electrode formed at the same time more than necessary, and the capacitor capacity is reduced. Can be prevented.</p><p> Further, a memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on a semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film. The transistor, the insulating film covering the upper and side surfaces of the gate electrode, the first through hole covering the memory cell conductor and opened on the source diffusion layer, and the second through hole opened on the drain diffusion layer The first interlayer insulating film on which the and was formed, the first embedded conductor embedded in the bottom of the first through hole and connected to the source diffusion layer, and embedded in the bottom of the second through hole, A second embedded conductor connected to the drain diffusion layer, an inner wall of the first through hole, and an upper surface of the first embedded conductor are formed, and the source diffusion layer is formed via the first embedded conductor. A capacitor having a connected capacitor storage electrode, a capacitor dielectric film formed so as to cover the capacitor storage electrode, and a capacitor facing electrode formed so as to cover the capacitor dielectric film, and a second through hole. On a memory cell having a first contact conductive film formed on an inner wall and an upper surface of the second embedded conductor and connected to a drain diffusion layer via the second embedded conductor, and on the memory cell. It is formed on the second interlayer insulating film formed and the bit wire contact hole is formed, and is connected to the first contact conductive film of the memory cell through the bit wire contact hole. Since the semiconductor storage device is composed of the bit wires, an ohmic contact is formed by the embedded conductor having low resistance in the region where the capacitor storage electrode or the conductive film for contact and the semiconductor substrate are in contact with each other. As a result, even when the integration of elements progresses and the aspect ratio of the through hole increases, the contact characteristics at the bottom of the through hole can be ensured.</p><p> Further, a memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on a semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film. A first through hole covering the transistor and the memory cell transistor and opened on the source diffusion layer, a second through hole opened on the drain diffusion layer, and a first through hole in a region separated from the semiconductor substrate. An opening having an opening diameter wider than that of the first through hole, and a first interlayer insulating film formed so as to surround the first through hole, and formed on the inner wall and bottom of the opening and the inner wall and bottom of the first through hole. A capacitor having a capacitor storage electrode connected to the source diffusion layer, a capacitor dielectric film formed so as to cover the capacitor storage electrode, and a capacitor counter electrode formed so as to cover the capacitor dielectric film. A memory cell having a first contact conductive film formed on the inner wall and bottom of the through hole 2 and connected to the drain diffusion layer, and a second memory cell formed on the memory cell to form a bit line contact hole. A capacitor is formed by the interlayer insulating film and the bit wire formed on the second interlayer insulating film and connected to the first contact conductive film of the memory cell via the bit wire contact hole to form a semiconductor storage device. The opening diameter of the through hole can be made extremely small without reducing the capacity. This makes it possible to prevent a short circuit between the bit wire and the word wire due to the adhesion of dust or the like.</p><p> Further, in the above-mentioned semiconductor storage device, a first columnar conductor formed inside the first through hole at a distance from the inner wall of the first through hole is provided on the capacitor electrode to form a second through hole. If a second columnar conductor formed inside the inner wall of the second through hole is provided on the first contact conductive film, the first columnar conductor also functions as a capacitor storage electrode. Therefore, the capacitor capacity can be significantly increased. Further, since the wiring between the drain diffusion layer and the bit wire can be formed by the first contact conductive film and the second columnar conductor, the wiring resistance between the drain diffusion layer and the bit wire can be reduced. ..</p><p> Further, in the above-mentioned semiconductor storage device, if the first interlayer insulating film in the region in contact with the insulating film covering the gate electrode is made of a material having etching characteristics different from that of the insulating film covering the gate electrode, a through hole is opened. In this case, the insulating film can be used as an etching stopper, and the substrate opening can be formed by self-alignment. Therefore, it is not necessary to secure a alignment margin with the gate electrode when forming the through hole, so that the memory cell area can be reduced.</p><p> Further, in the above semiconductor storage device, a silicon nitride film is applied to the insulating film covering the gate electrode, and a silicon oxide film or a silicon oxide film to which impurities are added is applied to a material having etching characteristics different from that of the insulating film covering the gate electrode. can do.</p><p> Further, in the above-mentioned semiconductor storage device, if the capacitor storage electrode is further provided with a columnar conductor projecting in a columnar shape in the opening from the first through hole, the surface area of the capacitor storage electrode is increased by the amount of the columnar conductor. Therefore, the capacity of the capacitor can be increased.</p><p> Further, if the bit wire and the capacitor counter electrode are insulated by providing a sidewall insulating film on the inner wall of the bit wire contact hole, a lithography process for forming the capacitor counter electrode and a lithography process for forming the bit wire contact hole can be performed. Can be done at once.</p><p> Further, a peripheral circuit transistor formed on a semiconductor substrate around the memory cell region in which the memory cell is formed and a wiring layer formed on the first interlayer insulating film and made of the same conductive layer as the bit wire. If the wiring layer is directly connected to the gate electrode, the source diffusion layer, or the drain diffusion layer of the peripheral circuit transistor, the above-mentioned semiconductor storage device can be configured without sacrificing the operating speed of the peripheral circuit.</p><p> Further, it is formed on a peripheral circuit transistor formed on a semiconductor substrate around a memory cell region in which a memory cell is formed, a third interlayer insulating film formed on a bit line, and a third interlayer insulating film. If the wiring layer is provided and the wiring layer is directly connected to the gate electrode, source diffusion layer or drain diffusion layer of the peripheral circuit transistor, the number of manufacturing steps is not increased and the operating speed of the peripheral circuit is sacrificed. The above-mentioned semiconductor storage device can be configured without the above.</p><p> Further, in the above-mentioned semiconductor storage device, if the wiring layer is directly connected to the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor, the capacitor counter electrode, or the bit wire, the number of manufacturing steps can be increased. The above-mentioned semiconductor storage device can be configured without sacrificing the operating speed of peripheral circuits.</p><p> Further, if an etching protection pattern having the same structure as the laminated film of the capacitor counter electrode and the second interlayer insulating film is provided directly under the bit wire in the region connecting the bit wire and the wiring layer, a peripheral circuit region can be provided. A deep through hole formed in the above and a shallow through hole formed on the bit wire or the counter electrode of the capacitor can be opened at the same time without causing a short circuit between the bit wire and the semiconductor substrate.</p><p> Further, a peripheral circuit transistor formed on a semiconductor substrate around a memory cell region in which a memory cell is formed, and a wiring layer formed on a second interlayer insulating film and made of the same conductive layer as a bit wire. The capacitor facing electrode and the second interlayer insulating film are provided so as to extend over the region where the peripheral circuit transistor is formed, and the wiring layer is formed on the gate electrode, the source diffusion layer or the drain diffusion layer of the peripheral circuit transistor. If directly connected, the wiring layer of the peripheral circuit can be formed without increasing the number of manufacturing steps.</p><p> Further, the peripheral circuit transistor formed on the semiconductor substrate around the memory cell region in which the memory cell is formed and the first interlayer insulation on the gate electrode, source diffusion layer, or drain diffusion layer of the peripheral circuit transistor. A second contact conductive film formed on the inner wall and bottom of the third through hole formed in the film is provided, and the gate electrode, source diffusion layer or drain diffusion layer of the peripheral circuit transistor is provided with the second contact. By connecting to the wiring layer formed on the first interlayer insulating film via the conductive conductive film, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps.</p><p> Further, a third embedded conductor formed at the bottom of the third through hole is provided, and the second contact conductive film is passed through the third embedded conductor to the gate electrode of the peripheral circuit transistor and the source diffusion. When connected to the layer or the drain diffusion layer, an ohmic contact is formed by the third embedded conductor having low resistance in the region where the second contact conductive film and the semiconductor substrate are in contact with each other. As a result, even when the integration of elements progresses and the aspect ratio of the through hole increases, the contact characteristics at the bottom of the through hole can be ensured.</p><p> Further, if the interlayer insulating film is formed of a laminated body in which a plurality of insulating materials having different etching characteristics are laminated, it is possible to easily open a through hole having a large aspect ratio with good controllability.</p><p> Further, as the above-mentioned laminated film, a laminated body in which a silicon nitride film is sandwiched between silicon oxide films and laminated can be applied.</p><p> Further, as the above-mentioned laminated film, a laminated body in which a silicon nitride film is laminated on a silicon oxide film can be applied.</p><p> Further, a memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on a semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film. The transistor, the insulating film covering the upper surface and the side surface of the gate electrode, the first interlayer insulating film covering the memory cell transistor and having the first through hole opened on the source diffusion layer, and the first through. A capacitor accumulating electrode having a contact portion formed on the inner wall and bottom of the hole and connected to the source diffusion layer, and a protruding portion connected to the contact portion and formed so as to project onto the first interlayer insulating film, and a capacitor. If the semiconductor storage device is configured by a memory cell having a capacitor having a capacitor dielectric film formed so as to cover the storage electrode and a capacitor facing electrode formed so as to cover the capacitor dielectric film, the semiconductor storage device is projected. Since the capacitor can be configured by using the front and back of the part, the capacitor capacity can be increased.</p><p> Further, in the above-mentioned semiconductor storage device, a second interlayer insulating film formed on the memory cell and having a bit line contact hole reaching the drain diffusion layer via the first interlayer insulating film and a second interlayer insulating film are formed. A bit wire formed on the interlayer insulating film and connected to the drain diffusion layer of the memory cell via a bit wire contact hole can be provided.</p><p> Further, in the above-mentioned semiconductor storage device, a second through hole opened on the drain diffusion layer is formed in the first interlayer insulating film, and is formed on the inner wall and the bottom of the second through hole. A contact conductive film connected to the drain diffusion layer and a bit wire formed on the memory cell via a second interlayer insulating film and connected to the contact conductive film can be provided.</p><p> Further, in the above-mentioned semiconductor storage device, the first interlayer insulating film is composed of a silicon nitride film and a silicon oxide film, the silicon nitride film is formed on the gate electrode, and the silicon oxide film is formed on the silicon nitride film. Then, the protruding portion can be easily formed. As a result, the variation in capacitor capacity can be reduced.</p><p> Further, if a conductive material that contacts N-type silicon and P-type silicon is used as the first contact conductive film, the second contact conductive film, or the capacitor storage electrode, the contact characteristics with the silicon substrate can be improved. it can.</p><p> Further, in the above-mentioned semiconductor storage device, if the bit line contact hole is formed to have a shape elongated in the extending direction of the bit line, the bit line and the word line can be arranged with the minimum processing dimensions, so that the memory cell area can be significantly increased. Can be reduced to.</p><p> Further, if the bit wires have a film thickness of half or less of the interval between the bit wires, the capacitive coupling between the bit wires can be suppressed.</p><p> In addition, a plurality of bit lines arranged in parallel, a plurality of word lines arranged in parallel in a direction intersecting the plurality of bit lines, and a sense amplifier provided at one end of each bit line and each word. A semiconductor storage device is composed of a decoder provided at one end of a line and a memory cell described in any of the above provided at an intersection of a bit line and a word line, and two sets of a plurality of sense amplifiers are provided. Each set is provided on the opposite side of the memory cell area in which the memory cell is formed, the plurality of decoders are divided into two sets, and each set is provided on the other opposite side of the memory cell area. For example, it is possible to configure a peripheral circuit connected to a bit line and a word line arranged with the minimum processing dimensions.</p><p> Further, a memory cell having a source diffusion layer and a drain diffusion layer formed on a semiconductor substrate, and a gate electrode formed on a semiconductor substrate between the source diffusion layer and the drain diffusion layer via a gate insulating film. A first interlayer insulating film covering the conductor, a memory cell transistor, and forming a first through hole opened on the source diffusion layer and a second through hole opened on the drain diffusion layer, and a first The embedded conductor embedded in the through hole 1 and the capacitor storage electrode formed on the first interlayer insulating film and connected to the source diffusion layer via the embedded conductor so as to cover the capacitor storage electrode. A memory cell having a formed capacitor dielectric film and a capacitor having a capacitor counter electrode formed so as to cover the capacitor dielectric film, and a second thru formed on a first interlayer insulating film. If a bit wire connected to the drain diffusion layer is provided via a hole and the embedded conductor and the bit wire are formed of the same conductive layer, a through hole for contact of the capacitor storage electrode is opened in the manufacturing process. Since the etching time required for this can be reduced, it is possible to prevent the bit wire from being exposed during this etching.</p><p> Further, in the above-mentioned semiconductor storage device, the embedded conductor may be formed only on the side wall and the bottom of the first through hole.</p><p> Further, in the above-mentioned semiconductor storage device, the first through hole and the second through hole can be formed so as to be separated from the outside of the gate electrode.</p><p> Further, if the upper surface and the side surface of the bit wire are covered with an insulating film that functions as an etching stopper for the second interlayer insulating film formed on the bit wire, the bit is opened when the through hole for contact of the capacitor storage electrode is opened. The damage to the line can be reduced.</p><p> Further, if a third through hole is formed in the second interlayer insulating film to expose the conductor embedded therein, and a capacitor dielectric film is formed on the side wall and the bottom surface of the third through hole, a peripheral circuit can be formed. Since the height difference between the area and the memory cell area can be reduced, the rules of the wiring layer formed on the upper layer can be reduced.</p><p> Further, after the first conductive film and the first insulating film are laminated and deposited on the semiconductor substrate, the first conductive film and the first insulating film are patterned, and the upper surface is covered with the first insulating film. A gate electrode forming step of forming a gate electrode composed of the first conductive film, a diffusion layer forming step of introducing impurities into a semiconductor substrate using the gate electrode as a mask, and forming a source diffusion layer and a drain diffusion layer, and a gate. A first sidewall insulating film forming step of forming a first sidewall insulating film on the side wall of the electrode, a first through hole opened on the source diffusion layer, and a second opened on the drain diffusion layer. The first interlayer insulating film forming step of forming the first interlayer insulating film in which the through holes are formed, and the second conductive film depositing the second conductive film on the semiconductor substrate on which the first interlayer insulating film is formed. The second conductive film on the first interlayer insulating film is removed so as to leave the second conductive film inside the first through hole and the second through hole, and the first Removal of the conductive film forming the first contact conductive film composed of the capacitor storage electrode formed in the through hole of the second conductive film and the second conductive film formed in the second through hole. On the semiconductor substrate on which the step, the capacitor storage electrode, and the first contact conductive film are formed, a second insulating film to be a capacitor dielectric film and a third conductive film to be a capacitor counter electrode are formed. Since the semiconductor storage device is manufactured by the capacitor facing electrode forming step of patterning the third conductive film and forming the capacitor facing electrode after the deposition, the semiconductor storage device having a small memory cell area can be used for bit line-drain diffusion. It can be formed without increasing the electrical resistance between the layers or decreasing the capacitance of the capacitor.</p><p> Further, in the capacitor counter electrode forming step, the third insulating film and the third conductive film deposited on the third conductive film are patterned, and the capacitor counter electrode and the bit wire opened on the second through hole are formed. After forming the contact hole and forming the capacitor counter electrode, a fourth insulating film is deposited, and the fourth insulating film is anisotropically etched to form a second sidewall insulating film on the inner wall of the bit wire contact hole. At the same time, the second sidewall insulating film forming step of removing the second insulating film at the bottom of the bit wire contact hole and the first one formed on the third insulating film and exposed in the bit wire contact hole. By performing the bit wire forming step of forming the bit wire connected to the contact conductive film, the lithography step of forming the capacitor counter electrode and the lithography step of forming the bit wire contact hole can be performed at the same time. .. As a result, the number of manufacturing processes can be reduced.</p><p> Further, after the first conductive film and the first insulating film are laminated and deposited on the semiconductor substrate, the first conductive film and the first insulating film are patterned to form a memory cell transistor. The first gate electrode made of the first conductive film whose upper surface is covered with the first insulating film is covered with the first insulating film in the region, and the second region forming the peripheral circuit transistor is covered with the first insulating film. A gate electrode forming step of forming a second gate electrode composed of the broken first conductive film, and an impurity introduced into the semiconductor substrate using the gate electrode as a mask, and the source diffusion layer and drain of the memory cell transistor in the first region. A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of a peripheral circuit transistor in a second region, and a first sidewall insulating film being formed on a side wall of a gate electrode. The sidewall insulating film forming step, the first through hole opened on the source diffusion layer of the memory cell conductor, and the second through hole opened on the drain diffusion layer of the memory cell transistor are formed. The first interlayer insulating film forming step of forming the interlayer insulating film of 1, the second conductive film depositing step of depositing the second conductive film on the semiconductor substrate on which the first interlayer insulating film is formed, and the first The second conductive film on the first interlayer insulating film is removed so as to leave the second conductive film inside the first through hole and the second through hole, and formed in the first through hole. A conductive film removing step of forming a first contact conductive film composed of a second conductive film formed in a second through hole and a capacitor storage electrode made of the second conductive film formed therein, and a capacitor storage electrode. After depositing the second insulating film to be the semiconductor dielectric film, the third conductive film to be the semiconductor counter electrode, and the third insulating film on the first contact conductive film, the third insulating film is deposited. A bit wire contact hole forming step of patterning the insulating film and the third conductive film to form a capacitor facing electrode and a bit wire contact hole opened on the second through hole, and a bit wire contact hole are formed. After depositing the fourth insulating film on the third insulating film, the fourth insulating film is anisotropically etched.A second sidewall insulating film is formed on the inner wall of the bit wire contact hole, and at the same time, a second sidewall insulating film forming step of removing the second insulating film at the bottom of the bit wire contact hole and a capacitor facing each other. A third through hole opened in a third insulating film on the electrode and a first interlayer insulating film on the source diffusion layer, drain diffusion layer, or second gate electrode of the peripheral circuit transistor. A second through-hole forming step of forming a fourth through hole, a bit wire connected to a first contact conductive film exposed in the bit wire contact hole, and a capacitor via a third through hole. A method for manufacturing a semiconductor storage device by a wiring layer forming step of forming a first wiring layer connected to a counter electrode and a second wiring layer connected to a peripheral circuit transistor via a fourth through hole. Therefore, the above-mentioned semiconductor storage device can be configured without sacrificing the operating speed of peripheral circuits.</p><p> Further, after the second sidewall insulating film forming step, a bit wire forming step of forming a bit wire connected to the contact conductive film exposed in the bit wire contact hole and a bit wire forming step on the semiconductor substrate on which the bit wire is formed are formed. In the second through-hole forming step, the second interlayer insulating film and the third insulating film reach the capacitor counter electrode. A fourth through that forms a third through hole and reaches the source diffusion layer, drain diffusion layer, or second gate electrode of the peripheral circuit transistor on the second interlayer insulating film and the first interlayer insulating film. In the process of forming holes and forming a wiring layer, a first wiring layer connected to a capacitor counter electrode via a third through hole and a second wiring layer connected to a peripheral circuit transistor via a fourth through hole. By forming the wiring layer of 2, the above-mentioned semiconductor storage device can be configured without increasing the number of manufacturing steps and without sacrificing the operating speed of peripheral circuits.</p><p> Further, when the fifth through hole connecting the bit wire and the wiring layer is formed in the second through hole forming step, the contact hole connecting the bit wire and the wiring layer is formed in the bit wire contact hole forming step. If an etching protection pattern composed of a laminated film of a third conductive film and a third insulating film is formed on the first interlayer insulating film of the region forming the peripheral circuit region, a deep through hole formed in the peripheral circuit region is opened. At this time, it is possible to prevent the first interlayer insulating film directly under the bit wire from being etched, so that a short circuit between the bit wire and the semiconductor substrate can be prevented.</p><p> Further, after the first conductive film and the first insulating film are laminated and deposited on the semiconductor substrate, the first conductive film and the first insulating film are patterned to form a memory cell transistor. A first gate electrode made of a first conductive film whose upper surface is covered with a first insulating film is covered with a first insulating film in a region, and a second region forming a transistor for a peripheral circuit is covered with a first insulating film. A gate electrode forming step of forming a second gate electrode composed of a broken first conductive film, and an impurity introduced into a semiconductor substrate using the gate electrode as a mask, and a source diffusion layer and a drain of a memory cell transistor in the first region. A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of peripheral circuit transistors in a second region, and a first sidewall insulating film being formed on a side wall of a gate electrode. The sidewall insulating film forming step, the first through hole opened on the source diffusion layer of the memory cell transistor, and the second through hole opened on the drain diffusion layer of the memory cell transistor are formed. A first interlayer insulating film forming step of forming one interlayer insulating film, a second conductive film deposition step of depositing a second conductive film on a semiconductor substrate on which the first interlayer insulating film is formed, and a first The second conductive film on the first interlayer insulating film is removed so as to leave the second conductive film inside the first through hole and the second through hole, and the second conductive film is formed in the first through hole. A conductive film removing step of forming a first contact conductive film composed of a second conductive film formed in a second through hole and a transistor storage electrode made of the second conductive film formed therein, and a transistor storage electrode After depositing a second insulating film to be a transistor dielectric film, a third conductive film to be a transistor counter electrode, and a third insulating film on the first contact conductive film, the third insulating film is deposited. The insulating film and the third conductive film are patterned to form a capacitor counter electrode and a bit wire contact hole opened on the second through hole, and the source diffusion layer and drain diffusion layer of the peripheral circuit transistor are formed. Alternatively, a bit wire transistor that opens a third through hole that opens on the second gate electrode up to the second insulating film.After the transistor hole forming step and the photoresist covering the bit wire contact hole are selectively formed, the second insulating film in the third through hole and the first interlayer insulating film are etched to be used for peripheral circuits. Since the semiconductor storage device is manufactured by the second through-hole forming step of forming the source diffusion layer, the drain diffusion layer, or the third through hole reaching over the second gate electrode of the transistor, the through hole is formed in the peripheral circuit portion. It is not necessary to perform fine alignment when opening the opening, and the lithography process can be simplified.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, in the bit wire contact hole forming step, a capacitor storage electrode, a second insulating film to be a capacitor dielectric film, and a capacitor counter electrode are formed on the second conductive film. After continuously depositing the third conductive film, the third insulating film, and the mask film that functions as an etching stopper, the mask film, the third insulating film, and the third conductive film are patterned to face the capacitors. A third through hole that forms an electrode and a bit wire contact hole opened on a second through hole and opens on a source diffusion layer, a drain diffusion layer, or a second gate electrode of a peripheral circuit transistor. Is opened up to the second insulating film, and in the second through hole forming step, after selectively forming a capacitor covering the bit wire contact hole, the mask film and the capacitor are used as an etching mask to form a third through hole. The second insulating film inside and the first interlayer insulating film are etched to form a third through hole that reaches over the source diffusion layer, drain diffusion layer, or second gate electrode of the peripheral circuit transistor. This also simplifies the lithography process.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, a silicon film can be applied to the mask film.</p><p> Further, after the first conductive film and the first insulating film are laminated and deposited on the semiconductor substrate, the first conductive film and the first insulating film are patterned to form a memory cell transistor. A first gate electrode made of a first conductive film whose upper surface is covered with a first insulating film is covered with a first insulating film in a region, and a second region forming a transistor for a peripheral circuit is covered with a first insulating film. A gate electrode forming step of forming a second gate electrode composed of a broken first conductive film, and an impurity introduced into a semiconductor substrate using the gate electrode as a mask, and a source diffusion layer and a drain of a memory cell transistor in the first region. A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of peripheral circuit transistors in a second region, and a first sidewall insulating film being formed on a side wall of a gate electrode. The sidewall insulating film forming step, the first through hole opened on the source diffusion layer of the memory cell transistor, the second through hole opened on the drain diffusion layer of the memory cell transistor, and the peripheral circuit transistor. The first interlayer insulating film forming step of forming the first interlayer insulating film in which the source diffusion layer, the drain diffusion layer, or the third through hole opened on the second gate electrode is formed, and the first In the second conductive film deposition step of depositing the second conductive film on the semiconductor substrate on which the interlayer insulating film is formed, the first through hole, the second through hole, and the inside of the third through hole. The second conductive film on the first interlayer insulating film is removed so as to leave the second conductive film, and the transistor storage electrode composed of the second conductive film formed in the first through hole and the second conductive film are formed. A first contact conductive film composed of a second conductive film formed in the second through hole, and a second contact conductive film composed of a second conductive film formed in the third through hole. A second insulation to be a capacitor dielectric film on a semiconductor substrate on which a conductive film removing step for forming a transistor, a capacitor storage electrode, a first conductive film for contact, and a second conductive film for contact is formed. After depositing the film, the third conductive film to be the counter electrode of the capacitor, and the third insulating film, the third insulating film and the third insulating film are deposited.A bit wire contact hole forming step of patterning the conductive film of 3 to form a capacitor facing electrode and a bit wire contact hole opened on the second through hole, and a third insulation in which the bit wire contact hole is formed. After depositing the fourth insulating film on the film, the fourth insulating film is anisotropically etched to form the second sidewall insulating film on the inner wall of the bit wire contact hole, and at the same time, the bottom of the bit wire contact hole. In the second sidewall insulating film forming step of removing the second insulating film, the bit wire connected to the first contact conductive film exposed in the bit wire contact hole, and in the third through hole. A semiconductor storage device is manufactured by a wiring layer forming step of forming a wiring layer connected to the formed second contact conductive film, and a conductive film directly connected to a peripheral circuit transistor is formed by a capacitor storage electrode or a bit. Since the structure is similar to that of the contact conductive film of the wire contact portion, it is possible to form contacts of peripheral circuits without increasing the number of manufacturing steps.To.To.</p><p> Further, when the conductive film to be the capacitor counter electrode is deposited, if it is embedded in the through hole so that the surface of the conductive film becomes flat, it is possible to prevent an unexpected step from occurring in the bit wire contact portion, and the contact characteristics. The reliability of the can be improved.</p><p> Further, in the above method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a fifth insulating film is deposited and the fifth insulating film is anisotropically etched to form a second conductive film. A third sidewall insulating film forming step of forming a third sidewall insulating film on the inner walls of the first through hole and the second through hole formed by the above, and a third sidewall insulating film were formed. By removing the third sidewall insulating film after the conductive film removing step and the fourth conductive film deposition step of depositing the first through hole and the fourth conductive film embedding the second through hole. A columnar conductor forming step of forming a first columnar conductor made of a fourth conductive film in a first through hole and a second columnar conductor made of a fourth conductive film in a second through hole. In the conductive film removing step, the fourth conductive film, the second conductive film, and the first interlayer insulating film are removed until the third sidewall insulating film is exposed on the surface. A first contact having a capacitor storage electrode having a first columnar conductor formed apart from the inner wall of the through hole and a second columnar conductor formed apart from the inner wall of the second through hole. Since the conductive conductive film can be formed, the capacitance of the capacitor can be significantly increased and the wiring resistance between the drain diffusion layer and the bit wire can be reduced. Further, in the above-mentioned manufacturing method of the semiconductor storage device, since the inside of the through hole is embedded when the second conductive film is removed, it is possible to prevent the abrasive or the like from entering the through hole. This makes it possible to prevent a decrease in yield due to an abrasive or the like.</p><p> Further, in the above-mentioned manufacturing method of the semiconductor storage device, if the surface of the first interlayer insulating film is flattened by polishing after the first interlayer insulating film is deposited and before the formation of through holes, the global flatness on the interlayer insulating film is obtained. Since the property is improved, the focus depth when opening the through hole can be made shallow, and fine patterning can be performed.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, if the second conductive film on the first interlayer insulating film is removed by polishing the surface of the semiconductor substrate, a capacitor storage electrode having a matching through-hole shape can be obtained. A conductive film for contacts can be easily formed.</p><p> Further, if a first interlayer insulating film is formed by a laminated film obtained by laminating a plurality of insulating materials having different etching characteristics and a through hole is opened by etching the insulating material one by one, a through hole having a large aspect ratio is opened. It can be easily done when doing so.</p><p> Further, in the above method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a photoresist is applied on the second conductive film, and the first through hole, the second through hole, or the third through hole or the third through hole is applied. After the conductive film removing step, the photoresist coating step to be embedded in the through hole of the above is performed, and the photoresist is peeled off from the first through hole, the second through hole, or the photoresist embedded in the third through hole. In the conductive film removing step, the first interlayer insulating film is performed so that the second conductive film and the photoresist remain inside the first through hole, the second through hole, or the third through hole. If the second conductive film and the photoresist are removed, the polishing agent and the like do not enter the through holes when the second conductive film is removed by polishing, so that the decrease in yield due to this is prevented. be able to.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a sixth insulating film having etching characteristics different from that of the first interlayer insulating film is deposited, and the first through hole, the first through hole, the first The insulating film deposition step to be embedded in the second through hole or the third through hole was embedded in the first through hole, the second through hole, or the third through hole after the conductive film removing step. A sixth insulating film removing step of removing the sixth insulating film is performed, and in the conductive film removing step, a second conductive film and a second conductive film are formed inside the first through hole, the second through hole, or the third through hole. If the second conductive film and the sixth insulating film on the first interlayer insulating film are removed so as to leave the sixth insulating film, an abrasive or the like is used when the second conductive film is removed by polishing. Does not enter the through hole, so that it is possible to prevent a decrease in yield due to this.</p><p> Further, in the above-mentioned manufacturing method of the semiconductor storage device, if an insulating film having etching characteristics different from that of the sixth insulating film is provided on the surface of the first interlayer insulating film, it is embedded in the through hole after polishing. Only the insulating film can be selectively removed.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, after the second conductive film deposition step, a sixth insulating film having substantially the same etching characteristics as the first interlayer insulating film is deposited, and the first through hole, the first through hole, the first The insulating film deposition step to be embedded in the second through hole or the third through hole was embedded in the first through hole, the second through hole, or the third through hole after the conductive film removing step. An insulating film removing step of removing the sixth insulating film and the first interlayer insulating film is performed, and in the conductive film removing step, a second through hole, a second through hole, or a second through hole is formed inside the third through hole. If the second conductive film and the sixth insulating film on the first interlayer insulating film are removed so as to leave the conductive film and the sixth insulating film of the above, when the second conductive film is removed by polishing. Since the abrasive or the like does not enter the through hole, it is possible to prevent a decrease in yield due to this.</p><p> Further, in the above-mentioned manufacturing method of the semiconductor storage device, the first interlayer insulating film is an insulating film having etching characteristics different from those of the sixth insulating film and having substantially the same etching characteristics as the sixth insulating film. By applying the laminated film in which the above is deposited, the sixth insulating film and the insulating film having substantially the same etching characteristics as the sixth insulating film can be selectively removed in the insulating film removing step.</p><p> Further, after the first conductive film and the first insulating film are laminated and deposited on the semiconductor substrate, the first conductive film and the first insulating film are patterned to form a memory cell transistor. The first gate electrode made of the first conductive film whose upper surface is covered with the first insulating film is covered with the first insulating film in the second region where the peripheral circuit transistor is formed. A gate electrode forming step of forming a second gate electrode composed of the first conductive film, and an impurity introduced into the semiconductor substrate using the gate electrode as a mask, and the source diffusion layer and drain of the memory cell transistor in the first region. A diffusion layer forming step of forming a diffusion layer and forming a source diffusion layer and a drain diffusion layer of peripheral circuit transistors in a second region, and a first sidewall insulating film being formed on a side wall of a gate electrode. A first interlayer insulating film that flattens the surface of the first interlayer insulating film after the sidewall insulating film forming step and the first interlayer insulating film are deposited on the semiconductor substrate on which the first sidewall is formed. The forming step, the second insulating film forming step of forming a second insulating film having different etching characteristics from the first interlayer insulating film on the flattened first interlayer insulating film, and the first interlayer insulating film. The first through hole opened on the source diffusion layer, the second through hole opened on the drain diffusion layer, and the source diffusion layer of the peripheral circuit transistor by patterning the film and the second insulating film, A through hole forming step of forming a drain diffusion layer or a third through hole opened on the second gate electrode, and a second conductive film depositing a second conductive film on the semiconductor substrate in which the through hole is opened. In the conductive film deposition step, the surface of the second conductive film is polished until the second insulating film is exposed on the surface, and the first embedded conductor embedded in the first through hole and the second through An embedded conductor forming step of forming a second embedded conductor embedded in the hole and a third embedded conductor embedded in the third through hole, and an opening on the first embedded conductor. A fourth through hole, a fifth through hole opened on the second embedded conductor, and an opening on the third embedded conductor.A second interlayer insulating film forming step of forming a second interlayer insulating film in which a sixth through hole is formed, and a third conductive film on a semiconductor substrate on which the second interlayer insulating film is formed. A second interlayer insulating film so as to leave the second conductive film inside the third through hole, the fifth through hole, and the sixth through hole. The third conductive film on the top is removed, and it is composed of a capacitor storage electrode made of a third conductive film formed in the fourth through hole and a third conductive film formed in the fifth through hole. Conduction embedded in the bottom of the through hole by a conductive film removing step of forming a first contact conductive film and a second contact conductive film composed of a third conductive film formed in the sixth through hole. Since the body is provided, the contact characteristics at the bottom of the through hole can be ensured even when the integration of the elements progresses and the aspect ratio of the through hole increases.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, when the embedded conductor is formed, the surface of the semiconductor substrate is polished to remove the third conductive film on the surface of the second interlayer insulating film, thereby forming the interlayer insulating film. An embedded conductor can be formed at the same time as flattening.</p><p> Further, if the first insulating film and the first sidewall covering the gate electrode are used as an etching stopper when forming a through hole to be opened on the semiconductor substrate, a source diffusion layer and a drain are provided at the bottom of the through hole. The diffusion layer can be easily exposed by self-alignment.</p><p> Further, a gate electrode forming step of depositing and patterning a first conductive film on a semiconductor substrate to form a gate electrode composed of the first conductive film, and introducing impurities into the semiconductor substrate using the gate electrode as a mask are performed. A diffusion layer forming step of forming a source diffusion layer and a drain diffusion layer, and interlayer insulation in which a first through hole opened on the source diffusion layer and a second through hole opened on the drain diffusion layer are formed. An interlayer insulating film forming step of forming a film, and an opening forming step of forming an opening having a larger opening diameter than the first through hole and not reaching the semiconductor substrate in the interlayer insulating film so as to surround the first through hole. The second conductive film deposition step of depositing the second conductive film on the semiconductor substrate on which the interlayer insulating film is formed, and the interlayer so as to leave the second conductive film inside the second through hole and the opening. A first conductive film composed of a second conductive film formed in the opening and a second conductive film formed in the second through hole by removing the second conductive film on the insulating film. On the semiconductor substrate on which the conductive film removing step for forming the contact conductive film, the capacitor storage electrode, and the first contact conductive film are formed, an insulating film to be a capacitor dielectric film and a capacitor counter electrode If the semiconductor storage device is manufactured by the step of forming the semiconductor counter electrode by patterning the third conductive film and forming the capacitor counter electrode after depositing the third conductive film, the distance between the gate electrode and the through hole can be obtained. It is possible to prevent the bit wire and the word wire from being short-circuited due to the influence of dust or the like generated in the manufacturing process. Further, since the opening for forming the capacitor dielectric film is provided in addition to the through hole having a small opening diameter, the capacitor capacity is not reduced.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, after the interlayer insulating film forming step, a fourth conductive film deposition step of depositing a fourth conductive film and embedding a first through hole and a second through hole is performed. In the opening forming step, if the columnar conductor made of the fourth conductive film embedded in the first through hole is formed so as to remain in the opening in a protruding state, the opening is formed. It is possible to prevent the semiconductor substrate exposed in the first through hole from being damaged at that time. Further, since the capacitor storage electrode is formed so as to cover the columnar conductor, the capacitor capacity can be increased.</p><p> Further, in the above-mentioned manufacturing method of the semiconductor storage device, the first through hole and the second through hole can be formed at the same time in the interlayer insulating film forming step.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, in the interlayer insulating film forming step, the interlayer insulating film is formed of a laminated film composed of two or more insulating films having different etching characteristics, and in the opening forming step, an opening is formed. By opening to the interface between insulating films having different etching characteristics, the depth of the opening can be controlled with good reproducibility, so that the variation in capacitor capacity can be reduced.</p><p> Further, a gate electrode forming step of depositing and patterning the first conductive film on the semiconductor substrate to form a gate electrode composed of the first conductive film, and introducing impurities into the semiconductor substrate using the gate electrode as a mask are performed. A diffusion layer forming step for forming a source diffusion layer and a drain diffusion layer, and interlayer insulation in which a first through hole opened on the source diffusion layer and a second through hole opened on the drain diffusion layer are formed. The interlayer insulating film forming step of forming the film, the second conductive film deposition step of depositing the second conductive film on the semiconductor substrate on which the interlayer insulating film was formed, and the patterning of the second conductive film, the first A second conductive film patterning step of forming a bit wire connected to the drain diffusion layer through the through hole of the second through hole and an embedded conductor embedded in the second through hole, and an embedded conductor on the interlayer insulating film. Semiconductor memory by a capacitor forming step of forming a capacitor having a capacitor storage electrode connected to a source diffusion layer via a body, a capacitor dielectric film covering the capacitor storage electrode, and a capacitor facing electrode covering the capacitor dielectric film. If the device is manufactured, the capacitor storage electrode is placed in the source diffusion layer via the embedded conductor embedded at the same time as the bit wire formation in the second through hole formed at the same time as the first through hole for the bit wire contact. Can be connected to. Therefore, since the etching time for forming the through hole for the capacitor storage electrode contact can be reduced without adding a new process, the insulating film on the bit wire is etched during this etching, and the bit wire is etched. Can be prevented from being exposed.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, after the second conductive film deposition step, the first insulating film deposition step of depositing the first insulating film on the second conductive film is performed by the second conductive film. After the film patterning step, a sidewall insulating film forming step of forming a sidewall insulating film on the side wall of the bit wire is performed, and in the second conductive film patterning step, the first insulating film and the second conductive film have the same pattern. If the upper part and the side wall of the bit wire are covered with an insulating film by processing, the embedded conductor is exposed to the surface at the same time. Therefore, a through hole for the capacitor storage electrode contact is formed by using a masking process as in the conventional case. You don't have to. That is, the masking process can be reduced by one process.</p><p> Further, in the above-mentioned method for manufacturing a semiconductor storage device, after the second conductive film patterning step, a second insulating film forming step of forming a second insulating film having an opening formed on the embedded conductor is performed. In the capacitor forming step, if the capacitor storage electrodes are selectively formed on the side wall and the bottom of the opening, the height difference between the memory cell region and the peripheral circuit region becomes small, so that the wiring rules of the wiring layer formed on the upper layer are strict. Can be designed.</p><p> Further, an interlayer insulating film forming step of depositing an interlayer insulating film on a semiconductor substrate and an opening are formed in a region where a first through hole and a second through hole should be formed on the interlayer insulating film to form an interlayer insulating film. An etching stopper film forming step of forming an etching stopper film having different etching characteristics from the film, a sidewall forming step of forming a sidewall having different etching characteristics from the interlayer insulating film on the side wall portion of the etching stopper film, and an etching stopper. An interlayer insulating film forming step by etching a second interlayer insulating film using the film and the sidewall as a mask and forming a through hole opening step of forming a first through hole and an interlayer insulating film in which a second through hole is formed. By forming an interlayer insulating film having a first through hole and a second through hole, it is possible to open a through hole having an opening diameter equal to or less than the resolution limit of the exposure apparatus.</p><p> Further, in the interlayer insulating film forming step, if the interlayer insulating film is deposited on the semiconductor substrate and then the interlayer insulating film is etched using the photoresist patterned by the electron beam drawing method as a mask, the solution of a normal exposure apparatus can be obtained. A first through hole and a second through hole having an opening diameter equal to or less than the image limit can be opened.</p>

[First Embodiment] The semiconductor storage device according to the first embodiment of the present invention and the manufacturing method thereof will be described with reference to FIGS. 1 to 7.

FIG. 1 is a plan view showing the structure of the semiconductor storage device according to the present embodiment, FIG. 2 is a schematic view showing a cross section of the AA ́ portion of the semiconductor storage device of FIG. 1, and FIGS. 3 to 6 are semiconductors according to the present embodiment. A process sectional view for explaining a method of manufacturing a storage device, FIG. 7 is a schematic sectional view of a semiconductor storage device according to a modified example of the present embodiment.

First, the structure of the semiconductor storage device according to the present embodiment will be described with reference to FIGS. 1 and 2.

The silicon substrate 10 is formed with element regions 14 and 15 defined by the element separation film 12. The source diffusion layer 24 and the drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. In this way, a memory cell transistor including a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is configured.

The gate electrode 20 is arranged in a direction orthogonal to the element region 14, and constitutes a word line that also functions as a gate electrode of a memory cell transistor in a plurality of other memory cells.

On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed is formed. It is formed. The gate electrode 20 is formed with an insulating film 42 formed by self-alignment so as to surround the gate electrode 20, and the through holes 38 and 40 are formed by self-alignment with the insulating film 42.

A capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner surface and the upper surface of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor composed of a capacitor storage electrode 46, a capacitor dielectric 48, and a capacitor counter electrode 54 is configured.

A contact conductive film 44 made of polycrystalline silicon is formed on the inner wall of the through hole 38, and bits are arranged in a direction orthogonal to the word line via an interlayer insulating film 53 formed on the capacitor facing electrode 54. It is connected to line 62.

Further, a wiring layer 70 is formed on the upper part of the bit wire 62 via an interlayer insulating film 64, and a DRAM composed of one transistor and one capacitor is formed.

On the other hand, a source diffusion layer (not shown) and a drain diffusion layer 34 are independently formed in the element region 15 of the peripheral circuit region adjacent to the memory cell region. A gate electrode 22 is formed on the semiconductor substrate 10 between the source diffusion layer and the drain diffusion layer 34 via the gate oxide film 16. In this way, a peripheral circuit transistor including a gate electrode 22, a source diffusion layer, and a drain diffusion layer 34 is configured.

A through hole 60 is formed in the interlayer insulating film 36 on the drain diffusion layer 34, and is connected to the wiring layer 70 formed on the interlayer insulating film 64 via the wiring layer 68 embedded in the through hole 60. Has been done.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, an element separation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, a normal LOCOS method, and element regions 14 and 15 are defined. Next, a gate oxide film 16 having a film thickness of about 10 nm is formed in the device regions 14 and 15 by a thermal oxidation method (Fig. 3 (a)).

Subsequently, by the chemical vapor deposition (CVD) method, a polycrystalline silicon film containing a high concentration of phosphorus (P) having a film thickness of about 150 nm and a silicon nitride film having a film thickness of about 200 nm are continuously formed. After the film is formed, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using ordinary lithography techniques and etching techniques. In this way, the gate electrodes 20 and 22 whose upper surface is covered with the silicon nitride film 18 are formed.

After that, using the silicon nitride film 18 and the gate electrodes 20 and 22 as masks, for example, P ions have an acceleration energy of 40 keV and an injection amount of 2 × 10.¹³cm^-2Ion implantation is performed under the above conditions to form the source diffusion layer 24 of the memory cell transistor, the drain diffusion layer 26, and the low concentration diffusion layer 28 of the peripheral circuit transistor. The low-concentration diffusion layer 28 has an LDD (Lightly Doped Drain) structure n.^-It becomes a layer (Fig. 3 (b)).

Next, after forming a silicon nitride film with a film thickness of about 100 nm by the CVD method, CHF₃/ H₂Anisotropic etching using a gas is performed to form a sidewalled nitride film 30 made of a silicon nitride film on the side walls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22 by self-matching. As a result, the side walls and the upper surface of the gate electrodes 20 and 22 are covered with the silicon nitride film 18 and the sidewall nitride film 30. In the following, for convenience of explanation, the silicon nitride film 18 and the sidewall nitride film 30 that cover the gate electrodes 20 and 22 are collectively referred to as an insulating film 42.

Then, using ordinary lithography technology, for example, arsenic (As) ions are injected into the N-type transistor region of the peripheral circuit with an acceleration energy of 40 keV and an injection amount of 4 × 10.¹⁵cm^-2Ion implantation is selectively performed under the above conditions to form the source diffusion layer and drain diffusion layer 34 of the N-type transistor of the peripheral circuit. As a result, a transistor for a peripheral circuit having an LDD structure is formed (Fig. 3 (c)).

Then, about 2 μm of silicon oxide film is deposited by the CVD method, and the surface is polished and flattened by the chemical mechanical polishing (CMP) method. Here, the amount of polishing by the CMP method is sufficient if the step between the gate electrodes 20 and 22 and the element separation membrane 12 can be removed, and is set to 500 nm in this embodiment.

The surface may be flattened by depositing a laminated film of silicon oxide film and BPSG film instead of the silicon oxide film and reflowing the BPSG film, but in consideration of global flatness, flattening by the CMP method is possible. desirable.

Then, after patterning the photoresist by a normal lithography process, C₂F₆Etching the silicon oxide film with an etching gas such as. After that, the photoresist was removed, and an interlayer insulating film 36 was formed in which a through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor and a through hole 40 opened on the source diffusion layer 24 of the memory cell transistor were formed. (Fig. 3 (d)).

At the time of this etching, the etching selectivity between the silicon oxide film and the silicon nitride film can be sufficiently ensured, and the etching of the interlayer insulating film 36 can be stopped by the insulating film 42.

The drain diffusion layer 26 and the source diffusion layer 24 are exposed on the bottom surfaces of the through holes 38 and 40 formed in this manner, respectively. Since it is formed by self-alignment with respect to the insulating film 42, it is not necessary to consider the alignment margin with respect to the gate electrode 20 when patterning the through holes 38 and 40. Therefore, the memory cell area can be reduced by the matching margin.

Further, the depth of the through hole 40 is an important parameter for determining the cell capacity, but in the present embodiment, the depth of the through hole 40 is about 1.5 μm, so that, for example, the size of the opening of the through hole 40 is large. Assuming that the value is 0.3 × 0.6 μm, the sum of the bottom area and the side wall area of the through hole 40 is [0.3 × 0.6 + 1.5 × (0.3 + 0.6) × 2] μm.²That is, about 2.88 μm²Can be secured. Therefore, if the film thickness of the capacitor dielectric is 4.5 nm in terms of oxide film, a sufficient capacitor having a capacity of about 22 fF can be formed.

Subsequently, a polycrystalline silicon film containing a high concentration of P is formed with a film thickness of about 50 nm by the CVD method, and then the polycrystalline silicon film on the interlayer insulating film 36 is completely removed by the CMP method. As a result, the contact conductive film 44 is formed in the through hole 38, and the capacitor storage electrode 46 is formed in the through hole 40 by self-alignment (FIG. 4 (a)).

Immediately after the interlayer insulating film 36 is deposited, the contact conductive film 44 and the capacitor storage electrode 46 may be self-aligned and flattened at the same time without being flattened by the CMP method. In this way, it is possible to reduce the polishing process by the CMP method by one process.

Further, the capacitor storage electrode 46 and the contact conductive film 44 may be formed of a polycrystalline silicon film having surface irregularities (for example, H. Watanabe, Ext. Abstract of 22nd SSDM, p869 (1990)). In this way, the surface area of the capacitor storage electrode 46 is increased to about twice that when it is formed by a normal method, so even if the depth of the through hole 40 is reduced to about half, about 0.8 μm. , The same capacitor capacity can be secured.

Then, after forming a silicon nitride film with a film thickness of about 5 nm by the CVD method, the surface of the silicon nitride film is oxidized in an 800 ° C wet atmosphere, and a capacitor dielectric film with a film thickness of about 4.5 nm in terms of oxide film is oxidized. Form 48.

Next, a polycrystalline silicon film 50 containing a high concentration of P having a film thickness of about 150 nm and a BPSG film 52 having a film thickness of about 200 nm are continuously formed by a CVD method, and then a BPSG film is formed by a reflow or CMP method. Flatten the surface of 52. At this time, the inside of the through hole 38 is completely embedded by the polycrystalline silicon film 50 (Fig. 4 (b)).

Subsequently, the BPSG film 52 and the polycrystalline silicon film 50 are simultaneously patterned by a normal lithography process and an etching process to form a capacitor counter electrode 54.

Then, after depositing a silicon oxide film with a thickness of about 100 nm by the CVD method, the entire surface is anisotropically etched to form a sidewall oxide film 56 on the side wall of the capacitor counter electrode 46, and at the same time, the capacitor dielectric on the through hole 38. Remove body membrane 48.

As a result, the capacitor counter electrode 54 is covered with the interlayer insulating film 53 composed of the sidewall oxide film 56 and the BPSG film, so that the opening formed on the through hole 38 can be used as the bit wire contact hole 58. That is, at the same time as forming the sidewall oxide film 56, the bit wire contact hole 58 can be formed by self-alignment (Fig. 5 (a)). Next, the contact hole 59 of the capacitor counter electrode 54 and the through hole 60 of the peripheral circuit transistor or the like are opened by a normal lithography process and etching process (FIG. 5 (b)).

Subsequently, a titanium (Ti) film having a film thickness of about 50 nm, a TiN film having a film thickness of about 50 nm, and a tungsten (W) film having a film thickness of about 200 nm are continuously formed by a sputtering method using a collimator. After that, a laminated film composed of a W film / TiN film / Ti film is patterned by a normal lithography process and an etching process to form a bit wire 62 and a wiring layer 68.

Next, an interlayer insulating film 64 made of a silicon oxide film having a film thickness of about 1 μm is deposited by the CVD method, the surface is flattened by the CMP method or the like as necessary, and then the via hole 66 is opened.

Subsequently, the W film is deposited by the CVD method and then patterned to form the wiring layer 70. An aluminum (Al) film deposited by a sputtering method may be used for the wiring layer 70.

In this way, a DRAM consisting of one transistor and one capacitor can be formed (Fig. 6).

As described above, according to the present embodiment, the lithography process that requires precise pattern formation includes element separation region demarcation, gate electrodes, through-holes for capacitor storage electrodes, through-hole openings for bit line contacts, counter electrodes, and peripherals. There are a total of eight processes: through-hole openings in the circuit, bit wires, via holes, and wiring layers. Therefore, as compared with the conventional example shown in FIG. 60, the lithography process can be reduced by one step.

On the other hand, when compared with the conventional example shown in FIG. 59, the number of lithography steps is the same, but in the present embodiment, the through holes for the capacitor storage electrode and the through holes for the bit wire contact are self-aligned with respect to the gate electrode. Since it is formed, the alignment margin can be reduced.

Further, since the through-hole for the bit wire contact and the through hole for the capacitor storage electrode are formed by self-alignment on the insulating film formed by self-alignment around the gate electrode, the through hole for the bit wire contact and the capacitor storage electrode It is not necessary to have a matching margin when forming the through hole, and the memory cell area can be reduced accordingly.

Further, although the capacitor storage electrode and the contact conductive film of the bit wire are formed at the same time, the wiring layer embedded in the through hole of the peripheral circuit and the contact conductive film are formed separately, so that the through hole of the peripheral circuit is completely formed. The capacitance of the capacitor storage electrode is not sacrificed for embedding.

In the peripheral circuit section of the above embodiment, the wiring layer 70 embedded in the via hole 66 is formed via the wiring layer 68 embedded in the through hole 60, so that the through hole 60 of the peripheral circuit is formed. Although a separate lithography process was required, this lithography process can be reduced by adopting the structure shown in FIG. 7.

In this case, the contact hole 59 for the capacitor counter electrode 54 and the through hole 60 for the peripheral circuit are opened after forming the interlayer insulating film 64, and the wiring layer 70 is the source of the capacitor counter electrode 54 and the transistor for the peripheral circuit. It may be configured to be in direct contact with the drain diffusion layer 34. [Second Embodiment] Next, the semiconductor storage device according to the second embodiment of the present invention and the manufacturing method thereof will be described with reference to FIGS. 8 to 14. The same components as those of the method for manufacturing the semiconductor storage device of the first embodiment shown in FIGS. 3 to 6 are designated by the same reference numerals, and the description thereof will be omitted or simplified.

8 is a plan view showing the structure of the semiconductor storage device according to the present embodiment, FIG. 9 is a schematic view showing a cross section of the AA ́ portion of the semiconductor storage device of FIG. 8, and FIGS. 10 to 13 are the semiconductor storage devices according to the present embodiment. FIG. 14 is a process sectional view for explaining the manufacturing method of the above, and FIG. 14 is a process sectional view for explaining the manufacturing method of the semiconductor storage device according to the modified example of the present embodiment.

In the semiconductor storage device according to the modified example of the first embodiment shown in FIG. 7, the process is simplified by embedding the through holes 60 of the peripheral circuit in the wiring layer 70. However, in this case, since the depth of the through hole 60 may reach about 3 μm, it may be difficult to completely embed the through hole.

The present embodiment provides a structure of a semiconductor storage device and a method for manufacturing the same, which can simplify the manufacturing process in consideration of this point.

First, the structure of the semiconductor storage device according to the present embodiment will be described.

The silicon substrate 10 is formed with element regions 14 and 15 defined by the element separation film 12. The source diffusion layer 24 and the drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. In this way, a memory cell transistor including a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is configured.

On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed is formed. It is formed. The gate electrode 20 is formed with an insulating film 42 formed by self-alignment so as to surround the gate electrode 20, and the through holes 38 and the through holes 40 are formed by self-alignment on the insulating film 42. There is.

A capacitor storage electrode 46 made of polycrystalline silicon is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner surface and the upper surface of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor composed of a capacitor storage electrode 46, a capacitor dielectric 48, and a capacitor counter electrode 54 is configured.

A contact conductive film 44 made of polycrystalline silicon is formed on the inner wall of the through hole 38, and bits are arranged in a direction orthogonal to the word line via an interlayer insulating film 53 formed on the capacitor facing electrode 54. It is connected to line 62.

Further, a wiring layer 70 is formed on the upper part of the bit wire 62 via an interlayer insulating film 64, and a DRAM composed of one transistor and one capacitor is formed.

On the other hand, a source diffusion layer (not shown) and a drain diffusion layer 34 are independently formed in the element region 15 of the peripheral circuit region adjacent to the memory cell region. A gate electrode 22 is formed on the semiconductor substrate 10 between the source diffusion layer and the drain diffusion layer 34 via the gate oxide film 16. In this way, a peripheral circuit transistor including a gate electrode 22, a source diffusion layer 32, and a drain diffusion layer 34 is configured.

A through hole 60 is formed in the interlayer insulating film 36 on the drain diffusion layer 34, and is connected to the wiring layer 70 formed on the interlayer insulating film 64 via the wiring layer 68 embedded in the through hole 60. Has been done.

The difference between the semiconductor storage device according to the present embodiment and the semiconductor storage device according to the first embodiment is that the polycrystalline silicon film 50 constituting the capacitor counter electrode 54 and the interlayer insulating film 53 in the upper layer thereof are located in the peripheral circuit region. It is in the process of extending to.

The advantage of configuring the capacitor counter electrode 54 and the interlayer insulating film 53 in this way is mainly that the manufacturing process can be simplified. Hereinafter, a method for manufacturing a semiconductor storage device according to the present embodiment will be shown and described in detail.

First, an element separation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, a normal LOCOS method, and element regions 14 and 15 are defined. Next, a gate oxide film 16 having a film thickness of about 10 nm is formed in the device regions 14 and 15 by a thermal oxidation method (FIG. 10 (a)).

Subsequently, by the CVD method, a polycrystalline silicon film containing a high concentration of P is continuously formed with a thickness of about 150 nm and a silicon nitride film with a thickness of about 200 nm, and then ordinary lithography and etching techniques are used. The silicon nitride film and the polycrystalline silicon film are patterned at the same time. In this way, the gate electrodes 20 and 22 whose upper surface is covered with the silicon nitride film 18 are formed.

After that, using the silicon nitride film 18 and the gate electrodes 20 and 22 as masks, for example, P ions have an acceleration energy of 40 keV and an injection amount of 2 × 10.¹³cm^-2Ion implantation is performed under the conditions of (Fig. 10 (b)) to form the source diffusion layer 24 of the memory cell transistor, the drain diffusion layer 26, and the low-concentration diffusion layer 28 of the peripheral circuit transistor (Fig. 10 (b)).

Next, after forming a silicon nitride film with a film thickness of about 100 nm by the CVD method, CHF₃/ H₂Anisotropic etching using a gas is performed to form a sidewalled nitride film 30 made of a silicon nitride film on the side walls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22 by self-matching. As a result, the side walls and the upper surface of the gate electrodes 20 and 22 are covered with the silicon nitride film 18 and the sidewall nitride film 30. Then, using ordinary lithography technology, for example, As ions are injected into the N-type transistor region of the peripheral circuit with an acceleration energy of 40 keV and an injection amount of 4 × 10.¹⁵cm^-2Ion implantation is selectively performed under the above conditions to form the source diffusion layer and drain diffusion layer 34 of the N-type transistor of the peripheral circuit. As a result, a transistor for a peripheral circuit having an LDD structure is formed (Fig. 10 (c)).

Then, a silicon oxide film of about 2 μm is deposited by the CVD method, and the surface is polished and flattened by the CMP method. Here, the amount of polishing by the CMP method is sufficient if the step between the gate electrodes 20 and 22 and the element separation membrane 12 can be removed, and is set to 500 nm in this embodiment.

Then, after patterning the photoresist by a normal lithography process, C₂F₆Etching the silicon oxide film with an etching gas such as. After that, the photoresist was removed, and an interlayer insulating film 36 was formed in which a through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor and a through hole 40 opened on the source diffusion layer 24 of the memory cell transistor were formed. (Fig. 10 (d)).

Subsequently, a polycrystalline silicon film containing a high concentration of P is formed with a film thickness of about 50 nm by the CVD method, and then the polycrystalline silicon film on the interlayer insulating film 36 is completely removed by the CMP method. As a result, the contact conductive film 44 is formed in the through hole 38, and the capacitor storage electrode 46 is formed in the through hole 40 by self-alignment (FIG. 11 (a)).

Then, after forming a silicon nitride film with a film thickness of about 5 nm by the CVD method, the surface of the silicon nitride film is oxidized in an 800 ° C wet atmosphere, and a capacitor dielectric film with a film thickness of about 4.5 nm in terms of oxide film is oxidized. Form 48.

Next, a polycrystalline silicon film 50 containing a high concentration of P having a film thickness of about 150 nm and a BPSG film 52 having a film thickness of about 200 nm are continuously formed by a CVD method, and then a BPSG film is formed by a reflow or CMP method. Flatten the surface of 52. At this time, the inside of the through hole 38 is completely embedded by the polycrystalline silicon film 50 (Fig. 11 (b)).

Subsequently, the photoresist 72 is patterned using a positive photoresist by a normal lithography process, and then the BPSG film 52 and the polycrystalline silicon film 50 are continuously etched to form the capacitor counter electrode 54. .. At this time, the polycrystalline silicon film 50 and the BPSG film 52 in the peripheral circuit region open only the region where the through hole 60 for the peripheral circuit is formed up to the capacitor dielectric film 48, and the other regions are not removed (FIG. 12 (a)). )).

Then, without removing the photoresist 72, resist patterning using a negative photoresist is performed to form a photoresist 74 that covers the memory cell region. In the patterning of the photoresist 74, since the memory cell area needs to be covered, fine alignment accuracy is not required, and the lithography process can be remarkably simplified.

The photoresist 74 was formed using the negative type photoresist in order to prevent inconveniences such as the underlying photoresist 72 being peeled off at the same time when the photoresist 74 was developed. Therefore, immediately after patterning the photoresist 72, UV curing or the like may be performed to cure the photoresist 72, and then patterning may be performed using a positive resist.

Subsequently, etching is performed using the photoresists 72 and 74 as masks to completely open the through holes 60 for peripheral circuits (FIG. 12 (b)).

After removing the photoresists 72 and 74, a silicon oxide film having a film thickness of about 100 nm is deposited by the CVD method, and the entire surface is anisotropically etched. As a result, the sidewall oxide film 56 is formed on the side wall of the capacitor counter electrode 46, and the sidewall oxide film 76 is formed on the inner wall of the through hole 60. At the same time, the capacitor dielectric film 48 on the through hole 38 is removed.

As a result, the capacitor counter electrode 54 is covered with the interlayer insulating film 53 composed of the sidewall oxide film 56 and the BPSG film, so that the opening formed on the through hole 38 can be used as the bit wire contact hole 58. That is, at the same time as forming the sidewall oxide film 56, the bit wire contact hole 58 can be formed by self-alignment (FIG. 13 (a)). Subsequently, a Ti film having a film thickness of about 50 nm is continuously formed by a sputtering method using a collimator, a TiN film having a film thickness of about 50 nm is formed by a CVD method, and a W film having a film thickness of about 200 nm is continuously formed. After that, a laminated film composed of a W film / TiN film / Ti film is patterned by a normal lithography process and an etching process to form a bit wire 62 and a wiring layer 68.

Next, an interlayer insulating film 64 made of a silicon oxide film having a film thickness of about 1 μm is deposited by the CVD method, the surface is flattened by the CMP method or the like as necessary, and then the via hole 66 is opened.

Subsequently, the W film is deposited by the CVD method and then patterned to form the wiring layer 70.

In this way, a DRAM consisting of one transistor and one capacitor can be formed (Fig. 13 (b)).

As described above, according to the present embodiment, when manufacturing a semiconductor storage device, the lithography process that requires precise pattern formation includes element separation region demarcation, a gate electrode, a through hole for a capacitor storage electrode, and a bit wire contact. There are a total of 7 processes including through-hole openings, counter electrodes, bit wires, via holes, and wiring layers. Further, the lithography process that can be simplified by this embodiment is a through-hole opening process of a peripheral circuit. Therefore, as compared with the conventional example shown in FIG. 60, the lithography process can be reduced by one step and simplified by one step.

On the other hand, when compared with the conventional example shown in FIG. 59, the alignment margin of the through hole for the capacitor storage electrode and the through hole for the bit wire contact with respect to the gate electrode can be reduced as in the first embodiment.

In the above embodiment, when the through holes in the peripheral circuit region are opened, the photoresist 72 is formed and opened to the capacitor dielectric film 48, and then the photoresist 74 is formed without removing the photoresist 72. Although this was done by completely opening the through hole 60, the through hole 60 may be opened by the manufacturing method shown below.

First, as shown in FIG. 11 (b), a BPSG film is deposited, and then a polycrystalline silicon film 78 having a film thickness of about 100 nm is deposited by a CVD method.

Next, after patterning the photoresist 72 by a normal lithography process, the polycrystalline silicon film 78, the BPSG film 52, and the polycrystalline silicon film 50 are continuously etched to form the capacitor counter electrode 54. At this time, the polycrystalline silicon film 50 and the BPSG film 52 in the peripheral circuit region are not removed, and only the region where the through hole 60 for the peripheral circuit is formed is opened to the capacitor dielectric film 48 (FIG. 14 (a)).

After removing the photoresist 72, the photoresist 74 is patterned again by a normal lithography process, and the memory cell area is covered with the photoresist 74.

Subsequently, the capacitor dielectric film 48 and the interlayer insulating film 36 are etched using the photoresist 74 as a mask to completely open the through holes 60. At this time, since the polycrystalline silicon film 78 is formed on the interlayer insulating film 53, the interlayer insulating film 53 is not etched when the through holes 60 are etched. Therefore, the patterning of the photoresist 74 does not require fine alignment accuracy, and the sography process can be simplified (FIG. 14 (b)).

Although the polycrystalline silicon film 78 remains even after the through hole is opened, there is no inconvenience if the patterning is performed at the same time as the bit wire 62 formed in the upper layer. [Third Embodiment] A semiconductor storage device according to a third embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 15 to 18. The semiconductor storage devices according to the first and second embodiments shown in FIGS. 1 to 14 and the same components as the manufacturing method thereof are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 15 is a schematic cross-sectional view of the semiconductor storage device according to the present embodiment, and FIGS. 16 to 18 are process cross-sectional views illustrating a method for manufacturing the semiconductor storage device according to the present embodiment.

In the present embodiment, by using the same structure for the bit line contact portion and the contact portion in the peripheral circuit region, the semiconductor storage device and the semiconductor storage device that can further simplify the manufacturing method of the semiconductor storage device according to the first embodiment and the second embodiment. The manufacturing method is provided.

First, the structure of the semiconductor storage device according to the present embodiment will be described.

The silicon substrate 10 is formed with element regions 14 and 15 defined by the element separation film 12. The source diffusion layer 24 and the drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. In this way, a memory cell transistor including a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is configured.

The gate electrode 20 constitutes a word line that also functions as a gate electrode of a memory cell transistor in a plurality of other memory cells.

On the semiconductor substrate 10 on which the memory cell transistor is formed, an interlayer insulating film 36 in which a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24 are formed is formed. It is formed. The gate electrode 20 is formed with an insulating film 42 formed in a self-aligned manner so as to surround the gate electrode 20, and the through holes 38 and the through holes 40 are formed in the insulating film 42 in a self-aligned manner. There is.

A capacitor storage electrode 46 made of a TiN film is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner surface and the upper surface of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor composed of a capacitor storage electrode 46, a capacitor dielectric 48, and a capacitor counter electrode 54 is configured.

A contact conductive film 44 made of a TiN film is formed on the inner wall of the through hole 38, and bit wires arranged in a direction orthogonal to the word line via an interlayer insulating film 53 formed on the capacitor facing electrode 54. It is connected to 62.

Further, a wiring layer 70 is formed on the upper part of the bit wire 62 via an interlayer insulating film 64, and a DRAM composed of one transistor and one capacitor is formed.

On the other hand, a source diffusion layer (not shown) and a drain diffusion layer 34 are independently formed in the element region 15 of the peripheral circuit region adjacent to the memory cell region. A gate electrode 22 is formed on the semiconductor substrate 10 between the source diffusion layer 32 and the drain diffusion layer 34 via the gate oxide film 16. In this way, a peripheral circuit transistor including a gate electrode 22, a source diffusion layer 32, and a drain diffusion layer 34 is configured.

Through holes 60 are formed in the interlayer insulating film 36 on the drain diffusion layer 34 and the gate electrode 22. Further, a conductive film 80 made of a TiN film is formed on the inner wall and the bottom surface of the through hole 60, and the drain diffusion layer 34 and the gate electrode 22 are connected to the wiring layer 68 via the conductive film 80. There is.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, an element separation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, a normal LOCOS method, and element regions 14 and 15 are defined. Next, a gate oxide film 16 having a film thickness of about 10 nm is formed in the device regions 14 and 15 by a thermal oxidation method.

Subsequently, by the CVD method, a polycrystalline silicon film containing a high concentration of P is continuously formed with a thickness of about 150 nm and a silicon nitride film with a thickness of about 200 nm, and then ordinary lithography and etching techniques are used. To remove a part of the silicon nitride film in the peripheral circuit region. This region becomes the gate contact portion 82 when the wiring is later pulled out from the gate electrode 22.

Next, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using ordinary lithography techniques and etching techniques to form the gate electrode 20 of the memory cell transistor and the gate electrode 22 of the peripheral circuit.

The upper surfaces of the gate electrodes 20 and 22 formed in this manner are covered with the silicon nitride film 18 except for the gate contact portion 82 of the peripheral circuit portion.

After that, using the silicon nitride film 18 and the gate electrodes 20 and 22 as masks, for example, P ions have an acceleration energy of 40 keV and an injection amount of 2 × 10.¹³cm^-2Ion implantation is performed under the above conditions to form the source diffusion layer 24 of the memory cell transistor, the drain diffusion layer 26, and the low concentration diffusion layer 28 of the peripheral circuit transistor. The low-concentration diffusion layer 28 has an LDD structure n.^-It becomes a layer (Fig. 16 (a)).

Next, after forming a silicon nitride film with a film thickness of about 100 nm by the CVD method, CHF₃/ H₂Anisotropic etching using a gas is performed to form a sidewalled nitride film 30 made of a silicon nitride film on the side walls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22 by self-matching. As a result, the side walls and the upper surface of the gate electrodes 20 and 22 are covered with the silicon nitride film 18 and the sidewall nitride film 30. In the following, for convenience of explanation, the silicon nitride film 18 and the sidewall nitride film 30 that cover the gate electrodes 20 and 22 are collectively referred to as an insulating film 42.

Then, using ordinary lithography technology, for example, As ions are injected into the N-type transistor region of the peripheral circuit with an acceleration energy of 40 keV and an injection amount of 4 × 10.¹⁵cm^-2Ion implantation is selectively performed under the above conditions to form the source diffusion layer 32 and the drain diffusion layer 34 of the N-type transistor of the peripheral circuit. As a result, a transistor for a peripheral circuit having an LDD structure is formed (Fig. 16 (b)).

Then, about 2.5 μm of silicon oxide film is deposited by the CVD method, and the surface is polished and flattened by about 0.5 μm by the CMP method.

Instead of the 2.5 μm silicon oxide film, for example, a laminated film of 50 nm silicon oxide film and 2 μm BPSG film is deposited, and the surface is flattened by reflowing the BPSG film in an atmosphere of 850 ° C nitrogen for about 15 minutes. It may be changed.

Then, after patterning the photoresist by a normal lithography process, C₂F₆Etching the silicon oxide film with an etching gas such as.

After that, the photoresist is removed, and the through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor, the through hole 40 opened on the source diffusion layer 24 of the memory cell transistor, and the through hole 60 in the peripheral circuit region are formed. The formed interlayer insulating film 36 is formed (FIG. 16 (c)).

The drain diffusion layer 26 and the source diffusion layer 24 are exposed on the bottom surfaces of the through holes 38 and the through holes 40 formed in this manner, respectively. Since it is formed by self-alignment with respect to the insulating film 42, it is not necessary to consider the alignment margin with respect to the gate electrode 20 when patterning the through holes 38 and 40. Therefore, the memory cell area can be reduced by the matching margin.

On the other hand, the gate electrode 22 of the peripheral circuit transistor and the drain diffusion layer 34 are exposed on the bottom surface of the through hole 60. In the gate contact portion 82 that opens the through hole 60, the insulating film 42 on the gate electrode 22 is removed in advance. Therefore, by opening the through hole 60 at the same time as the through hole 38 and the through hole 40, the through hole 60 is opened. The gate electrode 22 can be exposed in the hole 60.

Subsequently, a Ti film having a film thickness of about 10 nm and a TiN film having a film thickness of about 20 nm are continuously formed by the CVD method, and then the TiN film and the Ti film on the interlayer insulating film 36 are completely removed by the CMP method. As a result, the contact conductive film 44 is formed in the through hole 38, the capacitor storage electrode 46 is formed in the through hole 40, and the conductive film 80 is formed in the through hole 60 of the peripheral circuit portion by self-matching (FIG. 17). (a)).

When forming the conductive film 80, a Ti film may be deposited mainly on the bottom of the through hole by a collimated sputtering method having a large amount of sputtering components in the vertical direction, and then the TiN film may be grown by a CVD method.

Further, when forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80, a lithography technique is used instead of the CMP method to leave the photoresist in the through holes 38, through holes 40, and through holes 60. After that, the Ti film and the TiN film may be removed by etching using this photoresist as a mask.

The electrical resistance of the conductive film 80 embedded in the through hole 60 of the peripheral circuit portion is very important because it affects the operating speed of the peripheral circuit. However, since the sheet resistance of the conductive film 80 formed in this way is about 30 Ω / , the depth of the through hole 60 is about 2 μm, and the peripheral edge length of the through hole 60 is about 0.8 μm, the electrical resistance of the conductive film 80 is about 0.8 μm. Is a sufficiently low value of about 75Ω.

Next, a silicon nitride film having a film thickness of about 5 nm was formed at a low temperature of about 650 ° C by the CVD method, and then heat-treated in a wet atmosphere at 700 ° C. 4 atm for 10 minutes to oxidize the surface of the silicon nitride film and make a capacitor. The dielectric film 48 is formed.

By this heat treatment, the Ti film at the bottom of the through holes 38, through holes 40, and through holes 60 reacts with the underlying source / drain diffusion layers 24, 26, 32, 34 or the gate electrode 22 to silicidalize, and the contact resistance of these connections. Is reduced.

As described above, high-pressure oxidation at a low temperature was used for the heat treatment for forming the capacitor dielectric film 48. This is because when the TiN film and the silicon nitride film react with each other by high-temperature heat treatment, the withstand voltage of the capacitor dielectric film 48 may deteriorate, so high-pressure oxidation capable of lowering the heat treatment temperature is desirable.

Next, by the CVD method, a polycrystalline silicon film 50 containing a high concentration of P is continuously formed with a film thickness of about 150 nm, and a silicon oxide film 52 is continuously formed with a film thickness of about 200 nm. In this way, the inside of the through hole 38, the through hole 40, and the through hole 60 is embedded.

Subsequently, the silicon oxide film 52 and the polycrystalline silicon film 50 are simultaneously patterned by a normal lithography process and an etching process to form a capacitor counter electrode 54 (FIG. 17 (b)).

The silicon oxide film 52 and the polycrystalline silicon film 50 remain embedded in the through holes 38 and 60, but these films only contribute to flattening, and there is no adverse effect due to this.

Further, as the material of the capacitor counter electrode 54, a TiN film deposited by the CVD method may be used, but in the present embodiment, the dielectric film is damaged when the TiN film is grown using a chlorine-based reaction gas. Since there is a risk, the polycrystalline silicon film 50 was used.

After that, a silicon oxide film having a thickness of about 100 nm is deposited by the CVD method, and the entire surface is anisotropically etched to form a sidewall oxide film 56 on the side wall of the capacitor counter electrode 54, and at the same time, the capacitor dielectric on the through hole 38. Remove membrane 48.

As a result, the capacitor counter electrode 54 is covered with the sidewall oxide film 56 and the interlayer insulating film 53, so that the opening formed on the through hole 38 can be used as the bit wire contact hole 58. That is, at the same time as forming the sidewall oxide film 56, the bit wire contact hole 58 can be formed by self-alignment (FIG. 18 (a)). Subsequently, a titanium Ti film having a film thickness of about 50 nm is continuously formed by a sputtering method using a collimator, a TiN film having a film thickness of about 50 nm is formed by a CVD method, and a W film having a film thickness of about 200 nm is continuously formed. After that, a laminated film composed of a W film / TiN film / Ti film is patterned by a normal lithography process and an etching process to form a bit wire 62 and a wiring layer 68.

Next, an interlayer insulating film 64 made of a silicon oxide film having a film thickness of about 1 μm is deposited by the CVD method, the surface is flattened by the CMP method or the like as necessary, and then the via hole 66 is opened.

Subsequently, the W film is deposited by the CVD method and then patterned to form the wiring layer 70.

In this way, a DRAM consisting of one transistor and one capacitor can be formed (Fig. 18 (b)).

As described above, according to the present embodiment, by using a low resistance material for the conductive film that embeds the through hole connecting the bit wire and the memory cell transistor, the through hole of the peripheral circuit and the through hole of the memory cell region can be formed. Since the structure can be made the same, the number of lithography steps can be reduced by one.

Therefore, the lithography steps that require precise pattern formation are a total of seven steps of element separation region demarcation, gate electrode, through hole opening, counter electrode, bit wire, via hole, and wiring layer. Therefore, as compared with the conventional example shown in FIG. 60, the lithography process can be reduced by two steps.

On the other hand, when compared with the conventional example shown in FIG. 59, the number of lithography steps can be reduced by one step, and in the present embodiment, the through holes for the capacitor storage electrode and the through holes for the bit wire contact are self-aligned with respect to the gate electrode. Since it was formed with, the alignment margin can be reduced. Further, since the thickness of the capacitor storage electrode can be reduced, it is possible to prevent a decrease in the capacitor capacity.

In the above embodiment, the semiconductor storage device is configured by using a TiN film as the capacitor storage electrode, a SiN film as the capacitor dielectric film, and a polycrystalline silicon film as the capacitor counter electrode. For example, K. Koyama (Technical Digest). As disclosed by IEDM 1992, p.823 (1992)), H. Shinriki (IEEE Trans., Electron Devices, Vol.38 No.3, p.455 (1991)), Ta₂O₅Membrane and (Ba_xSr_1-x) TiO₃Even if a high-ferroelectric film such as a film is used as the capacitor dielectric film and a capacitor is constructed using a capacitor storage electrode and a capacitor counter electrode with W or Pt, which are electrode materials that can be used for these dielectric films. Good.

If the capacitor is constructed of a high-dielectric film in this way, a sufficient capacitor capacity can be secured even if the surface area of the capacitor electrode is reduced. Therefore, the one having the highest dielectric constant among the above-mentioned dielectric materials is used. If so, the depth of the through hole can be reduced to about 0.2 μm, which is extremely effective.

Further, in the above embodiment, a laminated film of a Ti film and a TiN film is used as the capacitor storage electrode and the capacitor counter electrode, but other materials may be used as long as the conductive film can sufficiently reduce the contact resistance. [Fourth Embodiment] A semiconductor storage device according to a fourth embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 19 to 21. The semiconductor storage device of the third embodiment shown in FIGS. 15 to 18 and the same components as the manufacturing method thereof are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 19 is a schematic cross-sectional view of the semiconductor storage device according to the present embodiment, and FIGS. 20 and 21 are process cross-sectional views illustrating a method for manufacturing the semiconductor storage device according to the present embodiment.

In the first to third embodiments, when the through holes 38, the through holes 40, and the like are opened, the interlayer insulating film 36 having a film thickness of about 2 μm is formed by one etching step. In the actual manufacturing process, overetching is usually performed in consideration of variations in film thickness during film formation, etc., in accordance with the film thickness of the interlayer insulating film. Therefore, considerable overetching is required to etch the interlayer insulating film 36 having a film thickness of about 2 μm.

On the other hand, when opening through holes 38, through holes 40, etc., a self-aligning contact is formed by using the insulating film 42 as an etching stopper. However, the silicon nitride film formed in the stepped portion such as the insulating film 42 has lower etching selectivity with respect to the silicon oxide film than the silicon nitride film formed in the flat portion. In particular, the etching of the insulating film 42 tends to proceed at the edges of the gate electrodes 20 and 22.

Therefore, when a through hole 38, a through hole 40, or the like is opened in a thick interlayer insulating film, the insulating film 42 is etched by excessive overetching to expose the gate electrodes 20 and 22, and the gate electrodes 20 and 22 are embedded in the through hole 38, for example. There is a risk that the contact conductive film and the gate electrode 20 will be short-circuited.

As described above, the formation of the through holes 38 and the through holes 40 is one of the most difficult manufacturing processes in the present invention.

In this embodiment, in consideration of the above problems, a semiconductor storage device capable of easily forming through holes 38 and through holes 40 and a method for manufacturing the same will be described.

The semiconductor storage device according to the present embodiment is characterized in that the interlayer insulating film formed between the bit wire 62 and the silicon substrate 10 is an insulating film having a three-layer structure.

That is, a silicon oxide film 84, a silicon nitride film 86, and a silicon oxide film 88 are sequentially laminated on a semiconductor substrate 10 on which a memory cell transistor composed of a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is formed. An interlayer insulating film 36 is formed.

The interlayer insulating film 36 is formed with a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24.

A capacitor storage electrode 46 made of a TiN film is formed on the inner wall of the through hole 40 and the source diffusion layer 24, and is connected to the source diffusion layer 24 at the bottom of the through hole 40. A capacitor dielectric film 48 is formed on the inner surface and the upper surface of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor composed of a capacitor storage electrode 46, a capacitor dielectric 48, and a capacitor counter electrode 54 is configured.

A contact conductive film 44 made of a TiN film is formed on the inner wall of the through hole 38, and bit wires arranged in a direction orthogonal to the word line via an interlayer insulating film 53 formed on the capacitor facing electrode 54. It is connected to 62.

Further, a wiring layer 70 is formed on the upper part of the bit wire 62 via an interlayer insulating film 64, and a DRAM composed of one transistor and one capacitor is formed.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, an element separation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, a normal LOCOS method, and an element region 14 is defined. Next, a gate oxide film 16 having a film thickness of about 10 nm is formed in the device region 14 by a thermal oxidation method.

Subsequently, by the CVD method, a polycrystalline silicon film containing a high concentration of P having a film thickness of about 150 nm and a silicon nitride film having a film thickness of about 200 nm are continuously formed, and then ordinary lithography and etching techniques are applied. It is used to remove a part of the silicon nitride film in the peripheral circuit region. This region becomes the gate contact portion 82 when the wiring is later pulled out from the gate electrode 22.

Next, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using ordinary lithography techniques and etching techniques to form the gate electrode 20 of the memory cell transistor and the gate electrode 22 of the peripheral circuit.

After that, using the silicon nitride film 18 and the gate electrodes 20 and 22 as masks, for example, P ions have an acceleration energy of 40 keV and an injection amount of 2 × 10.¹³cm^-2Ion implantation is performed under the conditions of (Fig. 20 (a)) to form the source diffusion layer 24 of the memory cell transistor, the drain diffusion layer 26, and the low-concentration diffusion layer 28 of the peripheral circuit transistor (Fig. 20 (a)).

Next, after forming a silicon nitride film with a film thickness of about 100 nm by the CVD method, CHF₃/ H₂Anisotropic etching using a gas is performed to form a sidewalled nitride film 30 made of a silicon nitride film on the side walls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22 by self-matching.

Then, using ordinary lithography technology, for example, As ions are injected into the N-type transistor region of the peripheral circuit with an acceleration energy of 40 keV and an injection amount of 4 × 10.¹⁵cm^-2Ion implantation is selectively performed under the above conditions to form the source diffusion layer 32 and drain diffusion layer 34 of the N-type transistor of the peripheral circuit (Fig. 20 (b)).

Then, about 1 μm of the silicon oxide film 84 is deposited by the CVD method, and the surface is polished and flattened by about 0.7 μm by the CMP method. Next, the silicon nitride film 86 is continuously grown at 20 nm and the silicon oxide film 88 is continuously grown at 1.8 μm by the CVD method.

Then, after patterning the photoresist 90 by a normal lithography process, C₂F₆Etching gas such as, etc. is used to etch the silicon oxide film 88. Here, since the silicon nitride film 86 was able to secure a selectivity of about 100 with respect to the silicon oxide film by depositing on the flattened silicon oxide film 84, it is sufficient as an etching stopper when etching the silicon oxide film 88. It can be used (Fig. 20 (c)).

Subsequently, using the same photoresist 90 as a mask, CHF₃/ CF₄Etching the silicon nitride film 86 using / Ar as the etching gas, and then C₂F₆Is used as the etching gas to etch the silicon oxide film 84.

After that, the photoresist is removed, and the through hole 38 opened on the drain diffusion layer 26 of the memory cell transistor, the through hole 40 opened on the source diffusion layer 24 of the memory cell transistor, and the through hole 60 in the peripheral circuit region are formed. The formed interlayer insulating film 36 is formed (FIG. 21 (a)).

After that, for example, a capacitor, a bit wire, a wiring layer, etc. are formed by the manufacturing process shown in FIGS. 17 (a) and later of the third embodiment, and a DRAM composed of one transistor and one capacitor shown in FIG. 21 (b) is configured. To do.

As described above, according to the present embodiment, since the etching of the very deep opening is divided into two stages, each etching can be performed relatively easily. In particular, since the film thickness of the silicon oxide film 84 to be etched in the etching process of the silicon oxide film 84 that diffuses the source diffusion layers 24 and 32 and the drain diffusion layers 26 and 34 can be remarkably reduced, the side surfaces of the gate electrodes 20 and 22 are insulated. It is possible to suppress the film loss of the element separation film 12 when the element separation film 12 is exposed in the opening due to the misalignment of the film 42 and the lithography process. [Fifth Embodiment] A semiconductor storage device according to a fifth embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 22 to 24. The semiconductor storage device of the third embodiment shown in FIGS. 15 to 18 and the same components as the manufacturing method thereof are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 22 is a schematic cross-sectional view of the semiconductor storage device according to the present embodiment, and FIGS. 23 and 24 are process cross-sectional views illustrating a method for manufacturing the semiconductor storage device according to the present embodiment.

In the third embodiment, after opening through holes 38, through holes 40, and through holes 60 in the interlayer insulating film 36, a Ti film and a TiN film are deposited by a CVD method or a collimated sputtering method, and the capacitor storage electrode 54 Etc. were formed.

Here, since the deposited Ti film reacts with the underlying silicon substrate 10 to form a titanium silicide film by the subsequent heat treatment, it is indispensable for enabling ohmic contact, and the through hole 38, Must deposit at the bottom of through holes 40, through holes 60.

However, when the integration of elements progresses and these through holes become fine and deep, it is difficult to embed the Ti film in this way.

In this embodiment, a semiconductor storage device capable of solving the above problems and a method for manufacturing the same will be described.

The semiconductor storage device according to the present embodiment is characterized in that the embedded conductor 92 is formed at the bottom of the through hole 38, the through hole 40, and the through hole 60 through hole.

That is, a silicon oxide film 84, a silicon nitride film 86, and a silicon oxide film 88 are sequentially laminated on a semiconductor substrate 10 on which a memory cell transistor composed of a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is formed. An interlayer insulating film 36 is formed.

The interlayer insulating film 36 is formed with a through hole 38 opened on the drain diffusion layer 26 and a through hole 40 opened on the source diffusion layer 24.

An embedded conductor 92 made of Ti and TiN is formed at the bottoms of the through holes 38 and the through holes 40.

A capacitor storage electrode 46 made of a TiN film is formed on the inner wall of the through hole 40 and the embedded conductor 92, and is connected to the source diffusion layer 24 via the embedded conductor 92. A capacitor dielectric film 48 is formed on the inner surface and the upper surface of the capacitor storage electrode 46. A capacitor counter electrode 54 is formed in the through hole 40 in which the capacitor storage electrode 46 and the capacitor dielectric film 48 are formed, and on the interlayer insulating film 36. In this way, a capacitor composed of a capacitor storage electrode 46, a capacitor dielectric 48, and a capacitor counter electrode 54 is configured.

A contact conductive film 44 made of a TiN film is formed on the inner wall of the through hole 38 and the embedded conductor 92, and the drain diffusion layer 26 and the bit wire 62 are connected via the embedded conductor 92.

Further, a wiring layer 70 is formed on the upper part of the bit wire 62 via an interlayer insulating film 64, and a DRAM composed of one transistor and one capacitor is formed.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, an element separation film 12 having a film thickness of about 300 nm is formed on the main surface of the P-type silicon substrate 10 by, for example, a normal LOCOS method, and an element region 14 is defined. Next, a gate oxide film 16 having a film thickness of about 10 nm is formed in the device region 14 by a thermal oxidation method.

Subsequently, by the CVD method, a polycrystalline silicon film containing a high concentration of P having a film thickness of about 150 nm and a silicon nitride film having a film thickness of about 200 nm are continuously formed, and then ordinary lithography and etching techniques are applied. It is used to remove a part of the silicon nitride film in the peripheral circuit region. This region becomes the gate contact portion 82 when the wiring is later pulled out from the gate electrode 22.

Next, the silicon nitride film and the polycrystalline silicon film are simultaneously patterned using ordinary lithography techniques and etching techniques to form the gate electrode 20 of the memory cell transistor and the gate electrode 22 of the peripheral circuit.

After that, using the silicon nitride film 18 and the gate electrodes 20 and 22 as masks, for example, P ions have an acceleration energy of 40 keV and an injection amount of 2 × 10.¹³cm^-2Ion implantation is performed under the conditions of (Fig. 23 (a)) to form the source diffusion layer 24 of the memory cell transistor, the drain diffusion layer 26, and the low-concentration diffusion layer 28 of the peripheral circuit transistor (Fig. 23 (a)).

Next, after forming a silicon nitride film with a film thickness of about 100 nm by the CVD method, CHF₃/ H₂Anisotropic etching using a gas is performed to form a sidewalled nitride film 30 made of a silicon nitride film on the side walls of the patterned silicon nitride film 18 and the gate electrodes 20 and 22 by self-matching.

Then, using ordinary lithography technology, for example, As ions are injected into the N-type transistor region of the peripheral circuit with an acceleration energy of 40 keV and an injection amount of 4 × 10.¹⁵cm^-2Ion implantation is selectively performed under the above conditions to form the source diffusion layer 32 and drain diffusion layer 34 of the N-type transistor of the peripheral circuit (Fig. 23 (b)).

Then, about 1 μm of the silicon oxide film 84 is deposited by the CVD method, and the surface is polished and flattened by about 0.7 μm by the CMP method. Next, the silicon nitride film 86 is grown to a film thickness of about 100 nm by the CVD method.

Then, after patterning the photoresist (not shown) by a normal lithography process, CHF₃/ CF₄Etching the silicon nitride film 86 using / Ar as the etching gas, and then C₂F₆Is used as the etching gas to etch the silicon oxide film 84. This exposes the source diffusion layers 24 and 32 and the drain diffusion layers 26 and 34.

Subsequently, a Ti film is continuously formed at 10 nm by the collimated sputtering method and a TiN film is formed at 200 nm by the CVD method, and embedded on the source diffusion layers 24 and 32 and the drain diffusion layers 26 and 34. Then, the Ti film and the TiN film on the silicon nitride film 86 are removed by the CMP method to form the embedded conductor 92 (FIG. 23 (c)).

Next, a silicon oxide film 88 having a film thickness of about 2 μm is grown by the CVD method, and the photoresist is patterned by a normal lithography process, and then C.₂F₆Etching gas such as, etc. is used to etch the silicon oxide film 88. At this time, C is added to the etching gas.₂F₆If gas is used, etching can be automatically stopped at the embedded conductor 92 or the silicon nitride film 86.

Subsequently, the photoresist is removed and a through hole 38 opened on the embedded conductor 92 on the drain diffusion layer 26 of the memory cell transistor and an opening on the embedded conductor 92 on the source diffusion layer 24 of the memory cell transistor. An interlayer insulating film 36 is formed in which a through hole 40 is formed and a through hole 60 is formed in a peripheral circuit region in which an embedded conductor 92 is formed in the bottom thereof (FIG. 24 (a)).

After that, a capacitor, a bit wire, a wiring layer, etc. are formed in the same manner as in the manufacturing process shown in FIGS. 17 (a) and later of the third embodiment, and a DRAM composed of one transistor and one capacitor shown in FIG. 24 (b) is formed. To configure.

As described above, according to the present embodiment, when forming a through hole or the like having a large aspect ratio, an embedded conductor is formed in advance in a region in contact with the silicon substrate to form an ohmic contact, so that the elements can be integrated. Even when these through holes become fine and deep, the contact characteristics at the bottom of the through holes can be ensured.

In the above embodiment, one lithography process is added to form the embedded conductor 92. For example, the salicide process (SALICIDE: Self-ALIgned siliCIDE; Technical Digest IEDM 1990, p.241) disclosed by JR Fiester (SALICIDE: Self-ALIgned siliCIDE; Technical Digest IEDM 1990, p.241). By using 1990)), a conductor for contact can be formed at the bottom of the through hole without adding a lithography process.

That is, after forming the insulating film 42 covering the gate electrodes 20 and 22, for example, a Ti film is deposited on the entire surface of the semiconductor substrate 10 by a sputtering method. After that, when heat treatment is performed, the silicidization reaction occurs only on the region where the silicon of the semiconductor substrate 10 and the deposited Ti film are in direct contact, for example, on the source diffusion layer 24 and the drain diffusion layers 26 and 34.

Then, if the unreacted Ti film is removed with, for example, aqua regia, a titanium silicide film can be self-consistently formed on the source diffusion layer 24 and the drain diffusion layers 26 and 34.

After forming the titanium silicide film on the source / drain diffusion layer in this way, if the semiconductor substrate device is manufactured in the same manner as the method for manufacturing the semiconductor storage device described in any one of the first to fourth embodiments, the semiconductor substrate device can be manufactured. Even when forming a through hole or the like having a large aspect ratio, the contact characteristics at the bottom of the through hole can be ensured.

As another metal film applicable to the salicide process, for example, Ta (tantalum), W (tungsten), Mo (molybdenum) and the like can be used. [Sixth Embodiment] A semiconductor storage device according to a sixth embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 25 to 28. The semiconductor storage device of the first embodiment shown in FIGS. 1 to 6 and the same components as the manufacturing method thereof are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 25 is a schematic cross-sectional view showing the structure of the semiconductor storage device according to the present embodiment, and FIGS. 26 to 28 are process cross-sectional views showing the manufacturing method of the semiconductor storage device according to the present embodiment.

In the method for manufacturing a semiconductor storage device according to the first embodiment, as shown in FIG. 4A, when the contact conductive film 44 and the capacitor storage electrode 46 are formed, polycrystalline silicon containing a high concentration of P is used. After forming the film, the polycrystalline silicon film on the interlayer insulating film 36 was removed by the CMP method.

However, if simply polishing is performed, powdery substances generated during polishing may enter the through holes 38 and 40, which may reduce the yield.

Further, in the semiconductor storage device according to the first embodiment, the contact conductive film 44 and the capacitor storage electrode 46 are formed of the same film. Therefore, if the contact conductive film 44 is made thicker, the inner surface of the through hole 40 of the capacitor storage electrode 46 can be formed. The surface area is reduced. Therefore, the capacitor capacity is sacrificed in order to reduce the resistance value of the contact conductive film 44.

Since the depth of the through hole 40 can be set to 2 μm or less up to about 256 MDRAM, the resistance of the contact conductive film 44 does not matter, but the degree of integration is further improved and the through hole 40 is deepened. When the thickness of the contact conductive film 44 is reduced, the resistance increase of the contact conductive film 44 becomes a serious problem.

In the present embodiment, it is possible to prevent powdery substances from remaining in the through holes 38 and 40 in the polishing step when forming the contact conductive film 44 and the capacitor storage electrode 46, and sacrifice the capacitor capacity. Provided is a semiconductor storage device capable of reducing the resistance of the contact conductive film 44 without any need, and a method for manufacturing the same.

The semiconductor storage device according to the present embodiment is characterized in that columnar conductors 112 and 114 are formed in the through holes 38 and 40, respectively.

That is, a columnar conductor 112 is formed in the through hole 38, which is connected to the contact conductive film 44 at the bottom and has a capacitor dielectric film 48 formed on the side wall thereof, and is formed in the through hole 40. A columnar conductor 114 is formed at the bottom thereof, which is connected to the capacitor storage electrode 46 and has a capacitor dielectric film 48 formed on the side wall thereof.

By providing the columnar conductor in this way, in the through hole 38, the electric path connecting the drain diffusion layer 26 and the bit wire 62 is composed of the contact conductive film 44 and the columnar conductor 112. The electrical resistance in the bit wire contact portion can be significantly reduced.

Further, by providing the columnar conductor 114 in the through hole 40, the capacitor dielectric film 48 is also formed on the side wall portion thereof, so that the area of the capacitor can be increased and the capacitor capacity can be significantly increased.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, a through hole 38 is formed on the drain diffusion layer 26 and on the source diffusion layer 24 in the same manner as in the method for manufacturing the semiconductor storage device according to the first embodiment shown in FIGS. 3 (a) to 3 (d). An interlayer insulating film 36 in which a through hole 40 is formed is formed in the above (FIG. 26 (a)). The size of the through hole 38 is, for example, 0.3 × 0.3 μm, and the size of the through hole 40 is, for example, 0.3 × 0.6 μm.

Next, a polycrystalline silicon film 106 containing a high concentration of P is formed with a film thickness of about 30 nm by the CVD method.

Subsequently, for example, a silicon oxide film is grown to a film thickness of about 80 nm by a CVD method using TEOS (tetraethoxysilane: ethyl orthosilicate) as a main raw material gas, and then the entire surface is vertically etched by the RIE method to obtain a sidewall 108. Form (Fig. 26 (b)).

As a result, a gap of [300-2 × (30 + 80)] × [300-2 × (30 + 80)] nm, that is, 80 × 80 nm remains in the through hole 38, and a gap of 80 × 80 nm remains in the through hole 40. Remains a gap of [300-2 × (30 + 80)] × [600-2 × (30 + 80)] nm, that is, 80 × 380 nm.

After that, a polycrystalline silicon film 110 having a film thickness of about 200 nm is deposited by the CVD method (Fig. 27 (a)). It is desirable that the film thickness of the polycrystalline silicon film 110 to be deposited is set so that the gaps in the through holes 38 and 40 are completely embedded and the whole is substantially flat.

The entire surface is then polished by the CMP method. At this time, some overpolishing is performed so that the upper surface of the sidewall 108 is completely exposed. As a result, the contact conductive film 44 made of the polycrystalline silicon film 106, the columnar conductor 112 made of the polycrystalline silicon film 110, and the sidewall 108 are completely embedded in the through hole 38, and the through hole 40 is completely embedded. Inside, the surface is flattened with the capacitor storage electrode 46 made of polycrystalline silicon film 106, the columnar conductor 114 made of polycrystalline silicon film 110, and the sidewall 108 completely embedded. Figure 27 (b)).

Then, for example, HF: NH₄The sidewall 108 is selectively removed by immersing the substrate in a solution of F = 1: 5. As a result, voids 116 are formed in the through holes 38 and 40 (FIG. 28 (a)).

After that, for example, by the same procedure as the method for manufacturing the semiconductor storage device according to the first embodiment shown in FIGS. 4 (b) to 6 (b), the capacitor dielectric film 48, the capacitor counter electrode 54, the bit wire 62, Wiring 70 etc. are formed (Fig. 28 (b)).

As described above, according to the present embodiment, by forming the columnar conductor 114 in the through hole 40, the columnar conductor 114 also functions as the capacitor storage electrode in addition to the capacitor storage electrode 46, so that the columnar conductor The surface area of the capacitor can be increased by the surface area of 114. Therefore, the depth of the through hole 40 can be made shallow even when the same capacitance value as that of the semiconductor storage device shown in FIG. 1 is obtained.

Further, since the lead-out electrode of the bit wire contact portion is formed of the contact conductive film 44 and the columnar conductor 112, the resistance of the lead-out electrode can be reduced. Further, since the capacitor capacity can be increased as described above, the through hole 38 can be made shallower, and the resistance of the lead-out electrode can be further reduced.

In the semiconductor storage device according to the present embodiment, the contact hole 60 for peripheral circuits is formed by the same structure as the semiconductor storage device according to the modified example of the first embodiment shown in FIG. 7, but the contact hole 60 for peripheral circuits is formed by another structure. You may. For example, as in the semiconductor storage device according to the first embodiment shown in FIG. 2, the via hole 66 may be opened on the wiring layer 68 to form the wiring layer 70. [7th Embodiment] A semiconductor storage device according to a seventh embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 29 to 31. The semiconductor storage device of the first embodiment shown in FIGS. 1 to 7 and the same components as the manufacturing method thereof are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 29 is a schematic cross-sectional view showing the structure of the semiconductor storage device according to the present embodiment, and FIGS. 30 and 31 are process cross-sectional views showing the manufacturing method of the semiconductor storage device according to the present embodiment.

In the semiconductor storage device according to the modified example of the first embodiment shown in FIG. 7, the through holes 60 of the peripheral circuit are opened after the interlayer insulating film 64 is formed, and the wiring layer 70 is the capacitor counter electrode 54 and the source of the peripheral circuit transistor. The lithography process is reduced by configuring the drain diffusion layer 34 to be in direct contact with the drain diffusion layer 34.

However, since the wiring layer 70 needs to be connected to the source / drain diffusion layer 34 of the peripheral circuit transistor, the capacitor counter electrode 54, the bit wire 62, etc. at the same time, the depth of the through hole 60, the contact hole 59, etc. is very large. It varies from deep to shallow.

In such hole etching in which the depths are significantly different, it takes a long time from the exposure of the surface of the bit wire 62 and the counter electrode 54 to the exposure of the source / drain diffusion layer 34 of the peripheral circuit transistor. The surface of the bit wire 62 and the counter electrode continues to be exposed to the etching gas. In particular, when the bit wire 62 is formed of a columnar crystalline metal thin film such as tungsten, damage such as etching of the underlying insulating film through the gaps between the crystals occurs, and as a result, the bit wire 62 and the silicon substrate 10 are short-circuited. There is a risk that it will end up.

The present embodiment provides a semiconductor storage device capable of simultaneously forming through holes of various depths and a method for manufacturing the same.

In the semiconductor storage device according to the present embodiment, an interlayer insulating film 53 made of a film having etching characteristics different from those of the interlayer insulating films 64 and 36 is formed on the capacitor counter electrode 54, and the bit wire 62 and the upper wiring layer 70 are formed. An etching stopper made of a laminated film 118 of a conductive film 124 and an insulating film 126 having different etching characteristics from the interlayer insulating films 64 and 36 is arranged below the bit wire 62 in the region forming the contact hole 120 connecting the two. It is characteristic that it is done.

That is, the wiring layer 70 formed on the interlayer insulating film 64 is connected to the gate electrode 22 of the peripheral circuit transistor via the through hole 122, and the source / drain diffusion layer of the peripheral circuit transistor is connected through the through hole 60. It is connected to 34, is connected to the capacitor counter electrode 54 via the contact hole 59, and is connected to the bit wire 62 via the contact hole 120. An interlayer insulating film 53 made of a silicon nitride film is formed on the capacitor counter electrode 54. A laminated film 118 composed of a conductive film 124 and an insulating film 126 made of a silicon nitride film is arranged below the contact hole 120 that opens on the bit wire 62.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described with reference to FIGS. 30 and 31.

First, the capacitor counter electrode 54 is formed by the same procedure as the method for manufacturing the semiconductor storage device according to the first embodiment shown in FIGS. 3 (a) to 5 (a). At this time, in the region where the contact between the bit wire and the upper wiring layer should be formed, the conductive film 124 formed of the same film as the capacitor counter electrode 54 and the insulating film formed of the same film as the interlayer insulating film 53. A laminated film 118 composed of 126 is arranged in advance (Fig. 30 (a)). The interlayer insulating film 53 is formed of an interlayer insulating film 36 and a material having different etching characteristics from the interlayer insulating film 64 deposited on the upper layer, for example, a silicon nitride film.

Next, an interlayer insulating film 64 is deposited on the entire surface to flatten the surface, and then a photoresist 72 in which a through-hole and contact hole pattern is formed is formed by a normal lithography technique.

Subsequently, the interlayer insulating film 64 and the interlayer insulating film 36 are etched using the photoresist 72 as a mask. Etching of the interlayer insulating films 64 and 36 is performed under conditions where a sufficient selective ratio can be obtained with respect to the interlayer insulating film 53.

At this time, the contact hole 59 formed on the capacitor counter electrode 54 and the contact hole 120 formed on the bit wire 62 are for the through hole 60 and the peripheral circuit opened on the source / drain diffusion layer 36 of the peripheral circuit transistor. Since it is shallower than the through-hole 122 that opens on the gate electrode 22 of the transistor, the interlayer insulating film 64 on the bit wire 62 is completely removed before the through-holes 60 and 122 are completely opened, and the surface of the bit wire 62 Is exposed to etching gas. The interlayer insulating film 53 is exposed on the capacitor counter electrode 54, but the interlayer insulating film 53 is hardly etched because it is formed of a silicon nitride film having different etching characteristics from the interlayer insulating film 64 made of a silicon oxide film. (Fig. 30 (b)).

By continuing the etching, the source / drain diffusion layer 36 of the peripheral circuit transistor is exposed (FIG. 31 (a)). At this time, if the bit wire 62 is formed of a material made of columnar crystals, for example, a tungsten film, the etching may reach the lower layer film at the crystal boundary. In FIG. 31 (a), this is emphasized and expressed so that the bit wire 62 itself disappears, but since the insulating film 126 made of a silicon nitride film is formed in the lower part of the bit wire 62, The interlayer insulating film 36 is not damaged.

Then, for example, CF₄/ CHF₃The silicon nitride film is removed by etching with / He gas. As a result, the interlayer insulating film 53 on the capacitor counter electrode 54 and the insulating film 42 on the gate electrode 22 of the peripheral circuit transistor are removed, and the through holes 60 and 122 and the contact holes 59 and 120 are completely opened (FIG. FIG. 31 (b)). At this time, the insulating film 126 under the bit wire 62 is also removed, but the etching is stopped by the conductive film 124 under the bit wire 62.

In the etching gas used here, the etching rate of silicon is slow, and the remaining silicon nitride film is not thick, so that the etching time can be set short. Therefore, the etching of the 36 parts of the source / drain diffusion layer of the peripheral circuit transistor that has already been exposed is negligible.

In this way, all through holes and contact holes can be formed without any inconvenience.

As described above, according to the present embodiment, the deep through holes 60 and 120 of the peripheral circuit are formed by forming the laminated film 118 in advance in the region where the contact between the bit wire 62 and the upper wiring layer is formed. Even during the formation, the interlayer insulating film 36 under the bit wire 62 is not etched, and a short circuit between the bit wire 62 and the semiconductor substrate 10 or the like can be prevented. [8th Embodiment] A semiconductor storage device according to an eighth embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 32 to 38. The semiconductor storage device of the first embodiment shown in FIGS. 1 to 7 and the same components as the manufacturing method thereof are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 32 is a diagram illustrating a problem in the method for manufacturing a semiconductor storage device according to the first embodiment, FIG. 33 is a plan view showing a structure of the semiconductor storage device according to the present embodiment, and FIG. 34 is a structure of the semiconductor storage device according to the present embodiment. 35 to 38 are schematic cross-sectional views showing a process cross-sectional view showing a method of manufacturing a semiconductor storage device according to the present embodiment.

In the method for manufacturing a semiconductor storage device according to the first embodiment shown in FIGS. 3 to 6, the contact conductive film 44 and the capacitor storage electrode 46 are self-aligned with the gate electrode 20 of the memory cell transistor. According to this method, it is not necessary to consider the alignment margin between the gate electrode 20 and the through hole 38, and therefore, there is an advantage that the memory cell area can be reduced.

However, as the memory cell becomes finer, the depth of the through hole 38 increases sharply, and etching of the through hole also becomes difficult rapidly. The problems in the semiconductor storage device according to the first embodiment will be described below.

In the process of manufacturing the semiconductor storage device shown in FIGS. 3A to 3B, when the silicon nitride film 18 is deposited on the polycrystalline silicon film 128 serving as the gate electrode 20, the silicon nitride film 18 is deposited on the polycrystalline silicon film 128. If the dust 130 is attached, the silicon nitride film 18 grown on the dust 130 is in a swelled state in the region where the dust 130 is attached (FIG. 32 (a)).

When the silicon nitride film 18 is etched using the photoresist 72 processed into the pattern of the gate electrode 20 as a mask, the film around the dust 130 is swollen, and a part of it remains as a residue 132 (Fig. 32 (b)). ..

When the underlying polycrystalline silicon film 128 is etched in this state, the residue 132 acts as a mask, and a part of the polycrystalline silicon film 128 remains as the residue 134 (FIG. 32 (c)).

After that, when the through holes 38 and 40 are formed in the same manner as in the manufacturing method of the semiconductor storage device shown in FIGS. 3 (b) to 3 (d), the residue 134 is exposed in the through holes 38, and finally. It will be short-circuited with the contact conductive film 44 (Fig. 32 (d)).

As described above, the structure of the semiconductor storage device according to the first embodiment is very sensitive to dust, which may lead to a decrease in yield. If the yield is simply reduced, it can be remedied by a method such as redundancy, but a short circuit between the bit line 62 and the word line 20 becomes a serious problem. That is, in the standby state, the potential of the bit line 62 is set to half of the power supply voltage, and the potential of the word line 20 is set to zero, so that a current constantly flows from the bit line 62 to the word line 20. Become. As a result, the current consumption during standby increases, and normal redundancy cannot be used for relief.

The present embodiment provides a semiconductor storage device and a manufacturing method that can solve the problems of the first embodiment as described above.

In the semiconductor storage device according to the present embodiment, as shown in the plan view of FIG. 33 and the cross-sectional view of FIG. 34, the contact between the fine through hole 38 connecting the bit wire 62 and the drain diffusion layer 26 and the capacitor storage electrode 46. A fine through hole 40 for use is formed, and the capacitor storage electrode 36 is characterized in that it is formed in a large opening 142 opened on the through hole 40.

With this configuration, the contact conductive film 44 embedded in the through hole 38 can be formed sufficiently separated from the gate electrode 20, so that the short circuit between the gate electrode 20 and the bit wire 62 is significantly short-circuited. Can be reduced to.

Further, since the polycrystalline silicon film 140 embedded in the through hole 40 exists as a columnar protrusion in the opening 142, the capacitor capacity can be increased.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, an element separation film 12 having a film thickness of about 300 nm is formed on the main surface of the silicon substrate 10 by, for example, a normal LOCOS method, and an element region 14 is defined. Next, a gate oxide film 16 having a film thickness of about 10 nm is formed in the device region 14 by a thermal oxidation method.

Subsequently, a polycrystalline silicon film containing a high concentration of P and having a thickness of about 150 nm is formed by the CVD method, and then the polycrystalline silicon film is patterned using ordinary lithography technology and etching technology to form a gate electrode 20. Form.

In the present embodiment, only the polycrystalline silicon film single layer is patterned to form the gate electrode 20, but as shown in the first embodiment, the polycrystalline silicon film and the silicon nitride film are continuously formed. , This laminated film may be patterned at the same time. In this case, it is possible to prevent the gate electrode 20 from being accidentally exposed in the through holes 38 and 40 when the through holes 38 and 40 are formed later.

After that, using the gate electrode 20 as a mask, for example, P ions are used for acceleration energy of 20 keV and injection amount of 2 × 10.¹³cm^-2Ion implantation is performed under the conditions of (1) to form the source diffusion layer 24 and the drain diffusion layer 26 of the memory cell transistor. Although not shown in this embodiment, the diffusion layer formed in this way is n of the LDD structure in the N-type transistor for peripheral circuits.^-It becomes a layer (Fig. 35 (a)).

Next, an anisotropic etching is performed after forming a silicon nitride film having a film thickness of about 100 nm by the CVD method, and a sidewall nitride film 30 is self-aligned on the side wall of the gate electrode 20 (FIG. 35 (b)). The sidewall to be formed may be a silicon oxide film.

Subsequently, for example, As ions are injected into the N-type transistor region (not shown) of the peripheral circuit with an acceleration energy of 40 keV and an injection amount of 4 × 10.¹⁵cm^-2Ion implantation is selectively performed under the above conditions to form a source / drain diffusion layer for N-type transistors in peripheral circuits. As a result, a transistor for a peripheral circuit having an LDD structure is formed.

Then, a BPSG film of about 2 μm is deposited by the CVD method to form an interlayer insulating film 36.

Next, after depositing a polycrystalline silicon film having a film thickness of about 100 nm on the interlayer insulating film 36 by the CVD method. The polycrystalline silicon film is patterned using ordinary lithography and etching techniques to form the polycrystalline silicon pattern 136.

Subsequently, a polycrystalline silicon film having a thickness of about 150 nm is deposited and then etched by the RIE method to form a polycrystalline silicon sidewall 138 on the side wall of the patterned polycrystalline silicon pattern 136 (FIG. 35 (c)).

After that, the polycrystalline silicon pattern 136 formed in this way and the interlayer insulating film 36 are etched using the polycrystalline silicon sidewall 138 as a mask, and the through hole 40 opened on the source diffusion layer 24 and the drain diffusion layer 26 are formed. A through hole 38 opened above is formed (Fig. 36 (a)).

Since the through holes 38 and 40 formed in this way open the polycrystalline silicon pattern 136 and the polycrystalline silicon sidewall 138 as masks, a fine opening having a size equal to or smaller than the minimum resolution of the exposure apparatus, for example, 0.1 μm, can be formed. Can be formed.

The above method for forming the through holes 38 and 40 requires a considerable number of steps. However, if the locations where the through holes 38 and 40 are used are limited to, for example, memory cells, an electron beam is required. It can also be formed by a lithography technique using a drawing method. In general, the throughput is long in the lithography by electron beam drawing, but by limiting the place to be used, it may be offset by the difference in the number of steps by the above method, and the throughput may be shortened.

Next, a polycrystalline silicon film 140 having a film thickness of about 100 nm is deposited by the CVD method, and through holes 38 and 40 are embedded (Fig. 36 (b)). Although this step is not always necessary, it is effective in increasing the capacity of the capacitor and in protecting the underlying substrate from damage during etching. This will be described later.

Subsequently, the polycrystalline silicon film 140, the polycrystalline silicon pattern 136, the polycrystalline silicon sidewall 138, and the interlayer insulating film 36 are patterned by ordinary lithography and etching techniques to form an opening 142 in the region where the capacitor is formed (). Figure 37 (a)). At this time, since the polycrystalline silicon film 140 embedded in the through hole 40 remains as a columnar protrusion, the surface of the silicon substrate 10 under the through hole 40 is not directly damaged by etching.

In the etching of the interlayer insulating film 36, it is necessary to stop the etching in the middle of the film. When sufficient etching accuracy cannot be obtained, the interlayer insulating film 36 may be a laminated film composed of, for example, a silicon nitride film and a BPSG film, and the etching of the opening 142 may be stopped by the silicon nitride film. By doing so, the number of steps is increased, but the depth control of the opening 142 is facilitated, the variation in the capacitor capacity is reduced, and the characteristics can be stabilized.

After that, a polycrystalline silicon film having a film thickness of about 20 nm is deposited by the CVD method and polished by the CMP method until the interlayer insulating film 36 is exposed on the surface. By doing so, the capacitor storage electrode 46 is formed in the opening 142, and the contact conductive film 44 is formed in the through hole 38 (FIG. 37 (b)).

Since the polycrystalline silicon film 140 remaining as columnar protrusions exists in the opening 142, the surface area of the capacitor storage electrode 46 increases. Thereby, the capacitor capacity can be increased.

After forming the contact conductive film 44 and the capacitor storage electrode 46 in this way, the capacitor dielectric film is formed in the same manner as in the method for manufacturing the semiconductor storage device according to the first embodiment shown in FIGS. 3 (b) to 6 for example. 48, capacitor counter electrode 54, bit wire 62, wiring 70, etc. are formed (Fig. 38).

As described above, according to the present embodiment, the opening diameters of the through holes 40 opened on the source diffusion layer 24 and the through holes 38 opened on the drain diffusion layer 26 can be made extremely small, so that the gate electrode 20 can have an extremely small opening diameter. Even when an etching residue is generated, the short circuit between the bit wire 62 and the gate electrode 20 can be greatly reduced.

Further, since the area of the capacitor storage electrode 54 is determined by the separately formed opening 142, the above effect can be obtained without reducing the area of the storage electrode 54.

Further, by depositing the polycrystalline silicon film 140 before forming the opening 142, columnar protrusions remain in the opening 142, so that the capacitor capacity can be increased. Thereby, the depth of the through hole for achieving a certain storage capacity can be reduced.

In the above embodiment, the polycrystalline silicon film is used as the conductive film to be embedded in the through holes 38 and 40, but for example, various conductors as shown in the third embodiment may be used. [9th Embodiment] A method for manufacturing a semiconductor storage device according to a ninth embodiment of the present invention will be described with reference to FIGS. 39 and 40. The semiconductor storage device of the first embodiment shown in FIGS. 1 to 7 or the semiconductor storage device of the third embodiment shown in FIGS. 15 to 18 and the same components as the manufacturing method thereof are designated by the same reference numerals and the description thereof is omitted. Simplify.

39 and 40 are process cross-sectional views showing a method of manufacturing a semiconductor storage device according to the present embodiment.

In the method for manufacturing a semiconductor storage device according to the first embodiment, as shown in FIG. 4A, when the contact conductive film 44 and the capacitor storage electrode 46 are formed, polycrystalline silicon containing a high concentration of P is used. After forming the film, the polycrystalline silicon film on the interlayer insulating film 36 was removed by the CMP method.

Further, in the method for manufacturing the semiconductor storage device according to the third embodiment, as shown in FIG. 17A, when the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 are formed, the Ti film and the TiN are formed. After the film was continuously formed, the TiN film and the Ti film on the interlayer insulating film 36 were removed by the CMP method.

However, as shown in the sixth embodiment, when the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 are formed in the through holes 38, 40, and 60 in this way, a powdery substance generated during polishing is generated. Etc. may enter the through holes 38, 40, 60 and reduce the yield.

Further, if a powdery substance or the like enters the through hole 40, the through hole 40 is filled up, and not only the capacity cannot be secured but also the withstand voltage is deteriorated.

Furthermore, a method of using lithography technology instead of the CMP method to leave a photoresist in the through holes 38, through holes 40, and through holes 60, and then etching and removing the Ti film and TiN film using this photoresist as a mask. As shown in the third embodiment, the etching cannot be controlled at the endpoint by this method.

In the time control, if a residue remains in a place other than the through holes 38, 40, 60, for example, the bit wire 62 and the capacitor storage electrode 46 are short-circuited, so that overetching is required. If this is done, even the capacitor storage electrode 46 on the side wall of the through hole 40 is etched, so that the capacitor capacity is reduced.

In the present embodiment, a method for manufacturing a semiconductor storage device capable of forming a contact conductive film 44, a capacitor storage electrode 46, and a conductive film 80 by the CMP method without invading powders or the like into the through holes 38, 40, 60. provide.

In the following description, the embodiment when applied to the method for manufacturing a semiconductor storage device according to the third embodiment is shown, but it can also be applied to the method for manufacturing a semiconductor storage device according to another embodiment.

First, through holes 38, 40, and 60 are formed in the interlayer insulating film 36 in the same manner as in the method for manufacturing the semiconductor storage device according to the third embodiment shown in FIGS. 16A to 16C.

Next, a Ti film having a film thickness of about 10 nm and a TiN film having a film thickness of about 30 nm are continuously formed by the CVD method to form a conductive film 144 (FIG. 39 (a)).

Subsequently, a resist containing a pigment is applied to the surface to form a photoresist 72 having a film thickness of about 2 μm. As a result, the through holes 38, 40, and 60 are completely embedded by the photoresist 72 (Fig. 39 (b)). A photosensitive polyimide may be used instead of the photoresist 72.

After that, the entire surface of the photoresist 72 is exposed, leaving the photoresist 72 only in the through holes 38, 40, and 60 (FIG. 40 (a)).

Next, the conductive film 144 on the interlayer insulating film 36 is removed by the CMP method. At this time, since the photoresist 72 is embedded in the through holes 38, 40, 60, powders and the like generated by polishing do not enter the through holes 38, 40, 60. In this way, the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 are formed.

The photoresist 72, the TiN film, and the Ti film may be removed by the CMP method without exposing the photoresist 72 to the entire surface.

Subsequently, the photoresist 72 remaining in the through holes 38, 40, and 60 is removed with a hydrogen peroxide solution (FIG. 40 (b)).

After that, the semiconductor storage device is formed by the manufacturing method shown in FIGS. 17 (a) to 18 (b).

As described above, according to the present embodiment, the photoresist 72 is embedded in the through holes 38, 40, and 60 before the polishing step when forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80. Therefore, powdery substances and polishing agents generated during polishing do not enter the through holes 38, 40, and 60, and it is possible to prevent a decrease in yield due to this.

In the above embodiment, the bit line contact portion and the contact portion in the peripheral circuit region are formed to have the same structure as in the semiconductor storage device according to the third embodiment, but the first embodiment or the second embodiment has the same structure. The contacts in the peripheral circuit region may be formed as in the semiconductor storage device according to the above.

Further, the structure of the semiconductor storage device according to the above embodiment can be applied to other embodiments according to the present invention. [10th Embodiment] A semiconductor storage device according to a tenth embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 41 to 43. The same components as those of the semiconductor storage device of the ninth embodiment and the manufacturing method thereof are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 41 is a schematic cross-sectional view showing the structure of the semiconductor storage device according to the present embodiment, and FIGS. 42 and 43 are process cross-sectional views showing the manufacturing method of the semiconductor storage device according to the present embodiment.

In the present embodiment, as in the ninth embodiment, there is provided a method for manufacturing a semiconductor storage device capable of forming a contact conductive film, a capacitor storage electrode, etc. by the CMP method without allowing powdery substances or the like to enter the through holes. ..

The semiconductor storage device according to the present embodiment is characterized in that an insulating film having etching characteristics different from that of the interlayer insulating film 36 is formed on the uppermost portion of the interlayer insulating film 36.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, a memory cell transistor and a peripheral circuit transistor are formed on the semiconductor substrate 10 in the same manner as in the method for manufacturing the semiconductor storage device according to the third embodiment shown in FIGS. 16A and 16B.

Next, a silicon oxide film having a film thickness of about 2 μm and a silicon nitride film having a film thickness of about 50 nm are continuously formed by a CVD method to form an interlayer insulating film 36 having a silicon nitride film 146 formed on the uppermost portion.

Subsequently, through holes 38, 40, and 60 are opened in the interlayer insulating film 36 having a two-layer structure composed of a silicon nitride film and a silicon oxide film (FIG. 42 (a)).

After that, a conductive film 144 composed of a Ti film having a film thickness of about 10 nm, a TiN film having a film thickness of about 30 nm, and a silicon oxide film 148 having a film thickness of about 0.15 μm are deposited by the CVD method (Fig. 42 (b)). The insides of the through holes 38, 40, and 60 are completely embedded by the silicon oxide film 148.

Next, the silicon oxide film 148 is removed onto the conductive film 144 by the CMP method, and then the conductive film 144 is removed onto the silicon nitride film 146 (FIG. 43 (a)). In this way, the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 are formed.

By forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80 in this way, powders and abrasives generated during the polishing of the conductive film 144 do not enter the through holes 38, 40, and 60. ..

Subsequently, the silicon oxide film 148 is subsequently removed by wet etching using, for example, a fluoroacid aqueous solution (FIG. 43 (b)).

After that, the semiconductor storage device is formed by the manufacturing method shown in FIGS. 17 (a) to 18 (b).

As described above, according to the present embodiment, the silicon oxide film 148 is embedded in the through holes 38, 40, and 60 before the polishing step when forming the contact conductive film 44, the capacitor storage electrode 46, and the conductive film 80. Therefore, powdery substances and polishing agents generated during polishing do not enter the through holes 38, 40, and 60, and it is possible to prevent a decrease in yield due to this. [11th Embodiment] The semiconductor storage device according to the eleventh embodiment of the present invention and the manufacturing method thereof will be described with reference to FIGS. 44 to 47.

FIG. 44 is a schematic cross-sectional view showing the structure of the semiconductor storage device according to the present embodiment, and FIGS. 45 to 47 are process cross-sectional views showing the manufacturing method of the semiconductor storage device according to the present embodiment.

In the semiconductor storage device according to the present embodiment and the manufacturing method thereof, the manufacturing method of the semiconductor storage device according to the fourth and tenth embodiments is applied to the semiconductor storage device having a double-sided cylinder capacitor.

That is, as shown in FIG. 44, the capacitor storage electrode 46 includes a contact portion 46a formed on the inner wall and the bottom of a through hole 40 formed in an interlayer insulating film composed of a silicon oxide film 84 and a silicon nitride film 86, and a contact portion 46a thereof. It is composed of a protruding portion 46b formed continuously on the upper part. The capacitor dielectric film 48 is formed so as to cover the inside of the capacitor storage electrode 46 and the outer wall of the protrusion 46b. The capacitor counter electrode is formed so as to cover the capacitor dielectric film 48. In this way, the double-sided cylinder capacitor is formed.

The interlayer insulating film 36 on which the through holes 40 are formed is formed of a laminated film made of films having different etching characteristics. That is, in the semiconductor storage device according to the present embodiment, the interlayer insulating film 36 is formed by the silicon oxide film 84 and the silicon nitride film 86.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, a three-layer structure of a silicon oxide film 84, a silicon nitride film 86, and a silicon oxide film 88 is performed by the same procedure as the method for manufacturing a semiconductor storage device according to the fourth embodiment shown in FIGS. 20 (a) to 21 (a). An interlayer insulating film is formed, and the through hole 40 is opened. In the method for manufacturing the semiconductor storage device according to the fourth embodiment, the through holes 38 that open on the drain diffusion layer 26 are formed at the same time, but they are not formed in the present embodiment (FIG. 45 (a)).

Next, a conductive film 144 made of a polycrystalline silicon film having a film thickness of about 50 nm and high-concentration P-doped and a silicon oxide film 148 having a film thickness of about 0.15 μm are deposited by the CVD method (Fig. 45 (b)). As a result, the inside of the through hole 40 is completely embedded by the silicon oxide film 148.

Subsequently, the silicon oxide film 148 is removed onto the conductive film 144 by the CMP method, and then the conductive film 144 is removed onto the silicon oxide film 88 (FIG. 46 (a)). In this way, the capacitor storage electrode 46 is formed.

When the capacitor storage electrode 46 is formed in this way, powdery substances and abrasives generated during polishing of the conductive film 144 do not enter the through holes 40.

After that, wet etching is performed using, for example, a fluoroacid aqueous solution. As a result, the silicon oxide film 148 and the silicon oxide film 88 are etched, and the capacitor storage electrode 46 is exposed as a cylinder-shaped protrusion (FIG. 46 (b)).

Next, the capacitor dielectric film 48 and the capacitor counter electrode 54 are formed to form a capacitor having a double-sided cylinder structure, and the interlayer insulating film 64 is deposited.

Subsequently, a through hole 38 penetrating the interlayer insulating film 64, the silicon nitride film 86, and the silicon oxide film 84 is opened, and a bit wire 62 is formed so as to embed the through hole 38 (FIG. 47).

By manufacturing the semiconductor storage device in this way, it is possible to form a DRAM cell having a capacitor having a double-sided cylinder structure.

As described above, according to the present embodiment, by embedding the silicon oxide film 148 in the through hole 40 before the polishing step when forming the capacitor storage electrode 46, powdery substances and polishing generated during polishing are performed. Since the agent does not enter the through hole 40, it is possible to prevent a decrease in yield due to this even in a semiconductor storage device having a cylinder capacitor.

In the above embodiment, the bit wire 62 formed on the interlayer insulating film 64 is directly connected to the drain diffusion layer 26, but it is formed at the same time as the capacitor storage electrode 46 in the same manner as the semiconductor storage device according to the first embodiment. It may be connected via the contact conductive film 44. [12th Embodiment] The structure of the semiconductor storage device according to the twelfth embodiment of the present invention will be described with reference to FIGS. 48 and 49. The same components as those of the semiconductor storage devices of the first to third embodiments are designated by the same reference numerals, and the description thereof will be omitted or simplified.

FIG. 48 is a plan view and a partial cross-sectional view showing the structure of the semiconductor storage device according to the present embodiment, and FIG. 49 is a diagram showing a peripheral circuit configuration example of the semiconductor storage device according to the present embodiment.

In the first to third embodiments described above, various alignment margins are not required by making full use of the self-alignment process. Therefore, it is possible to arrange the word line and the bit line with the line and space (L / S) of the minimum processing dimension.

However, if the word wire or bit wire is machined with the minimum machining size of L / S, it is not possible to secure an overlap margin between the contact hole and the wiring layer, and it is not possible to bend the wiring. Therefore, in order to realize such a memory cell, it is necessary to perform a pattern layout in consideration of the arrangement of peripheral circuits and the like in addition to those shown in the above embodiment.

In this embodiment, the structure of the semiconductor storage device that can realize the semiconductor storage device according to the first to third embodiments will be described in consideration of the layout of peripheral circuits.

As shown in FIG. 48 (a), in the semiconductor storage device according to the present embodiment, the bit lines 62 and the word lines 20 patterned with the minimum processing dimensions are arranged so as to be orthogonal to each other. When arranged in this way, a problem is the overlap margin between the bit wire contact hole and the bit wire.

As shown in FIG. 48 (b) which is a cross-sectional view of the XX ́ part of FIG. 48 (a), since the bit wire 62 needs to contact the contact conductive film 44, the contact conductive film 44 is a bit wire contact. Must be exposed in hall 58.

However, if the pattern end of the bit wire 62 is formed in the bit wire contact hole 58 due to the misalignment when patterning the bit wire 62, the contact conductive film 44 or the like is etched by the etching when the bit wire 62 is formed. This causes inconveniences such as an increase in steps. Therefore, as shown in FIG. 48 (c), which is a cross-sectional view of the YY ́ portion of FIG. 48 (a), the width of the bit wire contact hole 58 is required to be narrower than the width of the bit wire 62.

On the other hand, since the bit wire 62 is connected to the polycrystalline silicon film 50 embedded in the through hole 38, the polycrystalline silicon film 50 embedded in the through hole 38 and the capacitor counter electrode 54 do not remain connected. As described above, when patterning the capacitor counter electrode 54, it is necessary to form the capacitor facing electrode 54 sufficiently separated from the through hole 38. Therefore, it is desirable that the bit wire contact hole 58 is wide.

In order to satisfy these conflicting requirements for the bit wire contact hole 58, it is necessary to optimize the thickness of the contact conductive film 44 and the width of the sidewall oxide film 56.

For example, when the bit wire 62 is patterned with an L / S of 0.3 μm and the through hole is opened at 0.3 μm, the bit wire 62 overlaps with the bit wire contact hole 58 in consideration of the misalignment of the bit wire 62. Is set to 0.07 μm, for example, and the distance between the polycrystalline silicon film 50 and the capacitor counter electrode 54 is secured, for example, 0.1 μm.

Next, the film thickness of the contact conductor film 44 and the width of the sidewall oxide film 56 are optimized so as to satisfy the above parameters. For example, if the film thickness of the contact conductive film 44 is 0.05 μm and the width of the sidewall oxide film 56 is 0.12 μm, the distance between the capacitor facing electrodes 54 in the word line 20 direction is 0.4 μm and the width of the bit line contact hole 58. Is 0.16 μm.

The purpose of the bit wire contact hole 58 described here is to prevent the contact conductive film 44 and the like from being etched when the bit wire 62 is formed, and the etching is precisely controlled. For example, it goes without saying that the width of the bit wire contact hole 58 shown in FIG. 48 (c) may be wider than the width of the bit wire 62.

In this way, the minimum cell area can be realized by forming the rectangular bit line contact hole 58 extending in the bit line 62 direction as shown in FIGS. 48 (b) and 48 (c). The cell area at this time is 0.72 μm.²Will be.

Next, a configuration example of the peripheral circuit is shown.

As shown in FIG. 49, the decoder 94 and the sense amplifier 96 are formed on both sides of the memory cell area. By arranging the decoder 94 and the sense amplifier 96 in this way, the peripheral circuits can be arranged without any problem even when the matching margin is completely eliminated and the memory cell area is reduced.

In the present embodiment, since the word line and the bit line are arranged with the minimum processing dimension L / S, the bit line 62 cannot be bent in the middle. Therefore, it is not possible to adopt a twisted bit line structure that suppresses interference between bit lines by twisting the paired bit lines in the middle. Further, in order to adopt a shielded bit wire structure in which a shield plate is provided on the bit wires to suppress interference between the bit wires, an increase in the manufacturing process is unavoidable.

However, if the film thickness of the bit lines is made sufficiently thinner than the bit line spacing, the capacitive coupling between the bit lines can be suppressed, so that the interference between the bit lines can be suppressed. For example, if the structure of the bit wire is W film (50 nm) / TiN film (50 nm) / Ti film (30 nm) and the total film thickness is 0.13 μm, it can be smaller than half of the bit line spacing of 0.3 μm. Can deal with interference between lines.

As described above, according to the present embodiment, by optimizing the structure of the bit wire contact hole, even when the bit wire is arranged with the minimum machining dimension, the overlap margin between the bit wire contact hole and the bit wire can be maintained. Since it can be secured, it is possible to configure a semiconductor storage device in which the memory cell area is significantly reduced.

Further, since the decoder and the sense amplifier are provided on both sides of the memory cell area, peripheral circuits can be arranged without any problem even when the memory cell area is reduced by eliminating the matching margin at all. [13th Embodiment] The semiconductor storage device according to the thirteenth embodiment of the present invention and the manufacturing method thereof will be described with reference to FIGS. 50 to 56.

50 is a plan view showing the structure of the semiconductor storage device according to the present embodiment, FIG. 51 is a schematic view showing a cross section of the AA ́ portion of the semiconductor storage device of FIG. 50, and FIGS. 52 to 55 are the semiconductor storage device according to the present embodiment. FIG. 56 is a schematic cross-sectional view showing the structure of the semiconductor storage device according to the modified example of the present embodiment.

In this embodiment, a semiconductor storage device and a manufacturing method thereof to which other forming methods of bit wires and capacitors are applied to the semiconductor storage device and the manufacturing method thereof according to the eighth embodiment are shown.

First, the structure of the semiconductor storage device according to the present embodiment will be described with reference to the plan view of FIG. 50 and the cross-sectional view of FIG. 51. FIG. 51 basically shows a cross section of the AA ́ section of FIG. 50, but shows a part of the bit line 62 and the through hole 38 virtually moved. That is, in FIG. 51, the cross section of the BB ́ part and the cross-sectional view of the AA ́ part of FIG. 50 are shown at the same time.

The element region 14 defined by the element separation film 12 is formed on the silicon substrate 10. The source diffusion layer 24 and the drain diffusion layer 26 are independently formed in the element region 14. A gate electrode 20 is formed on the semiconductor substrate 10 between the source diffusion layer 24 and the drain diffusion layer 26 via a gate oxide film 16. In this way, a memory cell transistor including a gate electrode 20, a source diffusion layer 24, and a drain diffusion layer 26 is configured.

A bit wire 62 is arranged in a direction intersecting the gate electrode 20, and is connected to the drain diffusion layer 26 via a through hole 38. A capacitor storage electrode 46 is connected on the source diffusion layer 24 via a through hole 40, and a capacitor is formed by the capacitor dielectric film 48 and the capacitor counter electrode 54 formed on the capacitor storage electrode 46. There is. A wiring layer 70 is formed on the upper part of the capacitor via an interlayer insulating film 64, and a DRAM composed of one transistor and one capacitor is formed.

Here, the width of the gate electrode 20, that is, the word line is 0.2 μm, and the gate electrodes 20 are arranged at intervals of 0.3 μm. The through holes 38 and 40 have an opening diameter of 0.1 μm and are formed at a distance of 0.1 μm from the gate electrode 20. The width of the bit wires 62 is 0.2 μm, and they are arranged at intervals of 0.3 μm. The overlap with the through hole 38 is about 0.05 μm, and the distance from the through hole 40 is about 0.1 μm. Thus, the cell area is 0.5 μm²A memory cell having the above is formed.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, an element separation film 12 having a film thickness of about 300 nm is formed on the main surface of the silicon substrate 10 by, for example, a normal LOCOS method, and an element region 14 is defined. Next, a gate oxide film 16 having a film thickness of about 10 nm is formed in the device region 14 by a thermal oxidation method.

Subsequently, a polycrystalline silicon film having a film thickness of about 150 nm and containing a high concentration of P is grown by the CVD method, and then the polycrystalline silicon film is patterned using ordinary lithography and etching techniques to form a gate electrode. Form 20.

After that, using the element separation membrane 12 and the gate electrode 20 as masks, for example, P ions have an acceleration energy of 20 keV and an injection amount of 2 × 10.¹³cm^-2Ion implantation is performed under the conditions of (Fig. 52 (a)) to form the source diffusion layer 24 and drain diffusion layer 26 of the memory cell transistor (Fig. 52 (a)).

Next, a silicon oxide film having a film thickness of about 50 nm and a BPSG film having a film thickness of about 200 nm are sequentially grown by the CVD method, and then the surface is flattened by reflow to form the interlayer insulating film 150.

Subsequently, a polycrystalline silicon film 158 having a film thickness of about 50 nm is deposited by a CVD method and patterned to a width of about 0.3 μm using ordinary lithography techniques and etching techniques (Fig. 52 (b)).

After that, a polycrystalline silicon film having a thickness of about 100 nm is deposited by the CVD method and etched in the vertical direction by the RIE method to form a polycrystalline silicon sidewall 160 on the side wall of the patterned polycrystalline silicon film 158. Due to the polycrystalline silicon sidewalls 160 formed at intervals of 0.3 μm in width, the width of the interlayer insulating film 150 exposed between them is about 0.1 μm (Fig. 52 (c)).

Next, the interlayer insulating film 150 is etched using the polycrystalline silicon film 158 and the polycrystalline silicon sidewall 160 as masks, and the through hole 38 opened on the drain diffusion layer 26 and the through hole opened on the source diffusion layer 24. It forms with 40 (Fig. 52 (d)).

The opening diameters of the through holes 38 and 40 formed in this way are substantially equal to the distance between the polycrystalline silicon sidewalls 160, and thus are about 0.1 μm as described above.

In the present embodiment, the through holes 38 and 40 are opened using the polycrystalline silicon film 158 and the polycrystalline silicon sidewall 160 as masks to enable processing below the resolution limit of the exposure apparatus. As shown in the method for manufacturing a semiconductor storage device according to the embodiment, through holes 38 and 40 may be opened by using an electron beam drawing method. By using either method, it is possible to open through holes having dimensions that cannot be formed by ordinary lithography.

Subsequently, a polycrystalline silicon film having a film thickness of about 60 nm, a tungsten silicide film having a film thickness of about 100 nm, and a silicon nitride film are deposited by a CVD method and patterned by a normal lithography technique and an etching technique. As a result, a bit wire 62 having a tungsten polyside structure is formed in which the upper layer is covered with the silicon nitride film 156.

When patterning the bit wire 62, the polycrystalline silicon film 158 and the polycrystalline silicon sidewall 160 are simultaneously patterned so that the embedded conductor 162 made of the polycrystalline silicon film remains in the through hole 40 ( Figure 53 (a)).

The through hole 40 does not have to be embedded only with polycrystalline silicon. For example, it may be embedded with a polycrystalline silicon film and a tungsten silicide film, or as shown in FIG. 55, it may be embedded with a polycrystalline silicon film, a tungsten silicide film, and a silicon nitride film. Regardless of the structure, there is no problem because the contact can be taken at the entire bottom of the through hole 40.

Further, as the insulating film formed on the bit wire 62, it is desirable to use a silicon oxide film having a low dielectric constant in order to reduce the parasitic capacitance, but it is applicable when the insulating film on the bit wire 62 is used as an etching stopper film. It becomes difficult. Therefore, when used as an etching stopper film, it is also effective to form a laminated film of a silicon oxide film and a silicon nitride film on the bit wire 62.

After that, a silicon nitride film having a film thickness of about 80 nm is deposited by the CVD method and etched in the vertical direction by the RIE method. As a result, a sidewall 164 is formed on the side wall of the bit wire 62, and the bit wire 62 is completely covered by the silicon nitride film 156 and the sidewall 164 (FIG. 53 (b)).

Next, a polycrystalline silicon film having a thickness of about 500 nm is deposited by a CVD method and patterned by a normal lithography technique and an etching technique to form a capacitor storage electrode 46 (FIG. 54 (a)). By forming the capacitor storage electrode 46 in this way, the capacitor storage electrode 46 can be connected to the source diffusion layer 24 without using the masking process, so that the masking process can be reduced by one step as compared with the conventional method. can do.

Subsequently, a silicon nitride film having a film thickness of about 5 nm is deposited by a CVD method, and then the surface thereof is oxidized to form a capacitor dielectric film 48.

After that, a polycrystalline silicon film having a thickness of about 100 nm is deposited by a CVD method and patterned by a normal lithography technique and an etching technique to form a capacitor counter electrode 54 (FIG. 54 (b)).

Next, a BPSG film having a film thickness of about 300 nm is deposited by the CVD method and then reflowed to form an interlayer insulating film 154.

Subsequently, after forming a through hole in the peripheral circuit region (not shown), a metal material such as tungsten is deposited and patterned to form the wiring layer 70 (FIG. 55).

In this way, a DRAM consisting of one transistor and one capacitor is constructed.

In the above embodiment, since the height of the memory cell capacitor is large and the height difference between the peripheral circuit area and the memory cell area is large, the wiring layer 70 on the memory cell has a relaxed line width and spacing. It is supposed to be.

As described above, according to the present embodiment, the capacitor storage electrode 46 is embedded in the through hole 40 formed at the same time as the through hole 38 via the embedded conductor 162 embedded at the same time as the formation of the bit wire 62, and the source diffusion layer 24 It is connected to the. Therefore, it is possible to reduce the time that the silicon nitride film 156 on the bit wire 62 is exposed to the etching atmosphere without adding a new step to the formation of the through hole 40.

Further, since the embedded conductor 162 is exposed when the upper portion and the side wall of the bit wire 62 are covered with the insulating film, the contact through hole of the capacitor storage electrode 46 is masked as in the conventional manufacturing method. There is no need to use and form. Therefore, the masking process can be reduced by one process. [14th Embodiment] The semiconductor storage device according to the 14th embodiment of the present invention and the manufacturing method thereof will be described with reference to FIGS. 56 to 58.

FIG. 56 is a schematic cross-sectional view showing the structure of the semiconductor storage device according to the present embodiment, and FIGS. 57 and 58 are process cross-sectional views showing the manufacturing method of the semiconductor storage device according to the present embodiment.

In the semiconductor storage device according to the thirteenth embodiment, the height of the memory cell capacitor is large, and the height difference between the peripheral circuit area and the memory cell area is large, so that the wiring layer 70 on the memory cell is a relaxed wiring. Must be designed according to the rules. In the present embodiment, a semiconductor storage device for solving this problem and a method for manufacturing the same are provided.

The semiconductor storage device according to the present embodiment is characterized in that an interlayer insulating film is formed in the peripheral circuit region, and the height difference between the memory cell region and the peripheral circuit region is small.

That is, in the peripheral circuit region, the interlayer insulating film is formed by a three-layer structure composed of the interlayer insulating films 150, 152, and 154, and in the memory cell region, the interlayer insulating film is formed by the interlayer insulating films 150 and 154. .. Therefore, in the peripheral circuit region, the interlayer insulating film is thickened by the amount of the interlayer insulating film 152, and the height difference between the memory cell region and the peripheral circuit region is small.

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described.

First, the bit wire 62 and the embedded conductor 162 are formed by the same procedure as the manufacturing method of the semiconductor storage device according to the thirteenth embodiment shown in FIGS. 52 (a) to 53 (b) (FIG. 57 (a)). ..

Next, a BPSG film having a film thickness of about 300 nm is deposited by the CVD method, and an interlayer insulating film 152 having a flat surface is formed by reflow or polishing.

Subsequently, an opening 166 is formed in the interlayer insulating film 152 by using a normal lithography technique and an etching method of stopping with a silicon nitride film, and the bit wire 62 is covered with the silicon nitride film 156 and the sidewall 164 and embedded conductive. The body 162 is exposed (Fig. 57 (b)).

After that, a polycrystalline silicon film having a film thickness of about 20 nm is grown by a CVD method to polish the surface, and a capacitor storage electrode 46 is formed in the opening 166. The capacitor storage electrode 46 is connected to the embedded conductor 162 at the upper part of the through hole 40 (FIG. 58 (a)).

At the time of polishing, the method for manufacturing a semiconductor storage device according to the ninth to eleventh embodiments may be applied so that powdery substances and abrasives do not enter the opening 166.

Next, the interlayer insulating film 152 is etched at 50 nm by wet etching using, for example, a fluoroacid aqueous solution. When the interlayer insulating film 152 is formed in this way, the exposed area of the capacitor storage electrode 46 increases, so that the capacitor capacity increases, but the height difference between the memory cell region and the peripheral circuit region increases. Therefore, it is desirable not to perform etching when the height difference is a particular problem.

Subsequently, a capacitor dielectric film 48, a capacitor counter electrode 54, an interlayer insulating film 154, and a wiring layer 70 are formed to form a DRAM composed of one transistor and one capacitor (FIG. 58 (b)).

In the method of manufacturing the semiconductor storage device according to the present embodiment, the surface step of the interlayer insulating film 154 between the memory cell region and the peripheral circuit region can be reduced, so that the wiring layer 70 is the semiconductor storage according to the thirteenth embodiment. It can be placed according to stricter rules than the device.

As described above, according to the present embodiment, the height difference between the peripheral circuit area and the memory cell area can be reduced, so that the design rule of the wiring layer 70 can be made finer without increasing the number of manufacturing steps. it can.

<figref num="1">It is a top view which shows the structure of the semiconductor storage device according to 1st Embodiment of this invention.</figref><figref num="2">It is schematic cross-sectional view which shows the structure of the semiconductor storage device according to 1st Embodiment of this invention.</figref><figref num="3">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 1st Embodiment of this invention.</figref><figref num="4">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 1st Embodiment of this invention.</figref><figref num="5">It is a process sectional view (the 3) which shows the manufacturing method of the semiconductor storage device by 1st Embodiment of this invention.</figref><figref num="6">It is a process sectional view (the 4) which shows the manufacturing method of the semiconductor storage device by 1st Embodiment of this invention.</figref><figref num="7">It is schematic cross-sectional view which shows the structure of the semiconductor storage device by the modification of 1st Embodiment of this invention.</figref><figref num="8">It is a top view which shows the structure of the semiconductor storage device according to 2nd Embodiment of this invention.</figref><figref num="9">It is schematic cross-sectional view which shows the structure of the semiconductor storage device by 2nd Embodiment of this invention.</figref><figref num="10">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 2nd Embodiment of this invention.</figref><figref num="11">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 2nd Embodiment of this invention.</figref><figref num="12">It is a process sectional view (No. 3) which shows the manufacturing method of the semiconductor storage device by 2nd Embodiment of this invention.</figref><figref num="13">It is a process sectional view (the 4) which shows the manufacturing method of the semiconductor storage device by 2nd Embodiment of this invention.</figref><figref num="14">It is a process sectional view which shows the manufacturing method of the semiconductor storage device by the modification of 2nd Embodiment of this invention.</figref><figref num="15">It is schematic cross-sectional view which shows the structure of the semiconductor storage device according to 3rd Embodiment of this invention.</figref><figref num="16">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 3rd Embodiment of this invention.</figref><figref num="17">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 3rd Embodiment of this invention.</figref><figref num="18">It is a process sectional view (No. 3) which shows the manufacturing method of the semiconductor storage device by 3rd Embodiment of this invention.</figref><figref num="19">It is schematic cross-sectional view which shows the structure of the semiconductor storage device according to 4th Embodiment of this invention.</figref><figref num="20">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 4th Embodiment of this invention.</figref><figref num="21">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 4th Embodiment of this invention.</figref><figref num="22">It is schematic cross-sectional view which shows the structure of the semiconductor storage device according to 5th Embodiment of this invention.</figref><figref num="23">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 5th Embodiment of this invention.</figref><figref num="24">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 5th Embodiment of this invention.</figref><figref num="25">It is schematic cross-sectional view which shows the structure of the semiconductor storage device according to 6th Embodiment of this invention.</figref><figref num="26">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 6th Embodiment of this invention.</figref><figref num="27">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 6th Embodiment of this invention.</figref><figref num="28">It is a process sectional view (Part 3) which shows the manufacturing method of the semiconductor storage device by 6th Embodiment of this invention.</figref><figref num="29">It is schematic cross-sectional view which shows the structure of the semiconductor storage device according to 7th Embodiment of this invention.</figref><figref num="30">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 7th Embodiment of this invention.</figref><figref num="31">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 7th Embodiment of this invention.</figref><figref num="32">It is a figure explaining the problem in the manufacturing method of the semiconductor storage device by 1st Embodiment.</figref><figref num="33">It is a top view which shows the structure of the semiconductor storage device according to 8th Embodiment of this invention.</figref><figref num="34">It is schematic cross-sectional view which shows the structure of the semiconductor storage device according to 8th Embodiment of this invention.</figref><figref num="35">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 8th Embodiment of this invention.</figref><figref num="36">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 8th Embodiment of this invention.</figref><figref num="37">It is a process sectional view (Part 3) which shows the manufacturing method of the semiconductor storage device by 8th Embodiment of this invention.</figref><figref num="38">It is a process sectional view (the 4) which shows the manufacturing method of the semiconductor storage device by 8th Embodiment of this invention.</figref><figref num="39">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by the 9th Embodiment of this invention.</figref><figref num="40">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by the 9th Embodiment of this invention.</figref><figref num="41">It is schematic cross-sectional view which shows the structure of the semiconductor storage device by 10th Embodiment of this invention.</figref><figref num="42">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 10th Embodiment of this invention.</figref><figref num="43">It is a process sectional view (Part 2) which shows the manufacturing method of the semiconductor storage device by 10th Embodiment of this invention.</figref><figref num="44">It is the schematic sectional drawing which shows the structure of the semiconductor storage device by 11th Embodiment of this invention.</figref><figref num="45">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 11th Embodiment of this invention.</figref><figref num="46">It is a process sectional view (the 2) which shows the manufacturing method of the semiconductor storage device by 11th Embodiment of this invention.</figref><figref num="47">It is a process sectional view (part 3) which shows the manufacturing method of the semiconductor storage device by 11th Embodiment of this invention.</figref><figref num="48">It is a top view and a partial sectional view which shows the structure of the semiconductor storage device according to the twelfth embodiment of this invention.</figref><figref num="49">It is a figure which shows the peripheral circuit configuration example in the semiconductor storage device according to the twelfth embodiment of this invention.</figref><figref num="50">It is a top view which shows the structure of the semiconductor storage device by 13th Embodiment of this invention.</figref><figref num="51">It is the schematic sectional drawing which shows the structure of the semiconductor storage device by 13th Embodiment of this invention.</figref><figref num="52">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 13th Embodiment of this invention.</figref><figref num="53">It is a process sectional view (Part 2) which shows the manufacturing method of the semiconductor storage device by 13th Embodiment of this invention.</figref><figref num="54">It is a process sectional view (Part 3) which shows the manufacturing method of the semiconductor storage device by 13th Embodiment of this invention.</figref><figref num="55">It is schematic cross-sectional view which shows the structure of the semiconductor storage device by the modification of the 13th Embodiment of this invention.</figref><figref num="56">It is schematic cross-sectional view which shows the structure of the semiconductor storage device by 14th Embodiment of this invention.</figref><figref num="57">It is a process sectional view (the 1) which shows the manufacturing method of the semiconductor storage device by 14th Embodiment of this invention.</figref><figref num="58">It is a process sectional view (Part 2) which shows the manufacturing method of the semiconductor storage device by 14th Embodiment of this invention.</figref><figref num="59">It is schematic cross-sectional view (part 1) which shows the structure of the conventional semiconductor storage device.</figref><figref num="60">It is schematic cross-sectional view (part 2) which shows the structure of the conventional semiconductor storage device.</figref>

10 ... Semiconductor substrate 12 ... Element separation membrane 14 ... element area 15 ... element area 16 ... Gate oxide film 18 ... Silicon nitride film 20 ... Gate electrode (word line) 22 ... Gate electrode 24 ... Source diffusion layer 26 ... Drain diffusion layer 28 ... Low concentration diffusion layer 30 ... sidewall nitride film 32 ... Source diffusion layer 34 ... Drain diffusion layer 36 ... interlayer insulating film 38 ... Through hole 40 ... through hole 42 ... Insulating film 44 ... Contact conductive film 46 ... Capacitor storage electrode 48 ... Capacitor Dielectric Film 50 ... polycrystalline silicon film 52 ... BPSG membrane 53 ... interlayer insulating film 54 ... Capacitor counter electrode 56 ... sidewall oxide film 58 ... Bit wire contact hole 59 ... contact hole 60 ... Through hole 62 ... bit line 64 ... interlayer insulating film 66 ... Beer hall 68 ... Wiring layer 70 ... Wiring layer 72 ... Photoresist 74 ... Photoresist 76 ... sidewall oxide film 78 ... polycrystalline silicon film 80 ... conductive film 82 ... Gate contact 84 ... Silicon oxide film 86 ... Silicon nitride film 88 ... BPSG membrane 90 ... photoresist 92 ... Embedded conductor 94 ... Decoder 96 ... sense amplifier 98 ... Through hole 100 ... through hole 102 ... interlayer insulating film 104 ... polycrystalline silicon film 106 ... polycrystalline silicon film 108 ... sidewall 110 ... polycrystalline silicon film 112 ... Columnar conductor 114 ... Columnar conductor 116 ... void 118 ... Laminated film 120 ... contact hole 122 ... Through hole 124 ... Conductive 126 ... Insulating film 128 ... polycrystalline silicon film 130 ... Garbage 132 ... residue 134 ... residue 136 ... polycrystalline silicon pattern 138 ... polycrystalline silicon sidewall 140 ... polycrystalline silicon film 142 ... Aperture 144 ... Conductive 146 ... Silicon nitride film 148 ... Silicon oxide film 150 ... interlayer insulating film 152 ... interlayer insulating film 154 ... interlayer insulating film 156 ... Silicon nitride film 158 ... polycrystalline silicon film 160 ... polycrystalline silicon sidewall 162 ... Embedded conductor 164 ... sidewall 166 ... Aperture