A technique for forminig an interlayer dielectric material of increased reliability above a structure including closely spaced lines

In general, the present disclosure relates to the formation of integrated circuits, and more particularly to the formation of dielectric intermediate layers between and on circuit elements including narrowly spaced lines such as gate electrodes, polysilicon interconnect lines and the like.

During the manufacture of integrated circuits, a number of circuit elements are formed in a chip region according to a particular circuit layout. In general, multiple process technologies are currently being implemented, and in complex circuits such as microprocessors and storage chips, silicon-based MOS technology is in terms of operating speed and / or power consumption and / or cost effectiveness. Due to its excellent properties, it is currently the most promising approach. When manufacturing complex integrated circuits using MOS technology, millions of transistors (ie N-channel and / or P-channel transistors) are placed on substrates with crystalline semiconductor layers, such as silicon-based layers. It is formed. MOS transistors have so-called PN junctions for both N-channel and P-channel transistors, which are located between the highly concentrated drain and source regions and the drain and source regions. It is formed by an interface with a lightly doped channel region. The electrical conductivity of a channel region (ie, the ability of a conductive channel to carry current) is controlled by a gate electrode that has a linear portion, is formed over the channel region, and is insulated from the channel region by a thin insulating layer. To.

<p> Generally, circuit elements such as MOS transistors, capacitors, and resistors are formed in a common layer (hereinafter, this layer is referred to as a "device layer"). On the other hand, "wiring", that is, the electrical connection of circuit elements according to the circuit design, is formed only to some extent by polysilicon lines in the device layer, so one or more additional parts are added on the device layer. It may be necessary to form a "wiring" layer. Such wiring layers include metal wiring embedded in suitable dielectric materials such as silicon dioxide, silicon nitride, or, for advanced devices, have a dielectric constant of 3. Low-k materials of 0 or less are used. Hereinafter, the metal wiring and the dielectric material around it will be referred to as a "metallation layer". Individual dielectric intermediate layers are formed between the two stacked adjacent metallization layers and between the device layer and the first metallization layer to provide conduction between metal wiring or between circuit elements and metal wiring. , An opening in which metal is embedded is formed through the dielectric intermediate layer. In a typical application, the dielectric intermediate layer that separates the device layer from the first metallization layer is formed primarily from silicon dioxide. This silicon dioxide is deposited on the dielectric etch stop layer by the proven plasma chemical vapor deposition (PECVD) method, which produces a smooth, high density silicon dioxide film with sufficient conformability. , Can be formed at a moderately high deposition rate. Due to the continuous miniaturization of devices, the gate length of MOS transistors has reached the order of about 50 nm or less, and the distance between adjacent circuit elements such as polysilicon lines and gate electrodes has also become shorter. In CPUs, it reaches 200 nm or less, and the space width between densely filled polysilicon lines is about 100 nm or less. However, the gap fill capability of the proven high-speed PECVD method for depositing silicon nitride, which is often used as a material for the etch stop layer, and silicon dioxide, which is often used as an interlayer insulating film, is shown in Fig. 1a ~. As described in more detail with reference to 1b, it has been found that it is not sufficient to reliably form the dielectric intermediate layer. Therefore, there is a demand for an embedding method that provides high embedding ability.</p><p> In FIG. 1a, the semiconductor device 100 has a substrate 101, such as a bulk silicon substrate or a silicon on insulator (SOI) substrate on which the device layer 102 is formed. The device layer 102 has, for example, a silicon-based layer 110, on which a structure 103 including narrowly spaced polysilicon lines 104 is formed. The device layer 102 is a substantially crystalline silicon region or the like, and circuit elements such as field effect transistors and capacitors are formed. The structure 103 may be a region including a plurality of dense polysilicon lines, or the line 104 may be a gate electrode portion of a transistor element. The line 104 is formed on its sidewalk with a corresponding spacer structure 105, which is usually used to form a gate electrode structure. The spacer structure 105 includes a plurality of spacers, such as an offset spacer 105A, one or more "outer" spacers 105C, and a liner 105B that can act as an etch stop layer during the etching process to form the individual spacers 105C. Can be included. The structure 103 usually comprises silicon nitride and also has an etch stop layer 109 formed over the device layer 102 so as to cover the layer 110 and the line structure 103. A silicon dioxide layer 107 is formed on the etch stop layer 109 so as to completely surround the line structure 103.</p><p> A typical conventional process flow for forming the semiconductor device 100 shown in FIG. 1a may include the following processes. After performing a manufacturing process that includes proven lithography, deposition, etching, injection, and other methods to form circuit elements such as transistors, capacitors, and line structures 103, they are usually etched by PECVD. The stop layer 109 is formed. The reason for this is that PECVD of silicon nitride can be carried out at a reasonably low temperature of less than about 600 ° C, which is compatible with the manufacturing processes and materials (eg, metal silicide) previously carried out. In much of the prior art, the etch stop layer 109 can be given a high intrinsic stress level to act as a strain inducer to generate strain in the region 108 below the line 104. When the line 104 is a gate electrode, the region 108 becomes the channel region of the transistor, and the charge carrier mobility can be changed by generating distortion in this region. For example, in the case of the standard crystal orientation of the semiconductor layer 110, that is, when the layer 110 is a silicon-based material having a surface orientation (100) and the channel length is oriented in the &lt;110&gt; direction, the region 108. When compressive strain is applied, the mobility of holes can be increased, and when tensile strain is applied, electron mobility can be increased. Increasing charge carrier mobility directly improves transistor performance with respect to current drive capability and operating speed. To selectively improve transistor performance, the etch stop layer 109 can be deposited based on properly selected process parameters to obtain the desired magnitude and type of intrinsic stress. For example, PECVD can deposit silicon nitride with high tensile or compressive stresses, depending on the deposition parameters. Also, in order to improve the performance of both N-type and P-type transistors, a part of etch stop layer 109 with different types of intrinsic stress is selectively over different transistors using a proven process sequence. Can be formed in.</p><p> As explained above, the uninterrupted miniaturization of feature size also shortens the distance between adjacent circuit elements (such as the distance 111 between narrowly spaced lines 104), about 100 nm, and in some cases the distance 111 is 30 nm. It has reached the limit, and it is even shorter for CPUs with 90nm technology nodes. Therefore, in order to reliably and completely fill the empty space between the lines 104 with high density spacing, the deposition technique for forming a dielectric layer for embedding the line structure 103 separated by the open space requires an appropriate embedding ability. Must be met. Layer 109 can be slightly conformally deposited with a film thickness in the range of about 10-100 nm, according to the PECVD process recipe for silicon nitride. Perhaps different types of intrinsic stresses are applied on individual parts of the structure, requiring advanced deposition and patterning strategies, especially when it is necessary to prevent the formation of void 106a.</p><p> Subsequently, the silicon dioxide layer 107 is deposited. The deposition of silicon dioxide layer 107 is usually carried out by the precursor TEOS (tetraethyl orthosilicate) and oxygen-based PECVD in less critical applications. The reason for this is that PECVD is capable of depositing moderately conformal silicon dioxide, as opposed to thermal TEOS chemical vapor deposition (CVD), but has a lower gap fill than thermal CVD, 600. It has relatively high mechanical stability at temperatures below ° C and high deposition rates, resulting in high manufacturing yields.</p><p> However, as the distance 111 approaches about 30 nm, and in some cases even shorter, the embedding ability of the TEOS and oxygen-based proven PECVD method for depositing silicon dioxide with superior material properties is line 104. It has been found that it is not suitable for completely filling the empty space between them, and void 106b may be formed. Void poses a serious reliability problem during subsequent processing of the semiconductor device 100 (ie, during the formation of contacts that give the forming level of metallization an electrical connection between the individual elements of structure 103). May occur. Also, the silicon dioxide layer 107 has some degree of topography generated by the structure below the device layer 102 (eg, the line structure 103) and is below the circuit elements in the subsequent manufacturing process (layer 110). It should be noted that this can cause problems (such as the photolithography process for forming a contact opening to a portion or line 104). Therefore, in a standard process flow, the silicon dioxide layer 107 needs to be flattened, usually by chemical mechanical polishing (CMP). In CMP, the excess material of the silicon dioxide layer 107 is removed by chemical and mechanical interaction with the slurry and polishing pad in order to finally substantially flatten the surface of the silicon dioxide layer 107. To. The CMP process itself is an extremely complex process and requires advanced process recipes that are highly dependent on the properties of the silicon dioxide layer 107 (density, mechanical stress, moisture content, etc.). For this reason, PECVD TEOS silicon dioxide is often used in the dielectric intermediate layer of silicon-based semiconductor devices, and is also used in devices formed from other semiconductors, thus reliability for PECVD TEOS silicon dioxide. Great effort is required to develop a corresponding process recipe for a high and reproducible CMP process.</p><p> For the above reasons, the dielectric layer 107 formed on the silicon nitride layer 109 can be deposited by different deposition methods with extremely high gap fill capacity to prevent the formation of voids 106b. For this reason, the silicon dioxide layer 107 is formed by a TEOS and ozone based thermal CVD process that forms a silicon dioxide film with excellent gap fill capability. That is, this deposition method also exhibits flow-like behavior and reliably fills the empty space between lines 104. Thermal CVD processes are generally performed at much higher pressures (eg, in the range of 200-760 Torr) than plasma deposition methods in terms of membrane and deposition properties, and are therefore quasi-atmospheric chemical vapor deposition (SACVD). ) Also called. However, for example, the layer 107 formed by SACVD absorbs more water than the PECVD oxide and has a high degassing rate, so that the material properties and process properties of the SACVD oxide can be significantly different from those of the PECVD oxide. In addition, the deposition rate is low, leading to a decrease in throughput. For the above reasons, layer 107 is provided as an intermediate material used as the gap fill material and then added by PECVD to provide the desired deposition rate and high material properties for at least the upper portion of the interlayer insulating material. Silicon dioxide layer 107A can be deposited. For this reason, proven process techniques can be used in subsequent treatments (such as flattening the interlayer insulating material 107A), but SACVD oxides are inferior in material properties, resulting in the final interlayer insulating material, and thus the structure 103. Can adversely affect the overall reliability of.</p><p> FIG. 1b schematically shows a semiconductor device 100 according to an example for another explanation. In this example, the deposition process with the desired high gap fill capacity results in increased non-uniformity during subsequent processing of the device 100. As shown in the figure, the device 100 is in the form of a first portion 109A with a high intrinsic stress level (eg high compressive stress) and a second portion 109B with a high intrinsic stress level (eg tensile stress) with opposite behavior. Can have an etch stop layer of. As described above, line 104 of structure 103 is the gate electrode structure of the transistor, and as described above, the transistor by causing the individual channel regions 108 to generate a properly selected type of distortion. Performance can be improved. During the formation of parts 109A, 109B, individual deposition parameters such as deposition pressure, temperature, precursor flow rate, ionic impact can be adjusted to obtain the desired high intrinsic stress level. For example, according to a proven process recipe, a stressed dielectric material can be deposited highly conformally and then a portion of the dielectric material can be removed to obtain portion 109A. After that, a dielectric material having an intrinsic stress level opposite to that of the portion 109B is deposited, and an unnecessary portion of the dielectric material is removed from above the portion 109A to obtain the configuration shown in FIG. 1b.</p><p> During the manufacturing process described above, individual deposition parameters may be selected to obtain highly conformal deposition behavior in order to substantially prevent the formation of voids between the densely spaced lines 104. .. The interlayer insulating material 107 or a portion thereof can then be deposited based on a quasi-atmospheric deposition process, as described above, to ensure that the space between the lines 104 is filled. However, since the growth rate of this deposition process differs between the material having high compressive stress and the dielectric material to which tensile stress is applied, the thickness of the layer of the interlayer insulating material 107 on the part 109A and the part 109B is different. I know that will change. Therefore, during subsequent treatments (formation of additional interlayer insulating material such as material 107A, flattening of the resulting surface irregularities, etc.), process non-uniformity increases, resulting in, for example, flatness. In view of the decrease in the number of devices, the uniformity of individual devices is reduced.</p><p> For this reason, the high gap fill capacity of the quasi-atmospheric deposition method for silicon dioxide can be very advantageous in preventing structural defects, especially in tightly packed line structures and gate electrodes. However, especially in highly miniaturized semiconductor devices, poor material properties, as well as deposition-specific non-uniformity, can lead to reduced reliability and increased device non-uniformity.</p><p> The present disclosure is directed to a variety of techniques and devices that can avoid, or at least reduce, one or more of the effects of the problems described above.</p>

<p> Hereinafter, an outline of the invention will be described so that the basics of some aspects of the invention can be understood. This overview is not an overview of all of the present invention. It is not intended to identify the main or important elements of the invention or to describe the scope of the invention in detail. Its sole purpose is to briefly present some of the concepts prior to the detailed explanations described below.</p><p> In general, the subjects disclosed herein are increased water absorption, increased degassing, mechanical, while maintaining high gap fill capacity during the formation of interlayer insulating materials, eg, based on quasi-atmospheric deposition methods. It is intended for process technologies and semiconductor devices where adverse effects such as low material properties in terms of reduced stability, deposition-specific properties (low deposition rate, difference in deposition rate depending on the underlying material, etc.) are significantly reduced. .. To this end, by reducing the amount of interlayer insulating material deposited by a highly gap-filling deposition method or by providing a suitable conformal buffer layer before providing an interlayer insulating material with the desired material properties. , The deposition behavior during the process with the desired high gap fill capacity can be homogenized, or both can be done.</p><p> One exemplary method disclosed herein comprises the step of forming an etch stop material on a circuit element of a semiconductor device that has line features with high density spacing. The method is a first interlayer on the circuit element and the etch stop material by a first deposition process designed to substantially fill the space formed between the densely spaced linear features. It has a step of forming an insulating material. Further, a part of the first interlayer insulating material is removed so that the first interlayer insulating material is embedded and remains in at least a part of the space, and then the first interlayer insulating material is overlaid. A second interlayer insulating material is formed on the surface.</p><p> Another exemplary method disclosed herein comprises the step of forming a first etch stop layer with compressive intrinsic stress on top of the first transistor. The method further comprises forming a second etch stop layer with tensile intrinsic stress on top of the second transistor. The first etch stop layer and the first etch stop layer are also subjected to a first deposition method that imparts a substantially conformal deposition behavior to the space between the first transistor and the adjacent transistors of the second transistor. A buffer layer is formed on the etch stop layer of 2. Finally, the method comprises the step of forming at least a portion of the interlayer insulating material on the buffer layer by a second deposition method having a higher gap fill capability than the first deposition method.</p><p> One exemplary semiconductor device disclosed herein has a plurality of tightly packed gate electrode structures formed over a semiconductor region, between two adjacent gate electrode structures. Has a first device area with a defined space in. The semiconductor device has an etch stop material formed on the plurality of gate electrode structures and a first interlayer insulating material containing silicon dioxide, and the first interlayer insulating material is provided in the space. , The gate electrode structure is provided at a height level lower than the height level defined by the etch stop material. Further, the semiconductor device has a second interlayer insulating material containing silicon dioxide, and the second interlayer insulating material is formed on the first interlayer insulating material, and the first interlayer insulating material is formed. Has lower water absorption capacity than.</p>

<figref num="1a">Sectional drawing of a semiconductor device having a tightly packed line structure (such as a gate electrode) at various manufacturing stages when forming an interlayer insulating material based on a deposition method having a high gap filling ability according to a conventional strategy.</figref><figref num="1b">Sectional drawing of a semiconductor device having a tightly packed line structure (such as a gate electrode) at various manufacturing stages when forming an interlayer insulating material based on a deposition method having a high gap filling ability according to a conventional strategy.</figref><figref num="2a">To illustrateal embodiments disclosed herein, an interlayer insulating material is formed using a gap fill capability deposition process, while keeping the overall amount of material deposited by this process at a low level. Sectional view of semiconductor device at various manufacturing stages.</figref><figref num="2b">To illustrateal embodiments disclosed herein, an interlayer insulating material is formed using a gap fill capability deposition process, while keeping the overall amount of material deposited by this process at a low level. Sectional view of semiconductor device at various manufacturing stages.</figref><figref num="2c">To illustrateal embodiments disclosed herein, an interlayer insulating material is formed using a gap fill capability deposition process, while keeping the overall amount of material deposited by this process at a low level. Sectional view of semiconductor device at various manufacturing stages.</figref><figref num="2d">FIG. 2 is a cross-sectional view of the semiconductor device shown in FIGS. 2a-2c, where yet another exemplary embodiment provides high control during the material removal process to reduce the amount of unwanted interlayer insulating material.</figref><figref num="3a">A deposition process with high gap fill capability that improves the uniformity of individual growth rates on dielectric materials with different intrinsic stress levels, based on the buffer layer according to yet another exemplary embodiment disclosed herein. Sectional view of the semiconductor device in the sequence for forming a portion of the interlayer insulating material based on.</figref><figref num="3b">A deposition process with high gap fill capability that improves the uniformity of individual growth rates on dielectric materials with different intrinsic stress levels, based on the buffer layer according to yet another exemplary embodiment disclosed herein. Sectional view of the semiconductor device in the sequence for forming a portion of the interlayer insulating material based on.</figref><figref num="3c">Additional process steps may be performed to reduce the amount of interlayer insulating material deposited by the high gap fill capability deposition method according to yet another exemplary embodiment disclosed herein, shown in FIGS. 3a-3b. Sectional view of semiconductor device.</figref><figref num="3d">Additional process steps may be performed to reduce the amount of interlayer insulating material deposited by the high gap fill capability deposition method according to yet another exemplary embodiment disclosed herein, shown in FIGS. 3a-3b. Sectional view of semiconductor device.</figref>

The present invention will be understood by reading the following description in conjunction with the accompanying drawings. In the accompanying drawings, the same reference numerals refer to the same elements.

The subject matter described herein may take various modifications and alternatives, but a particular embodiment thereof is illustrated in the drawings as an example and is only described in detail herein. However, the detailed description of this particular embodiment is not intended to be limited to the particular embodiments disclosed by the present invention, and conversely, as well as the gist of the present invention as defined by the appended claims. It should be noted that all variants, equivalents and alternatives included in the scope are included.

Various exemplary embodiments of the invention are described below. For the sake of brevity, not all features of the actual implementation are described herein. Of course, in the development of actual embodiments, many implementation-specific decisions are required to achieve specific development objectives, such as adapting to system and business constraints. It is understood that it depends on the implementation. Moreover, it should be understood that this type of development work, which is complex and time consuming, is a routine work for those skilled in the art who will benefit from the present disclosure.

Next, the subject will be described with reference to the accompanying drawings. Various structures, systems and devices are schematically shown in the drawings so as not to obscure the present disclosure by explaining the details known to those skilled in the art for illustration purposes only. However, the accompanying drawings are attached to describe and illustrate exemplary examples of the present disclosure. The terms used herein should be understood and construed as being used interchangeably as they are understood by those skilled in the art. When a phrase is used consistently herein, the phrase has a special definition, that is, it is commonly and commonly used and does not have a definition different from what is understood by those skilled in the art. If a phrase has a special meaning, that is, is used in a meaning different from those understood by those skilled in the art, such a special definition shall be explicitly stated herein and the special definition shall be expressed directly and directly. Show clearly.

The subjects disclosed herein address the problem of reduced reliability of interlayer insulating films that can occur due to low material properties and / or deposition-specific non-uniformity. In the above subject matter, deposition methods with high gap fill capacity are used to form interlayer insulating materials, at least in the space of densely packed circuit elements, while deposition-specific properties and / or other achievements. The adverse effects that may be associated with lower material properties than some dielectric materials (such as silicon dioxide formed under the PECVD method based on TEOS as described above) are reduced. In some embodiments, a gap-filling deposition method is used to effectively reduce the individual aspect ratios of the space formed between narrowly spaced line structures, while extra material in other device areas. The behavior of the interlayer insulating material can be improved by substantially not providing the above, thereby reducing the overall amount of the interlayer insulating material having undesired material properties. Therefore, a major portion of the interlayer insulating material is provided with excellent material properties obtained by individual deposition methods (eg PECVD), and thus due to the earlier reduction in aspect ratio during the individual deposition process. It is possible to prevent the formation of voids or at least substantially reduce the probability of their formation.

In some exemplary embodiments, removal of excess material from the poorly characterized interlayer insulating material can be performed on the basis of an etching process. In doing so, the selectivity to other process materials (eg, the underlying etch stop layer) is advantageous in order to adjust the size of the "leveling" of the space by controlling the individual etching times. Can be used. In another exemplary embodiment, the removal of excess material can be performed on the basis of an etching process, which is performed, for example, on and / or between layers of underlying material to be removed in a subsequent etching process. It can be controlled by forming an appropriate etching index material or etching stop material in the insulating material, and the process uniformity can be improved by reducing the variation between the substrates of the corresponding etching process.

Another exemplary aspect of the subject matter disclosed herein addresses reliability issues caused by differences in deposition rates on underlayer dielectrics with different intrinsic stress levels by providing appropriate buffer layers. Is what you do. This buffer layer can significantly reduce the influence of the difference in stress level on the deposition of the interlayer insulating material by the deposition process having a high gap filling ability to be carried out later. In this case, this buffer layer is thinner than the interlayer insulating material formed later, but is formed with materials with different stress levels, and is optional to effectively average the deposition rates over various device regions. Can be provided in the form of suitable materials. In some exemplary embodiments, the interlayer insulating material deposited in the buffer layer is later, as described above, in order to reduce the amount of material with low material properties in the interlayer insulating material to the desired low level. Can be removed to some extent from. On the other hand, the buffer layer can improve the uniformity of the process when depositing the interlayer insulating material and when removing the portion thereof later. In some exemplary embodiments, the buffer layer is provided in the form of any suitable material that decouplings individual growth rates from the intrinsic stress level of the underlying material. Alternatively, the buffer layer improves the stability of the device in terms of "passivation" of the interlayer insulating material deposited on it, for example during later processing, thereby increasing the overall reliability of the device. It can be improved or both can be done.

It should be noted that the deposition process with high gap fill capacity is understood as a CVD-based process. In this process, the sedimentary environment is formed as a thermally active environment based on a suitable precursor material (precursor, eg TEOS), the corresponding pressure in the sedimentary environment is 250 Torr or higher, and the quasi-normal pressure deposition process (SACVD). ) May also be called. In other cases, the deposition process with high gap fill capability may be understood as a CVD-based process, where the deposition environment is formed on the basis of moderately high ambient plasma, for example above about 20 Torr, and is high. Sometimes referred to as a density PECVD process.

FIG. 2a schematically illustrates a cross-sectional view of a semiconductor 200 capable of having a substrate 201, wherein the substrate 201 is any suitable carrier for forming circuit elements on it, which is required in advanced semiconductor devices. Materials etc. For example, substrate 201 is a semiconductor substrate, the upper portion of which may define a device layer 210 containing a crystalline semiconductor region, perhaps with individual isolation structures (eg, shallow trench isolation, etc.). In another case, the substrate 201 is a carrier material on which an insulating layer (not shown) is formed, on which the device layer 210 is provided, for example, in the form of a crystalline semiconductor material. May be good. In this case, the substrate 201, together with the device layer 210, can be regarded as an SOI structure. It should be noted that the combination of substrate 201 and device layer 210 may have a bulk configuration in some device regions or an SOI configuration in another region, depending on the device requirements. In the exemplary embodiment shown, the semiconductor device 200 has a first device region 220 and a second device region 230, the first device region 220 and the second device region 230 being at least. The minimum spacing between adjacent structural features provided in these may vary. In one exemplary embodiment, the first device region 220 has a line structure 203, which may include a plurality of line features 204 such as polysilicon lines, gate electrode structures, and the like. For example, the line structure 203 may have substantially the same configuration as described above with reference to the line structures 103 shown in FIGS. 1a-1b. Thus, the line 204 may be a gate electrode that can be formed on the corresponding gate insulating layer 208A that separates the electrode 204 from the individual channel regions 208. Also, depending on the process strategy, individual spacer structures 205 may be formed next to line 204 at the manufacturing stage shown in the figure.

It should be noted that a suitable dopant profile may be previously formed in the device layer 210 in order to properly "pattern" the conductivity in the device layer 210. For example, as is known in the art, a properly selected dopant profile can define individual drain regions and source regions (not shown). On the other hand, the second device region 230 may be a region having a low surface uneven shape, for example, when the separation structure 231 is formed in the device layer 210. Further, the semiconductor device 200 also has an etch stop layer 209, which is optionally used to pattern the interlayer insulating material formed on the first device region 220 and the second device region 230. It may be a suitable material layer of. For example, as described above, the etch stop layer 209 may be provided in the form of a nitrogen-containing material such as silicon nitride, nitrogen-containing silicon carbide, or the layer 209 may be provided in the form of silicon carbide or the like. Good. In some exemplary embodiments, the etch stop layer 209 includes a type of circuit element (as described in more detail below with reference to FIGS. 3a-3d, or as described with reference to FIG. 1b). Different high intrinsic stress levels can be applied depending on (for example, P-channel transistor or N-channel transistor). The device 200 is also formed on top of the first device area 220 and the second device area 230 so that voids are not substantially formed in the space 211 between adjacent line features 204. It also has 1 interlayer insulating material 207. As explained above, the horizontal size of space 211 in the horizontal direction of FIG. 2a is on the order of 100 nm, so structure 203 is "closely spaced" or "densely spaced" as described above. Sometimes referred to as a "densely packed" line structure.

The semiconductor device 200 shown in FIG. 2a can be formed based on a process or technique similar to that described above with reference to device 100. That is, a substrate 201 having device layer 210 is provided, which is appropriately patterned to define a first device region 220 and a second device region 230, for example by forming a separation structure 231 and then individually. Circuit elements (such as line structure 203) can be formed based on proven process techniques. To this end, a line 204 is formed with the insulating layer 208A based on proven advanced lithography, deposition, oxidation, etching, and flattening methods, where line 204 is a gate electrode structure. After that, a suitable dopant profile (not shown) for obtaining individual transistor structures is defined. A metal silicid region (not shown) is then formed as needed, followed by deposition of the etch stop layer 209 by a proven deposition method, which is desired, for example, with respect to etching selectivity, intrinsic stress level, etc. Material properties are given.

As described above, multiple deposition and etching processes are involved in the formation of the etch stop layer 209 when different devices of different sizes or types are subjected to intrinsic stresses within the first device region 220. May be implemented. The first interlayer insulating material 207 can be deposited based on suitable process techniques with high gap fill capability to substantially prevent the formation of structural defects (such as voids) in space 211. .. The aspect ratio of the space 211 can be determined by the configuration of the line 204 including the spacer structure 205 and the characteristics of the etch stop layer 209. In one exemplary embodiment, layer 207 can be deposited by a TEOS-based SACVD process to form layer 207 as a silicon dioxide-based material. This deposition process provides a highly non-conformal deposition behavior, which preferably fills the remaining space 211. The film thickness of layer 207 may vary in the first device region 220 such that the film thickness T1 corresponding to space 211 is thicker than the film thickness T2 of the substantially horizontal portion of line 204. Further, the film thickness T3 in the second device region 230 can be a value equivalent to the film thickness T2 due to the substantially flow-like deposition behavior of the SACVD process, unlike the film thickness T1.

As described above, in some exemplary embodiments, the amount of material in layer 207 can be significantly reduced over traditional strategies, effectively without over-delivering space 211. The deposition of layer 207 can be controlled to ensure that is filled. For example, layer 207 can be deposited to obtain a film thickness indicated by T2 or T3, for example, with a film thickness of about 100-300 nm, depending on the device requirements.

FIG. 2b schematically shows a semiconductor device 200 at a further manufacturing stage. As shown, the device 200 is exposed to an etching environment 240 designed to selectively remove the material of layer 207 with respect to the underlying material (such as etch stop layer 209). In some exemplary embodiments, the etching environment 240 may be formed based on a plasma-based atmosphere containing etching chemicals that show extremely high selectivity for the etch stop layer 209. For example, the interlayer insulating material 207 is provided in the form of a silicon dioxide-based material, and the etch stop layer 209 is a silicon nitride material, a nitrogen-containing silicon carbide, for which highly selective etching recipes are well established in the industry. Material or silicon carbide material, etc. Thus, in some exemplary embodiments, the etching process 240 is performed as a substantially anisotropic process, allowing the material to be continuously removed from layer 207 in a substantially vertical direction. In that case, in the embodiment shown in FIG. 2b, the etching process can be continued until the horizontal material portion is substantially removed. That is, the etching front (etch) Because the front) is oriented substantially vertically, the thickness T1 is greater than the thickness values T2 and T3, so that the first layer 207 in space 211 is not completely stripped of material. The portion of the layer having the film thicknesses T2 and T3 of the device region and the second device region can be substantially removed. This leaves an individual remaining material portion 207R in space 211, which effectively reduces the effective aspect ratio as seen from the subsequent deposition process and provides later interlayer insulation with the desired material properties. The constraints of the deposition process for forming the material are relaxed. Due to the high etching selectivity, the actual height level 211H in the individual spaces 211 is processed in the etching process 240 without substantially adversely affecting the components in the structure 203, or the second device area 230. It can be adjusted according to the time. In this way, the amount of remaining material 207R can be reduced to a desirable value that is compatible with the gap fill capacity of the subsequent deposition process, while reducing the remaining material adversely affects material properties such as water absorption. Can be significantly reduced. As explained above, the water absorption capacity of SACVD-deposited silicon dioxide is much higher than that of PECVD-deposited silicon dioxide.

FIG. 2c schematically shows a semiconductor device 200 at a further manufacturing stage. In this figure, a second interlayer insulating material 207A is formed on the first device region 220 and the second device region 230, and the interlayer insulating material 207A has, for example, low degassing property during the subsequent CMP process. Has high material properties such as high resistance to water absorption and improved mechanical strength. Layer 207A is formed on the basis of a PECVD process using TEOS and ozone, eg, as described above, with high deposition due to the low aspect ratio of the rest of the material 207R, as described above. Uniformity is obtained. Therefore, the overall amount of material in layer 207 (ie, the remaining portion 207R) is significantly reduced compared to traditional strategies, which improves the overall reliability of the intermediate layer structure of device 200 and at the same time. , The uniformity of the process during the processing of the device 200 to be performed thereafter is improved. In the embodiment of the figure, depending on the previous surface shape, the remaining portion 207R of the material may be substantially absent in the second device region 230.

Subsequent processing can then be continued by, for example, flattening the surface irregularities of material 207A, based on, for example, CMP, where proven process techniques can be used, as described above. Individual contact openings are then formed based on photolithography and etching methods, in which the etch stop layer 209 serves as an efficient etch stop for forming contact openings in layer 207A and the rest of the 207R. Can be used. Then, depending on the device requirements, openings may be formed in the etch stop layer 209 and individual contact openings may extend into the contact areas of the device layer 210 and line 204.

FIG. 2d schematically illustrates a semiconductor device 200 according to another exemplary embodiment. In this figure, the process uniformity during the etching process 240 can be improved by providing the appropriate etching index material 241 in the appropriate position. For example, in one exemplary embodiment, an etching index material 241 is provided in the surface region of the etch stop layer 209, which when released during the etching process 240 produces a significant endpoint detection signal1 It may contain one or more suitable atomic species. As is known, individual optical measurement techniques called endpoint detection can be used during the plasma-based etching process. In this technique, an absorption spectrum or an emission spectrum can be obtained from a gaseous environment to identify individual wavelengths or wavelength ranges that indicate the presence or absence of a particular species and its amount. Therefore, by placing the appropriate species to provide a well-detectable endpoint signal, the exposure of the individual etch stop layers 209 can be detected with extremely high reliability, which allows the substrate during the etching process 240. The variation between them is reduced. In other cases, the indicator material 241 may be provided in layer 207, for example, by introducing a precursor material (precursor) of the indicator species 241 into the sedimentary atmosphere at the appropriate stage of the deposition process. This allows the progress of the etching process 240 to be monitored based on the presence or absence of individual species 241 in the etching environment. In general, the deposition process is more uniform than the etching process, so providing chemical species 241 within the interlayer insulating material 207 can improve the overall process uniformity. In yet another exemplary embodiment, indicator material 241 may be introduced into material 207 by ion implantation. In this case, any suitable species can be used and any suitable penetration depth can be selected based on the individual injection parameters for the known film thickness of layer 207. For this reason, again, in general, the process variation of individual injection processes is etched.

Yet another exemplary embodiment will be described with reference to FIGS. 3a-3d. In this embodiment, in addition to or instead of the above, interlayer insulation is performed by improving the uniformity of the process during deposition of the interlayer insulating material, based on a deposition process having a high gap fill capability such as SACVD. The reliability of the material can be improved.

FIG. 3a schematically shows a cross-sectional view of a semiconductor device 300 having a substrate 301 and a device layer 310 in the form of a substantially crystalline semiconductor layer (eg, a silicon-based layer). The device 300 may have, for example, a first circuit element 320 in the form of a field effect transistor and a second circuit element 350 in the form of a field effect transistor having a configuration different from, for example, the circuit element 320. In one exemplary embodiment, circuit elements 320,350 are reverse conduction transistors, which differ within the individual channel regions 308 to improve their transistor performance, as described above. Kind of distortion is needed. In this example, circuit elements 320,350 may have gate electrodes 304 formed on the individual gate insulating layers 308A. Further, the spacer structure 305 required in this manufacturing stage is provided, and a specific conduction type drain region and a source region 321 are provided in the circuit element 320, while the reverse conduction type drain region is provided in the circuit element 350. And the source area 351 can be provided. Further, a first etch stop layer 309A is formed on the circuit element 320, which provides the desired strain in the channel region 308 in order to increase the charge mobility in the channel region 308. It may have a suitable high intrinsic stress to generate. Similarly, on top of the second circuit element 350, a second etch with a high intrinsic stress of the opposite kind to layer 309A to generate the desired kind of distortion that improves the transistor performance of the circuit element 350. Stop layer 309B can be formed.

Further, the device 300 may also have a buffer layer 360 formed on (in some exemplary embodiments) the first etch stop layer 309A and the second etch stop layer 309B. The material properties of the buffer layer 360 and its film thickness can be selected to significantly reduce the effect of the intrinsic stress levels of the underlying layers 309A, 309B on the subsequently deposited material. For example, buffer layer 360 can be deposited with significantly lower intrinsic stress levels than layers 309A, 309B. Thus, then implementation, high deposition process of gap-filling ability is provided a deposition surface suitable for scan, the deposition rate on the first circuit element 320 of the second circuit element 350 becomes very uniform .. In one exemplary embodiment, the buffer layer 360 can be provided as a silicon dioxide layer with high mechanical strength (eg, in the form of PECVD silicon dioxide). In doing so, the film thickness of layer 360 provides conformal deposition behavior without increasing the probability of deposition defects (such as voids) between the first and second circuit elements 320,350. Is selected to be. In another exemplary embodiment, the buffer layer 360 compensates for the difference in stress levels while not unduely affecting the stress transfer mechanism provided by the high stress application layers 309A, 309B. It may be provided in the form of a low nitrogen-containing material or a silicon carbide material. In another case, if the influence of the buffer layer 360 on one of the layers 309A and 309B having the opposite intrinsic stress is acceptable, the buffer layer 360 may be subjected to a high intrinsic stress, in this case. The processing conditions of the subsequent deposition process (SACVD process, etc.) can be substantially unified.

FIG. 3b schematically shows a semiconductor device 300 in a further manufacturing stage. In this figure, at least a portion of the interlayer insulating material 307 is formed on the buffer layer 360 to ensure that individual spaces are filled on the buffer layer 360 based on a suitable deposition method (such as SACVD) as described above. Since the buffer layer 360 has a very uniform deposition rate on the circuit elements 320,350, the interlayer insulating material 307 can be deposited at any suitable film thickness, depending on the device requirements. In some cases, the buffer layer 360 can provide a valid "passivation" of the underlying circuit elements, for example with respect to moisture absorption. In another exemplary embodiment, the interlayer insulating material 307 fills the space reliably and, as described above, has a concavo-convex shape due to later deposition of the interlayer insulating material (such as PECVD silicon dioxide). Can be deposited with a film thickness designed to provide a low surface.

FIG. 3c schematically shows a semiconductor device 300 according to yet another exemplary embodiment. In this figure, the interlayer insulating material is subjected to etching process 340 in order to reduce the amount of material in layer 307 while improving the uniformity of the subsequent process during deposition of the interlayer insulating material with the desired material properties. 307 can be partially removed. As a result, as explained above, the aspect ratio of the individual spaces is sufficiently reduced, while the individual growth rates during deposition of material 307 are substantial, regardless of the stress level of the underlying etch stop layer. The buffer layer 360 improves the uniformity within the substrate during the etching process 340, because it is exactly equal to, or at least similar to. In addition, as described above, in some cases, a suitable indicator material for buffer layer 360 to provide a well-detectable endpoint detection signal to allow efficient control of the etching process 340. May be incorporated. In this way, the exposure of the etch stop layers 309A and 309B can be substantially prevented, whereby the strain-inducing action of the etch stop layers 309A and 309B is not adversely affected.

FIG. 3d schematically shows a semiconductor device 300 according to yet another exemplary embodiment. In this figure, some material in layer 307 can be removed based on the chemical mechanical polishing process 342. At that time, the buffer layer 360 can function as a CMP stop layer for confining the remaining material portion 307R of the layer 307 and substantially preventing overexposure of the individual etch stop layers 309A, 309B. In some exemplary embodiments, the etching process 340 and the polishing process 342 may be combined. In this case, for example, in the first step, the polishing process 342 is carried out to obtain a very flat surface, which is given a high degree of uniformity in order to leave the remaining portion 307R at the desired height level. Etching process 340 with can be carried out. In other cases, the etching process 340 may be performed first, followed by a polishing process 342 to obtain a very flat surface shape, which may be performed by an additional interlayer insulating material (eg, PECVD process) performed thereafter. The uniformity of the process of deposition of silicon dioxide) can be improved.

Thus, the subject matter disclosed herein is appropriate to reduce the amount of excess material or improve deposition uniformity on dielectric materials with different intrinsic stress levels, based on the etching process. By providing a good buffer layer and improving the process uniformity of the subsequent process, or by doing both, the adverse effects of unwanted material or process properties during the deposition of the components of the interlayer insulating material are reduced. Therefore, a method and a semiconductor device having a highly reliable interlayer insulating material are provided. Therefore, while the gap fill capacity of advanced SACVD processes is utilized in the formation of highly homogeneous interlayer insulating materials, the individual material properties (water absorption capacity, which is a general material property of TEOS silicon dioxide deposited by SACVD). The effects of rising, increased degassing, reduced mechanical stability, etc.) can be reduced more efficiently than traditional strategies. Therefore, on a low amount of SACVD material, an interlayer insulating material having good properties such as low water absorption, which is common in silicon dioxide by PECVD TEOS, can be formed.

The particular embodiments described above are merely examples, and the invention may be modified and practiced by alternative methods that are self-evident to those skilled in the art who will benefit from the teachings of the present disclosure. For example, the above process steps may be executed in a different order from the described order. Moreover, the configuration or design details described herein are not limited by anything other than the appended claims. Therefore, it is possible to modify or modify the specific embodiments described above, and it is clear that all such modifications are intended to be included in the scope and gist of the present invention. Therefore, the subject of the claim for protection here is as described in the appended claims.