Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a high-frequency power amplifier module, a semiconductor device in which the high-frequency power amplifier module is mounted on a mounting substrate (motherboard), and a technique effective in applying the manufacturing technique. ..

Japanese Unexamined Patent Publication No. 2005-217348 (Patent Document 1) is a connecting member for laminating a first circuit board and a second circuit board on which other electronic components are three-dimensionally mounted, and has a recessed portion and a frame portion. However, electronic components are mounted in the recessed portion, and lead-out wiring from other electronic components is provided, and a land portion for connecting the first circuit board and the second circuit board is formed on the upper and lower surfaces of the frame portion. A circuit module having a structure three-dimensionally connected via a relay board is disclosed.

Japanese Patent Application Laid-Open No. 6-13541 (Patent Document 2) describes a solder ball in which upper and lower chip carriers are arranged around a substrate and mounted on the upper and lower sides of the substrate in a stackable three-dimensional multi-chip module. The structure for connecting to each other is disclosed, and the structure for sealing the device by using the lid of the lower chip is disclosed. The height of the lid also discloses an interconnect structure of hourglass-shaped solder joints that act as natural standoff protrusions between carrier levels to maximize the endurance life of the joints.

Japanese Unexamined Patent Publication No. 2004-172176 (Patent Document 3) provides insulation with an insulating layer that covers a plurality of components arranged on a substrate, and a grounding electrode provided on the substrate while being exposed from the insulating layer. A circuit module is disclosed that includes a shield layer formed on the outside of the layer and connected to a grounding electrode, and the substrate and the end faces of the shield layer are located on the same plane.

Japanese Unexamined Patent Publication No. 2006-286915 (Patent Document 4) describes a circuit board provided with a wiring pattern and a ground layer, an electronic component group mounted on the mounting surface of the circuit board, and an insulation that seals the electronic component group. A circuit module including a conductive resin layer and a conductive resin layer formed on the surface of the insulating resin layer and composed of flaky metal is disclosed.

Japanese Unexamined Patent Publication No. 2005-109306 (Patent Document 5) describes an epoxy resin containing a circuit board having a ground pattern, a mounting component composed of an electronic component mounted on the upper surface of the circuit board, and an inorganic filler for sealing the mounted component. Discloses an electronic component package composed of an encapsulant composed of an encapsulant and an electromagnetic wave shield layer (electroless copper plating layer, electrolytic copper plating layer and coating layer) formed on the surface of the encapsulant and grounded to a ground pattern. ..

According to Japanese Patent Application Laid-Open No. 2005-333047 (Patent Document 6), a plurality of component-mounted units formed on a substrate are molded with an insulating resin and cured, and then grooves having a depth in the middle of the substrate are processed in a grid pattern. Further, after forming the surface layer of plating, a method of manufacturing a module with a built-in circuit component is disclosed, in which the remaining portion of the thickness of the substrate is removed to form a single module.

<p><patcit num="1"><text>Japanese Patent Application Laid-Open No. 2005-217348</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 6-13541</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2004-172176</text></patcit><patcit num="4"><text>Japanese Unexamined Patent Publication No. 2006-286915</text></patcit><patcit num="5"><text>Japanese Patent Application Laid-Open No. 2005-109306</text></patcit><patcit num="6"><text>Japanese Patent Application Laid-Open No. 2005-333047</text></patcit></p>

<p> Currently, the components mounted on the mounting board of mobile communication devices such as mobile phones are mounted in separate areas for each functional block such as a high-frequency module, a front-end module, a transmission / reception communication module, and a power supply module. , Metal electromagnetic shields are provided as needed.</p><p> The present inventors have integrated these functions into one for each required function, and then integrated two or more modules that were mounted side by side on a plane into one module. We are studying a technology that enables high-density mounting to achieve even smaller size than before.</p><p> An object of the present invention is to provide a technique capable of miniaturizing an integrated module in which a plurality of modules are mounted at high density.</p><p> The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.</p>

<p> A brief description of typical inventions disclosed in the present application is as follows.</p><p> (1) The semiconductor device according to the present invention is A first circuit board that uses a part of the wiring layer for the inner layer as ground wiring, A plurality of first mounting components mounted on the first component mounting surface of the first circuit board, A second circuit board laminated on the first component mounting surface of the first circuit board, and A plurality of second mounting components mounted on the second component mounting surface of the second circuit board, A plurality of connecting members that mechanically and electrically connect the first circuit board and the second circuit board, A first resin that collectively seals the first circuit board, the second circuit board, the plurality of first mounting components, and the plurality of second mounting components. Have.</p><p> (2) The method for manufacturing a semiconductor device according to the present invention is as follows. (a) A process of preparing a first substrate base in which a plurality of first circuit boards in which a part of the wiring layer for the inner layer is used as ground wiring are partitioned. (b) A process of mounting a plurality of first mounting components on the first component mounting surface of the first circuit board. (c) A step of preparing a second substrate base body in which a plurality of second circuit boards having the same planar outer shape as the first circuit board are partitioned. (d) A process of mounting a plurality of second mounting components on the second component mounting surface of the second circuit board. (e) After the step (b) and after the step (d), a plurality of connections are made so that the second circuit board is laminated on the first component mounting surface of the first circuit board. A step of mechanically and electrically connecting the first substrate base and the second substrate base via a member. (f) After the step (e), the first substrate base, the second substrate base, the plurality of first mounting parts, and the plurality of second mounting parts are collectively sealed with the first resin. The process of stopping, (g) The first resin, the first substrate base, and the second substrate base are diced along the outer shapes of the first circuit board and the second circuit board, and the first substrate is formed. A process of forming a groove in which the ground wiring is exposed on the side surface by dicing only the base body halfway in the thickness direction. (h) A step of covering the side wall of the groove and the first resin and forming a metal shield member so as to be in contact with the ground wiring. (i) After the step (h), a step of dicing the remaining first substrate base material along the groove and disassembling it into individual semiconductor devices. including.</p>

<p> Among the inventions disclosed in the present application, the effects obtained by typical ones will be briefly described as follows.</p><p> An integrated module in which multiple modules are mounted at high density can be miniaturized.</p>

<figref num="1">It is explanatory drawing which shows an example of the system of the digital mobile phone which has the semiconductor device which is one Embodiment of this invention.</figref><figref num="2">It is a circuit diagram which shows an example of the circuit of the power amplifier used for the digital mobile phone which has the semiconductor device which is one Embodiment of this invention.</figref><figref num="3">FIG. 5 is a cross-sectional view of a main part of a semiconductor chip in which an amplification stage of a power amplifier included in a semiconductor device according to an embodiment of the present invention is composed of an n-channel LD MOSFET.</figref><figref num="4">It is sectional drawing which shows an example of the primary mounting of the high frequency module in the digital mobile phone which has the semiconductor device which is one Embodiment of this invention.</figref><figref num="5">It is a top view of the insulator plate for demonstrating the module substrate of the multi-layer wiring structure formed by laminating a plurality of insulator plates in the semiconductor device which is one Embodiment of this invention and integrally forming.</figref><figref num="6">It is a top view of the insulator plate for demonstrating the module substrate of the multi-layer wiring structure formed by laminating a plurality of insulator plates in the semiconductor device which is one Embodiment of this invention and integrally forming.</figref><figref num="7">It is a top view of the insulator plate for demonstrating the module substrate of the multi-layer wiring structure formed by laminating a plurality of insulator plates in the semiconductor device which is one Embodiment of this invention and integrally forming.</figref><figref num="8">It is a top view of the insulator plate for demonstrating the module substrate of the multi-layer wiring structure formed by laminating a plurality of insulator plates in the semiconductor device which is one Embodiment of this invention and integrally forming.</figref><figref num="9">It is a top view explaining the positional relationship between the module substrate and the connecting member connecting the upper and lower module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="10">It is a top view explaining the positional relationship between the module substrate and the connecting member connecting the upper and lower module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="11">It is a top view explaining the positional relationship between the module substrate and the connecting member connecting the upper and lower module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="12">It is explanatory drawing which shows the expansion of the area of a module substrate when the same semiconductor chip and a chip component are mounted on one module substrate as compared with the module substrate in the semiconductor device which is one Embodiment of this invention. ..</figref><figref num="13">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="14">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="15">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="16">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="17">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="18">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="19">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="20">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="21">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="22">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="23">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="24">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="25">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="26">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="27">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="28">It is sectional drawing of the main part explaining the connection member connecting the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="29">It is a top view explaining the connection member which connects the upper and lower layer module substrates in the semiconductor device which is one Embodiment of this invention.</figref><figref num="30">It is a flowchart explaining a part of the manufacturing process of the semiconductor device which is one Embodiment of this invention.</figref><figref num="31">It is sectional drawing of the main part explaining the manufacturing process of the semiconductor device which is one Embodiment of this invention.</figref><figref num="32">It is sectional drawing of the main part in the manufacturing process of the semiconductor device which follows FIG.</figref><figref num="33">It is sectional drawing of the main part in the manufacturing process of the semiconductor device which follows FIG.</figref><figref num="34">FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the semiconductor device following FIG. 33.</figref><figref num="35">FIG. 3 is a cross-sectional view of a main part during the manufacturing process of the semiconductor device following FIG. 34.</figref><figref num="36">FIG. 5 is a cross-sectional view of a main part during the manufacturing process of the semiconductor device following FIG.</figref><figref num="37">It is sectional drawing which shows an example of the primary mounting of the high frequency module in the digital mobile phone which has the semiconductor device which is another Embodiment of this invention.</figref><figref num="38">It is sectional drawing which shows an example of the primary mounting of the high frequency module in the digital mobile phone which has the semiconductor device which is another Embodiment of this invention.</figref><figref num="39">It is sectional drawing which shows an example of the primary mounting of the high frequency module in the digital mobile phone which has the semiconductor device which is another Embodiment of this invention.</figref>

Before explaining the embodiment of the present invention in detail, the meanings of the terms in the following embodiments will be described as follows.

GSM (Global System for Mobile Communication) refers to one or standard of wireless communication methods used in digital mobile phones. GSM has three frequency bands of radio waves to be used. The 900MHz band is called GSM900 or simply GSM, the 1800MHz band is called GSM1800, DCS (Digital Cellular System) 1800 or PCN (Personal Communication Network), and the 1900MHz band is GSM1900. It is called DCS1900 or PCS (Personal Communication Services). The GSM1900 is mainly used in North America. In North America, the GSM850 in the 850MHz band may also be used. The GMSK (Gaussian filtered Minimum Shift Keying) modulation method is a method used for communication of audio signals and shifts the phase of the carrier wave according to the transmission data. Also, EDGE (Enhanced Data GSM) The Environment) modulation method is a method used for data communication in which an amplitude shift is further added to the phase shift of GMSK modulation.

Further, in the following embodiment, among a plurality of surface mount components mounted on one module substrate, a chip in which one or a plurality of active elements are formed on one chip substrate is referred to as a semiconductor chip. A chip in which a passive element such as a capacitor, an inductor, or a register is formed on one chip substrate is called a chip component. Further, a chip in which one passive element is formed on one chip substrate is called a single chip component, and a chip in which a plurality of passive elements are formed on one chip substrate is called an integrated chip component, and the two are distinguished from each other. If it is necessary to do so, describe it as an integrated chip part or a single chip part.

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is the other. It is related to some or all of the modified examples, details, supplementary explanations, etc.

Further, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. Needless to say. In addition, when the constituent elements, etc. are said to be "consisting of A" or "consisting of A" in the examples, etc., other elements are not excluded unless it is clearly stated that they are only those elements. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of a component or the like, the shape is substantially the same unless otherwise specified or when it is considered that it is not apparent in principle. Etc., etc. shall be included. This also applies to the above numerical values and ranges.

In addition, when referring to materials, etc., the specified material is the main material, and is a secondary element, additive, except when it is clearly stated that it is not the case, or when it is not the case in principle or situation. , Additional elements, etc. are not excluded. For example, the silicon member shall contain not only pure silicon but also additive impurities, binary and ternary alloys (for example, SiGe) having silicon as a main element, etc., unless otherwise specified.

Further, in all the drawings for explaining the present embodiment, those having the same function are, in principle, given the same reference numerals, and the repeated description thereof will be omitted.

Further, in the drawings used in the present embodiment, hatching may be partially added to make the drawings easier to see even if they are plan views.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) In the first embodiment, for example, a case where the present invention is applied to a digital mobile phone (mobile communication device) that transmits information using a GSM system network will be described.

FIG. 1 shows an example of a digital mobile phone system according to the present embodiment. In Fig. 1, PM is a power amplifier, ANT is an antenna for transmitting and receiving signal radio waves, 1 is a front-end device, 2 is a modulation method that converts an audio signal into a baseband signal, a received signal into an audio signal, and so on. Baseband circuit that generates switching signal and band switching signal, 3 is a modulation / demodulation circuit that down-converts the received signal and demotes it to generate a baseband signal or modulates the transmission signal, FLT1 and FLT2 It is a filter that removes noise and interfering waves from the received signal. Filter FLT1 is for GSM and filter FLT2 is for DCS.

The front-end device 1 includes impedance matching circuits MN1 and MN2, low-pass filters LPF1 and LPF2, switch circuits 4a and 4b, capacitors C1 and C2, and a demultiplexer 5. Impedance matching circuits MN1 and MN2 are circuits that are connected to the transmission output terminal of the power amplifier PM to perform impedance matching, low-pass filters LPF1 and LPF2 are circuits that attenuate harmonics, and switch circuits 4a and 4b are circuits for switching transmission and reception. , Capacitors C1 and C2 are elements that cut the DC component from the received signal, and demultiplexer 5 is a circuit that demultiplexes the GSM900 signal and the DCS1800 signal. In the digital mobile phone of the present embodiment, the power amplifier PM and the front-end device 1 are assembled into one module MA.

The switching signals CNT1 and CNT2 of the switch circuits 4a and 4b are supplied from the baseband circuit 2. The baseband circuit 2 is composed of a plurality of semiconductor integrated circuits such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory.

FIG. 2 shows an example of the circuit of the power amplifier PM.

For example, the power amplifier PM can use two frequency bands of GSM900 and DCS1800 (dual band method), and can use two communication methods of GMSK modulation method and EDGE modulation method in each frequency band.

This power amplifier PM has a power amplifier circuit A for GSM900, a power amplifier circuit B for DCS1800, and a peripheral circuit 6 for controlling and correcting the amplification operation of the power amplifier circuits A and B. .. The power amplifier circuits A and B have three amplifier stages A1 to A3 and B1 to B3, and three matching circuits AM1 to AM3 and BM1 to BM3, respectively. That is, the input terminals 7a and 7b of the power amplifier PM are electrically connected to the inputs of the first stage amplification stages A1 and B1 via the matching circuits AM1 and BM1 for input, and the first stage amplification stages A1 and The output of B1 is electrically connected to the inputs of the second stage amplification stages A2 and B2 via the interstage matching circuits AM2 and BM2, and the output of the second stage amplification stages A2 and B2 is for interstage. It is electrically connected to the inputs of the final stage amplification stages A3 and B3 via the matching circuits AM3 and BM3, and the outputs of the final stage amplification stages A3 and B3 are electrically connected to the output terminals 8a and 8b. In the first embodiment, the elements constituting such power amplifier circuits A and B are provided in one semiconductor chip IC1.

The peripheral circuit 6 includes a control circuit 6A and a bias circuit 6B or the like that applies a bias voltage to the amplification stages A1 to A3 and B1 to B3. The control circuit 6A is a circuit that generates a desired voltage applied to the power amplifier circuits A and B, and has a power supply control circuit 6A1 and a bias voltage generation circuit 6A2. The power supply control circuit 6A1 is a circuit that generates a first power supply voltage applied to each output of the amplification stages A1 to A3 and B1 to B3. The bias voltage generation circuit 6A2 is a circuit that generates a first control voltage for controlling the bias circuit 6B.

In the first embodiment, when the power supply control circuit 6A1 generates the first power supply voltage based on the output level designation signal supplied from the baseband circuit 2 outside the power amplifier PM, the bias voltage generation circuit 6A2 is the power supply control circuit. The first control voltage is generated based on the first power supply voltage generated by 6A1. The baseband circuit 2 is a circuit that generates an output level designation signal. This output level designation signal is a signal that specifies the output level of the power amplifier circuits A and B, and is generated based on the distance between the mobile phone and the base station, that is, the output level according to the strength of the radio wave. It has become like. In the first embodiment, the elements constituting such a peripheral circuit 6 are also provided in one semiconductor chip IC1.

Further, on the external terminal (pad electrode) formed on the main surface (the surface on which the circuit element is formed) of the semiconductor chip IC1 constituting the power amplifier PM, and on the component mounting surface of the module substrate on which the semiconductor chip IC1 is mounted. The formed substrate-side terminals are connected via a bonding material (for example, bump electrode BE), and the input / output of each amplification stage is transmitted through the connecting material to the transmission lines 9a1 to 9a5, 9b1 on the component mounting surface of the module substrate. It is electrically connected to ~ 9b5 and 9c.

The transmission lines 9a1 and 9b1 connected to the inputs of the first amplification stages A1 and B1 through the bump electrodes BE are electrically connected to the input terminals 10a and 10b via the capacitors Cm1 and Cm2, respectively. The transmission lines 9a2 and 9b2 electrically connected to the outputs of the first amplification stages A1 and B1 through the bump electrode BE are electrically connected to the power supply terminals 11a1 and 11b1 on the high potential side, respectively, and are respectively. It is electrically connected to the ground potential GND via capacitors Cm3 and Cm4 arranged near the power supply terminals 11a1 and 11b1. The transmission lines 9a3 and 9b3 electrically connected to the outputs of the second amplification stages A2 and B2 through the bump electrode BE are electrically connected to the power supply terminals 11a2 and 11b2 on the high potential side, respectively, and are respectively. It is electrically connected to the ground potential GND via capacitors Cm5 and Cm6 arranged near the power supply terminals 11a2 and 11b2. The transmission lines 9a4 and 9b4, which are electrically connected to the outputs of the final amplification stages A3 and B3 through the bump electrode BE, are electrically connected to the power supply terminals 11a3 and 11b3 on the high potential side, respectively, and are respectively. It is electrically connected to the ground potential GND via capacitors Cm7 and Cm8 arranged near the power supply terminals 11a3 and 11b3.

Further, the transmission lines 9a5 and 9b5 electrically connected to the outputs of the final amplification stages A3 and B3 through the bump electrode BE are electrically connected to the output terminals 12a and 12b via the capacitors Cm9 and Cm10, respectively. At the same time, it is electrically connected to the ground potential GND via capacitors Cm11 and Cm12 arranged in the middle of each line. The transmission line 9c, which is electrically connected to the external terminal for control of the peripheral circuit 6 through the bump electrode BE, is electrically connected to the control terminal 13. Further, the transmission lines 9a1 to 9a5 and 9b1 to 9b5 have a function as an inductor for impedance matching. Further, the capacitors Cm1 to Cm12 have a function as a capacitor for impedance matching, and are composed of chip parts.

Next, the structure of a typical element among the various elements constituting the power amplifier PM will be described. Here, an example of the internal configuration of the power amplifier PM in which the amplification stages A1 to A3 and B1 to B3 are composed of n-channel LD MOSFETs (laterally diffused Metal Oxide Semiconductor) will be described with reference to the cross-sectional view of the main part shown in FIG. .. This power amplifier PM is formed on one semiconductor chip IC1. In the first embodiment, the amplification stage is composed of an LD MOSFET, but the present invention is not limited to this, and for example, a hetero-junction bipolar transistor (HBT) may be used.

The substrate 21 on which the power amplifier PM is formed is, for example, p.⁺It is a low-resistive substrate made of type single crystal silicon and having a resistivity of about 1 to 10 mΩ · cm. On the substrate 21, for example, p^-An epitaxial layer 22 made of type single crystal silicon is formed. The resistivity of the epitaxial layer 22 is about 20 mΩ · cm, which is higher than the resistivity of the substrate 21. On the main surface of the epitaxial layer 22, LD MOSFETs for amplification stages A1 to A3 and B1 to B3, inductors for matching circuits AM1 to AM3 and BM1 to BM3, capacitors with high Q (Quality factor) values, and transmission lines are formed. Has been done. The LD MOSFET shown here is a unit MISFET, and in reality, a plurality of these unit MISFETs are connected in parallel to form one amplification stage.

A p-type well 23 is formed on a part of the main surface of the epitaxial layer 22. This p-type well 23 has a function as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LD MOSFET.

On the surface of the p-type well 23, for example, a gate insulating film 24 made of silicon oxide is formed by a thermal oxidation method or the like. The gate electrode 25 of the LD MOSFET is formed on the gate insulating film 24. The gate electrode 25 is, for example, an n-type polycrystalline silicon film and a tungsten silicide (WSi) formed on the film.₂) Consists of a laminated conductor film with a film. The p-type well 23 at the bottom of the gate insulating film 24 is a region where channels of the LD MOSFET are formed. A sidewall 26 made of silicon oxide is formed on the side wall of the gate electrode 25.

The source and drain of the LD MOSFET are formed in the regions of the epitaxial layer 22 that are separated from each other with the channel formation region in between. The drain touches the channel formation region n^-Type offset drain area 27 and this n^-N-type offset drain region 28 formed in contact with the type offset drain region 27 and separated from the channel forming region, and n formed in contact with the n-type offset drain region 28 and further separated from the channel forming region.⁺It consists of a mold drain region 29. These n^-Type offset drain area 27, n type offset drain area 28 and n⁺Of the mold drain regions 29, n closest to the gate electrode 25^-The mold offset drain region 27 has the lowest impurity concentration and is the farthest from the gate electrode 25.⁺The mold drain region 29 has the highest impurity concentration. n^-The mold offset drain region 27 is self-aligned with respect to the gate electrode 25, and the n-type offset drain region 28 is self-aligned with the sidewall 26 of the side wall of the gate electrode 25.

As described above, one of the features of the LD MOSFET shown in the first embodiment is the gate electrodes 25 and n.⁺The offset drain region between the mold drain region 29 and the mold drain region 29 has a double offset structure, and is the closest to the gate electrode 25.^-The impurity concentration in the type offset drain region 27 was relatively low, and the impurity concentration in the n-type offset drain region 28 separated from the gate electrode 25 was relatively high.

This structure allows a depletion layer to spread between the gate electrode 25 and the drain, resulting in n at the gate electrode 25 and its vicinity.^-The feedback capacitance formed between the mold offset drain region 27 and the mold offset drain region 27 becomes smaller. Further, since the impurity concentration in the n-type offset drain region 28 is high, the on-resistance is also small. Since the n-type offset drain region 28 is formed at a position separated from the gate electrode 25, the influence on the feedback capacitance is small. That is, according to the LD MOSFET of the present embodiment, in the conventional LD MOSFET, both the on-resistance and the feedback capacitance, which are in a trade-off relationship with each other, can be reduced, so that the power addition efficiency of the amplifier circuit is improved. be able to.

On the other hand, the source of the LD MOSFET is n in contact with the channel formation region.^-Type source area 30 and this n^-N formed in contact with the mold source region 30 and away from the channel formation region⁺It consists of a type source area 31. N in contact with the channel formation region^-The type source region 30 is n separated from the channel formation region.⁺The impurity concentration is lower and shallower than that of the mold source region 31. Also n^-Below the type source region 30, a p-type halo region 32 is formed to suppress the spread of impurities from the source to the channel formation region and further suppress the short channel effect. n^-The mold source region 30 is self-aligned with respect to the gate electrode 25 and n⁺The mold source region 31 is self-aligned with respect to the sidewall 26 on the side wall of the gate electrode 25.

n⁺The end of the type source region 31 (n)^-At the end (the end opposite to the side tangent to the type source region 30), n⁺A p-type punching layer 33 in contact with the type source region 31 is formed. In the vicinity of the surface of the p-type punching layer 33, p for reducing the resistance of the surface of the p-type punching layer 33.⁺The type semiconductor region 34 is formed. The p-type punched layer 33 is a conductive layer for connecting the source and the substrate 21, and one feature of the LD MOSFET of the first embodiment is that it is embedded in the groove 35 formed in the epitaxial layer 22. The p-type punching layer 33 is formed by a conductive layer made of a type polycrystalline silicon film.

In the conventional LD MOSFET, a punched layer is formed by ion-implanting impurities into the epitaxial layer 22. The p-type punched layer formed by ion implantation has a drawback that the parasitic resistance per unit area is large. However, by embedding a p-type polycrystalline silicon film doped with a high concentration of impurities inside the groove 35, a p-type punched layer 33 having a small parasitic resistance can be formed.

P-type punched layer 33 (p) of the above LD MOSFET⁺Type semiconductor region 34), source (n⁺Type source region 31) and drain (n⁺A plug 39 in a contact hole 38 formed in the silicon nitride film 36 and the silicon oxide film 37 is connected to each upper portion of the mold drain region 29). The plug 39 is composed of a conductive film mainly composed of a tungsten (W) film.

p-type punched layer 33 (p⁺Type semiconductor region 34) and source (n⁺A source electrode 40 is connected to the mold source region 31) via a plug 39, and a drain (n) is connected.⁺A drain electrode 41 is connected to the mold drain region 29) via a plug 39. The source electrode 40 and the drain electrode 41 are composed of a conductive film mainly composed of an aluminum (Al) alloy film.

A wiring 44 is connected to each of the source electrode 40 and the drain electrode 41 via a through hole 43 formed in a silicon oxide film 42 that covers the source electrode 40 and the drain electrode 41. The wiring 44 is composed of a conductive film mainly composed of an Al alloy film. A surface protective film 45 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the upper portion of the wiring 44. Further, on the back surface of the substrate 21, for example, a source back electrode 46 made of a laminated film of a nickel (Ni) film, a titanium (Ti) film, a Ni film and a gold (Au) film is formed.

The semiconductor chip IC1 on which the power amplifier PM is formed is mounted on the module substrate with its main surface facing downward (face down), and is mounted on the external terminals of the semiconductor chip IC1 and the component mounting surface of the module substrate. The formed substrate-side terminals are electrically connected by a bonding material, for example, a bump electrode BE made of solder.

Next, the configuration of the module MA after the primary mounting in which the surface mount components are mounted on the module board will be described. FIG. 4 is a cross-sectional view of a main part showing an example of the primary mounting of the module MA according to the first embodiment. 5 to 8 are plan views of the main parts of each insulator plate for explaining a module substrate having a multi-layer wiring structure formed by laminating and integrating a plurality of insulator plates. Here, the front-end device 1 and the power amplifier PM described above are assembled into one module MA, but it goes without saying that the configuration is not limited to this. For example, the front-end device 1 and the power amplifier PM may be configured as separate high-frequency modules. Further, although the semiconductor chip IC1 having the power amplifier PM having the amplification stage made of LD MOSFET as an example will be described here, a semiconductor chip having the power amplifier having the amplification stage made of HBT may be used.

As shown in FIG. 4, in the module MA, for example, a PCB (Printed Circuit Board) having a multilayer wiring structure in which a plurality of insulator plates are laminated and integrated is used as a module board 51. For example, a substrate side terminal 52 made of a copper (Cu) film and wiring are patterned on the component mounting surface of the module substrate 51, and electrodes 53G and 53S made of, for example, a Cu film are patterned on the back surface. There is.

FIG. 4 shows a semiconductor chip IC1 in which an active element is formed and a single chip component in which one passive element is formed on one chip substrate as surface mount components mounted on the component mounting surface of the module substrate 51. 54 and an integrated chip component 55 in which a plurality of passive elements are formed on one chip substrate are illustrated. The power amplifier PM described above is formed on the semiconductor chip IC1. A plurality of external terminals formed on the main surface of the semiconductor chip IC1 are connected to the corresponding substrate side terminals 52 of the module substrate 51 by a bonding material. Here, the bump electrode BE is used as the bonding material. Further, an underfill resin UF is filled and sealed between the semiconductor chip IC1 and the module substrate 51.

Further, these surface mount components are covered with a highly elastic sealing mold resin 56. The mold resin 56 is, for example, a highly elastic epoxy resin, and the allowable range of its elastic modulus is preferably 2 GPa or more at a temperature of 180 ° C. or more.

The semiconductor chip IC1 is fixed on the module substrate 51 by joining the bump electrode BE formed on the element forming surface to the chip mounting substrate side terminal 52 formed on the component mounting surface of the module substrate 51. ing.

Among the bump electrodes BE formed on the semiconductor chip IC1, those electrically connected to the source electrode 40 are conductive in a plurality of heat radiating vias 58 formed so as to penetrate from the component mounting surface to the back surface of the module substrate 51. It is electrically and thermally bonded to the electrode 53G formed on the back surface of the module substrate 51 through the material. A reference potential (for example, about 0 V at the ground potential GND) is supplied to this electrode 53G. That is, the reference potential supplied to the electrode 53G on the back surface of the module substrate 51 is supplied to the back surface of the semiconductor chip IC 1 through the heat dissipation via 58 and the substrate side terminal 52. On the contrary, the heat generated during the operation of the semiconductor chip IC1 is transmitted from the element forming surface of the semiconductor chip IC1 to the electrode 53G on the back surface of the module substrate 51 through the substrate side terminal 52 and the heat radiation via 58 and is dissipated. .. The electrode 53S near the outer circumference formed on the back surface of the module substrate 51 indicates an electrode for signals.

The single chip component 54 is a surface mount component in which passive elements such as capacitors, inductors, registers, and ferrite beads are formed on one chip substrate. Felide beads have a structure in which an internal electrode for energization is embedded in a ferrite element, and the ferrite acts as a magnetic material to generate high-frequency current components that cause electromagnetic interference (EMI) noise. It is an element that absorbs. The single chip component 54 is mounted on the module board 51 with its back surface facing the component mounting surface of the module board 51, and the connection terminals formed at both ends of the single chip component 54 are mounted on the module board via solder. It is solder-connected to the board-side terminal 52 formed on the component mounting surface of 51. For this solder connection, Pb-free solder containing no Pb, for example, Sn-3 silver (Ag) solder is used. The distance between the back surface of the single chip component 54 and the component mounting surface of the module substrate 51 is, for example, about 10 μm, and the gap is filled with the mold resin 56 for sealing without forming voids.

Although Pb-free solder is used as the solder material used for the solder connection of the single chip component 54, the solder material is not limited to this and can be changed in various ways. For example, Sn containing Pb (hereinafter, Pb) -Sn solder) may be used. However, considering Pb regulations in Europe, Pb-free solder is preferable.

The integrated chip component 55 is a surface mount component in which a plurality of passive elements such as low-pass filters LPF1 and LPF2 are formed on one chip substrate. The integrated chip component 55 is flip-chip connected to the module board 51 with its main surface facing the component mounting surface of the module board 51, and the connection terminal formed on the main surface of the integrated chip component 55 is a bump electrode BE. It is connected to the board-side terminal 52 formed on the component mounting surface of the module board 51 via. An underfill resin UF is filled and sealed between the main surface of the integrated chip component 55 and the component mounting surface of the module substrate 51.

The module substrate 51 is composed of a core material 60 and an insulating material called a prepreg 61 that sandwiches the core material 60 above and below. An inner layer Cu film 62 (second layer wiring Layer 2 and third layer wiring Layer 3) is formed in a pattern above and below the core material 60, and these inner layer Cu films 62 are sandwiched by the prepreg 61. Further, the second layer wiring Layer 2 and the third layer wiring Layer 3 are electrically connected via a conductor film formed on the side wall of the through hole 58a formed in the core material 60.

FIG. 5 shows an example of the wiring pattern (second layer wiring Layer 2) of the inner layer Cu film 62 formed between the core material 60 on the component mounting surface side of the module substrate 51 and the prepreg 61, and FIG. 6 shows. An example of the wiring pattern (third layer wiring Layer 3) of the inner layer Cu film 62 formed between the core material 60 on the back surface side of the module substrate 51 and the prepreg 61 is shown. The thickness of the Cu film 62 for the inner layer is, for example, about 0.02 mm, and the thickness of the prepreg 61 is, for example, about 0.06 mm.

Further, on the outer surface of the prepreg 61 on the component mounting surface side, the above-mentioned substrate side terminal 52 and an outer layer Cu film (first layer wiring Layer 1) such as wiring are closely attached to the prepreg 61 to form a pattern. FIG. 7 shows the wiring pattern (first layer wiring Layer 1) of the Cu film 63 for the outer layer formed on the outer surface of the prepreg 61 on the component mounting surface side of the module substrate 51, and the surface mount components mounted on the component mounting surface, for example. An example of the arrangement of the semiconductor chip IC1 and the chip component 64 (including the above-mentioned single chip component 54 and the integrated chip component 55) is shown. On the outer surface of the prepreg 61 on the back surface side, the Cu film for the outer layer (fourth layer wiring Layer 4) of the electrodes 53G and 53S described above is closely attached to the prepreg 61 to form a pattern.

FIG. 8 shows an example of the wiring pattern (fourth layer wiring Layer 4) of the Cu film 63 for the outer layer formed on the outside of the prepreg 61 on the back surface side of the module substrate 51. The thickness of the Cu film 63 for the outer layer is, for example, about 0.02 mm.

On the surface of the Cu film 63 for the outer layer, for example, a plating film having a laminated structure in which a Ni layer and an Au layer are formed in order from the lower layer by a plating method is formed. Further, the Cu film 63 for the outer layer is covered with a solder resist (not shown) except for the region where the surface mount component such as the semiconductor chip IC1 or the chip component 64 is mounted. The thickness of the solder resist is, for example, about 0.025 to 0.05 mm.

Between the two layers of Cu film 62 located above and below the core material 60 (between the second layer wiring Layer 2 and the third layer wiring Layer 3), or between the inner layer Cu film 62 and the outer layer Cu film 63. Between the first layer wiring Layer 1 and the second layer wiring Layer 2 or between the third layer wiring Layer 3 and the fourth layer wiring Layer 4), heat dissipation with a Cu film embedded through the core material 60 or prepreg 61. It is electrically connected via via 58. The core material 60, the prepreg 61 and the solder resist are made of a resin such as epoxy.

Further, a part of the second layer wiring Layer 2 or the third layer wiring Layer 3 shown in FIG. 4 (the portion shown by the inner layer Cu films 62 and 62A in FIGS. 4 and 5) is formed up to the outer periphery of the core material 60. It is electrically connected to the shield layer SL, which will be described later. More specifically, both ends of the inner layer Cu film 62 of the second layer wiring Layer 2, both ends of the inner layer Cu film 62A of the third layer wiring Layer 3, or both ends thereof are connected to the shield layer SL. .. Both ends of the inner layer Cu films 62 and 62A to be connected to the shield layer SL mentioned above are both ends of the part that can be connected by design. The Cu films 62 and 62A for the inner layer, which are electrically connected to the shield layer SL, are ground wirings and are formed on the outside of the prepreg 61 on the back surface side via the heat radiation via 58 formed on the core material 60 and the prepreg 61. It is electrically connected to the wiring pattern of the Cu film 63 for the outer layer (4th layer wiring Layer 4).

The module substrate 66 is laminated on the module substrate 51 via a conductive connecting member 65. The material and structure of the connecting member 65 will be described later. The module substrate 66 is formed of the same core material as the core material 60 in the module substrate 51, and has a back surface facing the module substrate 51 and a component mounting surface on the opposite side to the back surface. On the component mounting surface and the back surface of the module board 66, a board side terminal 52 in the module board 51 and a board side terminal 67 similar to wiring and the like are formed. One end of the connecting member 65 is connected to the board side terminal 52 on the component mounting surface of the module board 51, and the other end is connected to the board side terminal 67 on the back surface of the module board 66, and the module board is connected via the connecting member 65. The structure is such that the 51 and the module board 66 are electrically connected. That is, various signals are exchanged between the module board 51 and the module board 66 through the connecting member 65, and the power supply potential, the reference potential, and the like are supplied. Further, since the mold resin 56 described above is filled so as to fill the space between the module substrate 51 (semiconductor chip IC1, the single chip component 54 and the integrated chip component 55) and the module substrate 66, it acts on the module substrate 66. The structure is such that the module substrate 66 can be prevented from being warped due to the applied load or stress.

In the first embodiment, as a surface mount component mounted on the component mounting surface of the module substrate 66, an integrated chip component 68 in which a plurality of passive elements are formed on one chip substrate is illustrated. For example, a SAW (Surface Acoustic Wave) filter is formed on each of the integrated chip components 68.

The integrated chip component 68 mounted on the component mounting surface of the module substrate 66 is covered with the same mold resin 56 as the mold resin 56 described above. The mold resin 56 filled between the module substrate 51 and the module substrate 66 and the mold resin 56 covering the component mounting surface (integrated chip component 68) of the module substrate 66 are formed in the same process. It will be described later.

A shield layer SL is formed on a part of the side surface of the module substrate 51, the side surface of the module substrate 66, and the surface (upper surface and side surface) of the mold resin 56.

The shield layer SL is formed by an electroless plating method. The electroless plating method can selectively deposit a plating film on a catalytically active surface without using an external power source. For example, as described in "Plating Textbook Electroplating Study Group, 1986, published by Nikkan Kogyo Shimbun", in the autocatalytic electroless Cu plating method, the Cu precipitation reaction continues due to the oxidation reaction of the reducing agent. Further, by treating with an activating liquid containing Pd, a plating film can be uniformly formed even on a non-conductive material such as a mold resin, even if it is a portion having a complicated shape. Therefore, a uniform shield layer SL can be formed on the surface (upper surface and side surface) of the mold resin 56 that seals the surface mount component mounted on the module MA by the electroless plating method. As a result, a desired shielding effect can be obtained with the minimum required metal material, which is advantageous in reducing the cost of the product.

In the first embodiment, a first film having an electromagnetic wave shielding function formed by electroless plating on the shield layer SL, for example, a Cu film, and a touchproof film formed on the Cu film by the electroless plating method. It is composed of a second film having a function, for example, a laminated film with a Ni film.

Next, the connection positions of the module boards 51 and 66 and the connecting member 65 on a plane will be described with reference to FIGS. 9 to 11. Note that FIG. 9 shows the connection position of the module board 51 and the connecting member 65 on the plane, FIG. 10 shows the connection position of the module board 66 and the connecting member 65 on the plane, and FIG. 11 shows FIGS. 9 and 9. 10 layouts are superimposed, and FIG. 11 shows the integrated chip component 68 mounted on the component mounting surface of the module board 66 with hatching in order to make the layout easier to see. Further, FIG. 12 shows the expansion of the area of the module substrate when the same semiconductor chips and chip components as the module MA are mounted on one module substrate as compared with the module MA of the first embodiment.

As shown in FIG. 9, the connecting member 65 is mounted on the component mounting surface of the module substrate 51 at a position where it does not overlap with the semiconductor chip IC1, the single chip component 54, and the integrated chip component 55. On the other hand, as shown in FIG. 10, since the connecting member 65 is connected to the module board 66 on the back surface, it can be mounted even at a position where it overlaps with the integrated chip component 68 mounted on the component mounting surface of the module board 66 in a plane. It has become. As a result, the areas of the module boards 51 and 66 can be reduced, so that the area of the module MA can also be reduced. Further, as shown in FIG. 12, the integrated chip component 68 mounted on the component mounting surface of the upper module board 66 is also arranged at a position where it overlaps with the lower layer semiconductor chip IC1, the single chip component 54, and the integrated chip component 55 in a plane. it can. As a result, the areas of the module boards 51 and 66 can be further reduced.

Here, in FIG. 12, when all the semiconductor chip IC1, the single chip component 54, and the integrated chip components 55 and 68 are mounted on one module board, the area wider than the module boards 51 and 66 is shown by EA. (Shown by broken line). As described above, in the case of the laminated structure consisting of the module substrates 51 and 66 as in the module MA of the first embodiment, the area of the module MA is significantly reduced as compared with the case where only one module substrate is used. can do. According to the verification by the present inventors, it has been confirmed that the area of the module MA can be reduced by about 58%.

Next, various examples of the structure and material of the connecting member 65 will be described with reference to FIGS. 13 to 29.

First, as shown in FIG. 13, as the connecting member 65, a columnar connecting member 65 formed of a metal such as copper (Cu) will be illustrated. Both ends of such a columnar connecting member 65 are connected to the board-side terminal 52 of the module board 51 and the board-side terminal 67 of the module board 66 by solder 65A, respectively. As the solder 65A, Pb-free solder containing no Pb such as Sn-3 silver (Ag) -0.5Cu solder can be exemplified. The connecting member 65 made of such a columnar metal has a low manufacturing cost of the connecting member 65 itself, and the connection process to the module substrates 51 and 66 (board side terminals 52 and 67) by the solder 65A is also easy. Has advantages.

An example of the following connecting member 65 is a connecting member 65 made of a foamed metal such as copper (Cu) having a porous structure in which a large number of holes 65B are formed as shown in FIG. Similar to the case of the columnar connecting member 65, both ends of the connecting member 65 made of such foamed metal are connected to the substrate side terminal 52 of the module board 51 and the board side terminal 67 of the module board 66 by solder 65A, respectively. Can be done. Such a connecting member 65 made of foamed metal can be easily connected to the module substrates 51 and 66 (board side terminals 52 and 67) by solder 65A, and is molded during the filling process of the mold resin 56. Since the resin 56 infiltrates through the hole 65B of the connecting member 65, it has an advantage that it can be easily filled.

An example of the next connecting member 65 is a spherical connecting member 65 as shown in FIG. The spherical connecting member 65 has a nickel (Ni) film 65D having a film thickness of about 5 μm and a tin (Sn) film 65E having a film thickness of about 5 μm on the surface of a metal core 65C such as spherical copper in order from the metal core 65C side. It has a structure coated with. Similar to the case of the columnar connecting member 65 and the case of the connecting member 65 made of foamed metal, such a spherical connecting member 65 is formed by soldering 65A at both ends of the substrate side terminals 52 of the module substrate 51 and the module substrate 66, respectively. It can be connected to the board side terminal 67. Such a spherical connecting member 65 can be easily connected to the module boards 51 and 66 (board side terminals 52 and 67) by soldering 65A. Further, since the spherical connecting member 65 can obtain high connection strength after being connected to the module substrates 51 and 66 by the solder 65A, mechanical reliability and electrical reliability can be improved.

Further, as shown in FIG. 16, the spherical connecting member 65 may be formed by replacing the metal core 65C with a resin core 65F such as an epoxy resin. In this case, conductivity can be ensured by the nickel film 65D on the surface and the tin film 65E having a film thickness of about 5 μm. Even in the case of the connecting member 65 having such a resin core 65F, the connection process to the module boards 51 and 66 (board side terminals 52 and 67) by the solder 65A is performed as in the case of the connecting member 65 having the metal core 65C. It is easy, and after the connection to the module substrates 51 and 66 with the solder 65A, a high connection strength can be obtained, so that the mechanical reliability and the electrical reliability can be improved.

The following example of the connecting member 65 is a metal pin-shaped connection having a configuration in which it is attached by inserting and fixing it into an insertion hole 70 provided in at least one of the module boards 51 and 66 as shown in FIGS. 17 to 19. It is a member 65. In this case, the substrate-side terminal 52 on the module substrate 51 side, the substrate-side terminal 67 on the module substrate 66 side, or both of them have a structure formed on the side surface and the bottom surface of the insertion hole 70. The pin-shaped connecting member 65 is attached to the module boards 51 and 66 on the side where the insertion hole 70 is not formed by using the same solder 65A as in the case of the columnar connecting member 65 described above. On the other hand, by inserting one end of the pin-shaped connecting member 65 into the insertion hole 70 and then filling the gap with the solder 65A to fix the insertion hole 70, it is possible to form a structure in which electrical continuity is also obtained.

The following example of the connecting member 65 is a metal pin-shaped connection having a configuration in which it is attached by inserting and fixing it into a through hole 71 provided in at least one of the module boards 51 and 66 as shown in FIGS. 20 to 22. It is a member 65. The through hole 71 is formed so as to penetrate the front and back surfaces of the module boards 51 and 66, and the board side terminal 52 on the module board 51 side, the board side terminal 67 on the module board 66 side, or both of them are through holes. It is configured to extend from the side surface of 71 to the back surface of module boards 51 and 66. Further, the diameter of the through hole 71 in the presence of the terminals 52 and 67 on the substrate side is such that a gap is formed after the insertion as long as the pin-shaped connecting member 65 can be inserted and the surface can be contacted. May be good. The pin-shaped connecting member 65 is attached to the module boards 51 and 66 on the side where the through hole 71 is not formed by using the same solder 65A as in the case of the columnar connecting member 65 described above. Under the condition that the connecting member 65 is inserted into the through hole 71, the two openings of the through hole 71 in the module substrates 51 and 66 are closed with the above-mentioned solder 65A or the conductive adhesive. In addition, if there is a gap between the through hole 71 and the pin-shaped connecting member 65, the gap can be filled with solder 65A or a conductive adhesive to fix it, and electrical continuity can be obtained. Alternatively, the surface of the pin-shaped connecting member, for example, the Sn plating component may come into contact with the surface of the through hole, for example, the Cu member, and the metals may be solid-phase diffused after insertion to form a strong bond.

An example of the following connecting member 65 is a metal connecting member 65 having a spring mechanism 65G and a stopper mechanism 65H as shown in FIGS. 23 to 28. By inserting the spring mechanism 65G into the through hole 71 provided in at least one of the module substrates 51 and 66, the spring mechanism 65G can be fixed in the through hole 71 by the elastic force of the spring mechanism 65G. Further, the stopper mechanism 65H has a diameter larger than the diameter of the through hole 71, and prevents the spring mechanism 65G from entering too much in the through hole 71 direction by stopping at the opening portion of the through hole 71, thereby preventing the lower layer. The module substrate 51 and the upper module substrate 66 are laminated at a desired interval. Further, the gap of the through hole 71 into which the spring mechanism 65G is inserted may be filled with the above-mentioned solder 65A or the conductive adhesive (see FIGS. 24, 26 and 28). Thereby, the mechanical connection and the electrical connection between the connecting member 65 and the board-side terminal 52 on the module board 51 side or the board-side terminal 67 on the module board 66 side can be further ensured. It is possible to reduce the contact resistance between the board-side terminal 52 on the module board 51 side or the board-side terminal 67 on the module board 66 side. The advantage of using a connecting member 65 having such a spring mechanism 65G and a stopper mechanism 65H is that when the through hole 71 is not filled with solder 65A or a conductive adhesive, the spring mechanism 65G is simply inserted into the through hole 71. Since the mounting is completed, the mounting time can be shortened as compared with the connecting member 65 having the other configuration described above.

In the following example of the connecting member 65, as shown in FIG. 29, the connecting member 65 has a flat and mesh-like pattern. Here, in FIG. 29, the connecting member 65 is shown with 135 ° diagonal hatching. Since different signals or potentials are supplied to each connecting member 65, it is necessary that the mesh pattern of the connecting member 65 is appropriately divided so that each connecting member 65 is electrically independent. .. For reference, in FIG. 29, the arrangement position of the connecting member 65 when the above-mentioned columnar connecting member 65 is used is shown by a thick line, and each of the connecting members 65 having a divided mesh pattern is electrically independent. I showed that. When the connecting member 65 having such a flat mesh pattern is used, the contact area with the module substrates 51 and 66 is maximized, so that the connecting member 65 having another configuration is used as compared with the case where the connecting member 65 having another configuration is used. The mechanical strength can be maximized. As a result, the load and stress applied to the module substrates 51 and 66 can be reduced, so that it is possible to prevent the module substrates 51 and 66 from being warped undesirably. Further, since the connecting member 65 has a flat mesh pattern, there is a concern that the mold resin 56 may be difficult to fill in the filling step of the mold resin 56, but foaming of the porous structure described with reference to FIG. 14 By using the metal, the mold resin 56 infiltrates through the hole 65B (see FIG. 14) of the connecting member 65, so that it can be easily filled.

Next, an example of the manufacturing process of the module MA of the first embodiment will be described in the order of the processes with reference to FIGS. 30 to 36. Here, an example in which a columnar connecting member 65 (see FIG. 13) is used as the connecting member 65 will be described. FIG. 30 is a flowchart illustrating the manufacturing process of the module MA, and FIGS. 31 to 36 are cross-sectional views of a main part during the manufacturing process showing three module regions.

First, as shown in FIG. 31, a substrate base 51A in which a plurality of regions (hereinafter, referred to as module regions) to be the module substrate 51 described above are partitioned is prepared. Further, as shown in FIG. 32, a substrate base 66A in which a plurality of regions (hereinafter, referred to as module regions) to be the module substrate 66 described above are partitioned is prepared. The substrate bases 51A and 66A are multi-layer boards in which a plurality of (for example, about 80) module regions are partitioned by partition lines, and when 80 module regions are formed, the substrate region is used as an example. The size is about 90 mm x 75 mm, and the thickness is about 0.4 mm.

Next, in the substrate base 51A, after printing the solder paste on the outer layer Cu wiring 63 (board side terminal 52 (see FIG. 4)) to which the semiconductor chip IC1, the single chip component 54, and the integrated chip component 55 are connected, the solder paste is printed. The semiconductor chip IC1, the single chip component 54, and the integrated chip component 55 are arranged on the predetermined outer layer Cu wiring 63. At this time, the semiconductor chip IC1 and the integrated chip component 55 are arranged so that the bump electrode BE formed on the element forming surface faces the Cu wiring 63 for the outer layer. Subsequently, the semiconductor chip IC1, the single chip component 54, and the integrated chip component 55 are collectively solder-connected by performing reflow heating and flux cleaning to melt the solder (process S1). Similarly, in the substrate base 66A, after the solder paste is printed on the substrate side terminal 67 to which the integrated chip component 68 is connected, the integrated chip component 68 is arranged on the predetermined substrate side terminal 67. Subsequently, reflow heating and flux cleaning are performed to melt the solder, so that the integrated chip components 68 are collectively solder-connected (step S2). Here, an example of using a solder paste has been described, but an adhesive paste containing metal flakes can also be used instead of the solder paste.

Next, as shown in FIG. 33, in the substrate base 51A, after printing the solder paste on the substrate side terminal 52 (see FIG. 4) to which the connecting member 65 is connected, the connecting member 65 is attached to the predetermined substrate side terminal 52. Place on top. Subsequently, reflow heating and flux cleaning are performed to melt the solder, whereby the plurality of connecting members 65 are collectively solder-connected to the board-side terminal 52. Next, in the board base 66A, after printing the solder paste on the board side terminal 67 (see FIG. 4) to which the connecting member 65 is connected, the other ends of the plurality of connecting members 65 connected to the board base 51A are predetermined. It is placed on the board side terminal 67 of. Subsequently, reflow heating and flux cleaning are performed to melt the solder, whereby the plurality of connecting members 65 are collectively solder-connected to the board-side terminal 67. By the steps up to this point, it is possible to form a structure in which the substrate base 51A and the substrate base 66A are laminated via a plurality of connecting members 65 (step S3).

Next, as shown in FIG. 34, transfer molding is performed in which the component mounting surfaces (including the semiconductor chip IC1, the single chip component 54, and the integrated chip components 55 and 68) of the substrate bases 51A and 66A are sealed with the mold resin 56. (Step S4). First, the upper mold of the molding device is raised, and a structure in which the substrate base 51A and the substrate base 66A are laminated is installed in the lower mold. After that, the upper mold is lowered to fix the structure. The upper mold is provided with an air vent for sending air and resin in the molding mold between the upper mold and the lower mold to the outside. Subsequently, the inside of the molding die is forcibly depressurized to, for example, 1 Torr or less, the resin tablet is heated by a preheater to reduce the resin viscosity, and then the liquefied mold resin 56 is pressure-fed into the molding die. As the mold resin 56, for example, a thermosetting epoxy resin is used. Subsequently, after the sealing resin filled in the molding die is cured by a polymerization reaction, the upper mold and the lower mold are opened, and the structure covered with the molding resin 56 is taken out. After that, unnecessary sealing mold resin 56 is removed, and further baking treatment is performed to complete the polymerization reaction, so that the component mounting surfaces of the substrate bases 51A and 66A are sealed by the mold resin 56.

By charging the mold resin 56 after depressurizing the inside of the molding die in this way, the fluidity of the mold resin 56 can be increased, so that a narrow gap, for example, the back surface of the single chip component 54 and the component of the substrate base 51A can be obtained. The gap between the mounting surface (about 10 μm) and the gap between the main surface of the integrated chip component 55 and the component mounting surface of the substrate base 51A (about 10 to 20 μm) can be filled with mold resin 56 to prevent the formation of voids. it can. As a result, even if heat at a temperature of, for example, about 260 ° C. is applied to semi-melt the Pb-free solder during assembly of the module MA described below, the flush-like flow of the Pb-free solder can be prevented. Therefore, for example, the connection terminals at both ends of the single chip component 54 or the connection terminals on the main surface of the integrated chip component 55 are not connected, and a short circuit can be avoided.

Next, as shown in FIG. 35, the mold resin 56 and the substrate bases 51A and 66A are formed by half-cut dicing using a dicing cutter along the dicing line (corresponding to the above-mentioned partition line) (step S5). Half dicing is the depth to reach the inner layer Cu film 62A, which is a part of the ground wiring provided in the lower substrate base 51A, without completely cutting the mold resin 56 and the substrate bases 51A and 66A. It is a cutting that makes a notch 72 in, and the part below the Cu film 62A for the inner layer remains connected. The inner layer Cu film 62A used as the ground wiring is located on the second layer wiring near the component mounting surface of the substrate base 51A.

After that, for example, a trademark, a product name, a lot number, etc. are stamped on the upper surface of the mold resin 56 for each module area.

Next, as shown in FIG. 36, an electroless Me by Kki method, a shield layer SL so as to cover the surface (upper surface and side surfaces) of the inner layer exposed to the portion of the notches 72 for the Cu film 62A and the mold resin 56 is formed (Step S6). The process of forming the shield layer SL will be described step by step below. (1) As a pre-etching process, soak in a mixed solution of sodium hydroxide (20 g / L) at 70 ° C and an organic solvent (500 g / L) for 5 minutes, and then wash with water. (2) As a permanganate etching process, the mixture is immersed in a mixed solution of potassium permanganate (50 g / L) and sodium hydroxide (20 g / L) at 80 ° C for 5 minutes, and then washed with water. (3) As a neutralization process, soak in a mixed solution of hydroxylamine (20 g / L) at 50 ° C and concentrated sulfuric acid (50 ml / L) for 5 minutes, and then wash with water. (4) As a conditioning process, soak in ethanolamine (20 g / L) at 60 ° C for 5 minutes, and then wash with water. (5) As a soft etching process, soak in a mixed solution of sodium persulfate (150 g / L) and concentrated sulfuric acid (10 ml / L) at 25 ° C for 2 minutes, and then wash with water. (6) As a pre-immersion process, soak in concentrated hydrochloric acid (300 ml / L) at room temperature for 1 minute, and then wash with water. (7) As a catalyst, the mixture is immersed in a mixed solution of concentrated sulfuric acid (300 ml / L) at 25 ° C, palladium chloride (170 mg / L) and stannous chloride (10 g / L) for 3 minutes, and then washed with water. (8) For acceleration, soak in a mixed solution of concentrated sulfuric acid (50 ml / L) and hydrazine (0.5 g / L) at 25 ° C for 5 minutes, and then wash with water. (9) As electroless Cu plating, 70 ° C copper sulfate (10 g / L), EDTA2Na (sodium ethylenediamine tetraacetate) (30 g / L), 37% formaldehyde (3 ml / L) and stabilizer (bipyridine, etc.) ( Soak a mixed solution of (slightly) and polyethylene glycol in a plating bath adjusted to pH 12.2 with sodium hydroxide for 45 to 150 minutes, and then wash with water. (10) As a soft etching process, the mixture is immersed in a mixed solution of sodium peroxide (150 g / L) and concentrated sulfuric acid (10 ml / L) at 25 ° C for 2 minutes, and then washed with water. (11) As an activation process, soak in concentrated sulfuric acid (100 ml / L) at room temperature for 2 minutes, and then wash with water. (12) As a catalytic process, the mixture is immersed in a mixed solution of palladium chloride (170 mg / L) at 25 ° C, concentrated hydrochloric acid (1 ml / L) and an additive (copper salt, etc.) for 5 minutes, and then washed with water. (13) For alkaline electroless Ni plating, a mixed solution of nickel sulfate 26 g / L at 90 ° C, sodium citrate (60 g / L), sodium hypophosphite (21 g / L) and boric acid (30 g / L). Immerse in (adjusted to pH 8-9 with sodium hydroxide) for 5-18 minutes, then wash with water and dry at 150 ° C for 60 minutes.

In the water washing in each process, running water washing is performed for 2 minutes and running water washing with pure water is performed for 2 minutes. By this film forming step, a shield layer SL composed of a laminated film of a Cu plating film and a Ni plating film is formed. Then heat at 150 ° C for 1 hour. In this heating process, the holes through which hydrogen escapes, which are seen in the Ni plating film immediately after forming the shield layer SL, are closed, and minute crystal grains are connected and coarsened to form a Ni plating film with a smooth surface. Further, microchannel cracks having a breathable structure are formed. The Cu plating film has an electromagnetic wave shielding function, and the Ni plating film has a touchproof function. Further, the Ni plating film has improved corrosion resistance due to a change in the crystal structure of the surface due to heat treatment. The appropriate range for the thickness of the Cu plating film is, for example, 2 to 10 μm (not to mention that it is not limited to this range depending on other conditions). Further, as a range suitable for mass production, a peripheral range centered on 2.5 to 4 μm is considered to be the most suitable. For example, the thickness of the Ni plating film is considered to be in an appropriate range of 0.1 to 0.3 μm (not to mention that it is not limited to this range depending on other conditions). Further, as a range suitable for mass production, a peripheral range centered on 0.25 μm is considered to be the most suitable. Microchannel cracks are randomly formed along the grain boundaries in the shield layer SL, and the width of the microchannel cracks on the surface of the Ni plating film is considered to be in an appropriate range, for example, 100 nm or less (other conditions). Of course, some are not limited to this range). Further, the range suitable for mass production is considered to be 1 to 60 nm, but the peripheral range centered at 30 nm is considered to be the most suitable. When heated to 260 ° C in consideration of the reflow process, the width of the microchannel crack widens, but the width is 100 nm or less. The crack width in the Cu plating film is smaller than the width on the surface of the Ni plating film.

Next, the substrate base 51A below the notch 72 is further cut and separated into individual module MAs (see FIG. 4) (step S7). Next, the electrical characteristics of the module MA are measured according to the items according to the product standard, the module MA is selected (process S8), and then the non-defective module MA is packed (process S9).

Next, the mounting process of the module MA will be described.

As shown in FIG. 4 above, electrodes 53G and 53S for solder connection are formed on the back surface of the module substrate 51 so that they can be mounted on the motherboard. First, print the solder paste on the motherboard. Subsequently, after arranging the module MA on the motherboard, reflow heating is performed at a temperature of, for example, 250 ° C. or higher, and the module MA is mounted on the motherboard 66 via solder. After that, the electrical characteristics are tested and the mounting is completed.

In the present embodiment, the case where the surface mount component mounted on the module substrate 51 is covered with the highly elastic mold resin 56 has been described, but the present invention is not limited to this, and for example, a low elasticity resin, for example, is described. It is also possible to use a silicon resin.

In addition, the case where it is applied to the dual band system that can handle radio waves in two frequency bands of GSM900 and GSM1800 has been described, but the present invention is not limited to this, and for example, three frequencies of GSM900, GSM1800 and GSM1900 are described. It may be applied to a triple band system capable of handling band radio waves. It can also support the 800MHz band and 850MHz band.

As described above, according to the present embodiment, for example, in a digital mobile phone system, even if the module MA includes a surface mount component that generates an electromagnetic wave, for example, a semiconductor chip IC1 on which a power amplifier PM is formed, the module MA is surface mounted. A shield layer SL made of a Cu / Ni laminated film is formed on the surface (upper surface and side surface) of the mold resin 56 covering the parts by an electroless plating method, and the shield layer SL and the ground wiring are electrically connected sufficiently. By having the electromagnetic wave shielding effect, the electromagnetic waves generated from the power amplifier PM can be shielded by the shield layer SL.

Further, in the shield layer SL made of a Cu / Ni laminated film formed by the electroless plating method, microchannel cracks having a width of 100 nm or less (typically 1 to 60 nm) are formed along the grain boundaries. Microchannel cracks lead from the surface of the shield layer SL to the mold resin 56. Therefore, even if the water contained in the mold resin 56, the water contained in the module substrate 51, or the water invading the interface between the module substrate 51 and the mold resin 56 becomes water vapor due to reflow heating or the like, the water vapor remains in the microchannel. It can be discharged to the outside of the module MA through the crack. As a result, the volume expansion does not occur even if the moisture is vaporized by reflow heating or the like, so that the shield layer SL can be prevented from peeling off.

Further, by forming the shield layer SL made of a Cu / Ni laminated film by an electroless plating method, a shield layer SL having good ductility can be obtained. As a result, the coefficient of linear expansion of the shield layer SL and the coefficient of linear expansion of other component materials are different from each other, and even if deformation occurs during reflow heating of the module MA or during actual operation, the shield layer SL is destroyed or cracked due to stress concentration. It is possible to suppress the occurrence of such. From these facts, it is possible to provide a module MA having an electromagnetic wave shielding effect and high reliability against reflow heating.

(Embodiment 2) Next, the module MA of the second embodiment will be described with reference to FIG. 37.

As shown in FIG. 37, in the module MA of the second embodiment, a part of the substrate side terminal 67 (shown as the substrate side terminal 67A) is formed up to the outer periphery of the module substrate 66, and is electrically connected to the shield layer SL. Is connected to. This board-side terminal 67A, which is electrically connected to the shield layer SL, is a ground wiring.

The module MA of the second embodiment having the above configuration can also obtain the same effect as the module MA of the first embodiment.

(Embodiment 3) Next, the module MA of the third embodiment will be described with reference to FIG. 38.

As shown in FIG. 38, the module MA of the third embodiment omits the sealing with the mold resin 56 and the electromagnetic wave shielding structure with the shield layer SL, and has a sealing structure using a metal cap MCAP and an electromagnetic wave shielding structure. There is. On the side surface of the module substrate 51, a Cu film 73 that connects to the inner layer Cu film 62A, which is the ground wiring, is formed. Further, the metal cap MCAP is formed with a protrusion 74 in contact with the Cu film 73 on the side surface of the module board 51 when the metal cap MCAP is fitted into the structure composed of the module boards 51 and 66. The electromagnetic shielding structure by the metal cap MCAP is realized by contacting the Cu film 73 which is electrically connected to the ground wiring.

The Cu film 73 may be provided on the side surface of the module substrate 66. In that case, the module substrate 66 is provided with the substrate side terminal 67A which is the ground wiring described in the second embodiment, and the substrate side terminal 67A is provided. The configuration is such that 67A and Cu film 73 are connected. Even in such a configuration, when the metal cap MCAP is fitted into the structure composed of the module substrates 51 and 66, the protrusion 74 of the metal cap MCAP is in contact with the Cu film 73 on the side surface of the module substrate 66. 74 is formed.

According to the module MA of the third embodiment as described above, since the mold resin 56 is omitted, the manufacturing process of the module MA can be simplified. In addition, since the electromagnetic wave shield structure is realized by fitting the metal cap MCAP, it is possible to realize the electromagnetic wave shield structure more easily and easily than when the shield layer SL is formed by electroless plating. ..

The module MA of the third embodiment having the above configuration can also obtain the same effect as the module MA of the first and second embodiments.

(Embodiment 4) Next, the module MA of the fourth embodiment will be described with reference to FIG. 39.

As shown in FIG. 39, the module MA of the fourth embodiment is mounted on the module substrate 51 with the semiconductor chip IC1 facing the module substrate 51 on the back surface, and is an adhesive material 75 such as DAF (Die Attach Film). It is fixed to a predetermined board side terminal 52 by. Further, a plurality of external terminals formed on the main surface (element forming surface) of the semiconductor chip IC1 are connected to the substrate side terminals 52 of the corresponding module substrate 51 by a bonding material. Here, a bonding wire BW made of fine Au wires is used as the bonding material.

Further, since the bonding wire BW is used for the semiconductor chip IC1, a plating film is formed on the surfaces of all the substrate side terminals 52. The plating film is composed of, for example, a laminated film in which a Ni layer and an Au layer are formed by a plating method in order from the lower layer. Therefore, the single chip component 54 is solder-connected to the plating film at its connection terminal, and the integrated chip component 55 is connected to the plating film at its connection terminal and is an external terminal formed on the main surface of the semiconductor chip IC1. The bonding wire BW connected to is connected to the plating film on the surface of the substrate side terminal 52.

The configuration of the module MA of the fourth embodiment other than the above is substantially the same as that of the module MA of the first embodiment.

The module MA of the fourth embodiment having the above configuration can also obtain the same effect as the module MA of the first embodiment.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Needless to say.

The semiconductor device of the present invention and the manufacturing method thereof can be applied to a semiconductor device having a structure in which a plurality of semiconductor chips and chip components are mounted and a manufacturing process thereof.

1 Front-end device 2 baseband circuit 3 Modulation / demodulation circuit 4a, 4b switch circuit 5 demultiplexer 6 Peripheral circuit 6A control circuit 6A1 power control circuit 6A2 bias voltage generation circuit 6B bias circuit 7a, 7b input terminal 8a, 8b output terminal 9a1 ~ 9a5, 9b1 ~ 9b5, 9c transmission line 10a, 10b input terminal 11a1 ~ 11a3, 11b1 ~ 11b3 power supply terminal 12a, 12b output terminal 13 Control terminal 21 board 22 Epitaxy layer 23 p type well 24 Gate insulating film 25 Gate electrode 26 sidewall 27 n^-Type offset drain area 28 n-type offset drain area 29 n⁺Mold drain area 30 n^-Type source area 31 n⁺Type source area 32 p type halo area 33 p type punching layer 34 p⁺Type semiconductor area 35 grooves 36 Silicon nitride film 37 Silicon oxide film 38 contact holes 39 plug 40 Source electrode 41 Drain electrode 42 Silicon oxide film 43 Through hole 44 Wiring 45 Surface protective film 46 Source back electrode 51 Module board 51A board base 52 Board side terminal 53G, 53S electrodes 54 Single chip parts 55 Integrated chip components 56 Mold resin 58 Heat dissipation via 58a through hole 60 core material 61 prepreg 62, 62A Cu film for inner layer 63 Cu film for outer layer 64 Chip parts 65 Connection member 65A solder 65B hole 65C metal core 65D nickel film 65E tin film 65F resin core 65G spring mechanism 65H stopper mechanism 66 Module board 66A board base 67 Board side terminal 67A Board side terminal 68 Integrated chip parts 70 Insertion hole 71 Through hole 72 notch 73 Cu film 74 protrusions 75 Adhesive A, B power amplifier circuit A1 ~ A3, B1 ~ B3 amplification stage AM1 ~ AM3, BM1 ~ BM3 matching circuit ANT antenna BE bump electrode BW bonding wire C1, C2 capacitors Cm1 ~ Cm12 capacitors CNT1, CNT2 switching signal FLT1, FLT2 filter GND ground potential IC1 semiconductor chip Layer1 1st layer wiring Layer2 2nd layer wiring Layer3 3rd layer wiring Layer4 4th layer wiring LPF1, LPF2 low pass filter MA module MCAP metal cap MN1, MN2 Impedance matching circuit PM power amplifier S1 ~ S9 process SL shield layer UF underfill resin