Apparatus and method of page program operation for memory devices with mirror back-up of data

Cross-reference of related applications This application claims the interests of US Patent Provisional Application No. 60 / 891,115 prior to the application filed February 22, 2007, the disclosure of which is incorporated herein by reference in its entirety.

The present invention generally relates to semiconductor devices. More specifically, the present invention relates to devices and methods for operating page programs for memory devices.

Electronic devices use memory devices such as flash memory to store data or information. In a memory system, the memory controller programs the selected flash memory device by transmitting the data to a page buffer in the selected flash memory device in which the data is temporarily stored. The programming of the data from the page buffer into the flash memory begins, the programming result is verified, and the verification result is brought as "success" or "failure". The program and verification operations are performed several times during the period specified by "Program Time". After the program time, in case of failure, the data is reloaded from the memory controller and the page program operation resumes within the same selected device.

The disadvantage is that flash memory requires a long program time, for example, to verify the program status. The memory inside the memory controller must hold the initial program data in order to recover the original program data in the event of a program failure. The initial program data occupies the space in the memory of the memory controller, and as a result, this memory space cannot be used for other purposes.

<p><patcit num="1"><text>U.S. Patent Application No. 60 / 891,115</text></patcit><patcit num="2"><text>U.S. Patent Application No. 11 / 594,564</text></patcit><patcit num="3"><text>U.S. Patent Application No. 60 / 868,773</text></patcit><patcit num="4"><text>U.S. Patent Application No. 60 / 787,710</text></patcit><patcit num="5"><text>U.S. Patent Application No. 11 / 521,734</text></patcit><patcit num="6"><text>U.S. Patent Application No. 60 / 802,645</text></patcit><patcit num="7"><text>U.S. Patent Application No. 11 / 750,649</text></patcit><patcit num="8"><text>U.S. Patent Application No. 11 / 840,692</text></patcit><patcit num="9"><text>U.S. Patent Application No. 60 / 892,705</text></patcit></p>

<p> According to one aspect of the invention, there is provided a device for controlling a plurality of memory devices interconnected in series, each having a page buffer and a memory cell. This device writes data to the page buffer of the selected memory device among multiple memory devices and the page buffer of other memory devices among multiple memory devices, and the page buffer to the selected memory device. A mirror backup of the data was used by instructing the memory cell to be programmed with the data loaded into it, as well as determining if the data was successfully programmed into the memory cell of the selected memory device. It includes a data processor configured to perform page program operations and recover data from the page buffers of other memory devices.</p><p> For example, a data processor is configured to recover data from the page buffer of another memory device by reading it back from the page buffer of the other memory device without programming the data into the memory cells of the other memory device. Will be done.</p><p> The device may further include data storage for storing data prior to writing data to the page buffers of the selected memory device and the page buffers of other memory devices.</p><p> According to another aspect of the present invention, a plurality of memory devices interconnected in series, each having a page buffer and a memory cell, and a device for controlling the plurality of memory devices, the plurality of memory devices. Write data to the page buffer of our selected memory device and the page buffer of another memory device among multiple memory devices, and to the selected memory device, the data loaded in that page buffer is stored in that memory. Mirror backup of data was used by instructing the cell to be programmed and by recovering the data from the page buffer of another memory device if the data was not successfully programmed in the memory cell of the selected memory device. A system is provided that includes a device that includes a data processor that is configured to perform page program operations.</p><p> According to another aspect of the invention, there is provided a method for controlling multiple memory devices interconnected in series, each having a page buffer and a memory cell. This method involves transmitting data to the page buffer of the selected memory device among the multiple memory devices and the page buffer of the other memory device of the multiple memory devices, and to the selected memory device. The step of instructing the data loaded in the page buffer to be programmed into that memory cell, and recovering the data from the page buffer of another memory device if the data is not successfully programmed into the memory cell of the selected memory device. Including steps to do.</p><p> For example, the step of recovering data from the page buffer of another memory device includes reading back the data from the page buffer of another memory device without programming the data into the memory cells of the other memory device.</p><p> This method stores the data before writing it to the page buffers of the selected memory device and the page buffers of other memory devices, and whether the data was successfully programmed into the memory cells of the selected memory device. Further includes a step of freeing the space occupied by the data before determining.</p><p> According to another aspect of the present invention, a memory device for use as one of a set of memory devices connected in series is provided. The memory device comprises an input connection, an output connection, a device address identification of the memory device, and a device controller, which receives messages for entering and exiting multiple address detection modes, and accordingly multiple. Enters and exits address detection mode, receives commands containing device addresses over an ingress connection, and while not in multiple address detection mode, processes commands only if the device address of the command matches the device address of the device, multiple While in address detection mode, i) process the command if the device address of the command is the same as the device address of the device, and ii) if the device address of the command is the same as the device address of at least one other given device. It is configured to handle commands.</p><p> According to another aspect of the invention, a method is provided in a memory device that forms a portion of a set of memory devices connected in series, the method being in a step of maintaining device addresses and in multiple address detection modes. A step to receive a message to enter and exit, a step to receive a command including a device address, a step to process a command only if the destination address matches the device address while not in multi-address detection mode, and a multi-address detection step. While in mode, the step is to process the command if the device address of the command is the same as the device address of the device, and to process the command if the device address of the command is the same as the device address of at least one other given device. including.</p><p> Other aspects and features of the invention will become apparent to those skilled in the art by examining the following description of specific embodiments of the invention, along with the accompanying drawings.</p><p> Next, each embodiment will be described with reference to the accompanying drawings.</p>

<figref num="1">FIG. 3 is a block diagram of an exemplary system having an architecture featuring serially connected devices to which embodiments of the present invention are applicable.</figref><figref num="2">FIG. 6 is a schematic representation of an exemplary command format for serially connected memory devices.</figref><figref num="3">It is a schematic diagram of an exemplary procedure for page programming and verification.</figref><figref num="4">It is a block diagram of two memory devices, one of which is used as a mirror backup for data.</figref><figref num="5">FIG. 3 is a block diagram of a system with an architecture featuring serially connected devices, where the page buffer is used as a mirror backup for the data.</figref><figref num="6">FIG. 3 is a block diagram of another system with an architecture featuring serially connected devices, where the page buffer is used as a mirror backup for the data.</figref><figref num="7">FIG. 6 is an exemplary timing diagram of the steps that enable and disable the LSB (least significant bit) ignore mode in the system of FIG.</figref><figref num="8">It is a block diagram of the system of FIG. 6 that performs data recovery after a program failure.</figref><figref num="9">It is a block diagram which shows a part of the memory device connected in series shown in FIG.</figref><figref num="10">It is the schematic of the typical circuit of the memory device shown in FIG.</figref><figref num="11">It is a flow chart of the method of a program operation using a mirror backup.</figref><figref num="12">A table of exemplary command sets.</figref><figref num="13">It is a table of an exemplary operation table.</figref><figref num="14">It is a table showing an example of detailed command and address formats.</figref><figref num="15">It is an exemplary timing diagram which shows the basic input timing in a memory system.</figref><figref num="16">It is an exemplary timing diagram showing the input sequence of a bitstream in a modular command NAND flash memory system.</figref><figref num="17">It is an exemplary timing diagram which shows the basic output timing in a memory system.</figref><figref num="18">It is an exemplary timing diagram showing the output sequence of a bitstream in a memory system.</figref><figref num="19">It is a flow chart of the method of a page reading operation.</figref><figref num="20">It is an exemplary timing diagram showing a page read operation and a burst data read operation.</figref>

Examples of embodiments of the present invention will be described in detail below with reference to the accompanying drawings forming a portion thereof, but for the sake of explanation, specific examples of embodiments in which the present invention can be implemented are shown. These embodiments will be described in sufficient detail so that those skilled in the art can practice the invention, but other embodiments may be utilized and are logical without departing from the scope of the invention. It should be understood that mechanical, electrical and other changes may be made. Therefore, the following detailed description should not be taken in a limited sense, and the scope of the present invention is defined by the appended claims.

FIG. 1 shows a system according to an embodiment of the present invention. Referring to FIG. 1, system 150 is serialized with memory controller 151 and multiple (M) memory devices 154-1, 154-2, 154.3, ..., and 154-M interconnected in series. Have a connection (M is an integer greater than or equal to 2). The memory controller 151 and each memory device are interconnected via a link with a data width of n (n is an integer greater than or equal to 1). When n is 1, the interconnect link becomes a serial link, and when n is 2 or more, the interconnect link becomes a parallel link. The memory controller 151 is connected to the first memory device 154-1 of the series interconnect. The last memory device 154-M is also the first, second, third, ... and Mth memory devices 154-1, 154-2, 154.3, ... and of the series interconnect. The 154-M is connected to the memory controller 151 so that it forms a ring connection structure with the memory controller 151. In the example shown in the figure, the memory devices 154-1 to 154-M are flash memory devices. Subsequent examples are also specific to flash memory. However, it should be understood that embodiments of the present invention are also applicable to other types of non-volatile memory devices.

In the specific example shown in FIG. 1, the memory devices 154-1 to 154-M connected in series are flash memory devices such as NAND flash devices, respectively. The flash memory device has a page buffer for temporarily storing information about data. The stored information is written to the flash memory cells of the device according to page programming. When programmed, the information stored in the page buffer is corrupted due to the programmed cell validation process.

The memory controller 151 includes a data storage 152 and a processor 153. The data storage 152 stores various data including information about operation instructions, addresses and memory data to be processed and stored in serially connected memory devices. Information about operation instructions is used to control serially connected memory devices. The data storage 152 is, for example, static random access memory (SRAM) or other type of embedded memory. More generally, any suitable data storage may be implemented. Processor 153 performs data processing and control operations on memory devices that access data stored in data storage 152. The memory controller 151 has a plurality of connections, namely a command signal output connection CIO, a command signal input connection COI, an input strobe connection CSIO, an output strobe connection DSIO and a clock output connection CKO.

In operation, the memory controller 151 uses the command input (CI) signal S via the command signal output connection CIO._C1Is sent to the first device 154-1 and the command output (CO) signal S via the command signal input connection COI._{C (M + 1)}Is received from the last device 154-M in series interconnection. The memory controller 151 also receives a command strobe input (CS1) signal S via an input strobe connection CSIO._CS1And also the data strobe input (DS1) signal S via the output strobe connection DSIO_DSIIs supplied to the first device 154-1. Further, the memory controller 151 supplies the clock signal CK to all the devices 154-1 to 154-M in a common clock source system via the clock output connection CKO.

Memory devices 154-1, 154-2, 154.3, ... and 154-M have page buffers 154-1, 158-2, 158-3 ,,,, and 158-M, respectively, and also. It has flash memory cells 159-1, 159-2, 159-3, ... and 159-M, respectively. Each of the memory devices 154-1 to 154-M has a CI signal S from the previous device._CiSignal input connection CI to receive (i = 1 ~ M), CI signal S to subsequent device_{C (i + 1)}Signal output connection CO to supply, CSI signal S from previous device_CSiInput strobe input connection CS1 for receiving, output CSI signal S to subsequent devices_{CS (i + 1)}Input strobe output connection CSO for sending, DSI signal S from the previous device_DSiOutput strobe input connection DSI for receiving, and output DSI signal S to subsequent devices_{DS (i + 1)}Has an output strobe output connection DSO for sending.

Each of the memory devices 154-1 to 154-M has a unique hard-wired or pre-allocated device address (DA), so that in normal operation one device can be selected or specified at a time. A detailed example of an architecture featuring devices connected in series is provided in US Patent Application No. 11 / 594,564, entitled "Daisy Chain Cascading Devices," filed July 31, 2006, the disclosure of which. Incorporated herein as a whole by reference. Another detailed example of an architecture featuring devices connected in series is the "System and Method of Operating Memory Devices of Varying" filed December 6, 2006. It is set forth in US Patent Provisional Application No. 60 / 868,773 entitled "Type", the disclosure of which is incorporated herein by reference in its entirety. Examples of device address assignments for multiple memory devices connected in series are US Patent Application No. 60 / 787,710 filed March 28, 2006 and US Patent Application No. 11 / 521,734 filed September 15, 2006. No., U.S. Patent Application No. 60 / 802,645 filed May 23, 2006, and U.S. Patent Application No. 11 / 750,649 filed May 18, 2007, all of which are disclosed by reference. Incorporated herein as.

In normal operation, the memory controller 151 contains the CI signal S containing the command._C1Is sent. The command includes a device address (DA) and an operation code (hereinafter referred to as OP code) representing an operation instruction. Some commands include more address information, and some commands include more data. Each OP code is associated with its own behavior. As used herein, each command is also considered to have the type associated with the OP code contained within the command. For example, a command that contains a read OP code is called a "read command." Each of the memory devices 154-1 to 154-M is a memory device (device 154-1 in the example shown) in which a given device is directly connected to the memory controller via its respective CI. In some cases, the command is received directly from the memory controller, or for other devices, from the immediately preceding memory device adjacent to it. Each of the memory devices 154-1 to 154-M uses its respective CO to be a device whose output is connected to a memory controller (device 154-M in the example shown). Transfer commands to memory controller 151, or to adjacent subsequent devices, if any. A command containing a write OP code addressed to a particular flash memory device results in the data being written to the page buffer of that device and then transferred from this page buffer to the flash memory cells of the memory device. A command containing a read OP code addressed to a particular flash memory device results in data being read from the flash memory cell of the memory device into the page buffer of the memory device and then transferred from this page buffer.

The memory controller 151 issues commands, and each of the commands includes a device address (DA) and a command operation code (hereinafter OP code). Depending on the command, the address information may be further included, and depending on the command, the data may be further included. Each OP code is associated with its own behavior. As used herein, each command is also considered to have the type associated with the OP code contained within the command. For example, a command containing a read OP code may be called a "read command". For example, the commands for use with serially connected devices are flexible modular commands, the structure of which is shown in Table 1.

<tables num="1"><img file="JP2010519641A_D0001.tif" /></tables>

In Table 1, DA is the device address, OP code is the operation code, RA is the row address, CA is the column address, and DATA is the write data. Examples of commands related to OP code are the "Burst Data Load" command and the "Burst Data Read" command. It may be either (i) a row address or a column address, (ii) neither a row address nor a column address, or (iii) no data.

FIG. 2 is a schematic of an exemplary command format for serially interconnected memory devices. Next, referring to FIG. 2, the first command format 109-1 contains an ID number and an OP code. The ID number is used to uniquely identify the selected memory device, and the OP code field contains the OP code executed by the selected device. A command having the first command format 109-1 may be used, for example, for a command containing an OP code for reading a register value. The second command format 109-2 contains the ID number, OP code and data. A command having a second command format 109-2 may be used, for example, for a command containing an OP code for writing data to a register. The third command format 109-3 contains the ID number, OP code and additional address. Additional addresses include, for example, row addresses and / or column addresses for addressing locations within memory cells. A command having a third command format 109-3 may be used, for example, for a command containing an OP code for reading data from a memory cell of a selected memory device. The fourth command format 109-4 includes an ID number, an OP code, additional addresses, and data. A command having a fourth command format 109-4 may be used, for example, for a command containing an OP code for writing data to a memory cell of the selected memory device. Note that all four exemplary command formats 109-1, 109-2, 109-3, 109-4 begin with an ID number for addressing purposes. From the above description, the command can contain ID numbers, OP codes, additional addresses, data, or any other information related to controlling the configuration of memory devices interconnected in series. The term "command" in the specification does not simply refer to the command OP code.

Specific examples of the command structure described above are US patent application No. 11 / 840,692 filed on August 17, 2007, and US patent provisional application filed on March 2, 2007, which were assigned to the assignee of the present application. It is taught in No. 60 / 892,705, the contents of which are incorporated herein by reference in their entirety. These applications disclose various command structures for distinguishing between a page buffer access operation with a relatively short access time and a core access operation with a relatively long processing time. Further details of the modular command structure are given below under the heading "Modular Command Structure".

Seeing Figure 1 again, each of the memory devices 154-1, 154-2, 154.3, ..., and 154-M allows a given device to go directly to the memory controller via its respective CI. The command is received directly from the memory controller if it is a connected memory device (device 154-1 in the example shown), or from the immediately preceding device that is adjacent to other devices. Each memory device uses its respective CO to the memory controller if the given device is a device whose output is connected to the memory controller (device 154-M in the example shown). Or transfer the command to an adjacent subsequent device. In the traditional command structure, a command containing a read OP code addressed to a particular flash memory device results in data being read from the flash memory cell of the memory device into the page buffer of the memory device, and then from this page buffer. Transferred. A command containing a write OP code addressed to a particular flash memory device results in data being written to that device's page buffer and then transferred from this page buffer to the flash memory cell of the memory device.

Figure 3 shows an exemplary procedure for page programming and validation. With reference to Figures 1 to 3, an example of how to perform a write operation will be explained. The data is assumed to be written to memory device 154-2. The programmed data (eg, 100110 ... 0100) is loaded from the storage element 152 of the memory controller 151 into the page buffer 158 of the memory device 154-2 (step 112-1). The step of programming the data to the assigned row address (page orientation) of the flash memory begins (step 112-2). The result of programming is verified (step 112-3). The verification result is generated in the page buffer and overwrites the contents of the page buffer written to the flash memory core in the "1" state indicating success and the "0" state indicating failure. The programming operation may not be successful due to defects on the memory cells, wear of the cell gate oxide, or other defects. Internally, program and validation operations are performed several times during a specified period of time called program time. As shown in 112-4, if all cells in the selected row (page orientation) are properly programmed, the final contents of page buffer 158 will all be in the "1" state. After the program time, if any "0" value in the page buffer 158 of device 154-2 still exists, the page program failed, as shown in 112-5. In case of failure, the data is reloaded from the storage element 152 of the memory controller 151 and the page program operation to a different row address (page direction) of the same selected device is restarted.

In general, flash memory has the fundamental limitation of long program time due to the time used to verify cell characteristics and program status. Since the page program operation may fail, the data storage element 152 of the memory controller 151 holds the initial program data so that the original program data can be recovered if the program fails. As a result, the initial program data occupies a space within the data storage element 151, thereby preventing this space from being used for other purposes. As a result, you must wait for the page program operation and validation to complete before you can perform other page program operations. A feasible approach to improving performance may be to increase the capacity of the storage elements in the memory controller, but this can be costly.

In the exemplary system 150 shown in FIG. 1, when performing a page program operation on the selected memory device, the memory controller 151 fills the page buffer 158 of the selected memory device and the page buffer of another memory device. Also loads the data and remembers a backup copy of the data. In this example, it is assumed that the selected memory device is the first memory device 154-1 and the other memory devices are the second memory device 154-2. More generally, the selected memory device and other memory devices may be any two of the memory devices 154-1, 154-2, 154.3, ..., and 154-M. If the data is not successfully programmed in the memory cells of the selected memory device 154-1, the memory controller 151 recovers the data from the page buffer 158 of the second memory device 154-2. The page buffer 158 of the second memory device 154-2 is accessed regardless of the program operation. As a result, the data can be recovered without having to program the data in the memory cell of the second memory device 154-2. Since the copy of the data is stored in the page buffer 158 of the second memory device 154-2, the memory controller 151 does not need to store the data locally in its data storage element 152. Therefore, the memory controller 151 frees up space in the data storage element 152 where the data is stored before determining whether the data was successfully programmed into the memory cells of the selected memory device 154-1. Can be done.

In a specific example, one embodiment of the invention uses three "modular" memory device access commands so that the page buffer can act as a mirror backup. The first command is called the "burst data load" command and contains the burst data load OP code. This writes the data to the page buffer, but this command alone does not transfer the data to the flash memory cells. In the following examples, 4Xh and 5Xh are used for this, but more generally, the command structure should be defined based on a concrete implementation base. The second command is called the "burst data read" command and contains the burst data read OP code. This allows the data to be read directly from the page buffer without first reading from the flash memory cells. In the examples that follow, 2Xh is used for this, but more generally, the command structure should be defined based on a concrete implementation base. The third command is called the "page program" command and contains the page program OP code. As a result, the data previously stored in the page buffer is written to the flash memory, and the contents of the page buffer are discarded in the process for verification purposes. In the examples that follow, 6Xh is used for this, but more generally, the command structure should be defined based on a concrete implementation base.

FIG. 4 shows the two memory devices shown in FIG. With reference to FIGS. 1 and 4, the two devices 120 and 127 represent two devices in system 150, which are adjacent to or separated from each other in an interconnect configuration. One of the two devices 120 and 127 is used as a mirror backup for the data.

The first memory device 120 has an input connection 139, an output connection 140, a flash memory cell 121, a page buffer 122, and a device controller 126. Similarly, the second memory device 127 has an input connection 141, an output connection 142, a flash memory cell 128, a page buffer 129, and a device controller 130. The two memory devices 120, 127 are any two memory devices that form part of an architecture that features devices interconnected in series. In a specific example, one of the two memory devices 120 and 127 is used as a mirror backup for the data. Device controllers 126 and 130 include any suitable circuitry for successful command processing. Subsequent examples do not refer to any device controller, but it should be understood that these examples include circuits for processing commands.

In operation, the page buffer 122 of the first memory device 120 is loaded with data by the burst data load commands (4Xh and 5Xh) via the input connection 139, as shown by 123. In this example, the data is also loaded into the page buffer 129 of the second memory device 127 over the input connection 141, as shown by 137. Page programming in the memory device 120 is performed by the page program command (6Xh), as indicated by 124. The page buffer 122 is read through the output connection 140 using "device status read (D0h)" as shown by 125 to verify whether the page programming operation was successful. The second memory device 127 is used as a mirror backup for the page program operation if page programming is unsuccessful for the first memory device 120. A memory controller (not shown) constantly monitors which memory device is being used for mirror backup. If the program fails, the data can be recovered from the mirror backup via the output connection 142, as shown in 138. This eliminates the need for the memory controller to store the contents in its storage element. Therefore, the location used by the memory controller to store data before being programmed into page buffers 122, 129 can be freed for other purposes.

The page buffer mirroring function in a system with an architecture in which each device is interconnected in series will be described below with reference to FIGS. 5 and 6. Figure 5 shows an example of writing the same data to two different page buffers using two separate write commands (ie, one command for each page buffer). Other implementations use a single write command to write the same data to more than one page buffer. An example of this is shown below with reference to FIG.

Figure 5 shows a system with an architecture featuring serially connected devices, where the page buffer is used as a mirror backup for the data. First referring to FIG. 5, the system 190 has a memory controller 191 and a plurality of memory devices 193-1, 193-2, 193-3, ..., And 193-15 connected in series. In a specific example, system 190 includes 15 memory devices. More commonly, two or more memory devices are provided. The memory controller 191 includes a data storage element 192 and a data processor 203. The memory controller 191 also has an output connection CIO for connecting to the first memory device 193-1 and an input connection COI for connecting to the last memory device 199-15. Memory devices 193-1, 1932, 193-3, ..., and 193-15 have page buffers 194, 196, 198, and 190, respectively, and memory devices 193-1, 1932, 193- Each of 3, ..., and 193-15 has a memory cell (not shown).

The memory controller 191 and the memory devices 193-1, 193-2, 193-3, ..., and 193-15 are interconnected by a serial link. Other examples described herein are also specific to serial links between successive devices. However, it should be understood that embodiments of the present invention are also applicable to architectures characterized by parallel links between successive devices. More generally, embodiments of the present invention are applicable to architectures characterized by serial links between successive devices. This serial link may be a serial link or a parallel link. System 190 uses a page buffer as a mirror backup for the data. In the example shown, the two devices are interconnected by a link with one I / O pin. Alternatively, the link can have multiple I / O pins. Memory devices 193-1, 193-2, 193-3, ..., and 193-15 process the signal from the previous device over the CI connection, and the processed result is next over the CO connection. Each has a processing circuit for outputting to the device of. For simplicity, these circuits are shown in a typical D-type flip-flop (D-FF).

In this example, the memory controller 191 needs to write data to the memory cells of memory device 193-1 and the page buffer 194-2 of memory device 193-2 can be used as a mirror backup. Assumed. In operation, the memory controller 191 issues a first write command to load the data from the data storage element 192 into the page buffer 194-1 of the first memory device 193-1. Loading data into page buffer 194-1 is shown overall in 201. To keep a backup copy of the data in the event of page programming failure, memory controller 191 also issues a write command (page buffer load) to page buffer 194-2 on second memory device 193-2. Load the same data. Loading data into page buffer 194-2 is shown overall in 202. The memory controller 191 then issues a page program command to program the data loaded in the page buffer 194-1 into a memory cell (not shown) of the first memory device 193-1. In the example shown, the data is not programmed in the memory cell of the second memory device 193-2. Instead, if page programming for the first memory device 193-1 fails, the data is kept in page buffer 194-1 as a mirror backup copy of the data.

The memory controller 191 constantly monitors which memory device 193-2 is used as a mirror backup. If the program fails, the data can be recovered from the mirror backup. This eliminates the need for the memory controller 191 to store its contents in its data storage element 192. Therefore, as soon as the page buffer is loaded, the data storage element 192 previously used to store the data is released for use elsewhere. The memory controller constantly monitors which data storage element 192 is free and which data storage element is in use. If the page programming operation is successful, the position in the page buffer 194-2 used as a mirror backup is released.

Note that the first memory device 193-1 and the second memory device 193-2 are selected by the memory controller 191. The memory controller 191 can alternately select various memory devices. Each write command is addressed to the target memory device by the DA.

Note that for each device connected in series, there is a clock cycle-based latency delay between each memory device to synchronize the input (CI) to the output result (CO). The latency can be determined according to the specifications of the system and device. All examples assume a waiting time of one clock cycle between the input and the output. Therefore, there is a one-cycle difference between two adjacent memory devices when the input data is captured. However, it should be understood that the clock cycle latency may be smaller, such as half a cycle, or larger, such as more than two cycles. In any case, the memory device gets the input stream with a latency delay.

Figure 6 shows another system with an architecture featuring serially connected devices, where the page buffer is used as a mirror backup for the data. Referring to FIG. 6, system 210 uses page buffer 214-2 as a mirror backup for data. The system 210 has a memory controller 211 and a plurality of memory devices 213-1, 213-2, 213-3, ..., And 213-15. The memory controller 211 has, for example, a data storage element 212 that is SRAM. The memory controller 211 also has a data processor 209, an output connection CIO for connecting to the first memory device 213-1 and an input connection COI for connecting to the last memory device 213-1. The memory devices 213-1, 213-2, 213-3, ..., and 213-15 have page buffers 214-1, 214-2, 214-3, and 214-15, respectively, and are of memory devices. Each has a memory cell (not shown). The memory controller 211 and the memory devices 213-1, 213-2, 213-3, ..., and 213-15 are interconnected by a link. A detailed example of the mirror backup operation in the system of FIG. 6 will be further described below.

In an exemplary system, a memory device that acts as a mirror backup for a given memory device is statically defined. Specific examples of such static definitions are defined in the table below. In this table, for a given device with an even device address, the device acting as a mirror backup for this given device is one with an address one greater than the address of this given device. Yes (see Table 2), for a given device with an odd number of addresses, there is one device that acts as a mirror backup for this given device than the address of this given memory device. It is assumed to be a device with a small address (see Table 3).

Table 2: For even device addresses, the static association between the specified target address (DAt) and the mirror address (MA) is defined by MA = DAt + 1.

<tables num="2"><img file="JP2010519641A_D0002.tif" /></tables>

Table 3: For odd device addresses, the static association between the specified target address (DAt) and the mirror address (MA) is defined by MA = DAt-1.

<tables num="3"><img file="JP2010519641A_D0003.tif" /></tables>

In the examples defined in Tables 2 and 3 above, the designated target device and mirror device share a common address except for the LSB (least significant bit). More generally, the relationship between a designated target device and a mirror device is used, in some cases, to efficiently address two devices without the need to send two separate commands.

This example applies to the definition of mirror backup devices in Tables 2 and 3, where the new mode of operation is called "ignore LSB mode", where all devices have the address of each input command except the LSB. Compare all bits with the corresponding bit in the device address of the device (ie, all bits except the LSB). In such a mode, both the device with the given specified target address and the appropriate mirror device will process the command. Depending on the implementation, a command is first sent to turn on the ignore LSB mode. This can be done using an address that is processed by all devices, called the broadcast address. This is followed by a command to load the data into the page buffer, which results in the data being loaded into the page buffers of both the designated target device and the mirror device. After this, the ignore LSB mode is turned off again and a command is sent to write the contents of the page buffer of the specified target device to core memory, which is processed only by the specified target device. In another example, another OP code is defined indicating the ignore LSB mode for that command. In other embodiments, the ignore LSB mode is active for at most one command that follows, so it is not necessary to turn off the ignore LSB mode when such a command is issued. In other embodiments, another field of command is used to indicate the ignore LSB mode.

Next, this example will be described with reference to FIG. 6. In FIG. 6, the memory controller 211 uses the page buffer 214-2 of the memory device 213-2 as a mirror backup of the memory device 213-1. It is assumed that the decision was made to write data to a memory cell. In this example, the memory controller 211 issues a single write command to transfer the data from the data storage element 212 to the page buffer 214-1 of the first memory device 213-1 and the second memory device 213-2. It differs from the example in Figure 5 in that it loads into both page buffers 214-2. This is done during "ignore LSB mode", where each memory device ignores the LSB of the target device address found in a single write command. In this example, the memory controller 211 issues the "ignore LSB" command to all memory devices 213-1, 213-2, 213-3, ..., and 213-15 of each device connected in series. Send to notify that the LSB of the target device address of subsequent commands received should be ignored. The ignore LSB command is, for example, a "write link configuration register" command with an OP code of FFh and is sent to the broadcast address processed by all memory devices. Any suitable structure for such broadcast commands may be used, and more generally any suitable mechanism can be implemented to allow neglected LSB mode. As mentioned above, various examples have been provided.

When ignore LSB mode is enabled, a single target address selects two memory devices. For example, a page buffalo load command with a target address of "0000" is for a first memory device 213-1 with a device address (DA) of "0000" and a second memory device 2132 with a device address of "0001". It will be processed by both. Note that the first device 213-1 and the second memory device 213-2 have the same device address except for the LSB. One of the two memory devices 213-1 and 213-2 (for example, the first memory device 213-1) is used as the "designated target device" and the other memory device (for example, the memory device 213-2). ) Is used as a "mirror device" whose page buffer stores mirror program data. Data loading begins when the page buffer load command is issued. The page buffers 214-1 and 214-2 of the two selected devices 213-1 and 2132 store data in them. Loading of data into page buffers 214-1 and 214-2 is shown overall in 221 and 222. Prior to programming, the ignore LSB mode is reset and normal operation resumes with only one memory device selected at a time. This is accomplished, for example, by issuing another broadcasting command. The details of the exemplary timing of enabling and disabling the neglected LSB mode in system 210 are described below with reference to FIG.

FIG. 7 shows an exemplary timing diagram of the steps that enable and disable the LSB ignore mode in the system of FIG. With reference to FIGS. 6 and 7, the memory controller 211 outputs three signals: a clock signal CK, a command strobe input signal CSI, and a command input signal CI. Note that the CSI signal is asserted during the three stages, namely the first, second and third stages.

The first stage is shown in 281. The memory controller 211 sends a "ignore LSB" command to notify each memory device to ignore the LSB of the target device address of subsequent commands. This command contains broadcast DA and OP code to enable ignore LSB mode. Here, "FF" is assumed to be a broadcast address to which each memory device in each device connected in series will receive and process this command.

The second stage is shown in 282. Memory controller 211 sends a command to load data into page buffers 214-1 and 214-2 of the first two memory devices 213-1 and 213.2. This command includes a device identifier (ID) and burst data load instruction (CMD) for the first memory device 213-1. Since the neglected LSB mode was enabled, both the first and second memory devices 213-1 and 231-2 process commands and load data into their page buffers 214-1 and 214-2. ..

The third stage is shown in 283. The memory controller 211 issues a command to disable the ignore LSB mode. This ID is also the broadcast ID "FF".

When the ignore LSB mode is disabled, the memory controller 211 issues a page program command to transfer the data loaded in the page buffer 214-1 to the memory cell (not shown) of the first memory device 213-1. Program. In the example shown, the data is not programmed into the memory cell (not shown) of the second memory device 213-2. Instead, if page programming to the first memory device 213-1 fails, the data is kept in the page buffer 214-2 of the second memory device 213-2 as a mirror backup copy of the data. The second memory device 213-2 shall not be accessed for any core operation using page buffer 214-2. However, register-based commands such as status and configuration register read / write are possible. Other memory devices 213-3, ..., and 213-15 can be freely accessed.

FIG. 8 shows the system 210 of FIG. 6 which performs data recovery after a program failure. Next, referring to FIG. 8, the data path for data recovery is shown overall in 223. First, the program data in the mirror buffer 214-2 of the second memory device 213-2 is transmitted to the data storage element 212 of the memory controller 211, whereby the memory controller 211 is used for other purposes. Therefore, it becomes possible to recover the original program data that may not have been held in the data storage element 212. The program data recovered from the mirror buffer 214-2 is then sent to the new page address by executing the page buffer load and page program. This data may be directed to another page on the first memory device 213-1 or a page on another memory device. If it is another memory device, reloading the data into the two page buffers will start the process from scratch. Alternatively, the recovered data can be loaded into the page buffer of another memory device while the data loaded in the mirror buffer 214-2 can be maintained. Memory controller 211 constantly monitors failed pages and does not use them. In the example shown in FIG. 8, as shown in 224, the program data recovered from the mirror buffer 214-2 is sent to the page buffer 214-1 of another memory device 213-1.

The example shown above does not provide specific details of the memory device for performing the ignore LSB function. It should be understood that each memory device can be implemented with any suitable control circuit to perform the neglected LSB function. Specific implementations are shown below with reference to FIGS. 9 and 10 for exemplary purposes.

FIG. 9 shows a part of the memory devices connected in series shown in FIG. As shown in the figure, the command input signal S input from the previous device 154- (i-1) to the device 154-i._CiCan be transmitted to the next device 154- (i + 1).

FIG. 10 shows a memory device circuit for use within the memory device of each device connected in series. The memory device circuit implements the ignore LSB function. Referring to FIG. 10, the memory device 154-i has a clock input CLK for receiving the clock signal CK and a command strobe signal S._CSiCommand strobe input CSI to receive, data strobe signal S_DSiData strobe input DSI to receive, and command input signal S_CiHas multiple inputs, including a command input CI to receive. The memory device 154-i has a command strobe signal S._{CS (i + 1)}Command strobe output CSO for output, data strobe signal S_{DS (i + 1)}Data strobe output DSO to output, and command input signal S_{C (i + 1)}Has multiple outputs, including the command output CO to output to the next device 154-(i + 1).

Clock signal CK, command strobe signal S_CSi, Command input signal S_Ci, And data strobe signal S_DSiIs buffered by the input buffers 281, 282, 283 and 284, respectively. The buffered clock signal and command input signal are sent to the clock generator 264 which outputs the internally generated clock signal, that is, the ID clock signal Clkid, the OP code clock signal Clkop, the address clock signal Clkad, and the data clock signal Clkda. Is done. The ID clock signal Clkid, the OP code clock signal Clkop, the address clock signal Clkad, and the data clock signal Clkda are sent to the ID register 265, the OP code register 266, the address register 268, and the data register 269. Command input signal S_CiThe appropriate fields of the command are entered in ID register 265, OP code register 266, address register 268, and data register 269 in response to their respective clock signals. The OP code held in the OP code register 266 is sent to the OP code decoder 267 for decoding. The OP code decoder 267 outputs the 1-bit signal SIGB to the 1-bit register 276 and outputs the multi-bit (m-bit, for example, 3-bit) decoded OP code signal SDOP to the core logic and storage circuit 285. The core logic and storage circuit 285 also receives a buffered data strobe signal.

Command input signal S_CiIs latched by D-FF 251, its output is also buffered, and the command input signal S is transferred to the next memory device 154- (i + 1)._{C (i + 1)}To generate.

The memory device 154-i receives the n-bit output of the ID register 265 and the n-bit contents of the device ID register 273 as inputs to hold the value of the device address (DA). A logic circuit 272 is provided. The XNOR logic circuit 272 performs n-bit width XNOR operations between the n-bit output of ID register 265 and the n-bit contents of device ID register 273, and produces n-bit outputs, n XNOR gates. Have. The LSB of the n-bit output of the XNOR logic circuit 272 is input to one input of the OR gate 274, and the remaining bits of the n-bit output of the XNOR logic circuit 272 are input to the AND logic circuit 275. A 1-bit register 276 for registering the "ignore LSB enable bit" (in the signal SIGB) from the OP code decoder 267 is provided. The output of the 1-bit register 276 is input to the OR gate 274 as a second input, and the output of the OR gate 274 is input to the AND logic circuit 275 as another input. The operation of these components will be described below.

In operation, the memory device 154-i uses the command input signal S._CiReceive the command in. Command strobe signal S_CSiBased on the timing of the clock signal CK and the clock signal CK, the clock signal generator 264 generates an internal clock signal for properly latching the contents of the command to the appropriate register. More specifically, the ID register 265 registers the ID of the command. The OP code register 266 registers the OP code. The address register 268 registers the column / row address. The data register 269 registers arbitrary data included in the command. Further, the OP code decoder 267 receives the command registered in the OP code register 266 and decodes it. The buffered clock signal is supplied to the D-FF in the circuit (clock signal path is not shown).

If this command contains a broadcast DA or is addressed to a particular device, the OP code is decrypted and processed by this device. For broadcast DA, all devices are assertable and ready to receive commands. Upon receiving the command to enter the ignore LSB mode determined by the OP code decoder 266, the 1-bit register 276 is set and therefore the "ignore LSB enable bit" is set to enable the LSB ignore mode.

The ID register 265 outputs the registered DA, which is the target DA, in parallel with the n-bit data. The XNOR logic circuit 272 compares the target DA (represented by the ID number included in the command) with the device ID held in the device ID register 273 on a bit-wise basis. If the target DA and device ID are the same, the output of the XNOR logic circuit 272 is all "1". The LSB of the comparison value is sent to the OR gate 274, and the other bits are sent to the AND logic circuit 275. The LSB of the comparison value being "high" is sufficient for the output of the OR gate 274 to be "high". The OR gate 274 is also sent the "ignore LSB enable bit" of the 1-bit register 276. The "ignore LSB enable bit" of the 1-bit register 276 is also "high", which is sufficient for the output of the OR gate 274 to be "high". Therefore, if the "ignore LSB enable bit" of the 1-bit register 276 is high, it does not matter whether the LSB of the target DA matches the LSB of the device ID. Rather, the non-LSB bits are the problem. The AND logic circuit 275 outputs an ID match signal 277 indicating whether or not a match exists between the target DA and the device ID. This is true if all N inputs to the AND logic are high. In neglected LSB mode, this is true if the other (n-1) bits except the LSB match in neglected LSB mode. This is true if all n bits match when not in neglected LSB mode. The ID match signal 277 from the AND logic circuit 275 determines whether the memory device 154-i executes the command. Upon receiving a command to exit ignore LSB mode, the 1-bit register 276 is cleared. The ID matching signal 277 is supplied to the core logic and the storage circuit 285, and the AND gate 278. The output of 1-bit register 276 is in

When there is no match between the target DA and the device ID, the ID match signal 277 is "Low" and the multiplexer 254 is selected for its "0" input. Therefore, the latched command input signal is the command input signal S._{C (i + 1)}Is supplied to the next device 154- (i + 1). Also, the latched command strobe signal is also the command strobe signal S._{CS (i + 1)}Is supplied to the next device 154- (i + 1) via the multiplexer 256. Therefore, there is no ID match, device 154-1 is not the target device, and the command input signal S_CiAnd command strobe signal S_CSiIs transferred to the next device 154-(i + 1). When a data strobe signal is input (for example, in data read mode operation), the latched data strobe signal is the data strobe signal S, regardless of the status of the ID match signal 277._{DS (i + 1)}Is supplied to the next device 154- (i + 1) via the multiplexer 255. If no ID match exists, the core logic and storage circuit 285 will not be activated.

When a match exists between the target DA and the device ID during ignore LSB mode (ie, when the output of 1-bit register 276 is "high"), the ID match signal 277 is "high" and the core logic and The storage circuit 285 is activated. However, the output signal of the inverter 279 is "low" and the "0" inputs of the multiplexers 254 and 256 are selected. The input signal is the command input signal S_{C (i + 1)}Is supplied to the next device 154- (i + 1). After all, the command strobe signal is the command strobe signal S._{CS (i + 1)}Is supplied to the next device 154- (i + 1).

In non-negligible LSB mode, when a match exists between the target DA and the device ID (ie, when the output of 1-bit register 276 is "low"), the ID match signal 277 is "high" and the core logic and The storage circuit 285 is activated, the decoded OP code of the decoded signal SDOP from the OP code decoder 267 is executed, and it operates according to a command command. The output signal of the inverter 279 is high and the AND logic output signal of the AND gate 278 is high. The "1" input for multiplexers 254 and 256 is selected. If the instruction is a data read, the core logic and storage circuit 285 executes the read command and reads data from the memory (not shown) in it according to the row and / or column addresses. The output data DATAout from the core logic and storage circuit 285 is the command input signal S._{C (i + 1)}Is supplied to the next device 154- (i + 1).

The example presented above shows how a single command can be processed when two memory devices have the same device address except for the minimum significant bit. This is done while each memory device is in ignore LSB mode. More generally, each embodiment of the invention allows two or more memory devices to process a single command based on the target address of a single command. For example, in other embodiments, each memory device enters a multi-address detection mode. This can happen, for example, when the memory controller broadcasts a first message instructing each memory device to enter multiple address detection mode. In multi-address detection mode, upon receiving a command with a destination address different from the device address, the memory device conditionally processes the command based on the destination address. After a while, the memory device exits multi-address detection mode. This can happen, for example, when the memory controller broadcasts a second message instructing each memory device to exit multiple address detection mode. The broadcast message for entering and exiting multi-address detection mode is, for example, a write link configuration register command containing the op code of FFh.

There are many ways a memory device can conditionally process commands based on its destination address. Depending on the implementation, the memory device maintains the identification of the alternate device address. If the target device address of the received command matches the alternate device address, the memory device processes the command. In other implementations, the memory device conditionally processes the command if the destination address is different from the device address in the default way. For example, a memory device processes a command if the destination address differs from the device address by only a single default bit. A single default bit can be the least significant bit, an example of which has been shown above. Alternatively, a single default bit is some other bit.

FIG. 11 shows a method of program operation using mirror backup. This method can be implemented by a memory controller, such as the memory controller 211 shown in FIG.

Referring to FIGS. 6 and 11, in step 311 the memory controller 211 ignored LSB to all memory devices 213-1, 213-2, 213-3, ..., and 213-15 connected in series. Send a command telling you to ignore the LSB of the received target device address. In step 312, memory controller 211 sends the target device address as part of the command to write to the page buffer. In a specific example, the target device address is assumed to be "0000", that is, the device address of device 213-1 in FIG. Using that address, both devices 213-1 and 2132 will process the command in ignore LSB mode. More generally, for a given target device address, two of each device will process the command. The command to write to the page buffer contains the data to write. If the device addresses match, the data is latched by both memory device 213-1 and memory device 213.2. Therefore, the transmitted data is only loaded into the page buffers of both devices (step 312). This is done using a single command.

The memory controller 211 was then found in the commands it received, sending "normal DA set" commands to all memory devices 213-1, 213-2, 213-3, ..., and 213-15. Notify that the LSB of the target device address is no longer ignored (step 313). The memory controller 211 then initiates page programming for the specified device by sending the addressed page program to the specified device (step 314). If the memory controller 211 determines that the page programming was successful (yes in step 315), the process ends. The page programming decision is made by reading the program status from the page buffer. If the memory controller 211 determines that the program has failed (if "no" in step 315), the memory controller 211 reloads the program data from the page buffer of the mirror memory device 213-2 (step 316). This program data is locally stored in the data storage element of the memory controller.

The memory controller 211 then loads the program data back into the page buffer of the specified memory device in step 317. The process continues in step 314 by retrying to program the data into the memory cells of the specified memory device, the details of which have been shown above. In this example, it is assumed that another attempt is made to program the data in the same memory device. Alternatively, the data can be programmed into a memory cell of another memory device. This example also assumes that the mirror backup copy is kept in the same location (device 213-2 in this example) until the page program operation completes successfully. Alternatively, the mirror backup copy can be made at another location.

In some cases, the systems described herein have been implemented using flexible modular command structures and have already provided exemplary details. Further exemplary details are given in this section with reference to Figures 12-20. It should be understood that the details presented in this section are very specific for exemplary purposes only.

Figure 12 is a table of exemplary commands with modular commands set for flash memory in byte mode. This table includes the following 15 actions. That is, page read, copy page read, burst data read, burst data load start, burst data load, page program, block erase address input, page pair erase address input, erase, operation stop, device status read, device information register read. , Link configuration register read, and link configuration register write (device-specific) and link configuration write (broadcast). Each action has a command containing the device address (DA) (1 byte) and action (OP) code (1 byte). Some commands include row addresses (3 bytes) and column addresses (2 bytes), and some commands include input data (1 to 2112 bytes). "X" is "0h" with respect to "bank 0". The "X" is "1h" with respect to "bank 1", where it is assumed that each device has two memory banks for this embodiment. More generally, each device has at least one memory bank. For the last command in the table, the write link configuration (broadcast), the device address is set to "FFh" to indicate the "broadcasting" command.

FIG. 13 is an exemplary operation table. This table contains modes for each of multiple combinations of / RST (reset signal complement), / CE (chip enable signal complement), CSI (command strobe input), and DSI (data strobe input). These modes include command data packets, read data packets, NOP (NO Operation), standby, and reset.

All commands, addresses, and data are shifted in and out of memory devices, including the most significant bit (MSB). The command input (CI) signal is sampled at the positive or negative clock edge (ie, at the intersection of the CK and / CK clocks) while the command strobe input (CSI) signal is "high". Each command contains a 1-byte device address (DA) and 1-byte OP code, and / or, if necessary, a column address / row address / data entry byte. When the CSI transitions to the logic "high", the 1-byte DA (device address) is shifted in to the DA register, and then the 1-byte OP code is shifted in to the OP code register. The most significant bit (MSB) then begins with the CI signal, and each bit is latched at the intersection of the CK and / CK clocks while the CSI is in the logically high state. However, every input sequence in byte mode starts at the rising edge of the clock CK (= falling edge of CK). Depending on the command, the OP code is followed by address bytes, data bytes, or both, or neither, as shown in Figure 12. In this example, the address cycle has a 2-byte column address and a 3-byte row address. FIG. 14 shows an exemplary command and address format definition, including the position of each bit.

For memory devices connected in series, a special device address (= FFh) is assigned to the "broadcast" operation. More generally, addresses defined for broadcast mode operation can be defined for each specific implementation. This "broadcast device address" may be used in any command. However, it is not recommended to use the broadcast device address (FFh) with the "read type" command because the read data from the last device is the only valid output data.

In some implementations, commands, addresses, and data all share one or more of the same pins, so the signal bus on the modular command flash device is fully multiplexed. The logical high state of a CSI signal validates a command input (CI) signal, which can be an n-bit wide signal containing multiplexed command / address / data information for a memory device. If the CSI signal remains in the logical low state, the device ignores the signal input from the CI pin. Command input sequences are typically 1-byte DA (device address) latch cycles, 1-byte command latch cycles, address latch cycles (= 3 bytes for row addresses, or 2 bytes for column addresses) and / or 2, It consists of a data input latch cycle of up to 112 bytes. In 1-bit link mode, a 4-clock cycle at DDR (double data rate) produces 1 byte of a series packet. In 2-bit link mode, a 2-clock cycle at DDR (double data rate) produces 1 byte of a series packet. In 4-bit link mode, one clock cycle at DDR (double data rate) produces one byte of a series packet. After the CSI has performed the HIGH to LOW transition, any set of commands may be followed by two additional CK and / CK transitions. In some embodiments, an additional number of CK and / CK transitions are used after the CSI transition to low, which in number is equal to 2 + # of devices in the architecture in which each device is connected in series. All input sequences defined in Figure 12 are "byte-based", which means that CSI and CI must be enabled in a unit with 8 latch cycles (= 4 clock cycles at double data rate). To do. If the CSI makes a HIGH-to-LOW transition before the byte completes, the corresponding command and / or address sequence will be ignored by the device. For data input sequences, the last incomplete byte of the input data will be ignored, but one or more previous complete bytes of the input data will be valid.

FIG. 15 is an exemplary timing diagram showing the basic input timing. Clocks for CK and / CK when all DA / command / address / data inputs are constantly asserted through one or more CI ports and / CE is "low" and CSI signal is "high". Are captured at the intersection of. The input data is shifted into the memory device, the most significant bit (MSB) is first located on the CI, and each bit is latched at the intersection of the CK and / CK clocks. The bitstream input sequence is shown in Figure 16. As shown, every input sequence in byte mode starts at the rising edge of the clock CK. Any input with incomplete bytes will be ignored.

FIG. 17 is an exemplary timing diagram showing the basic output timing. When / CE is "low" and the DSI signal is "high", the output of the command output (CO) is synchronously shifted out at the intersection of the CK and / CK clocks. FIG. 18 shows an exemplary output sequence in byte mode. The output data is shifted from the memory device, the most significant bit (MSB) is located first on the CO signal, and each bit is synchronized at the intersection of the CK and / CK clocks. The DSI signal is activated relative to the rising edge of the CK so that any output sequence in byte mode has a rising edge of the CK (= tOL) with a read latency of 1 clock, as shown in Figure 17. Start at.

Two typical commands that characterize modular commands, namely the page read (DA &amp; 0Xh) and burst data read (DA &amp; 2Xh) commands, are described below. FIG. 19 shows a flow diagram using these commands, and FIG. 20 shows an exemplary command sequence.

Referring to FIG. 19, in step 411, the memory controller issues a page read (DA &amp; 0Xh) command to the command register via CI with a 3-byte row address to enter page read mode. At step 412, issuing DA &amp; 0Xh to the command register begins the address latch cycle. Next, a 3-byte row address is entered. When the address latch cycle is complete, the internal page read operation begins. 2,112 bytes of data in the selected page are detected and transferred to the page buffer in less than tR (transfer time from cell array to page buffer). At step 413, the status register can be inspected. After tR, in step 414, read burst data (DA) with a 2-byte column address. The &amp; 2Xh) command can be issued (discussed in more detail below), then the DSI signal is enabled through the CO until the DSI signal is low, and the data in the page buffer from a given column address. Can be read. If the user wants to monitor the internal page read status to determine if the transfer from the cell array to the page buffer is complete, the device status read (DA &amp; D0h) command can be issued. Modular command flash has an 8-bit status register that the software can read while the device is operating.

Read page, the page program and block erasure takes a long time The core access operation, such as to, those processing time varies with variations in PVT (Process / Voltage / Temperature). Therefore, by issuing the core access command, the user can monitor the status of each operation after asserting the command without interfering with the internal operation. Another purpose of the status register is to check if page programs and block erases are performed without failure. If it fails, the memory controller determines the new row position, and the memory controller issues a new command containing the new row address to write to the old row position and write the same data that failed to write. .. Without monitoring the status register, the memory controller does not know that the program and erase operations are running without failure.

After the device status read (DA &amp; D0h) command, the DSI is used to read all 8-bit status from the status register until the DSI goes low. After the burst data read (DA &amp; 2Xh) command is issued and then the DSI goes high, the data is output from the first column address in step 415 as a result of the serial output timing shown in Figure 20. The column address will be automatically increased while the data is being output. At step 416, ECC generation takes place. When ECC is verified in step 417, the page read is complete. Otherwise, you will get an error in step 418.

The burst data read (DA &amp; 2Xh) command described above allows the user to read data in the page buffer from a given column address within the selected page size while the DSI is high. Will be able to be specified. Burst data read mode is enabled after a normal page read (DA &amp; 0Xh) command and page loading time (= tR). You can issue burst data read (DA &amp; 2Xh) commands without any restrictions within the page. Any burst data read command can have the same or different column address as the previous burst data read command. Only the data on the current page buffer can be read. If you want to read a different page, you must issue a new read page (DA &amp; 0Xh) command. Then, after tR, you can issue a new burst data read (DA &amp; 2Xh) command to access the new page data.

In the above embodiments, for the sake of brevity, each element of the device and each circuit are connected to each other as shown in each figure. In practical applications of the present invention, elements, circuits, etc. may be directly connected to each other. Similarly, elements, circuits and the like may be indirectly connected to each other via other elements, circuits and the like necessary for the operation of the memory device or device. Thus, in the actual configuration of devices and devices, the elements and circuits are directly or indirectly coupled or connected to each other.

Each of the aforementioned embodiments of the present invention is intended to be merely exemplary. Specific embodiments may be modified, modified, and modified by one of ordinary skill in the art without departing from the scope of the invention as defined solely by the claims herein.

150 system 150 151 Memory controller 151 151-1 ~ M Memory device 152 data storage 153 processor 158-1 ~ M Page buffer 159-1 ~ M Flash memory cell 109-1 ~ 4 Command format 112-2 programming 112-3 Verification 112-4 In case of success 112-5 In case of failure 120 First memory device 121 flash memory cell 122 page buffer 126 device controller 127 Second memory device 128 flash memory cell 129 page buffer 130 device controller 139 Input connection 140 output connection 141 Input connection 142 Output connection 190 system, page buffer 191 memory controller 193-1 ~ 15 Memory device 192 Data storage element 194 page buffer 196 page buffer 198 page buffer 203 data processor 209 data processor 210 system 211 memory controller 212 Data storage device 213-1 ~ 15 Memory device 214-1 ~ 15 page buffer 254 multiplexer 256 multiplexer 264 clock generator 265 ID register 266 OP code register 267 OP code decoder 268 Address register 269 data register 272 Exclusive Negative OR Logic Circuit 273 Device ID register 274 OR gate 275 AND logic circuit 276 1-bit register 277 ID match signal 278 AND gate 279 Inverter 281 First stage, input buffer 282 Second stage, input buffer 283 Third stage, input buffer 284 input buffer 285 Core logic and storage circuit