Circuit for clamping current in a charge pump

As will be appreciated by those skilled in the art, charge pumps can be characterized as circuits that use capacitors to produce either higher or lower voltages. Charge pumps are used in a wide variety of applications, for example with applications involving delay lock loops (DLLs) and phase lock loops (PLLs).

With respect to the PLL, the charge pump can be used to supply the control voltage applied to the voltage controlled oscillator (VCO). Typically, a PLL comprises a phase detector, a loop filter coupled to the output of a charge pump, an amplifier, and a VCO interconnected in a known manner to form a feedback system. The charge pump converts the logic level pulse generated by the phase detector into a current pulse supplied to the loop filter. The loop filter integrates the current pulse to generate a control voltage for the VCO.

For DLLs, charge pumps can be used to supply control voltage to the DLL's voltage control delay line (VCDL). As will be appreciated by those skilled in the art, in certain types of equipment (eg, DRAM equipment), DLLs can be used to change the phase of a clock signal. In this case, the DLL includes a delay chain consisting of multiple delay gates connected in series (daisy chain).

In addition to applications involving DLLs and PLLs, for example, charge pumps are used in electronic circuits with accurately-controlled current sources / sinks for voltage regulation on filters or storage capacitors. Those skilled in the art will appreciate that there are other uses.

According to one embodiment, a method of clamping current in a charge pump is disclosed. The charge pump includes a switching circuit and a capacitor. The charge pump forms the first and second paths. For each of the first and second paths, (i) current is supplied to the capacitor and (ii) current is supplied from the capacitor through the selected one. Within the current from at least one of the plurality of transistors in the switching circuit, at least one parasitic spike is generated while the at least one transistor is switched off. After a short period of time, the at least one parasitic spike disappears. The method of the present invention includes the step of supplying at least one control signal for switching off the at least one transistor when the value changes from the first value to the second value. In the same method, the value of the at least one control signal is set so that the at least one parasitic spike is only partially transmitted through one of the selected ones of the first and second pathways. It also includes the step of forming an additional path for the current from the at least one transistor when the value changes from one to a second. The method also includes the step of eliminating the additional pathway after the additional pathway has been formed for the short period of time.

According to another embodiment, a circuit that clamps a current in a charge pump is disclosed. The charge pump includes a switching circuit and a capacitor, and the charge pump forms first and second paths. For each of the first and second paths, i) current is supplied to the capacitor and ii) current is supplied from the capacitor through the selected one. Within the current from at least one of the transistors in the switching circuit, at least one parasitic spike is generated while the at least one transistor is switched off. The circuit of the present invention comprises first and second pairs of transistors, each of which supports on and off states and includes control electrodes so that transitions between the states can be controlled. One of the first pair of transistors is electrically connected to the first transistor in the switching circuit transistor via a first node. The first path extends through the first node. One of the second pair of transistors is electrically connected to the second transistor in the switching circuit transistor via a second node. The second path extends through the second node. The circuit of the present invention also includes a first delay introduction inverter circuit and a second delay introduction inverter circuit, and each of the first inverter circuit and the second inverter circuit is a pair of transistors. The signal input to one of the control electrodes is used as an input signal, and the delayed output signal is supplied to the other control electrode of each of the pair of transistors. At the moment the switch to off occurs, both the input signal and the delayed output signal have values that create the on state. At least one of the first and second pair of transistors has been switched off so that the at least one parasitic spike is only partially transmitted through any path towards the capacitor. From at least one of the transistors

According to another embodiment, a device including a charge pump is disclosed. The charge pump includes a plurality of switching transistors, a current clamp circuit, and a capacitor. The charge pump forms first and second paths. For each of the first and second paths, i) current is supplied to the capacitor and ii) current is supplied from the capacitor through the selected one. One of the switching transistors is located in one of the selected paths of the first and second paths. The switching transistor produces parasitic spikes in the current when switched off. The parasitic spike disappears after a short period of time. It has an input that supplies a control signal that switches the switching transistor off when that value changes from a first value to a second value. In the current clamp circuit, (i) the value of the control signal is such that the at least one parasitic spike is only partially transmitted through said one of the first and second paths. When changing from the first value to the second value, an additional path is formed for the current from the switching transistor, and (ii) the additional path is eliminated after the additional path has been formed for the short period of time. Let me.

According to another embodiment, a method of clamping current in a charge pump is disclosed. The charge pump includes a plurality of switching transistors, a current clamp circuit, and a capacitor. The charge pump forms first and second paths. For each of the first and second paths, i) current is supplied to the capacitor and ii) current is supplied from the capacitor through the selected one. Within the current from at least one of the transistors in the switching circuit, at least one parasitic spike is generated while the at least one transistor is switched off. The method of the present invention includes the step of supplying at least one control signal for switching off the at least one transistor when the value changes from the first value to the second value. The method of the invention is the value of the at least one control signal such that the at least one parasitic spike is only partially transmitted through a selected one of the first and second pathways. Also includes the step of forming an additional path for the current from at least one of the transistors when the first value changes to the second value. The additional path is provided to at least one of the transistors via a first node. The value of the voltage at the first node changes while the at least one transistor is switched off. In the method of the present invention, after at least one of the transistors is switched off, the leakage current flowing through the transistor on one of the first and second paths is minimized with reference to the capacitor. Also includes the process of making.

The step of minimizing the leakage current flow preferably comprises preventing the voltage at the first node from moving away from a fixed voltage value while the at least one transistor is switched off.

It is preferable that the method of the present invention further includes a step of instantaneously eliminating the additional route after the additional route is formed.

According to another embodiment, a device including a charge pump is provided. The charge pump includes a plurality of switching transistors, a current clamp circuit, and a capacitor, and the charge pump forms first and second paths. For each of the first and second paths, i) current is supplied to the capacitor and ii) current is supplied from the capacitor through the selected one. One of the switching transistors is located in one of the selected paths of the first and second paths. The switching transistor produces parasitic spikes in the current when switched off. The circuit can supply a control signal that turns off the switching transistor when its value changes from a first value to a second value. The current clamp circuit has the first control signal value such that (i) the parasitic spike is only partially transmitted through the one of the first and second paths. When the value changes to the second value, it forms an additional path for the current from the switching transistor. The additional path is provided to the switching transistor via the first node. The value of the voltage at the first node changes while the switching transistor is switched off. The current clamp circuit also (ii) collects leakage current through the transistor on one of the first and second paths after the at least one transistor in the transistor has been switched off. To the minimum.

Minimizing the leakage current flow preferably includes preventing the voltage at the first node from moving away from a fixed voltage value while the at least one transistor is switched off.

The charge pump further comprises first and second FETs, both of which are electrically connected to the capacitor, the first FET being arranged along the first path and the second FET being the second FET. It is preferably arranged along the path of 2.

The current clamp circuit comprises two transistors connected in series and installed along the additional path, and the current clamp circuit connects the first node to the two when the additional path is formed. It is preferred to connect to a second node between the transistors.

The charge pump also has a V in the capacitor._cForming a node, the current clamp circuit is the V._cIt is preferred to include a repeater that produces a replica of the voltage at the node, the replicated voltage being coupled to the first node once the additional path is formed.

Therefore, it would be advantageous to improve the circuit that clamps the current in the charge pump.

<figref num="1">FIG. 1 is a schematic circuit diagram of a charge pump.</figref><figref num="2">FIG. 2 is a diagram showing an example of the waveform of the current passing through the specific path of the circuit of FIG. 1 over time.</figref><figref num="3">FIG. 3 is a schematic circuit diagram of another charge pump similar to the charge pump shown in FIG. 1 in some respects, but with an additional static clamp.</figref><figref num="4">FIG. 4 is a schematic circuit diagram of another charge pump that is similar in some respects to the charge pump shown in FIG. 1 but further comprises a clamp according to one embodiment.</figref><figref num="5">FIG. 5 is a schematic circuit diagram of another charge pump with the clamp according to the second embodiment.</figref><figref num="6">FIG. 6 is a schematic circuit diagram of another charge pump including the clamp according to the third embodiment.</figref><figref num="7">FIG. 7 is a schematic circuit diagram of another charge pump including the clamp according to the fourth embodiment.</figref><figref num="8">FIG. 8 is a schematic circuit diagram of another charge pump including the clamp according to the fifth embodiment.</figref><figref num="9">FIG. 9 is a schematic circuit diagram of another charge pump including the clamp according to the sixth embodiment.</figref><figref num="10">FIG. 10 is a schematic circuit diagram of another charge pump including the clamp according to the seventh embodiment.</figref><figref num="11">FIG. 11 is a schematic circuit diagram of another charge pump including the clamp according to the eighth embodiment.</figref><figref num="12">FIG. 12 is a schematic circuit diagram of another charge pump including the clamp according to the ninth embodiment.</figref><figref num="13">FIG. 13 is a schematic circuit diagram of another charge pump including the clamp according to the tenth embodiment.</figref><figref num="14">FIG. 14 is a graph of the signal applied to the gate of the transistor of the clamp shown in FIG. 4, and a waveform diagram of another example. The waveform diagram shows the current passing through a specific path of the circuit of FIG. 4 over time. ..</figref><figref num="15">FIG. 15 is a schematic circuit diagram of another charge pump, which is conceptually similar to the charge pump of FIG. 4, but consists of a bipolar transistor instead of a FET.</figref><figref num="16">FIG. 16 is a schematic circuit diagram of another charge pump, which is conceptually similar to the charge pump of FIG. 5, but consists of a bipolar transistor instead of a FET.</figref>

In the detailed description of the following embodiments, many of the illustrated circuits and circuit components are of the type that perform known operations on electronic signals. Those skilled in the art will have knowledge of alternative circuits or circuit components that are recognized as equivalent. Because they do the same thing for the same signal.

With reference to the drawings, FIG. 1 is a schematic circuit diagram of the charge pump 100. In some examples, the charge pump 100 is part of a memory circuit (eg DRAM) and is used in the PLL to control the voltage applied to the VCO. In another example, the charge pump 100 may also be part of some kind of memory circuit and is used, for example, in a DLL rather than a PLL. In yet another example, the charge pump 100 may be part of a clock management / distribution circuit, memory interface, FPGA module, and the like.

The charge pump 100 includes a capacitor 102. The charge pump 100 also includes a switching circuit, which in this embodiment comprises a MOSFET switching transistor 104 and an NMOS switching transistor 108. The switching transistor 104 is switched according to the pump-up control signal PU applied to the gate 112 of the transistor. The switching transistor 108 is switched according to the pump down control signal PD applied to the gate 116 of the transistor.

For the illustrated charge pump 100, either the switching transistor 104 or the switching transistor 108 is the output node V._cNot directly connected to. Those skilled in the art will have knowledge of circuits in which the switching transistor is directly connected to the output node, but one of the drawbacks of such a configuration is when there is a signal transition at the gate of the switching transistor. , The point is that parasitic noise is introduced into the output node.

In this embodiment, a MOSFET transistor 120 and an NMOS transistor 124 to which a bias voltage is applied to the gate are connected between the two switching transistors 104 and 108, respectively. In some examples, current mirrors are used to provide a voltage reference source that supplies the bias voltage. V to gate 128_biaspTransistor 120 to which is applied has a current I_pIs capable of flowing through the channel of the transistor, and is supplied to the node 130 when the switching transistor 104 is turned on according to the request of the signal PU applied to the gate 112. As will be appreciated by those skilled in the art, the gate is the control electrode of the FET, which allows control of the transition between the on and off states of the FET. In other types of transistors, the control electrode is not always referred to by the name gate. For example, in a bipolar transistor, the term commonly used when referring to the control electrode of a bipolar transistor is "base".

It can be seen that the switching transistor 104 is switched on when the signal PU changes from logic "high" to logic "low". On the contrary, when the signal PU changes from logic low to logic high, the switching transistor 104 is switched off. On the other hand, V at gate 132_biasnThe transistor 124 to which is applied has a current I when the switching transistor 108 is turned on according to the request of the signal PD applied to the gate 116._nIs in a state where it can flow through the channel of the same transistor so that is discharged from the node 130. It can be seen that the switching transistor 108 is switched on when the signal PD changes from logic low to logic high. On the contrary, when the signal PD changes from logic high to logic low, the switching transistor 108 is switched off.

For convenience of reference, it would be more accurate to describe the charge pump 100 as having both a source and a sink. Transistors 112 and 120 are part of the source section. Transistors 116 and 124 are part of the sink (those skilled in the art will appreciate that the "sink" is instead referred to as the "drain").

Figure 2 shows the current I_pAnd I_nIt is a figure which shows an example of the waveform of. In the graph of Figure 2, time t₁, T₂, And t₃Corresponds to the time in which one or more of the switching transistors 104 and 108 are switched on or off. Especially the time t₁Switching transistor 108 turns on near₂Switching transistor 104 turns on near₃Both switching transistors 104 and 108 are switched off in the vicinity of.

Time t₃Refer to the current I when the switching transistor 104 is switched off._pIt can be seen that the upward spike 204 occurs in. Also time t₃In, when the switching transistor 108 is switched off, the current I_nA downward spike 208 occurs in. The current spikes 204 and 208 can be explained as follows. When either switching transistors 104 or 108 are switched off, they generate current as a result of switching signal coupling due to gate-drain capacitance. This current is already added to the current flowing through the transistor. In the charge pump of FIG. 1, this added current has nowhere to go except for each of the neighboring transistors 120 or 124.

As will be appreciated by those skilled in the art, current spikes 204 and 208 will cause DLL / PLL loop errors, which will result in phase offsets. At least one of the reasons is that the current spike 204 is not symmetrical with the current spike 208. Current tailouts 216 and 220 can also cause DLL / PLL loop errors. As will be appreciated by those skilled in the art, the presence of current tailouts 216 and 220 causes the transistors 120 and 124 to be shut off gradually rather than rapidly (rather than the voltage at the source of the transistors 120 and 124 being rapidly). This is because it gradually transitions to the shut-off voltage value).

FIG. 3 is a schematic circuit diagram of another charge pump 300. The charge pump 300 is similar in some respects to the charge pump of FIG. 1, but further comprises a static clamp 304 to provide a path for off-switch currents from the switching transistor 104 or 108. .. The illustrated static clamp 304 includes an NMOS transistor 308 and a MOSFET transistor 312. The drain 316 of the transistor 308 is electrically connected to the switching transistor 104 via the node 320. With respect to the transistor 312, the drain 324 of the transistor is electrically connected to the switching transistor 108 via the node 328.

The static clamp 304 of the charge pump 300 provides an additional path for the current while the switching transistor 104 is switched off, so that the current along the path between the switching transistor 104 and the capacitor 102. Current along the path between switching transistor 108 and capacitor 102 by reducing spikes and also providing an additional path for current while switching transistor 108 is switched off. It works to reduce spikes. The magnitude of the current spikes can be much smaller than the illustrated current spikes 204 and 208 in terms of the design impact that the static clamp 304 can have on the waveform shown in FIG. Also, current tailout can be reduced.

The constraint when using the static clamp 304 in the charge pump 300 is V_cBut V_biaspUpper limit and V defined by_biasnThe point is that it is limited to the range between the lower limit defined by. As understood by those skilled in the art, this V_cThe limitation is that transistors 308 and 312 are still on after switching transistors 104 and 108 are switched off. In particular, the voltage at node 320 reaches the ground potential once the switching transistor 104 is switched off. If V_cIs V_biaspWhen greater than, the current is the current I_p''The transistor 120 flows in the direction opposite to the direction indicated by the arrow indicating (V)._cThe larger the voltage value of, the larger the leakage current), the current I_p''Is V_cHas an undesired effect on the value of. Similarly, the voltage at node 328 is V once the switching transistor 108 is switched off._ddTo reach. If V_cIs V_biasnWhen it gets smaller, the current becomes the current I_n''''The transistor 124 flows in the direction opposite to the direction indicated by the arrow indicating (in this case, V)._cThe smaller the voltage value of, the larger the leakage current), so the current I_n''''Is V_cHas an undesired effect on the value of.

Now refer to Figure 4. FIG. 4 is a schematic circuit diagram of another charge pump 500. The charge pump 500 is similar to the charge pump of FIG. 1 in some respects, but further comprises a clamp 504 according to one embodiment. Like the static clamp 304 (FIG. 3), the clamp 504 can provide an additional path for off-switch currents from either switching transistors 104 or 108. However, unlike the static clamp 304, the clamp 504 is a V_biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 504 includes a pair of NMOS transistors 508 and 512, a pair of MOSFET transistors 516 and 520, a delay introduction inverter circuit (or inverter) 524, and another delay introduction inverter circuit 528. (For example, each of the inverters 524 and 528 can be realized by using a combination of well-known transistors such as a pair of NMOS and MOSFETs. Further, in FIG. 4, the delay introduction inverter circuit 524 and the delay introduction inverter circuit 528, respectively, can be realized. Is shown as only one inverter, but in one example you will find that a delayed introduction inverter circuit can have three or more real inverters instead of one.

It will be found that the optimum delay that can be introduced by the inverter circuit of the clamp according to the embodiment of the present invention varies depending on various factors. These factors include, for example, the size of the transistor that provides an additional path for the current and the size of the transistor used to implement the inverter circuit.

In the illustrated embodiment, half of the clamp 504 with the transistor 508, the transistor 512, and the inverter 524 is operational interlocked with the switching transistor 104, and the clamp with the transistor 516, the transistor 520, and the inverter 528. The other half of the 504 is in operation with the switching transistor 108.

For half of the illustrated clamp 504 that is operational with the switching transistor 104, the drain 532 of the transistor 508 is electrically connected to the switching transistor 104 via the node 536. Further, the source 540 of the transistor 508 is electrically connected to the drain 544 of the transistor 512. The same signal, that is, PU, is applied to both the input 548 of the inverter 524 and the gate 552 of the transistor 508. The output 556 of the inverter 524 is electrically connected to the gate 560 of the transistor 512.

For half of the illustrated clamp 504 that is operational with the switching transistor 108, the drain 564 of the transistor 520 is electrically connected to the switching transistor 108 via a node 568. Further, the source 572 of the transistor 520 is electrically connected to the drain 576 of the transistor 516. The same signal, that is, PD, is applied to both the input 580 of the inverter 528 and the gate 584 of the transistor 520. The output 588 of the inverter 528 is electrically connected to the gate 592 of the transistor 516.

While the switching transistors 104 and 108 are switched off at the same time (of course, in at least some examples you will find that it is not necessary to switch the two transistors off at the same time), the operation of the illustrated clamp 504 is It is as follows. For a short period of time, the length of which is determined by the delay of the inverters 524 and 528, the two pairs of transistors that form part of the clamp 504 cause a current spike while the switching transistors 104 and 108 are switched off. Provide a route to reduce. These paths exist by turning on both of the transistors in each pair. However, after a period of time determined by the delay of the inverter, both transistors are no longer on in either pair of transistors, eliminating the clamping effect of the two pairs of transistors and V as desired._cGreat flexibility to set (ie V)_biaspAnd V_biasnNot limited to the limits defined by).

Now refer to Figure 5. FIG. 5 is a schematic circuit diagram of another charge pump 600. The charge pump 600 is similar to the charge pump of FIG. 4 in some respects, but includes a clamp 604 according to another embodiment. Like the other clamps illustrated and described here, the clamp 604 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 604 comprises a first pair of transistors 606 and 608 and a second pair of transistors 610 and 612. In at least one example, transistors 606 and 610 are NMOS transistors and transistors 608 and 612 are MOSFET transistors.

In the illustrated embodiment, half of the clamp 604 with transistors 606 and 608 is operational interlocked with the switching transistor 104, and the other half of the clamp 604 with transistors 610 and 612 is operational interlocked with the switching transistor 108. are doing.

For half of the illustrated clamp 604 that is operational with the switching transistor 104, the drain 614 of the transistor 606 is electrically connected to the switching transistor 104 via a node 616. Further, the source 618 of the transistor 606 is electrically connected to the source 620 of the transistor 608. The same signal, that is, PU, is applied to both the gate 622 of the transistor 606 and the gate 624 of the transistor 608.

For half of the illustrated clamp 604 that is operational with the switching transistor 108, the drain 626 of the transistor 612 is electrically connected to the switching transistor 108 via a node 628. Further, the source 630 of the transistor 612 is electrically connected to the source 632 of the transistor 610. The same signal, that is, PD, is applied to both the gate 634 of the transistor 612 and the gate 636 of the transistor 610.

When the signal PD is logic high, the transistors 108 and 610 are conducting, whereas the transistor 612 is not conducting. During this time, the node between the source 639 and the source 632 is precharged to a voltage level approximately equal to the threshold voltage level of the NMOS transistor 610. When the signal PD goes to logic low, the transistor 610 turns off and cuts off the leak path. Also, the MOSFET transistor 612 is turned on, causing charge exchange between the node 628 and the node between the source 639 and the source 632. For example, charge exchange occurs between the parasitic capacitances of two transistors 610 and 612. During this charge exchange, an additional current path is provided through the node 628 so that the parasitic current spike only partially follows the path between the switching transistor 108 and the capacitor 102. As a result of the charge exchange, the current level at node 628 rises rapidly, cutting off transistor 124 rapidly. During this passive state, to minimize leakage current flow, the new voltage value at which the voltage transitions at node 628 is maintained while switching transistor 108 is switched off.

Similarly, when the signal PU is logic low, the transistors 104 and 608 are conducting, but the transistors 606 are not conducting. When the signal PU goes logic high, the transistor 608 turns off and cuts off the leak path. Transistor 606 is also turned on, causing charge exchange between node 616 and the node between source 618 and source 620. For example, charge exchange occurs between the parasitic capacitances of two transistors 606 and 608. During this charge exchange, an additional current path is provided through node 616 so that the parasitic current spike only partially follows the path between the switching transistor 104 and the capacitor 102. As a result of the charge exchange, the current level at node 616 drops rapidly, cutting off transistor 120 rapidly. During this passive state, to minimize leakage current flow, the new voltage value at which the voltage transitions at node 616 is maintained while the switching transistor 104 is switched off.

Next, refer to FIG. FIG. 6 is a schematic circuit diagram of another charge pump 650. The charge pump 650 is also similar to the charge pump of FIG. 4 in some respects, but comprises a clamp 654 according to yet another embodiment. Like the other clamps illustrated and described here, the clamp 654 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 654 includes an NMOS transistor 656 to which a signal PU is applied to the gate 657, a MOSFET transistor 658 to which a signal PD is applied to the gate 659, and an analog repeater 660. The input 662 of the repeater 660 is connected to the node 130, while the output 664 of the repeater 660 is electrically connected to the source 666 of the transistor 656 and the source 668 of the transistor 658.

In the illustrated clamp 654, the transistor 656 is operational interlocked with the switching transistor 104. In particular, the drain 670 of the transistor 656 is electrically connected to the switching transistor 104 via the node 672. In addition, the transistor 658 is interlocked with the switching transistor 108. In particular, the drain 674 of transistor 658 is electrically connected to switching transistor 108 via node 676.

As will be appreciated by those skilled in the art, as a result of the logic high signal being applied to the gate 657, the transistor 656 begins to conduct while it is switched off. Since the transistor 656 is conducting in this way, the V supplied by the repeater 660_cA voltage replica is linked to node 672. Leakage current is minimized because the voltage drop is small over the entire leakage current path and the voltage at node 672 does not drop significantly while transistor 104 is switched off. Also, the parasitic current spikes generated when switching off only partially pass through the path between the switching transistor 104 and the capacitor 102 (additional current path through node 672 when transistor 656 is conducting). Will be provided again).

Similarly, because a logic high signal is applied to the gate 659, the transistor 658 begins conduction while transistor 108 is switched off. V supplied by repeater 660 because transistor 656 is conducting_cA voltage replica is linked to node 676. Again, the leakage current is kept to a minimum because the voltage difference is small over the entire leakage current path and the voltage at node 676 does not rise significantly while transistor 108 is switched off. In addition, the parasitic current spike (circuit sink) generated when switching off only partially passes through the path between the switching transistor 108 and the capacitor 102 (if transistor 658 is conducting, the node. It will be found again) that an additional current path through 676 will be provided again).

In some examples, the repeater 660 does not exist. For example, nodes 672 and 676 may be directly connected to node 130 while transistors 104 and 108 are switched off. However, in such cases, charge injection during concatenation occurs. In particular, the parasitic capacitances of transistors 656 and 658 cause charge injection at connection to node 130.

Now refer to Figure 7. FIG. 7 is a schematic circuit diagram of another charge pump 700. The charge pump 700 includes a clamp 704 according to yet another embodiment. The charge pump 700 is similar in some respects to the other charge pumps illustrated and described above. For example, like many other clamps illustrated and described here, the clamp 704 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 704 includes two inverters 706 and 708, a MOSFET transistor 710, an MIMO transistor 712, and an analog repeater 714. In terms of circuit configuration, a signal PU is supplied to the input 716 of the inverter 706, and the output 718 of the inverter 706 is applied to the gate 720 of the transistor 710. Similarly, the signal PD is supplied to the input 724 of the inverter 708, and the output 728 of the inverter 708 is applied to the gate 732 of the transistor 712. Further, the input 736 of the repeater 714 is connected to the node 130, while the output 740 of the repeater 714 is electrically connected to the drain 744 of the transistor 710 and the drain 748 of the transistor 712.

In the illustrated clamp 704, the transistor 710 is in operation interlocking with the switching transistor 104. In particular, the drain 752 of transistor 710 is electrically connected to switching transistor 104 via node 756. In addition, transistor 712 is interlocked with switching transistor 108. In particular, the drain 760 of transistor 712 is electrically connected to switching transistor 108 via node 764.

It can be seen that the clamp 704 in FIG. 7 is operationally similar to the clamp 654 in FIG. Again, the shown repeaters are not present in all examples.

Now refer to Figure 8. FIG. 8 is a schematic circuit diagram of another charge pump 800. The charge pump 800 includes a clamp 804 according to yet another embodiment. Again, it can be seen that the charge pump 800 is similar in some respects to the other charge pumps illustrated and described above. For example, like many other clamps illustrated and described here, the clamp 804 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 804 includes a pair of MOSFET transistors 808 and 812, a pair of NMOS transistors 816 and 820, and two inverters 824 and 828. Half of the clamp 804 with the transistor 808, the transistor 812 and the inverter 824 is operational interlocked with the switching transistor 104, and the other half of the clamp 804 with the transistor 816, the transistor 820 and the inverter 828 is , The operation is linked with the switching transistor 108.

For half of the illustrated clamp 804 that is operational with the switching transistor 104, the source 832 of the transistor 808 is electrically connected to the switching transistor 104 via the node 836. Further, the drain 840 of the transistor 808 is electrically connected to the source 844 of the transistor 812, and the voltage at the node between the drain 840 and the source 844 does not drop to the ground potential. The same signal, that is, PU, is applied to the input 848 of the inverter 824 and the gate 112 of the transistor 104. The output 856 of the inverter 824 is electrically connected to the gate 860 of the transistor 808. Signal V at gate 862 of transistor 812_biasp1Is applied. (At least in some examples, V_biasp1Is V_biaspHas similar or substantially the same value as. ) For half of the illustrated clamp 804 that is operational with the switching transistor 108, the source 864 of the transistor 820 is electrically connected to the switching transistor 108 via the node 868. Further, the drain 872 of the transistor 820 is electrically connected to the source 876 of the transistor 816, and the voltage at the node between the drain 872 and the source 876 is V._ddDoes not rise until. The same signal, that is, PD, is applied to the input 880 of the inverter 828 and the gate 116 of the transistor 108. The output 882 of the inverter 828 is electrically connected to the gate 884 of the transistor 820. Signal V at gate 894 of transistor 816_biasn1Is applied. (At least in some examples, V_biasn1Is V_biaspHas similar or substantially the same value as. ) With reference to half of the illustrated clamp 804, which continues to work with the switching transistor 108, transistor 820 begins to conduct while transistor 108 is switched off, with node 868, drain 872 and source 876. It can be seen that charge exchange takes place with the node between the transistors (eg, the parasitic capacitances of transistors 816 and 820 exchange charge with each other). Transistor 816 size and V_biasn1With proper selection of the value of, the voltage level at node 868 can be increased when transistor 108 is switched off, thereby cutting off the tail-out current rapidly. In particular, the voltage transition is generally V._biasn-V_{T # n}From V_biasn1-V_{T # n1}The range is up to. In addition, the clamp 804 has a voltage of V at node 868._biasn1-V_{T # n1}Limit it so that it is not lower. The voltage at node 868 is V_biasn-V_{T # n}Since there is very little leakage current unless it is lower, the clamp 804 effectively Vs the voltage at node 868 while the switching transistor 108 is switched off._biasn1-V_{T # n1}Keep in the vicinity.

With reference to the half of the illustrated clamp 804 that works in conjunction with the switching transistor 104, when the transistor 104 is switched off, the transistor 808 begins to conduct, between node 836 and the drain 840 and source 844. It can be seen that charge exchange takes place with a node (for example, the parasitic capacitances of transistors 808 and 812 exchange charge with each other). Transistor 812 size and V_biasp1With proper selection of the value of, when the transistor 104 is switched off, the voltage level at node 836 drops significantly enough to cut off the tail-out current rapidly. In particular, the voltage transition is generally V._biasp+ V_{T # p}From V_biasp1+ V_{T # p1}The range is up to. In addition, the clamp 804 has a voltage of V at node 836._biasp1+ V_{T # p1}Limit it so that it does not grow larger. The voltage at node 836 is V_biasp+ V_{T # p}As long as it is larger, there is very little leakage current, so the clamp 804 effectively Vs the voltage at node 836 while the switching transistor 104 is switched off._biasp1+ V_{T # p1}Keep in the vicinity of.

One point is captured for the embodiment shown in FIG. A leakage current path is present when either switching transistor is switched off. In particular, the leakage current paths are i) paths through transistors 120, 808, and 812, and ii) paths through transistors 124, 820, and 816. However, the leakage current is smaller than, for example, the charge pump 300 shown in FIG. The clamp 804 also optionally accommodates very small current sources 896 and 898 to further ensure that the voltage at nodes 836 and 868 is maintained near a constant value while the switching transistor is switched off. You may prepare with. These current sources equally cancel small currents due to parasitic capacitance. In one example, the current source 896 is a MOSFET transistor (the source and gate of the MOSFET transistor are V, respectively._ddAnd V_biaspThe current source 898 is realized by using the NMOS transistor (the source and gate of the MOSFET are the ground potential and V, respectively)._biasnIt is realized by using (the state of being connected to).

Now refer to Figure 9. FIG. 9 is a schematic circuit diagram of another charge pump 900. The charge pump 900 comprises a clamp 904 according to yet another embodiment. Again, it can be seen that the charge pump 900 is similar in some respects to the other charge pumps illustrated and described above. For example, like many other clamps illustrated and described here, the clamp 904 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 904 comprises a MOSFET transistor 908, an MIMO transistor 920, and two inverters 924 and 928. Half of the clamp 904 with the transistor 908 and the inverter 924 is working with the switching transistor 104, and the other half of the clamp 904 with the transistor 920 and the inverter 928 is working with the switching transistor 108. There is.

For half of the illustrated clamp 904 that is in operation with the switching transistor 104, the source 932 of the transistor 908 is electrically connected to the switching transistor 104 via the node 936. In addition, signal V is sent to the drain 940 of transistor 908._biaspIs applied. The same signal, that is, PU, is applied to the input 948 of the inverter 924 and the gate 112 of the transistor 104. The output 956 of the inverter 924 is electrically connected to the gate 960 of the transistor 908.

For half of the illustrated clamp 904 that is in operation with the switching transistor 108, the source 964 of the transistor 920 is electrically connected to the switching transistor 108 via the node 968. In addition, the signal V is sent to the drain 972 of the transistor 920._biasnIs applied. The same signal, that is, PD, is applied to the input 980 of the inverter 928 and the gate 116 of the transistor 108. The output 982 of the inverter 928 is electrically connected to the gate 984 of the transistor 920.

The operation of the clamp 904 is similar to the operation of the clamp 804 shown in FIG. The main difference between the two clamps is that the clamp 904 does not have the transistors 812, 816, and the corresponding bias voltage applied to the gates of those transistors. Instead, the drain 940 of transistor 908 is V_biaspAnd similarly the drain 972 of transistor 920 is V_biasnIs connected to.

Now refer to Figure 10. FIG. 10 is a schematic circuit diagram of another charge pump 1000. The charge pump 1000 comprises a clamp 1004 according to still another embodiment, the clamp 1004 comprising an NMOS transistor 1008 and a MOSFET transistor 1012. Again, it can be seen that the charge pump 1000 is similar in some respects to the other charge pumps illustrated and described above. For example, like many other clamps illustrated and described here, the clamp 1004 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit. In addition, the clamp 1004 is particularly similar to the clamp 904 shown in FIG. 9, and the main difference between the two clamps is that the MIMO transistor 908 is replaced by the MOSFET transistor and the NMOS transistor 920 is replaced by the MOSFET transistor. Is the point that was excluded.

With respect to the NMOS transistor 1008, this transistor is in operation interlocking with the switching transistor 104. In particular, the drain 1016 of transistor 1008 is electrically connected to switching transistor 104 via node 1020. Also, the signal V is connected to the drain 1024 of transistor 1008._biaspIs applied. The same signal, that is, PU, is applied to the gate 1028 of the transistor 1008 and the gate 112 of the transistor 104.

With respect to the MOSFET transistor 1012, this transistor is in operation interlocking with the switching transistor 108. The drain 1032 of transistor 1012 is electrically connected to switching transistor 108 via node 1036. Also, the signal V is sent to the source 1040 of the transistor 1012._biasnHas been applied. The same signal, that is, PD, is applied to the gate 1044 of the transistor 1012 and the gate 116 of the transistor 108.

In some applications, the effectiveness of the clamp 1004 can be enhanced by using larger transistors (ie, increasing the size of transistors 1008 and / or transistors 1012).

Now refer to Figure 11. FIG. 11 is a schematic circuit diagram of another charge pump 1100. The charge pump 1100 comprises a clamp 1104 according to yet another embodiment. Again, it can be seen that the charge pump 1100 is similar in some respects to the other charge pumps illustrated and described above. For example, like many other clamps illustrated and described here, the clamp 1104 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 1104 includes a pair of NMOS transistors 1108 and 1112, a pair of MOSFET transistors 1116 and 1120, a delay-introducing inverter circuit (or inverter) 1124, another delay-introducing inverter circuit 1128, and two additional transistors. It is equipped with 1132 and 1136.

In the illustrated embodiment, half of the clamp 1104 with the transistors 1108, 1112, 1132 and the inverter 1124 is in operation interlocking with the switching transistor 104 and of the clamp 1104 with the transistors 1116, 1120, 1136 and the inverter 1128. The other half is interlocked with the switching transistor 108.

For half of the illustrated clamp 1104 that is operational with the switching transistor 104, the drain 1140 of the transistor 1108 is electrically connected to the switching transistor 104 via the node 1144. Further, the source 1148 of the transistor 1108 is electrically connected to the gate 1156 of the transistor 1132 and the drain 1152 of the transistor 1112. The same signal, or PU, is applied to both the input 1160 of the inverter 1124 and the gate 1164 of the transistor 1108. The output 1168 of the inverter 1124 is electrically connected to the gate 1180 of the transistor 1112 and to both the source 1172 and the drain 1176 of the transistor 1132.

For half of the illustrated clamp 1104 that is operational with the switching transistor 108, the drain 1181 of the transistor 1120 is electrically connected to the switching transistor 108 via a node 1182. Further, the source 1184 of the transistor 1120 is electrically connected to the drain 1185 of the transistor 1116. The same signal, or PD, is applied to both the input 1187 of the inverter 1128 and the gate 1188 of the transistor 1120. The output 1190 of the inverter 1128 is electrically connected to the gate 1196 of the transistor 1116 and to both the drain 1192 and the source 1192 of the transistor 1136.

The operation of the clamp 1104 is similar to the operation of the clamp 504 shown in FIG. However, the clamp 1104 includes additional transistors 1132 and 1136 configured as a capacitor built-in device. Transistor 1132 acts as a capacitor, injecting additional charge into node 1144 while transistor 104 is switched off. Transistor 1136 also acts as a capacitor, reducing additional charge from node 1182 while transistor 108 is switched off. You will find that the transistors 1132 and 1136 do not need to be non-standard, as the voltage drop across their plates will not be less than the transistor's threshold voltage.

Now refer to Figure 12. FIG. 12 is a schematic circuit diagram of another charge pump 1200. The charge pump 1200 includes a clamp 1204 according to yet another embodiment. It can be seen that the charge pump 1200 is similar in some respects to the other charge pumps illustrated and described above. For example, like many clamps illustrated and described here, the clamp 1204 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 1204 comprises two inverters 1208 and 1212, two transmission gates 1216 and 1220, and an analog repeater 1224. In terms of circuit configuration, the signal PU is input to both the control input 1227 of the transmission gate 1216 and the input 1228 of the inverter 1208, and the output 1232 of the inverter 1208 is supplied to the control input 1236 of the transmission gate 1216. Similarly, the signal PD is input to both the control input 1239 of the transmission gate 1220 and the input 1240 of the inverter 1212, and the output 1244 of the inverter 1212 is supplied to the control input 1248 of the transmission gate 1220. Further, the input 1252 of the repeater 1224 is connected to the node 130, while the output 1256 of the repeater 1224 is electrically connected to the inputs 1260 and 1264 of the transmission gates 1216 and 1220, respectively.

Within the illustrated clamp 1204, the transmission gate 1216 is operational interlocked with the switching transistor 104. In particular, the output 1270 of the transmission gate 1216 is electrically connected to the switching transistor 104 via the node 1272. Further, the transmission gate 1220 is interlocked with the switching transistor 108. In particular, the output 1272 of the transmission gate 1220 is electrically connected to the switching transistor 108 via the node 1285.

While the transistor 104 is switched off, the transmission gate 1216 begins to conduct, which causes the node 1272 to connect with the node at output 1256 of the repeater 1224 (V)._csnode). Leakage current is minimized because the voltage drop is small across the leakage current path and the voltage at node 1272 does not drop significantly while transistor 104 is switched off. .. Also, the parasitic current spike that occurs when switching off only partially flows through the path between the switching transistor 104 and the capacitor 102 (an additional current path through node 1272 while the transmission gate 1216 is conducting). Is provided).

Similarly, while transistor 108 is switched off, transmission gate 1220 begins conduction and V on node 1285._csConnect to a node. Duplication voltage V_csIs the voltage V to be replicated_cNode 1285 (or node 1272) is so close to V when the switching transistor is switched off._cConnected to a node with a voltage value close to. Thus, the voltage drop across the leak path is small enough to minimize the leak. Again, the parasitic current spike (the source of the circuit) that occurs when switching off only partially flows through the path between the switching transistor 108 and the capacitor 102 (while the transmission gate 1220 is conducting). An additional current path is provided through node 1285).

Now refer to Figure 13. FIG. 13 is a schematic circuit diagram of another charge pump 1300. The charge pump 1300 comprises a clamp 1304 according to yet another embodiment. It can be seen that the charge pump 1300 is similar in some respects to the other charge pumps illustrated and described above. For example, like many other clamps illustrated and described here, the clamp 1304 is a V._biaspAnd V_biasnV within the limits defined by_cDoes not limit.

The illustrated clamp 1304 comprises two inverters 1308 and 1312, two transmission gates 1316 and 1320, and two transistors 1324 and 1328. In terms of circuit configuration, the signal PU is input to both the control input 1330 of the transmission gate 1316 and the input 1332 of the inverter 1308, and the output 1334 of the inverter 1308 is applied to the control input 1336 of the transmission gate 1316. Similarly, the signal PD is input to both the control input 1340 of the transmission gate 1320 and the input 1342 of the inverter 1312, and the output 1344 of the inverter 1312 is applied to the control input 1346 of the transmission gate 1320.

Within the illustrated clamp 1304, the transmission gate 1316 is in operation interlocking with the switching transistor 104. In particular, the output 1349 of transmission gate 1316 is electrically connected to switching transistor 104 via node 1350, and node 1350 is in the state of MOSFET transistor 1324 on and transmission gate 1316 is conducting. There is an open path between and ground. Further, the transmission gate 1320 is interlocked with the switching transistor 108. In particular, the output 1352 of the transmission gate 1320 is electrically connected to the switching transistor 108 via the node 1354, and when the MOSFET transistor 1328 is turned on and the transmission gate 1320 is conducting, the node 1354 and V_ddThere is an open path between and.

While the transistor 104 is switched off, the transmission gate 1316 begins to conduct, which connects the node 1350 to the node 1380 located between the input 1382 of the transmission gate 1316 and the drain 1384 of the transistor 1324. When switched off, the potential of node 1380 is approximately ground potential, and charge exchange between nodes 1380 and 1350 occurs while the voltage at node 1350 drops rapidly and the tailout current is cut off. Occur. Also, an additional path is provided through the node 1350 so that the parasitic current spike only partially follows the path between the switching transistor 104 and the capacitor 102 when this charge exchange is occurring. The new voltage value at which the voltage transitions at node 1350 is maintained while the switching transistor 104 is switched off so that the leakage current flow is minimized in this passive state. Also, the transistor 1324 is turned off so that the leak path is cut off.

Similarly, while transistor 108 is switched off, transmission gate 1320 begins to conduct, thereby connecting node 1354 to node 1390, which is located between the input 1392 of transmission gate 1320 and the drain 1394 of transistor 1328. Will be done. When switched off, the potential of node 1390 is about V_ddA charge exchange occurs between nodes 1390 and 1354 while the voltage at node 1354 rises rapidly and the tailout current is cut off. Also, an additional path is provided through node 1354 such that the parasitic current spike only partially follows the path between the switching transistor 108 and the capacitor 102 when this charge exchange is occurring. The new voltage value at which the voltage transitions at node 1354 is maintained while the switching transistor 108 is switched off so that the leakage current flow is minimized in this passive state. Also, transistor 1328 is turned off so that the leak path is broken.

Now refer to Figure 14. Similar to FIG. 2, FIG. 14 is an example of a current (time) waveform diagram, which is a waveform diagram of the current flowing through the circuit path shown in FIG. 4 (not the circuit path shown in FIG. 1). Is. An example signal PU and PD (and signals output from gates 560 and 592) are also shown in the graph above the example waveform diagram.

Now with reference to FIGS. 4 and 14, time t_c1(Corresponding to the point where transistor 108 starts to switch off) Start time t_c2It can be seen that during the period ending with, the logic row value (which creates an on state when applied to the gates of the MOSFET transistor) is applied to the gates of both transistors 516 and 520. Thus, for a short period of time, the pair of transistors 516 and 520 provide an additional path for the off-switching current from transistor 108. However, at other times, it can be seen that at least one of the transistors 516 and 520 is turned off, so no additional path is provided in such cases. With respect to the pair of transistors (ie, transistors 508 and 512) that make up the source of the clamp 504, they function similarly. However, as will be appreciated by those skilled in the art, it is the value of logic high (rather than logic low) that creates the on state when applied to the gate of an NMOS transistor.

This time the current I in Figure 2_pAnd I_nGraph and current I in Figure 14_pAnd I_nCompare the graphs of. In that case, the effect of the clamp 504 is clear. Especially when the switching transistor 104 is switched off, the current I_p'It turns out that there is only a very small upward spike 694. Similarly, when the switching transistor 108 is switched off, the time t_c2Then you can see that there is only a very small downward spike 696. Time t_c1After the current I_p'And I_n'It is clear from the waveform diagram that the clamp 504 affects the rapid cutout of the tailout current, as it drops rapidly to about 0 μA. The same is true for the clamp simulation results shown in Figures 5 to 13 (extremely small current spikes, rapid cutoff of tail-out current).

The charge pump shown in the attached drawing has both a source portion and a sink portion, but in some examples, the charge pump may have only a source portion or a sink portion. Also, although the transistor in the circuit of the illustrated embodiment is a FET, the teachings contained herein provide instructions for implementing a charge pump having a clamp consisting of other types of transistors, such as bipolar transistors. You can see that. With reference to FIGS. 15 and 16, they are schematic circuit diagrams of charge pumps 1500 and 1600 as an example, including clamps 1504 and 1604, respectively. The charge pumps 1500 and 1600 are conceptually similar to the charge pumps in FIGS. 4 and 5, respectively, but they consist of bipolar transistors rather than FETs.

Some modifications and changes can be made to the embodiments described. Therefore, it should be considered that the above embodiments are for illustration purposes only and are not limiting.