Semiconductor device

The present invention relates to a semiconductor device capable of transmitting an electric signal between two circuits in which the potentials of input electric signals are different from each other.

When transmitting an electric signal between two circuits in which the potentials of the input electric signals are different from each other, a photocoupler is often used. A photocoupler has a light emitting element such as a light emitting diode and a light receiving element such as a phototransistor. The input electric signal is converted into light by the light emitting element, and this light is returned to the electric signal by the light receiving element. It is transmitting an electric signal.

However, since the photocoupler has a light emitting element and a light receiving element, it is difficult to reduce the size. Further, when the frequency of the electric signal is high, it becomes impossible to follow the electric signal. As a technique for solving these problems, for example, as described in Patent Document 1, a technique for transmitting an electric signal by inductively coupling two inductors has been developed.

Further, Patent Document 2 describes that an inductor pair is used when connecting the first semiconductor chip on the transmitting side and the second semiconductor chip on the receiving side to each other via a transmission path. Specifically, the transmission line and the first semiconductor chip are non-contactly connected by electromagnetic coupling of the transmitting inductor pair. Further, the transmission line and the second semiconductor chip are non-contactly connected by electromagnetic coupling of the receiving side inductor pair.

<p><patcit num="1"><text>Special Table 2001-513276 Gazette</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2008-113093</text></patcit></p>

<p> When connecting the circuit on the transmitting side and the circuit on the receiving side via a wiring board, the circuit on the transmitting side and the wiring board are connected by an inductor pair, and the wiring board and the circuit on the receiving side are connected by an inductor pair. Can be considered. In this case, since there are two inductor pairs, the signal is attenuated during transmission, and there is a possibility that the signal cannot be transmitted accurately. In order to transmit signals accurately, the distance between the two inductors that make up the inductor pair should be narrowed. However, when the reference voltage of the circuit on the transmitting side and the circuit on the receiving side are different, if the distance between the two inductors that make up the inductor pair is narrowed in each of the two inductor pairs, the circuit on the transmitting side and the circuit on the receiving side It becomes impossible to secure the insulation between them. As described above, it is difficult to secure the insulation between the circuit on the transmitting side and the circuit on the receiving side while accurately transmitting the signal.</p>

<p> According to the present invention, one or two semiconductor chips having a wiring layer and a wiring board attached to the wiring layer side of the one or two semiconductor chips are provided. The one or two semiconductor chips The first circuit that generates the signal and A first inductor formed in the wiring layer and connected to the first circuit, The second circuit that processes the signal and A second inductor formed in the wiring layer and connected to the second circuit, Have, The wiring board is With the third inductor located above the first inductor, A fourth inductor located above the second inductor and connected to the third inductor, Have, A semiconductor device is provided in which the distance from the first inductor to the third inductor is different from the distance from the second inductor to the fourth inductor.</p><p> According to the present invention, the distance from the first inductor to the third inductor is different from the distance from the second inductor to the fourth inductor. The withstand voltage between the first circuit and the second circuit is determined by the sum of the distance from the first inductor to the third inductor and the distance from the second inductor to the fourth inductor. Therefore, the sum of the distance from the first inductor to the third inductor and the distance from the second inductor to the fourth inductor must have a certain value or more. When designing a semiconductor device, the above-mentioned necessary values are distributed to the distance from the first inductor to the third inductor and the distance from the second inductor to the fourth inductor. If the distance from the 1st inductor to the 3rd inductor and the distance between the 2nd inductor and the 4th inductor are different from each other and set to appropriate values, the signal transmission efficiency from the 1st circuit to the 2nd circuit will be maximized. can do. Therefore, it is possible to secure the insulation between the first circuit and the second circuit while accurately transmitting the signal.</p>

<p> According to the present invention, when the wiring board and the first circuit on the transmitting side and the wiring board and the second circuit on the receiving side are connected by an inductor pair, the first circuit and the second circuit are transmitted accurately while transmitting signals. Insulation between circuits can be ensured.</p>

<figref num="1">It is sectional drawing which shows the structure of the semiconductor device which concerns on 1st Embodiment.</figref><figref num="2">It is a plan schematic diagram of the semiconductor device shown in FIG.</figref><figref num="3">It is an equivalent circuit diagram of the semiconductor device shown in FIG.</figref><figref num="4">It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment.</figref><figref num="5">FIG. 5 is a schematic plan view of the semiconductor device shown in FIG.</figref><figref num="6">It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment.</figref><figref num="7">FIG. 6 is a schematic plan view of the semiconductor device shown in FIG.</figref><figref num="8">It is an equivalent circuit diagram of the semiconductor device shown in FIG.</figref><figref num="9">It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment.</figref><figref num="10">It is a plan schematic diagram of the semiconductor device shown in FIG.</figref>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all drawings, similar components are designated by the same reference numerals, and description thereof will be omitted as appropriate.

FIG. 1 is a diagram showing a configuration of a semiconductor device according to the first embodiment, and FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. Figure 1 corresponds to the AA ́ cross section in Figure 2. In FIG. 1, the number of turns of the first inductor 302 and the second inductor 322, which will be described later, is different from that in FIG. 2 in order to simplify the drawing. This semiconductor device includes two semiconductor chips 10, 20 and a wiring board 60. The semiconductor chip 10 has a multilayer wiring layer 400, and the semiconductor chip 20 has a multilayer wiring layer 500.

The semiconductor chip 10 includes a first substrate 102, a first circuit 100, and a first inductor 302. The first substrate 102 is a semiconductor substrate such as a silicon substrate. The first circuit 100 produces a signal to be transmitted. The first inductor 302 is formed in the multilayer wiring layer 400. The first inductor 302 is connected to the first circuit 100, and the signal generated by the first circuit 100 is input.

The semiconductor chip 20 has a second substrate 202, a second circuit 200, and a second inductor 322. The second substrate 202 is a semiconductor substrate such as a silicon substrate. The second circuit 200 receives and processes the signal generated by the first circuit 100. The second inductor 322 is formed in the multilayer wiring layer 500. The second inductor 322 is connected to the second circuit 200 and transmits a signal to the second circuit 200. The transmitted signal is, for example, a digital signal, but may be an analog signal.

The wiring board 60 is mounted on the first inductor 302 of the semiconductor chip 10 and on the second inductor 322 of the semiconductor chip 20. The wiring board 60 is attached to the semiconductor chip 10 and the semiconductor chip 20 via, for example, an adhesive (not shown). The wiring board 60 has a third inductor 304 and a fourth inductor 324. The third inductor 304 is located above the first inductor 302. The fourth inductor 324 is located above the second inductor 322 and is connected to the third inductor 304. The distance from the first inductor 302 to the third inductor 304 is longer than the distance from the second inductor 322 to the fourth inductor 324. Each inductor has a spiral wiring pattern.

In the example shown in FIG. 1, the wiring board 60 is a silicon interposer formed by using the silicon board 602. However, the wiring board 60 may be an interposer or a wiring board using a resin substrate. When the wiring board 60 is formed by using the silicon substrate 602 and the first substrate 102 and the second substrate 202 are silicon substrates, the impurity concentration of the silicon substrate of the wiring board 60 is the substrate impurities of the first substrate 102. It is preferably lower than the concentration and the substrate impurity concentration of the second substrate 202. In this way, it is possible to suppress the generation of eddy currents in the silicon substrate 602.

In the present embodiment, the third inductor 304 and the fourth inductor 324 are formed on the surface of the wiring board 60 opposite to the semiconductor chip 10 and the semiconductor chip 20. The third inductor 304 and the fourth inductor 324 are formed on the wiring layer 604 formed on the silicon substrate 602. The wiring layer 604 is a multi-layer wiring layer, and the third inductor 304 and the fourth inductor 324 are connected to each other via wiring (not shown) in the wiring layer 604.

The first inductor 302 and the third inductor 304 constitute the first signal transmission element 300, and the second inductor 322 and the fourth inductor 324 constitute the second signal transmission element 320. As described above, the distance from the first inductor 302 to the third inductor 304 is different from the distance from the second inductor 322 to the fourth inductor 324.

Specifically, the first inductor 302 is formed in the multilayer wiring layer 400 of the semiconductor chip 10, and the second inductor 322 is formed in the multilayer wiring layer 500 of the semiconductor chip 20. The multilayer wiring layers 400 and 500 are formed by alternately laminating an insulating layer and a wiring layer a plurality of times or more in this order. In the present embodiment, the multilayer wiring layer 400 has a configuration in which an insulating layer 410, a wiring layer 412, an insulating layer 420, a wiring layer 422, an insulating layer 430, a wiring layer 432, an insulating layer 440, and a wiring layer 442 are stacked in this order. Have. Further, the multilayer wiring layer 500 has a configuration in which an insulating layer 510, a wiring layer 512, an insulating layer 520, a wiring layer 522, an insulating layer 530, a wiring layer 532, an insulating layer 540, and a wiring layer 542 are stacked in this order. .. Each insulating layer may have a structure in which a plurality of insulating films are laminated, or may be one insulating film. The multilayer wiring layers 400 and 500 are covered with a protective film (not shown). Further, the number of layers of the multilayer wiring layers 400 and 500 may be the same or different from each other.

In the example shown in this figure, the first inductor 302 is provided in the wiring layer 412 which is the first wiring layer of the multilayer wiring layer 400, and the second inductor 322 is the wiring layer 542 of the uppermost layer of the multilayer wiring layer 500. It is provided in.

The wiring of each wiring layer is a Cu wiring formed by the damascene method, and is embedded in a groove formed in each wiring layer. Pads (not shown) are formed on the top layer wiring. In the multilayer wiring layers 400 and 500, at least one of the wiring layers may be Al alloy wiring. The wiring formed in each wiring layer is connected to each other via a plug embedded in the insulating layer.

Each insulating film constituting the insulating layer and the wiring layer is SiO₂It may be a film or a low dielectric constant film. The low dielectric constant film can be, for example, an insulating film having a relative permittivity of 3.3 or less, preferably 2.9 or less. As the low dielectric constant film, in addition to SiOC, polyhydrogensiloxane such as HSQ (hydrogencil sesquioxane), MSQ (methyl silsesquioxane), or MHSQ (methylated hydrogen silsesquioxane), Aromatic organic materials such as polyaryl ether (PAE), divinylsiloxane-bis-benzocyclobutene (BCB), or Silk®, SOG, FOX (flowable oxide)®, Cytop® ), BCB (Bensocyclobutene), etc. can also be used. Further, as the low dielectric constant film, these porous films can also be used.

If the thicknesses of the multilayer wiring layer 400 and the multilayer wiring layer 500 are different, it is possible that the wiring board 60 is tilted. In this case, the backside grinding amounts of the first substrate 102 and the second substrate 202 may be changed to make the thicknesses of the semiconductor chip 10 and the semiconductor chip 20 the same.

The first circuit 100 is a transmission circuit, and the second circuit 200 is a reception circuit. Therefore, the first inductor 302 functions as a transmitting inductor, and the third inductor 304 functions as a receiving inductor. The fourth inductor 324 functions as a transmitting inductor, and the second inductor 322 functions as a receiving inductor.

The first circuit 100 is, for example, a transmission side driver circuit (for example, a gate driver), and amplifies a transmission signal in which a digital signal is modulated and outputs the signal to the first inductor 302. The second circuit 200 is, for example, a receiving side driver circuit (for example, a gate driver), and amplifies and outputs a digital signal generated by modulating a signal received by the second inductor 322.

In the first circuit 100 and the second circuit 200, the potentials of the input electric signals are different from each other, but the first signal transmission element 300 and the second signal transmission element 320 transmit the electric signal by using the inductive coupling. There is no problem with the 1st circuit 100 and the 2nd circuit 200. In the configuration of FIG. 1, when "the potentials of the input electric signals are different from each other" and the amplitudes of the electric signals (the difference between the potentials indicating 0 and the potentials indicating 1) are different from each other, the reference potentials of the electric signals ( There are cases where the potentials indicating 0) are different, the amplitudes of the electric signals are different from each other, and the reference potentials of the electric signals are different.

The first circuit 100 of the semiconductor chip 10 has a first transistor. The first transistor includes an N-type transistor and a P-type transistor. The N-type first transistor 121 is formed in the P-type well 120 and has two N-type impurity regions 124 and a gate electrode 126 that serve as a source and a drain. The P-type first transistor 141 is formed in the N-type well 140, and has two P-type impurity regions 144 and a gate electrode 146 that serve as a source and a drain. A gate insulating film is located under each of the gate electrodes 126 and 146. These two gate insulating films are approximately equal in thickness. The first transistors 121 and 141 constitute the above-mentioned transmission side driver circuit, for example, an inverter.

A P-type impurity region 122 is formed in the well 120, and an N-type impurity region 142 is formed in the well 140. A wiring that gives a reference potential (ground potential) of the N-type first transistor 121 is connected to the impurity region 122, and a wiring that gives a power supply potential of the P-type first transistor 141 is connected to the impurity region 142. There is.

The second circuit 200 of the semiconductor chip 20 has a second transistor. The second transistor also includes an N-type transistor and a P-type transistor. The N-type second transistor 221 is formed in a P-type well 220 and has two N-type impurity regions 224 and a gate electrode 226 as sources and drains. The P-type second transistor 241 is formed in an N-type well 240, and has two P-type impurity regions 244 and a gate electrode 246 that serve as a source and a drain. A gate insulating film is located under each of the gate electrodes 226 and 246. The second transistors 221, 241 constitute the above-mentioned receiving side driver circuit, for example, an inverter.

A P-type impurity region 222 is formed in the well 220, and an N-type impurity region 242 is formed in the well 240. A wiring that gives a reference potential of the N-type second transistor 221 is connected to the impurity region 222, and a wiring that gives a power supply potential of the P-type second transistor 241 is connected to the impurity region 242.

In the example shown in this figure, the first transistor 121, 141 and the second transistor 221, 241 have different gate insulating film thicknesses, but may be the same.

The area of the wiring board 60 is smaller than the sum of the area of the semiconductor chip 10 and the area of the semiconductor chip 20.

FIG. 3 is an equivalent circuit diagram of the semiconductor device shown in FIG. The signal generated by the first circuit 100 is received by the second circuit 200 via the first signal transmission element 300 and the second signal transmission element 320. The first signal transmission element 300 transmits a signal by inductive coupling of the first inductor 302 and the third inductor 304, and the second signal transmission element 320 transmits a signal by inductive coupling of the fourth inductor 324 and the second inductor 322. To do.

Next, the operation and effect of this embodiment will be described. In the first circuit 100 and the second circuit 200, the potentials of the input electric signals are different from each other. The withstand voltage between the first circuit 100 and the second circuit 200 is determined by the sum of the distance between the first inductor 302 and the third inductor 304 and the distance between the second inductor 322 and the fourth inductor 324. Therefore, the sum of the distance between the first inductor 302 and the third inductor 304 and the distance between the second inductor 322 and the fourth inductor 324 must be greater than or equal to a certain value. Then, when designing a semiconductor device, the above-mentioned necessary values are distributed to the distance between the first inductor 302 and the third inductor 304 and the distance between the second inductor 322 and the fourth inductor 324. If the spacing between the 1st inductor 302 and the 3rd inductor 304 and the spacing between the 2nd inductor 322 and the 4th inductor 324 are different from each other and set to appropriate values, the signals from the 1st circuit 100 to the 2nd circuit 200 will be signaled. The transmission efficiency can be maximized. In the present embodiment, the distance from the first inductor 302 to the third inductor 304 is different from the distance from the second inductor 322 to the fourth inductor 324. Therefore, it is possible to secure the insulation between the first circuit 100 and the second circuit 200 while accurately transmitting the signal.

For example, since the first inductor 302, which is the transmitting side inductor of the first signal transmitting element 300, is connected to the first circuit 100, which is the transmitting circuit, a relatively large current flows. On the other hand, the fourth inductor 324, which is the transmitting side inductor of the second signal transmitting element 320, is relatively small because the induced current flowing through the third inductor 304, which is the receiving side inductor of the first signal transmitting element 300, flows. Current flows. Therefore, a relatively large induced current is generated in the third inductor 304, which is the receiving side inductor of the first signal transmitting element 300, and the second inductor 322, which is the receiving side inductor of the second signal transmitting element 320, generates a relatively large induced current. A relatively small induced current is generated. Therefore, as in the present embodiment, when the first inductor 302 is arranged in the lowermost wiring layer 412 of the multilayer wiring layer 400 and the second inductor 322 is arranged in the uppermost wiring layer of the multilayer wiring layer 500, the first The signal transmission efficiency of the second signal transmission element 320 can be increased while ensuring the withstand voltage in the signal transmission element 300.

Further, in the present embodiment, the third inductor 304 is formed on the surface of the wiring board 60 opposite to the semiconductor chip 10. Therefore, the withstand voltage of the first signal transmission element 300 can be increased by separating the first inductor 302 and the third inductor 304.

Further, when the substrate impurity concentration of the silicon substrate 602 of the wiring board 60 is lower than the substrate impurity concentration of the first substrate 102 and the substrate impurity concentration of the second substrate 202, the first signal transmission element 300 and the second signal transmission element 320 The generated magnetic field suppresses the generation of eddy currents on the silicon substrate 602.

FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment, and FIG. 5 is a schematic plan view of the semiconductor device shown in FIG. Figure 4 corresponds to the BB ́ cross section of Figure 5. In this semiconductor device, the semiconductor according to the first embodiment except that the third inductor 304 and the fourth inductor 324 are formed on the surfaces of the wiring substrate 60 facing the semiconductor chip 10 and the semiconductor chip 20. It has the same configuration as the device.

Also in this embodiment, it is possible to secure the insulation between the first circuit 100 and the second circuit 200 while accurately transmitting the signal. Further, the fourth inductor 324 is formed on the surface of the wiring board 60 facing the semiconductor chip 20. Therefore, the fourth inductor 324 and the second inductor 322 can be brought close to each other to increase the signal transmission efficiency of the second signal transmission element 320.

FIG. 6 is a schematic cross-sectional view showing the configuration of the semiconductor device according to the third embodiment, and FIG. 7 is a plan schematic view of the semiconductor device shown in FIG. Figure 6 corresponds to the CC ́ cross section of Figure 7. This semiconductor device has the same configuration as that of the first embodiment except that the transmission / reception circuit 606 is formed on the surface of the silicon substrate 602 on which the wiring layer 604 is formed.

FIG. 8 is an equivalent circuit diagram of the semiconductor device shown in FIGS. 6 and 7. The transmission / reception circuit 606 is provided between the third inductor 304 and the fourth inductor 324 on the circuit. The transmission / reception circuit 606 includes a reception circuit and a transmission circuit. The third inductor 304 demodulates the signal received from the first inductor 302, then modulates it again and outputs it to the fourth inductor 324. As shown in FIG. 6, the transmission / reception circuit 606 is formed on the surface of the wiring board 60 on which the wiring layer 604 is formed, but may be formed on the surface opposite to the surface on which the wiring layer 604 is formed. ..

The same effect as that of the first or second embodiment can be obtained by this embodiment as well. Further, in the transmission / reception circuit 606, after the third inductor 304 demodulates the signal received from the first inductor 302, it is modulated again and output to the fourth inductor 324. Therefore, the signal transmission efficiency is further improved.

FIG. 9 is a schematic cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment, and FIG. 10 is a plan schematic view of the semiconductor device shown in FIG. FIG. 9 corresponds to the DD ́ cross section of FIG. In this semiconductor device, the first circuit 100 and the first inductor 302 are formed in the first region 12 of the semiconductor chip 10, and the second circuit 200 and the second inductor 322 are formed in the second region 14 of the semiconductor chip 10. The configuration is the same as that of any of the first to third embodiments, except that Note that FIGS. 9 and 10 show the same cases as in the third embodiment.

The first substrate 102 is an SOI (Silicon On Insulator) substrate, and has a configuration in which an insulating layer 106 and a silicon layer 108 are laminated in this order on a silicon substrate 104. An insulating separation layer 109 that insulates the first region 12 and the second region 14 is embedded in the silicon layer 108. The lower end of the insulating separation layer 109 reaches the insulating layer 106.

The same effect as that of the first to third embodiments can be obtained by this embodiment as well. Further, the semiconductor chip 10 can be formed with a first circuit 100 as a transmission circuit and a second circuit 200 as a reception circuit.

Although the embodiments of the present invention have been described above with reference to the drawings, these are examples of the present invention, and various configurations other than the above can be adopted.

10 Semiconductor chip 12 1st area 14 Second area 20 semiconductor chips 60 Wiring board 100 1st circuit 102 1st board 104 Silicon substrate 106 Insulation layer 108 Silicon layer 109 Insulation Separation Layer 120 wells 121 1st transistor 122 Impurity area 124 Impurity region 126 Gate electrode 140 wells 141 1st transistor 142 Impurity area 144 Impurity area 146 Gate electrode 200 2nd circuit 202 2nd board 220 wells 221 2nd transistor 222 Impurity area 224 Impurity region 226 Gate electrode 240 wells 241 Second transistor 242 Impurity region 244 Impurity region 246 Gate electrode 300 1st signal transduction element 302 1st inductor 304 3rd inductor 320 2nd signal transduction element 322 2nd inductor 324 4th inductor 400 multi-layer wiring layer 410 Insulation layer 412 Wiring layer 420 insulation layer 422 Wiring layer 430 Insulation layer 432 Wiring layer 440 insulation layer 442 Wiring layer 500 multi-layer wiring layer 510 insulation layer 512 wiring layer 520 Insulation layer 522 Wiring layer 530 Insulation layer 532 Wiring layer 540 Insulation layer 542 Wiring layer 602 Silicon substrate 604 Wiring layer 606 transceiver circuit