Thin film transistor, method for manufacturing polycrystalline oxide semiconductor thin film, and method for manufacturing thin film transistor

The present invention relates to a thin film transistor, a method for manufacturing a polycrystalline oxide semiconductor thin film, and a method for manufacturing a thin film transistor.

In recent years, a transparent thin film transistor (sometimes referred to as TFT in the following description) used for an image display device or the like has been actively developed. In particular, the In-Ga-Zn-O system (sometimes referred to as IGZO in the following description) has been actively developed due to its wide optical bandgap and activates amorphous IGZO. There is a large amount of literature on TFTs used as layers (see, for example, Patent Document 1).

Here, one reason why amorphous IGZO is used in TFT is that it is possible to prepare an active layer having a flat surface because it is amorphous, and the TFT characteristics due to carrier traps caused by the unevenness of the surface of the active layer. It is possible to avoid deterioration of the quality and variation in quality.

On the other hand, in order to increase carrier mobility, which is one of the TFT characteristics, crystalline semiconductors are generally more effective than amorphous semiconductors. Even IGZO, which is a type of semiconductor, cannot be compared unconditionally because the composition ratio is different, but amorphous InGaZnO₄Carrier mobility in TFT using a thin film consisting of 6 to 9 cm as an active layer²V^-1S^-1(on / off ratio 10³), While single crystal InGaO₃(ZnO)₅Carrier mobility in TFT using a thin film consisting of an active layer is 80 cm.²V^-1S^-1(on / off ratio 10⁶), It is inferred that crystalline IGZO has higher carrier mobility than amorphous. Therefore, in TFT, it is considered more effective to use crystalline IGZO in order to increase carrier mobility (see, for example, Non-Patent Documents 1 and 2).

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2008-53356</text></patcit><patcit num="2"><text>Japanese Patent Application Laid-Open No. 2007-73701</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2003-41362</text></patcit><nplcit num="1"><text>Nature, Vol.432 (2004) p. 488</text></nplcit><nplcit num="2"><text>Sience, Vol.300 (2003) p. 1269</text></nplcit>

<p> However, when a thin film made of crystalline material, particularly polycrystalline IGZO, is used as the active layer, as shown in Patent Document 2, the surface of the active layer is compared with the case where a thin film made of amorphous IGZO is used as the active layer. The properties tend to be rough, and there is a problem that the TFT characteristics are deteriorated and the quality varies due to the carrier trap caused by the unevenness of the surface of the active layer.</p><p> Patent Document 3 states that the polycrystalline In, which has been heat-treated at 800 ° C.₂O₃(ZnO)₂₀Although a thin film composed of is disclosed, its surface property is not disclosed.</p><p> The present invention relates to a thin film transistor capable of having a thin film made of an oxide semiconductor containing at least one element in the group consisting of In, Ga and Zn having high TFT characteristics, and a method for producing a polycrystalline oxide semiconductor thin film. And a method for manufacturing a thin film transistor.</p>

<p>&lt;1&gt; A thin film transistor having a surface roughness Ra value of 1.5 nm or less and comprising an active layer made of a polycrystalline oxide semiconductor containing at least one element in the group consisting of In, Ga and Zn. &lt;2&gt; The thin film transistor according to &lt;1&gt;, wherein the polycrystalline oxide semiconductor is an In-Ga-Zn-O-based transparent oxide. &lt;3&gt; The thin film transistor according to &lt;1&gt; or &lt;2&gt;, wherein the polycrystalline oxide semiconductor has a crystallinity of 70% or more. &lt;4&gt; A temperature region in which a thin film of an amorphous oxide semiconductor containing at least one element in the group consisting of In, Ga, and Zn is polycrystalline while maintaining its surface roughness Ra value of 1.5 nm or less. A method for producing a polycrystalline oxide semiconductor thin film, which comprises a step of firing in. &lt;5&gt; The method for producing a polycrystalline oxide semiconductor thin film according to &lt;4&gt;, wherein the polycrystalline thin film contains an In-Ga-Zn-O-based transparent oxide. &lt;6&gt; The method for producing a polycrystalline oxide semiconductor thin film according to &lt;4&gt; or &lt;5&gt;, wherein the temperature range is 660 ° C or more and 840 ° C or less. &lt;7&gt; The method for producing a polycrystalline oxide semiconductor thin film according to any one of &lt;4&gt; to &lt;6&gt;, wherein the firing is performed in an oxygen atmosphere. &lt;8&gt; Temperature at which a layer made of an amorphous oxide semiconductor containing at least one element in the group consisting of In, Ga, and Zn is polycrystalline while maintaining its surface roughness Ra value of 1.5 nm or less. A method for producing a thin film transistor, which comprises a step of firing in a region to form an active layer. &lt;9&gt; The method for producing a thin film transistor according to &lt;8&gt;, wherein the active layer contains an In-Ga-Zn-O-based transparent oxide. &lt;10&gt; The method for manufacturing a thin film transistor according to &lt;8&gt; or &lt;9&gt;, wherein the temperature range is 660 ° C or more and 840 ° C or less. &lt;11&gt; The method for manufacturing a thin film transistor according to any one of &lt;8&gt; to &lt;10&gt;, wherein the firing is performed in an atmosphere containing oxygen.</p>

<p> According to the present invention, a thin film transistor made of an oxide semiconductor containing at least one element in the group consisting of In, Ga and Zn can have high TFT characteristics, and a polycrystalline oxide semiconductor thin film can be manufactured. A method and a method for manufacturing a thin film transistor are provided.</p>

Hereinafter, an example of the embodiment of the present invention will be described with reference to the drawings.

Those having substantially the same function are described with the same reference numerals throughout the drawings, and the description may be omitted in some cases. Further, in the present embodiment, "transparent" means transparent or translucent with respect to visible light, and substantially has a light transmittance of 20% or more with respect to visible light.

Further, in the present embodiment, the term "polycrystal" refers to a thin film having a crystallinity of 70% or more, which will be described later, and the term "amorphous" refers to a thin film having a crystallinity of less than 70%.

FIG. 1 is a schematic view of the polycrystalline oxide semiconductor thin film produced in the present embodiment.

The polycrystalline oxide semiconductor thin film 10 according to the present embodiment is provided on the substrate 12.

(Thin film) The polycrystalline oxide semiconductor thin film 10 of the present invention contains a polycrystalline IGZO-based oxide semiconductor and has high flatness. Therefore, when the polycrystalline oxide semiconductor thin film 10 is used as the active layer of the TFT, it is possible to avoid deterioration of the TFT characteristics and variation in quality due to carrier traps caused by the unevenness of the surface of the active layer.

The flatness according to the present embodiment is expressed by the Ra value defined by the following equation in the JIS standard, and this value is 1.5 nm or less, preferably 1.0 nm or less, and more preferably 0.8 nm or less. Is.

<maths num="1"><img file="JP2010177431A_D0001.tif" /></maths> However, Ra is the value measured by the atomic force microscope, L is the scanning distance of the line profile, and F (x) is the height of the measurement point x. The maximum height Ry is also a value defined by the JIS standard, which is the height difference between the highest point and the lowest point in the scanning range.

The polycrystalline oxide semiconductor thin film 10 may contain polycrystalline IGZO as a main component, and may also contain amorphous IGZO, impurities, and the like.

As IGZO, for example, an oxide containing at least one of In, Ga and Zn (for example, In-O type) is preferable, and an oxide containing at least two of In, Ga and Zn (for example, In-) is preferable. Zn-O-based, In-Ga-based, Ga-Zn-O-based) is more preferable, and oxides containing In, Ga and Zn are particularly preferable. In particular, the composition in the crystalline state is InGaO₃(ZnO)_mPolycrystalline oxide represented by (m is a natural number less than 6) is preferable, among which InGaZnO₄Is more preferable.

IGZO has transparency according to the thickness of the thin film 10 not only in the amorphous state but also in the polycrystalline state, and the polycrystalline oxide semiconductor thin film 10 containing IGZO is about 80 with respect to visible light. Has a light transmittance of% or more (see Fig. 10).

The shape, structure, size, etc. of the polycrystalline oxide semiconductor thin film 10 are not particularly limited, and may be selected according to the application, purpose, and the like of the thin film.

(substrate) The material of the substrate 12 is not particularly limited as long as it has heat resistance in the firing temperature range described later, and examples thereof include an inorganic material, a metal material, and an organic material. In this embodiment, in particular, heat resistant, such as YSZ (zirconia-stabilized yttrium), glass, quartz, sapphire, MgO, SiC, ZnO, LiF, CaF₂Inorganic materials such as, etc. are preferably mentioned.

The shape, structure, size, etc. of the substrate 12 are not particularly limited, and may be selected according to the application, purpose, etc. of the thin film.

Such a polycrystalline oxide semiconductor thin film 10 is suitably applied as the following active layer of TFT.

(TFT configuration) The TFT according to the present embodiment has at least a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, and a voltage is applied to the gate electrode to control the current flowing through the active layer to control the current flowing through the active layer. It is an active element having a function of switching the current between the drain electrodes.

The TFT structure may have either an inverted staggered structure (also referred to as a bottom gate type) or a staggered structure (also referred to as a top gate type).

FIG. 2 is a schematic diagram showing an example of a TFT having an inverted staggered structure, which is a TFT according to the present embodiment. The TFT 20 has a gate electrode 24, a gate insulating layer 26, and an active layer 28 stacked in this order on a substrate 12, and the source electrode 30 and the drain electrode 32 are separated from each other on the surface of the active layer 28. It is an installed configuration.

On the other hand, FIG. 3 is a schematic diagram showing an example of a TFT having a staggered structure, which is a TFT according to the present embodiment. In the TFT 40, the active layer 28 is laminated on the surface of the substrate 12, the source electrode 30 and the drain electrode 32 are installed on the active layer 28 so as to be separated from each other, and the gate insulating layer 26 and the gate electrode 24 are further placed on these. And are stacked in order.

The TFT according to the present embodiment can have various configurations other than the above, and even if it is appropriately provided with a protective layer on the active layer 28, an insulating layer on the substrate 12, and the like. Good.

(Gate electrode) The gate electrode 24 controls the current flowing between the source electrode 30 and the drain electrode 32 by applying a voltage. Examples of the material forming the gate electrode 24 include metals such as Al, Mo, Cr, Ta, Ti, Au and Ag, alloys such as Al-Nd and APC, tin oxide, zinc oxide, indium oxide and indium tin oxide. Preferred examples thereof include metal oxide conductors such as (ITO) and indium tin oxide (IZO), organic conductive compounds such as polyaniline, polythiophene and polypyrrole, or mixtures thereof.

The thickness of the gate electrode 24 is preferably 10 nm or more and 1000 nm or less.

When the TFT is an inverted staggered TFT 20, the gate electrode 24 is formed below the active layer 28. Therefore, as will be described later, the gate electrode 24 is also fired together with the active layer 28 in a high temperature region. , It is preferable that the material has heat resistance in this temperature range. On the other hand, in the case of the staggered TFT 40, since the gate electrode 24 is formed above the active layer 28, it does not have to be fired in a high temperature region and does not have heat resistance.

(Gate insulating layer) Examples of the material for forming the gate insulating layer 26 include an inorganic compound and an organic compound having a high relative permittivity.

Examples of the inorganic compound include silicon oxide, silicon nitride, germanium oxide, germanium nitride, aluminum oxide, aluminum nitride, yttrium oxide, tantalum oxide, hafnium oxide, silicon nitride nitride, silicon carbide oxide, silicon nitride carbide, silicon nitride nitride, and the like. Examples thereof include germanium oxide, germanium oxide, germanium carbide, germanium oxide, germanium oxide, aluminum nitride, aluminum oxide, aluminum nitride, aluminum nitride and mixtures thereof.

Examples of the organic compound include polyimide, polyamide, polyester, polyacrylate, photoradical polymerization type, photocationic polymerization type photocurable resin, copolymer containing an acrylonitrile component, polyvinylphenol, polyvinyl alcohol, novolak resin, and Examples thereof include cyanoethylpurulan. In addition, particles obtained by coating these polymer fine particles with an inorganic oxide can also be mentioned.

The film thickness of the gate insulating layer 26 is preferably 30 nm to 3 μm, more preferably 50 nm to 1 μm.

When the TFT is an inverted staggered TFT 20, the gate insulating layer 26 is formed below the active layer 28. Therefore, as will be described later, the gate insulating layer 26 is also fired together with the active layer 28 in a high temperature region. Therefore, it is preferable that the material has heat resistance in this temperature range. On the other hand, in the case of the staggered TFT 40, since the gate insulating layer 26 is formed above the active layer 28, it does not have to be fired in a high temperature region and does not have heat resistance.

(Active layer)

The active layer 28 has the same structure as the polycrystalline oxide semiconductor thin film 10 described above.

The thickness of the active layer 28 varies depending on the use and purpose of the TFT, but is preferably 10 nm or more and 1 μm or less, more preferably 20 nm or more and 500 nm or less, and particularly preferably 30 nm or more and 200 nm or less.

(Source electrode and drain electrode) The source electrode 30 and the drain electrode 32 are formed on the active layer 28 so as to be separated from each other.

The source electrode 30 and the drain electrode 32 are not particularly limited as long as they are conductive materials, and for example, platinum, gold, silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, aluminum, zinc, magnesium, etc. Molybdenum, alloys of these metals, conductive metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), inorganic and organic semiconductors with improved conductivity by doping, etc. (silicon single crystal, polysilicon, Amorphous silicon, germanium, graphite, polyacetylene, polyparaphenylene, polythiophene, polypyrrole, polyaniline, polythienylene vinylene, polyparaphenylene vinylene, etc.), and composites of these materials can be mentioned. In particular, the electrode material used for the source region and the drain region is preferably one having a low electrical resistance at the contact surface with the active layer 28 among the above materials.

The thickness of the source electrode 30 and the drain electrode 32 is preferably 10 nm or more and 1 μm or less, more preferably 30 nm or more and 500 nm or less, and particularly preferably 50 nm or more and 200 nm or less.

In the case of TFTs 20 and 40 as well, since the source electrode 30 and the drain electrode 32 are formed above the active layer 28, they do not have to be fired in a high temperature region and do not have heat resistance.

(Manufacturing method of polycrystalline oxide semiconductor thin film) Hereinafter, the method for producing the above-mentioned polycrystalline oxide semiconductor thin film 10 will be described in detail.

4 (a) to 4 (c) are main partial process diagrams of the method for manufacturing the polycrystalline oxide semiconductor thin film according to the present embodiment, and are vertical cross-sectional views of the polycrystalline oxide semiconductor thin film 10 shown in FIG. ..

1. First step First, as shown in FIGS. 4 (a) and 4 (b), a known method such as a sputtering method or a pulsed laser vapor deposition method (PLD method) is used on the substrate 12 to form an In. A thin film 10A made of an amorphous oxide semiconductor containing at least one element in the group consisting of Ga and Zn is formed. Here, as the target of the sputtering method or the PLD method, a polycrystalline sintered body having an IGZO-based composition may be used alone, or an IGZO-based polycrystalline sintered body and a ZnO target may be used at the same time. IGZO-based polycrystalline sintered body and Ga₂O₃Targets may be used at the same time, or In₂O₃Target, Ga₂O₃The target and the ZnO target may be used at the same time.

2. Second step Next, as shown in Fig. 4 (b), the temperature at which a thin film 10A made of an amorphous oxide semiconductor is charged into an electric furnace and polycrystallized while maintaining its surface roughness Ra value at 1.5 nm or less. Bake in the area. This temperature range is 660 ° C or higher and 840 ° C or lower, preferably 667 ° C or higher and 800 ° C or lower, and particularly preferably 700 ° C or higher and 800 ° C or lower.

As other conditions for the above firing, for example, it is preferable to fire in an oxygen atmosphere because IGZO tends to cause oxygen deficiency.

By applying the above steps, the polycrystalline oxide semiconductor thin film 10 as shown in FIGS. 4 (c) and 1 can be obtained.

(Manufacturing method of inverted staggered thin film transistor) Hereinafter, the method for producing the above-mentioned inverted stagger type TFT20 will be described in detail.

In the present embodiment, since the active layer 28 is formed by a known method, the description thereof will be omitted as appropriate.

5 (a) to 5 (c) are main partial process charts of the thin film transistor manufacturing method according to the present embodiment, and are vertical cross-sectional views of the inverted staggered TFT 20 shown in FIG.

First, as shown in FIG. 5A, the gate electrode 24 and the gate insulating layer 26 are sequentially formed by the following known methods. As a method for forming the gate electrode 24, for example, a gate electrode 24 patterned by photolithography is formed on a substrate 12 after forming a film by sputtering with a material having heat resistance in the above temperature range selected from the above. There is a way to do it. Further, as a method for forming the gate insulating layer 26, for example, a physical vapor deposition method such as a vapor deposition method, a sputtering method, or an ion plating method is used by using a material having heat resistance in the above temperature range selected from the above. There are liquid phase growth methods such as method (PVD), various chemical vapor deposition methods (CVD), and plating and solgel methods.

Next, as shown in FIG. 5 (b), a group consisting of In, Ga, and Zn is formed on the gate insulating layer 26 by the same method as the first step of the method for producing the polycrystalline oxide semiconductor thin film 10. A layer 28A made of an amorphous oxide semiconductor containing at least one element is formed.

Then, the layer 28A made of the amorphous oxide semiconductor is fired by the same method as the second step of the method for producing the polycrystalline oxide semiconductor thin film 10.

As a result, the active layer 28 according to the present embodiment can be obtained as shown in FIG. 5 (c).

Finally, the source electrode 30 and the drain electrode 32 are formed on the active layer 28 apart from each other in the same manner as the gate electrode 24 to obtain a TFT 20 as shown in FIG.

(Manufacturing method of staggered thin film transistor) Hereinafter, the method for manufacturing the above-mentioned inverted stagger type TFT40 will be described in detail.

In the present embodiment, since the active layer 28 is formed by a known method, the description thereof will be omitted as appropriate.

6 (a) to 6 (c) are main partial process diagrams of the method for manufacturing a thin film transistor according to the present invention, and are vertical cross-sectional views of the staggered TFT 40 shown in FIG.

First, as shown in FIGS. 6 (a) and 6 (b), a group consisting of In, Ga, and Zn is formed on the substrate 12 by the same method as the first step of the method for producing the polycrystalline oxide semiconductor thin film 10. A layer 28A made of an amorphous oxide semiconductor containing at least one of these elements is formed.

Then, the layer 28A made of the amorphous oxide semiconductor is fired by the same method as the second step of the method for producing the polycrystalline oxide semiconductor thin film 10.

As a result, the active layer 28 according to the present embodiment can be obtained as shown in FIG. 6 (c).

Finally, the source electrode 30, the drain electrode 32, the gate insulating layer 26, and the gate electrode 24 are sequentially formed by a known method as described above to obtain a TFT 40 as shown in FIG.

Although the present embodiment has been described above, the present invention is not limited to this embodiment. For example, the manufacturing process includes a step of patterning the layer 28A before firing or the active layer 28 after firing by photolithography according to the active layer 28 to be formed, and holes corresponding to the active layer 28 to be formed. A step of forming the layer 28A before firing at a predetermined position and shape via a mask may be included.

Further, although the case where the firing of the second step in the TFT 20 or the TFT 40 is performed before forming the source electrode and the drain electrode or the gate insulating layer 26 and the gate electrode 24 on the active layer 28 has been described, In and Ga have been described. If the amorphous oxide semiconductor containing at least one element in the group consisting of and Zn can be polycrystalline, it may be performed after forming all of them. However, in this case, it is better to form the gate electrode 24, the gate insulating layer 26, the source electrode 30 and the drain electrode 32 so as to have heat resistance in the above temperature range.

Further, as a method for polycrystallizing the amorphous thin film 10A and layer 28A, in addition to firing in an electric furnace, for example, a method such as SPC method (Solid Phase Crystallization) or RTA method (Rapid Thermal Annealing) can be used. However, if laser annealing (ELA: Excimer Laser Annealing) is performed by irradiating an excimer laser beam using XeCl, an increase in substrate temperature can be suppressed, and a substrate 12 having low heat resistance can be used.

Furthermore, the IGZO constituting the active layer 28 generally has oxygen indefinite specificity. Therefore, IGZO in this embodiment, for example, InGaO₃(ZnO)_mAnd InGaZnO₄May include those in which the amount of oxygen has increased or decreased.

Hereinafter, examples according to the present invention will be described.

Examples of the polycrystalline oxide semiconductor thin film 10 according to the present invention will be described with reference to FIGS. 1 and 4. The same applies to the examples of the active layer 28 of TFT20 and TFT40, and the description thereof will be omitted.

(Manufacturing of polycrystalline oxide semiconductor thin film) In this example, the polycrystalline oxide semiconductor thin film 10 made of IGZO was formed by undergoing the above-mentioned sputtering film formation (first step) and firing in an oxygen atmosphere (second step).

In the first step, an IGZO (In: Ga: Zn = 1: 1: 1) target and a ZnO target are placed on a 10 mm square glass substrate 12 by a sputtering method, and a mixed gas of argon and oxygen (argon) is used. IGZO having a film thickness of about 150 nm, co-sputtered in an atmosphere of about 99% and about 1% oxygen), that is, an amorphous substance containing at least one element in the group consisting of In, Ga and Zn. A thin film 10A made of a quality oxide semiconductor was formed. The composition ratio of this thin film 10A was In: Ga: Zn = 1.11: 0.91: 1.00 as confirmed by a known fluorescent X-ray analysis method.

The reason why the ZnO target is used separately is to compensate for the decrease in ZnO sputtering efficiency due to the IGZO target. When the target of IGZO (In: Ga: Zn = 1: 1: 1) is used alone, the composition ratio of the thin film 10A becomes about 1: 0.9: 0.7, and Ga and Zn are slightly reduced. Therefore, preferably IGZO and Ga₂O₃, Co-sputter the ZnO target or In₂O₃, Ga₂O₃, ZnO target is co-sputtered to obtain IGZO (In: Ga: Zn = 1: 1: 1) thin film 10A, but in this example, IGZO and ZnO target are used together, and the resulting thin film 10A is obtained. Apparently InGaZnO₄It was treated as a thin film of (In: Ga: Zn = 1: 1: 1).

Since it was possible to sputter eight substrates 12 with one sputtering, the first step was repeated twice to obtain 10 thin film samples.

In the second step, one is removed from the above thin film sample, the others are placed in an electric furnace, and the temperature is between 600 ° C and 1000 ° C (600 ° C, 633 ° C, 667 ° C, 700 ° C, 733 ° C). , 767 ° C, 800 ° C, 833 ° C, 900 ° C) for 1 hour. In this electric furnace, the flow rate is 200 sccm (SI unit system, 0.338 Pa m) during firing.³100% oxygen gas adjusted to / s) was flowed.

Hereinafter, for convenience of explanation, each sample name is described. Sample 1: Thin film before firing, Sample 2: Thin film fired at 600 ° C, Sample 3: Thin film fired at 633 ° C, Sample 4: Thin film fired at 667 ° C, Sample 5: Fired at 700 ° C Thin film, sample 6: 733 ° C fired thin film, sample 7: 767 ° C fired thin film, sample 8: 800 ° C fired thin film, sample 9: 833 ° C fired thin film, sample 10: 900 Thin film fired at ° C

(X-ray diffraction measurement) The diffraction intensity of each thin film sample 1 to 10 was measured by a well-known X-ray diffraction method using a measuring device Rint-Ultima III (Rigaku).

The measurement conditions are as follows. Measurement angle range: 15deg ~ 80deg Step width: 0.01deg Scanning speed: 4deg / min

FIG. 7 is a diagram showing X-ray diffraction patterns of the thin film samples 1 to 10 according to this embodiment. This diffraction pattern is after smoothing the measurement data obtained by performing the X-ray diffraction measurement.

The diffraction patterns of each thin film sample 4 to 10 fired at 667 ° C to 900 ° C are space group R-3m (166), a-axis lattice constant = about 3.295 Å, b-axis lattice constant = about 3.295 Å, c-axis. InGaZnO with lattice constant = about 26.070 Å, inter-axis angle α, β = 90 degrees, inter-axis angle γ = 120 degrees₄(101), (104), (10-5), (110) Crystal planes, etc. can be indexed, and each thin film sample calcined at 667 ° C to 900 ° C 4 to 10 Was confirmed to be an oxide semiconductor of IGZO.

(Calculation of crystallinity) Next, the diffraction pattern was subjected to multiple peak separation in the range of 25 ° C to 40 ° C. using analysis software JADE (Rigaku), and the crystallinity of each sample 1 to 10 was calculated. This crystallinity is expressed by the following equation.

<maths num="2"><img file="JP2010177431A_D0002.tif" /></maths> The polycrystalline peak and the amorphous peak can be classified according to the half-value width obtained by the multiple peak separation. In this example, IGZO (009), (101), (104), and (10) can be classified. -5) The peaks with a half width of 2.0 or less located at the angle of the crystal plane were defined as polycrystalline peaks, and those with a half width of 2.0 or more were defined as amorphous peaks.

Table 1 summarizes the experimental results related to this example.

As shown in Table 1, the thin film samples 4 to 10 calcined at 667 ° C to 900 ° C were judged to be polycrystalline because the crystallinity was 70% or more.

On the other hand, the samples before firing and the thin film samples 1 to 3 fired at 600 ° C to 633 ° C were judged to be amorphous because the crystallinity was less than 70%.

(Surface roughness measurement) The surface roughness of each thin film sample was measured using an AFM image of 3 μm square of each sample by an atomic force microscope (AFM, Nano-R manufactured by Pacific Nanotechnology).

Here, the "surface roughness" is specifically the average value of the surface roughness Ra obtained from three line profiles having a scanning distance of 3 μm in the AFM image of each sample. At the same time, the maximum height Ry was measured by the same method. In the following, the average value of Ra is referred to as "Ra average", and the average value of Ry is referred to as "Ry average".

The maximum height Ry is also a value defined by the JIS standard, and is the height difference between the highest point and the lowest point in the scanning range.

FIG. 8 is a diagram showing the measurement results of the surface roughness Ra. Further, FIG. 9 is a diagram showing the measurement result of the maximum height Ry.

From Fig. 8, Fig. 9 and Table 1, the Ra average (Ra value) is 1.5 nm or less and the Ry average is 8.0 nm from the thin film sample before firing and the thin film sample fired at 600 ° C to 800 ° C. It was confirmed that both are relatively small values. On the other hand, it was confirmed that both the Ra average and the Ry average of the sample calcined at 833 ° C or higher increased sharply.

Based on the above results, referring to Table 1, by firing the IGZO-based amorphous oxide semiconductor thin film 10A at 667 ° C to 833 ° C, the surface roughness is similar to that of the thin film 10A. The polycrystalline oxide semiconductor thin film 10 can be produced by firing the crystalline oxide semiconductor thin film 10, that is, the thin film 10A in a temperature region where it is polycrystalline while maintaining the surface roughness Ra value of 1.5 nm or less. You can see that.

If the polycrystalline oxide semiconductor thin film 10 fired in this temperature range is used for the active layer 28 of the TFT 20 or TFT 40, the carrier mobility is higher than that of the IGZO-based amorphous TFT, and the deterioration of the yield due to the unevenness of the channel layer can be reduced. ..

(Transparency) The light transmittance of each thin film sample was measured using a spectrophotometer U-3310 manufactured by Hitachi, Ltd.

The measurement conditions are as follows. Mode: Wavelength scan Data mode:% T Scan range: 240 ~ 900nm Scan speed: 600 nm / min Sampling interval: 1.00 nm Slit: 2 nm Photomal voltage: automatic control Light source switching mode: Automatic switching Light source switching wavelength: 340.00 nm

FIG. 10 is a diagram showing the measurement results of the light transmittance of the thin film sample according to this example.

As shown in FIG. 10 and Table 1, it was confirmed that each thin film sample had a light transmittance of about 80% or more with respect to visible light regardless of whether it was amorphous or not. It was also found that the light transmittance can be improved on the low wavelength side by raising the firing temperature.

In addition, FIG. 10 and Table 1 show the measurement results of the light transmittance of the thin film sample before firing and the thin film samples 2, 5 and 8 fired at 600 ° C, 700 ° C and 800 ° C. It was confirmed that other thin film samples were also transparent to visible light.

Similar to the amorphous oxide semiconductor thin film 10A, such a transparent polycrystalline oxide semiconductor thin film 10 can be used for the active layer 28 of TFT 20 or TFT 40, which is required to have transparency, and has an activity made of other materials. It will be more useful than layer 28.

<tables num="1"><img file="JP2010177431A_D0003.tif" /></tables>

<figref num="1">It is a schematic diagram of the polycrystalline oxide semiconductor thin film produced in this embodiment.</figref><figref num="2">It is a schematic diagram which shows an example of the TFT of the inverted stagger type structure which is the TFT which concerns on this embodiment.</figref><figref num="3">It is a schematic diagram which shows an example of the TFT of the stagger type structure which is the TFT which concerns on this embodiment.</figref><figref num="4">(a) to (c) are main partial process charts of the method for manufacturing a polycrystalline oxide semiconductor thin film according to the present embodiment, and are vertical cross-sectional views of the polycrystalline oxide semiconductor thin film shown in FIG.</figref><figref num="5">(a) to (c) are main partial process charts of the thin film transistor manufacturing method according to the present embodiment, and are vertical cross-sectional views of the inverted staggered TFT shown in FIG.</figref><figref num="6">(a) to (c) are main partial process charts of the method for manufacturing a thin film transistor according to the present invention, and are vertical cross-sectional views of the staggered TFT shown in FIG.</figref><figref num="7">It is a figure which shows the X-ray diffraction pattern of the thin film sample which concerns on this Example.</figref><figref num="8">It is a figure which shows the measurement result of the surface roughness Ra.</figref><figref num="9">It is a figure which shows the measurement result of the maximum height Ry.</figref><figref num="10">It is a figure which shows the measurement result of the light transmittance of the thin film sample which concerns on this Example.</figref>

10 Polycrystalline oxide semiconductor thin film 10A amorphous oxide semiconductor thin film 12 board 20, 40 TFT 24 Gate electrode 26 Gate insulating layer 28 Active layer 28A layer 30 Source electrode 32 Drain electrode