Semiconductor integrated circuit device and operating method thereof

The present invention relates to a semiconductor integrated circuit device and its operation method, and in particular, even if the storage capacity of the built-in semiconductor memory using the replica bit line (RBL) is increased, the fluctuation of the generation timing of the sense amplifier enable signal is changed. Regarding technologies that are useful for mitigation.

A minute amplitude bit line (BL) and a clocked sense amplifier are used to read out SRAM (Stick Random Access Memory) built into a semiconductor integrated circuit device at high speed and with low power consumption. However, for fast and reliable operation, the sense amplifier enable (SAE) signal must track global and local process, voltage and temperature (PVT) delay fluctuations on the minute amplitude bit line (BL). .. If the sense amplifier enable (SAE) signal is activated before the differential bit line signal exceeds the sense amplifier offset, a read error will occur at the sense amplifier output. Conversely, too late activation of the sense amplifier enable (SAE) signal will unnecessarily increase access time and power consumption.

In Non-Patent Document 1 below, replica bit lines (RBL) track bit line (BL) delays better than simple buffer chains with respect to global (PVT) skew, so replica bit lines (RBL) in SRAM. ) Is used to set the self-timing of the sense amplifier enable (SAE) signal. In this SRAM, a replica word line (RWL), a replica memory cell, a replica bit line (RBL), a dummy memory cell, and an inverter are arranged between a word decoder and a sense amplifier. In the read operation, the replica word line (RWL) generated from the word decoder is asserted in response to the clock signal, multiple replica memory cells are turned on, and the replica bits to which the load dummy memory cells are connected are connected. Discharge the wire (RBL). The sense amplifier enable (SAE) signal generated by the full amplitude replica bit line (RBL) signal being inverted and buffered by the inverter is fed to the sense amplifier. Replica Bitline (RBL) signals are also used to limit bitline amplitude and deactivate wordlines to save power. Global PVT fluctuations correlate read current fluctuations in memory cells of the same semiconductor die, enabling good tracking of replica bit line (RBL) delays and bit line (BL) delays. Is.

<nplcit num="1"><text>Umut Arslan et al, Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines, IEEE 2008 Custom Integrated Circuits Conference (CICC) 21-24 Sept, 2008, PP.415 ~ 418.</text></nplcit>

<p> Prior to the present invention, the present inventors have been engaged in research and development of a system LSI called a system on chip (SoC) incorporating a large number of intellectual property rights (IP) cores and various types of memories corresponding to a large number of IP cores. Engaged.</p><p> Due to the miniaturization of the semiconductor manufacturing process, the cell size of the memory cell has been reduced, and it has become possible to incorporate a larger capacity memory into the SoC. On the other hand, due to process miniaturization, local delay fluctuations in semiconductor manufacturing processes are increasing. In order to track the delay of the bit line (BL) of the built-in SRAM due to the local delay fluctuation of the semiconductor manufacturing process, the sense amplifier enable using the replica bit line (RBL) described in Non-Patent Document 1 above. Self-timing of (SAE) signals is an effective technique.</p><p> FIG. 1 is a diagram showing a configuration of a SRAM using a replica bit line (RBL) examined by the present inventors based on the technique described in Non-Patent Document 1 prior to the present invention.</p><p> The SRAM shown in Fig. 1 includes a word driver (WD), a decoding control circuit (CTRL), a replica word line (rplwl), and multiple (j, j&gt; 1) replica memory cells (RPCELL). , Replica bit lines (rplbt), multiple (k, k&gt; 1) dummy memory cells (DMYCELL), precharge transistors (PCH), inverter (INV), buffer (BUF) Includes. Further, the SRAM shown in FIG. 1 has a plurality of (n + 1&gt; 1) word lines (wl [0] to [n]) and a plurality of (m + 1&gt; 1) bit lines / inverted bit line pairs ( bt [0], bb [0] ~ bt [m], bb [m]), multiple ((n + 1) × (m + 1)) SRAM / memory cells (MEMCELL), and multiple ((n + 1) × (m + 1)) Includes m + 1&gt; 1) sense amplifier (SA).</p><p> By supplying the clock CLK and the address signals [0] to [h] to the decode control circuit CTRL, the decode control circuit CTRL supplies the decoder signals dec [0] to [i] to the word driver WD for decoding. The replica word line signal rplwl is supplied from the control circuit CTRL to the precharge transistor PCH and a plurality of (j) replica memory cells RPLCELL. The source of the P-channel MOS transistor P0 as the precharge transistor PCH is the power supply voltage V._DDThe drain of transistor P0 is connected to the replica bit line rpfbt. This replica bit line rpfbt is connected to multiple (k&gt; 1) dummy memory cells DMYCELL, multiple (j&gt; 1) replica memory cells RPLCELL, and the input terminals of the inverter INV. The inverting replica bit line rpfbtn generated from the output terminal of the inverter INV is supplied to the decode control circuit CTRL and the input terminal of the buffer BUF, and the sense amplifier enable signal sae is generated from the output terminal of the buffer BUF, and multiple (m) It is supplied to the sense amplifier SA of + 1&gt; 1). Difference between multiple sense amplifier SAs with SRAM cell read signals from multiple (m + 1&gt; 1) bit line / inverted bit line pairs bt [0], bb [0] to bt [m], bb [m] By being supplied to the dynamic input terminals, read data q [0] to [m] are generated from the output terminals of a plurality of sense amplifiers SA.</p><p> FIG. 2 is a waveform diagram of each part of the SRAM shown in FIG. 1 for explaining the operation of the SRAM shown in FIG.</p><p> As shown in FIG. 2, one selected signal of the decoder signals dec [0] to [i] stands in response to the address signals [0] to [h] that change in synchronization with the rising edge of the clock signal CLK. Go down. From the word lines of wl [0] to [n], one word line corresponding to the address signal is selected and started up. Multiple (m + 1&gt; 1) bit lines / inverted bit lines paired with bt [0], bb in response to the memory retention state of the multi-bit (m + 1) memory cell to which the rising selected word line is connected. The charge of one bit line of each bit line / inverted bit line pair of [0] to bt [m] and bb [m] begins to be extracted. While the replica word line rplwl is at a low level, the replica bit line rplbt is at a high level due to the P channel MOS transistor P0, which is a precharge transistor PCH._DDIs precharged to.</p><p> On the other hand, in response to the rising edge of the clock signal CLK, the potential of the replica word line rplwl rises to a high level. Inside multiple (j) replica memory cells RPLCELL, a high level power supply voltage V is applied to the input terminal of the CMOS inverter composed of the P-channel MOS transistor P11 and the N-channel MOS transistor N11._DDIs supplied, so the output terminal of this CMOS inverter is maintained at the ground potential GND. When the potential of the replica word line rplwl rises to a high level, the N-channel MOS transistor N12 as the transfer transistor inside multiple (j) replica memory cells RPLCELL is turned on, so the replica bit line rpfbt The precharge charge is discharged to the ground potential GND via the plurality (j) transfer transistors N12 inside the plurality (j) replica memory cells RPLCELL. When the potential of the replica bit line rplbt drops to a level lower than the logical threshold value of the inverter INV due to this discharge, the output of the inverter INV becomes a high level and the potential of the inverted replica bit line rplbtn rises. Inverted replica bit line rpfbtn The signal of is supplied to the input terminal of the buffer BUF, and the sense amplifier enable signal sae generated from the output terminal of the buffer BUF is supplied to a plurality of (m + 1&gt; 1) sense amplifier SAs. Potential difference ΔV of multiple (m + 1&gt; 1) bit line / inverted bit line pairs (bt [0], bb [0] to bt [m], bb [m]) of the rising timing of the sense amplifier enable signal sae Is amplified by a plurality of (m + 1&gt; 1) sense amplifiers SA, and the read data q [0] to [m] are output. If the potential difference ΔV between the bit line / inverted bit line pair is smaller than the offset of the input potential difference of the sense amplifier SA, data reading fails. Selection of word line wl [0] to [n] The potential of the word line rises and the potential difference ΔV between multiple (m + 1&gt; 1) bit lines and inverted bit lines is from the offset of the input potential difference of the sense amplifier SA. The timing is adjusted so that the timing at which the replica word line rplwl rises and the timing at which the replica bit line rplbl falls and the sense amplifier enable signal sae rises are approximately simultaneous. The adjustment of the rising timing of the potential of the sense amplifier enable signal sae can be performed by adjusting the number (j) of replica memory cells RPLCELL connected to the replica bit line rpfbt. That is, by increasing or decreasing the number of replica memory cells RPLCELL (j), the discharge rate of the precharge charge of the replica bit line rplbt to the ground potential GND is increased or decreased, and the rising timing of the potential of the sense amplifier enable signal sae is increased or decreased. Adjustment is possible.</p><p> As described above, by adopting the self-timing setting technique of the sense amplifier enable signal using the replica bit line (RBL) described in Non-Patent Document 1, the local delay fluctuation of the semiconductor manufacturing process is caused. It is possible to realize delayed tracking of the bit line (BL) of the built-in SRAM.</p><p> However, a sense amplifier enable signal in SRAM using a replica bit line, which was examined by the present inventors prior to the present invention based on the technique described in Non-Patent Document 1 described in FIGS. 1 and 2. It has become clear that the self-timing setting technology has the following problems.</p><p> This is a problem when the delay of the replica bit line rbpbt increases due to the increase in the number of words due to the increase in the storage capacity of the internal memory built into the SoC. That is, when the delay of the replica bit line rplbt increases due to the increase in the number of words due to the increase in the storage capacity, multiple (j) replica memories that discharge the precharge charge of the replica bit line rplbt to the ground potential GND. The delay fluctuation of the replica bit line rplbt increases due to the fluctuation of the cell current due to the local fluctuation of the cell RPLCELL. Furthermore, as the storage capacity is increased, the local fluctuation of the logical threshold value of the inverter INV to which the replica bit line rbpbt signal is supplied increases. As a result, it was clarified that the delay fluctuation of the replica bit line rpfbt and the local fluctuation of the logical threshold value of the inverter INV increase the fluctuation of the generation timing (rising timing) of the sense amplifier enable signal sae. This fluctuation causes a failure in reading data at the output terminal of the sense amplifier SA.</p><p> FIG. 17 shows the delay variation of the replica bit line rpfbt of the SRAM using the replica bit line and the logical threshold value of the inverter INV, which were examined by the present inventors prior to the present invention described in FIGS. 1 and 2. It is a figure which shows the state of the fluctuation of the generation timing (rising timing) of the sense amplifier enable signal sae due to the local fluctuation of.</p><p> In the example of FIG. 17, the number of SRAM word lines (wl [0] to [n]) is 1024, and the signal of the replica bit line rplbt causes an amplitude change of about 1 volt with the elapsed time of t_sae. Even with this amplitude change of the replica bit line rplbt, the delay of the replica bit line rplbt may be small and the high-speed amplitude change characteristic rplbt_ft may be obtained, or the delay of the replica bit line rplbt may be large and the slow amplitude change characteristic rplbt_sl may be obtained. .. On the other hand, the logical threshold of the inverter INV to which the replica bit line rbpbt signal is supplied is the high logical threshold voltage V._LWhen th_high and low logical threshold voltage V_LIt may be th_low. Therefore, the high-speed amplitude change characteristic rpfbt_ft and the high logic threshold voltage V_LThe crossover with th_high determines when the small delay sae_ft of the sense amplifier enable signal sae is generated. In addition, the crossover between the low-speed amplitude change characteristic rplbt_sl and the low-speed amplitude change characteristic rplbt_sl determines the generation timing of the large delay sae_sl of the sense amplifier enable signal sae. As a result, it was found that the fluctuation range Δt_sae of the generation timing of the sense amplifier enable signal sae is as large as 8% of the whole.</p><p> The present invention has been made as a result of the above-mentioned studies by the present inventors prior to the present invention.</p><p> Therefore, an object of the present invention is to change the generation timing of the sense amplifier enable signal even if the storage capacity of the semiconductor memory built in the semiconductor integrated circuit device and using the replica bit line (RBL) is increased. Is to reduce.</p><p> The above and other objects and novel features of the present invention will become apparent from the description and accompanying drawings herein.</p>

<p> A typical invention disclosed in the present application will be briefly described as follows.</p><p> That is, in the semiconductor integrated circuit device according to the typical embodiment of the typical invention of the present invention, a plurality of word lines (wl [0] to wl [n]) and a plurality of bit lines (bt [0], bb [0] ~ bt [m], bb [m]), multiple normal memory cells (MEMCELL), access control circuits (WD, CTRL), multiple sense amplifiers (SA), and the first Replica bit line (rplbt [0]), second replica bit line (rplbt [1]), first replica memory cell (RPLCELL]), and second replica memory cell (RPLCELL) A first logic circuit (INV0) and a second logic circuit (INV1) are provided.</p><p> The first replica memory cell is connected to the first replica bit line, and the second replica memory cell is connected to the second replica bit line. The input terminal of the first logic circuit is connected to the first replica bit line, and the output terminal of the first logic circuit is connected to the second replica bit line. The input terminal of the second logic circuit is connected to the second replica bit line, and a sense amplifier enable signal (sae) is generated from the output terminal of the second logic circuit (see FIG. 3).</p><p> By supplying the sense amplifier enable signal (sae) to the plurality of sense amplifiers (SA), a plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and the plurality of sense amplifiers It is characterized in that a plurality of read data (q [0] to q [m]) are generated from a plurality of output terminals (see Fig. 4).</p>

<p> The effects obtained by typical inventions disclosed in the present application will be briefly described as follows. That is, even if the storage capacity of the semiconductor memory using the replica bit line (RBL) is increased, the fluctuation of the generation timing of the sense amplifier enable signal can be reduced.</p>

&lt;&lt; Typical embodiment &gt;&gt; First, a typical embodiment of the invention disclosed in the present application will be outlined. Reference numerals in the drawings referenced in parentheses in the schematic description of a typical embodiment merely exemplify those included in the concept of the component to which it is attached.

[1] A typical embodiment of the present invention is Multiple word lines (wl [0] ~ wl [n]) arranged approximately parallel to the row direction, Multiple bit lines (bt [0], bb [0] ~ bt [m], bb [m]) arranged approximately parallel in the column direction, A plurality of normal memory cells (MEMCELL) connected to the plurality of word lines and the plurality of bit lines, and An access control circuit (WD, CTRL) capable of selecting any one word line of the plurality of word lines in response to an address signal (a [0] to a [h]), and It is a semiconductor integrated circuit device including a plurality of sense amplifiers (SA) connected to the plurality of bit lines.

The semiconductor integrated circuit device includes a first replica bit line (rplbt [0]), a second replica bit line (rplbt [1]), and a first replica memory cell (RPL CELL]). It further includes a second replica memory cell (RPL CELL), a first logic circuit (INV0), and a second logic circuit (INV1).

The first replica memory cell is connected to the first replica bit line, and the second replica memory cell is connected to the second replica bit line.

The input terminal of the first logic circuit is connected to the first replica bit line, and the output terminal of the first logic circuit is connected to the second replica bit line.

The input terminal of the second logic circuit is connected to the second replica bit line, and a sense amplifier enable signal (sae) is generated from the output terminal of the second logic circuit (see FIG. 3). ..

By supplying the sense amplifier enable signal (sae) to the plurality of sense amplifiers (SA), a plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and the plurality of sense amplifiers It is characterized in that a plurality of read data (q [0] to q [m]) are generated from a plurality of output terminals (see Fig. 4).

According to the above embodiment, since the replica bit line is divided into a plurality of replica bit lines, the delay amount of each divided replica bit line is reduced. By reducing the delay amount of each divided replica bit line, the delay fluctuation of each divided replica bit line is reduced. Therefore, the variation in the generation timing of the sense amplifier enable signal (sae) due to the reduced delay variation of each replica bit line and the local variation of the logic thresholds of the first and second logic circuits (INV0, INV1) is reduced. Can be done (see Figure 18).

A semiconductor integrated circuit device according to a preferred embodiment further comprises a first precharge transistor (PCH0) and a second precharge transistor (PCH1).

The first precharge transistor is connected to the first replica bit line (rplbt [0]), and the second precharge transistor is the second replica bit line (rplbt [1]). It is connected to the.

The first precharge transistor and the second precharge transistor are described before a plurality of read data is generated from the plurality of output terminals of the plurality of sense amplifiers in response to the sense amplifier enable signal. A predetermined precharge potential (V) is applied to the first replica bit wire and the second replica bit wire, respectively._DD) Is set (see Fig. 4).

A semiconductor integrated circuit apparatus according to another preferred embodiment further comprises a first dummy memory cell (DMYCELL) and a second dummy memory cell (DMYCELL).

The first dummy memory cell is connected to the first replica bit line (rplbt [0]), and the second dummy memory cell is connected to the second replica bit line (rplbt [1]). ]) Is connected (see Fig. 3).

In the semiconductor integrated circuit apparatus according to still another preferred embodiment, the word driver (WD) included in the access control circuit is a plurality of CMOS word drivers ..., (K-1, CMOS_Drv), (K, CMOS_Drv). , (K + 1, CMOS_Drv), (K + 2, CMOS_Drv), ...

The plurality of CMOS word drivers are arranged in the column direction, and two CMOS word drivers ((K, CMOS_Drv), (K + 1, CMOS_Drv)) that are close to each other among the plurality of CMOS word drivers are in between. Includes intermediate regions (611, 612, 613, 621, 622). The first precharge transistor (PCH0) and the first logic circuit (INV0) are characterized in that they are formed inside the intermediate region (see FIGS. 5 and 6).

In a semiconductor integrated circuit apparatus according to a more preferred embodiment, the first logic circuit (701) is formed by a first CMOS memory cell (INVCELL), and the first precharge transistor (702) is formed. It is characterized by being formed by a second CMOS memory cell (PCHCELL) (see FIGS. 7, 8 and 9).

In a semiconductor integrated circuit apparatus according to an even more preferred embodiment, the first CMOS memory cell forming the first logic circuit and the second CMOS memory cell forming the first precharge transistor. Is connected to the first dummy memory cell (DMYCELL) connected to the first replica bit line (rplbt [0]) and the second replica bit line (rplbt [1]). It is characterized in that it is formed in the middle of the second replica memory cell (RPL CELL) (see FIG. 7).

In the semiconductor integrated circuit (1) according to one specific embodiment, the first dummy memory cell (703) connected to the first replica bit line (rplbt [0]) is a third. The second dummy memory cell (703) formed by a CMOS memory cell (DMYCELL) and connected to the second replica bit line (rplbt [1]) is a fourth CMOS memory cell. It is characterized in that it is formed by (DMYCELL) (see Fig. 7, Fig. 10 to Fig. 14).

One more specific embodiment is characterized in that the plurality of normal memory cells (MEMCELL) are SRAM memory cells (see FIG. 3).

[2] A typical embodiment of the present invention according to a typical embodiment of another aspect of the present invention is Multiple word lines (wl [0] ~ wl [n]) arranged approximately parallel to the row direction, Multiple bit lines (bt [0], bb [0] ~ bt [m], bb [m]) arranged approximately parallel in the column direction, A plurality of normal memory cells (MEMCELL) connected to the plurality of word lines and the plurality of bit lines, and An access control circuit (WD, CTRL) capable of selecting any one word line of the plurality of word lines in response to an address signal (a [0] to a [h]), and This is an operation method of a semiconductor integrated circuit device including a plurality of sense amplifiers (SAs) connected to the plurality of bit lines.

The semiconductor integrated circuit device includes a first replica bit line (rplbt [0]), a second replica bit line (rplbt [1]), and a first replica memory cell (RPL CELL]). It further includes a second replica memory cell (RPL CELL), a first logic circuit (INV0), and a second logic circuit (INV1).

The first replica memory cell is connected to the first replica bit line, and the second replica memory cell is connected to the second replica bit line.

The input terminal of the first logic circuit is connected to the first replica bit line, and the output terminal of the first logic circuit is connected to the second replica bit line.

The input terminal of the second logic circuit is connected to the second replica bit line, and a sense amplifier enable signal (sae) is generated from the output terminal of the second logic circuit (see FIG. 3). ..

By supplying the sense amplifier enable signal (sae) to the plurality of sense amplifiers (SA), a plurality of read signals of the plurality of bit lines are amplified by the plurality of sense amplifiers, and the plurality of sense amplifiers It is characterized in that a plurality of read data (q [0] to q [m]) are generated from a plurality of output terminals (see Fig. 4).

&lt;&lt; Explanation of the embodiment &gt;&gt; Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, parts having the same functions as those in the above figure are designated by the same reference numerals, and the repeated description thereof will be omitted.

[Embodiment 1] SRAM configuration&gt;&gt; FIG. 3 is a diagram showing a configuration of a SRAM using a replica bit line (RBL) according to the first embodiment of the present invention.

The SRAM shown in FIG. 3 is basically different from the SRAM shown in FIG. 1 in that one replica bit line rbpbt of the SRAM shown in FIG. 1 is a plurality of replica bit lines rbpbt in the SRAM shown in FIG. By dividing into 0] and rpfbt [1], the amount of delay in the replica bit line is reduced.

Similar to the SRAM shown in FIG. 1, the SRAM shown in FIG. 3 also has a word driver (WD), a decoding control circuit (CTRL), and a plurality of (n + 1&gt; 1) word lines (wl [0] to []. n]) and multiple (m + 1&gt; 1) bit line / inverted bit line pairs (bt [0], bb [0] ~ bt [m], bb [m]) and multiple ((n +) It includes 1) × (m + 1)) SRAM / memory cells (MEMCELL) and multiple (m + 1&gt; 1) sense amplifiers (SA).

The SRAM shown in FIG. 3 differs from the SRAM shown in FIG. 1 in the first replica word line (rplwl [0]), the second replica word line (rplwl [1]), and the first. Replica bit wire (rplbt [0]) and second replica bit wire (rplbt [1]), first precharge transistor PCH0 (P channel MOS transistor P0) and second precharge transistor PCH1 ( P-channel MOS transistor P1), first inverter (INV0) and second inverter (INV1), first replica memory cell (RPLCELL) and second replica memory cell (RPLCELL), and first Contains a dummy memory cell (DMYCELL) and a second dummy memory cell (DMYCELL).

By supplying the clock CLK and the address signals [0] to [h] to the decode control circuit CTRL, the decode control circuit CTRL supplies the decoder signals dec [0] to [i] to the word driver WD for decoding. The first replica word line signal rplwl [0] is supplied from the control circuit CTRL to the first precharge transistor PCH0 and a plurality of (p, p&gt; 1) first replica memory cells RPLCELL. The source of the P-channel MOS transistor P0 as the first precharge transistor PCH0 is the power supply voltage V._DDThe drain of transistor P0 is connected to the first replica bit line rpfbt [0]. This first replica bit line rpfbt [0] includes a plurality of (p&gt; 1) first replica memory cells RPLCELL and a plurality (q&gt; 1) first dummy memory cells DMYCELL. It is connected to the input terminal of the first inverter INV0. The second replica word line signal rplwl [1] generated from the output terminal of this first inverter INV0 is the second replica of the second precharge transistor PCH1 and a plurality (r pieces, r&gt; 1). It is supplied to the memory cell RPLCELL. The source of the P-channel MOS transistor P1 as the second precharge transistor PCH1 is the power supply voltage V._DDThe drain of transistor P1 is connected to the second replica bit line rpfbt [1]. This second replica bit line rpfbt [1] is a plurality of (r pieces, r&gt; 1) second replica memory cells RPLCELL and a plurality of (s pieces&gt; 1) second dummy memory cells. It is connected to the input terminal of DMYCELL and the second inverter INV1. The inverting replica bit line rpfbtn generated from the output terminal of this second inverter INV1 is supplied to the decode control circuit CTRL and the input terminal of the buffer BUF, and the sense amplifier enable signal sae is generated from the output terminal of the buffer BUF. It is supplied to multiple (m + 1&gt; 1) sense amplifiers SA. Difference between multiple sense amplifier SAs with SRAM cell read signals from multiple (m + 1&gt; 1) bit line / inverted bit line pairs bt [0], bb [0] to bt [m], bb [m] By being supplied to the dynamic input terminals, read data q [0] to [m] are generated from the output terminals of a plurality of sense amplifiers SA.

&lt;&lt; Operation of SRAM &gt;&gt; FIG. 4 is a waveform diagram of each part of the SRAM shown in FIG. 3 for explaining the operation of the SRAM according to the first embodiment of the present invention shown in FIG.

As shown in FIG. 4, one selected signal of the decoder signals dec [0] to [i] stands in response to the address signals [0] to [h] that change in synchronization with the rising edge of the clock signal CLK. Go down. From the word lines of wl [0] to [n], one word line corresponding to the address signal is selected and started up. Multiple (m + 1&gt; 1) bit lines / inverted bit lines paired with bt [0], bb in response to the memory retention state of the multi-bit (m + 1) memory cell to which the rising selected word line is connected. The charge of one bit line of each bit line / inverted bit line pair of [0] to bt [m] and bb [m] begins to be extracted. While the first replica word line rplwl [0] is at low level, the first replica bit line rplbt [0] is at high level by the P channel MOS transistor P0 which is the first precharge transistor PCH0. Power supply voltage V_DDIs precharged to. Therefore, in response to the high level of the first replica bit line rpfbt [0], the second replica word line (rplwl [1]) of the output terminal of the first inverter (INV0) becomes low level. .. As a result, in response to the low level of the second replica word line (rplwl [1]), the second replica bit line (rplbt) of the drain of the second precharge transistor PCH1 (P channel MOS transistor P1). [1]) is a high level. Therefore, in response to the high level of the second replica bit line (rplbt [1]), the inverting replica bit line rplbtn of the output terminal of the second inverter (INV1) and the sense amplifier enable of the output terminal of the buffer BUF Each signal sae is at a low level.

On the other hand, in response to the rising edge of the clock signal CLK, the potential of the first replica word line rplwl [0] rises to a high level. Inside a plurality of (p&gt; 1) first replica memory cells RPLCELL, a high level power supply voltage V is applied to the input terminal of the CMOS inverter composed of the P-channel MOS transistor P11 and the N-channel MOS transistor N11._DDIs supplied, so the output terminal of this CMOS inverter is maintained at the ground potential GND. N-channel MOS transistor N12 as an internal transfer transistor of multiple (p&gt; 1) first replica memory cells RPLCELL by raising the potential of the first replica word line rplwl [0] to a high level. Is turned on, so the precharge charge of the first replica bit line rbpbt [0] is multiple (p&gt; 1). Multiple (p) transfer transistors inside the first replica memory cell RPLCELL. It will be discharged to the ground potential GND via N12. When this discharge lowers the potential of the first replica bit line rpfbt [0] to a level lower than the logical threshold of the first inverter INV0, the second replica word line rplwl of the output of the first inverter INV0. [1] is a high level. Then, the N-channel MOS transistor N12 as the transfer transistor inside the multiple (r&gt; 1) second replica memory cells RPLCELL is turned on, so the second replica bit line rpfbt [1] is precharged. The electric charge is discharged to the ground potential GND via the plurality of (r) transfer transistors N12 inside the plurality of (r&gt; 1) second replica memory cells RPLCELL. When this discharge lowers the potential of the second replica bit line rplbt [1] to a level lower than the logical threshold of the second inverter INV1, the potential of the inverted replica bit line rplbtn of the output of the second inverter INV1 Stands up. The signal of the inverting replica bit line rbpbtn is supplied to the input terminal of the buffer BUF, and the sense amplifier enable signal sae generated from the output terminal of the buffer BUF is supplied to multiple sense amplifier SAs (m + 1&gt; 1). .. Multiple rise timings of the sense amplifier enable signal sae (m + 1&gt; The potential difference ΔV of the bit line / inverted bit line pair (bt [0], bb [0] ~ bt [m], bb [m]) of 1) is amplified by a sense amplifier SA with multiple (m + 1&gt; 1) sense amplifiers. Then, the read data q [0] to [m] are output. If the potential difference ΔV between the bit line / inverted bit line pair is smaller than the offset of the input potential difference of the sense amplifier SA, data reading fails. Selection of word line wl [0] to [n] The potential of the word line rises and the potential difference ΔV between multiple (m + 1&gt; 1) bit lines and inverted bit lines is from the offset of the input potential difference of the sense amplifier SA. The first and second replica word lines rplwl [0] and rplwl [1] rise and the first and second replica bit lines rplbt [0] and rplbt [1]) fall. The timing is adjusted so that the timing at which the sense amplifier enable signal sae rises is approximately simultaneous. The adjustment of the rising timing of the potential of the sense amplifier enable signal sae is performed by the number (p) of the first replica memory cells RPLCELL connected to the first replica bit line rbpbt [0] and the second replica bit. It can be executed by adjusting the number (r) of the second replica memory cells RPLCELL connected to the line rbpbt [1]. The timing at which the potential difference ΔV between the bit line and the inverted bit line in 1) becomes larger than the offset of the input potential difference of the sense amplifier SA, and the first and second replica word lines rplwl [0] and rplwl [1] rise. The timing is adjusted so that the timing at which the first and second replica bit lines rpfbt [0] and rpfbt [1]) fall and the sense amplifier enable signal sae rises is approximately simultaneous. The adjustment of the rising timing of the potential of the sense amplifier enable signal sae is performed by the number (p) of the first replica memory cells RPLCELL connected to the first replica bit line rbpbt [0] and the second replica bit. It can be executed by adjusting the number (r) of the second replica memory cells RPLCELL connected to the line rbpbt [1]. The timing at which the potential difference ΔV between the bit line and the inverted bit line in 1) becomes larger than the offset of the input potential difference of the sense amplifier SA, and the first and second replica word lines rplwl [0] and rplwl [1] rise. The timing is adjusted so that the timing at which the first and second replica bit lines rpfbt [0] and rpfbt [1]) fall and the sense amplifier enable signal sae rises is approximately simultaneous. The adjustment of the rising timing of the potential of the sense amplifier enable signal sae is performed by the number (p) of the first replica memory cells RPLCELL connected to the first replica bit line rbpbt [0] and the second replica bit. It can be executed by adjusting the number (r) of the second replica memory cells RPLCELL connected to the line rbpbt [1].

In the SRAM according to the first embodiment of the present invention shown in FIG. 3, since the replica bit line is divided into a plurality of replica bit lines rlpbt [0] and rrpbt [1], each of the divided replica bits. The delay amount of lines rpfbt [0] and [1] is reduced. By reducing the delay amount of each divided replica bit line rlpbt [0], [1], the delay variation of each divided replica bit line rlpbt [0], [1] is reduced. As a result, the generation timing of the sense amplifier enable signal sae due to the reduced delay fluctuation of each replica bit line rpfbt [0], [1] and the local fluctuation of the logical thresholds of the first and second inverters INV0 and INV1. Fluctuations can be reduced.

FIG. 18 shows the generation timing of the sense amplifier enable signal sae due to the delay variation of the replica bit line of the SRAM and the local variation of the logical threshold value of the inverter according to the first embodiment of the present invention described in FIGS. 3 and 4. It is a figure which shows the state of the fluctuation of the rise timing).

In the example of FIG. 18, the number of SRAM word lines (wl [0] to [n]) is 1024, and specifically, the replica bit line is divided into eight replica bit lines rpfbt. .. Therefore, the load capacitance and the amount of delay of each divided replica bit line rbpbt are significantly reduced. That is, as compared with FIG. 17, in the case of 8 divisions, the delay amount of each replica bit line rpfbt divided into 8 is reduced to about 1/8 as shown on the left of FIG. At that time, as in FIG. 17, even when the replica bit line rbpbt is divided into eight as shown on the left side of FIG. 18, the delay of the replica bit line rlpbt is small and the high-speed amplitude change characteristic rlpbt_ft is obtained, and the delay of the replica bit line rrpbt. May be large and the low-speed amplitude change characteristic rplbt_sl may be obtained. On the other hand, the logical threshold of the inverter INV to which the signal of each replica bit line rbpbt divided into 8 is supplied is the high logical threshold voltage V._LWhen th_high and low logic threshold voltage V_LIt may be th_low. High-speed amplitude change characteristic rlpbt_ft and high logic threshold voltage V_LThe crossover with th_high determines the generation timing of the small delay sae_ft of the sense amplifier enable signal sae, and the crossover of the low-speed amplitude change characteristic rplbt_sl and the low-speed amplitude change characteristic rplbt_sl determines the generation timing of the large delay sae_sl of the sense amplifier enable signal sae. It is determined. However, as shown on the left of Fig. 18, the delay fluctuation of each replica bit line divided into eight and the fluctuation of the logical threshold voltage of the inverter INV cause the fluctuation of the generation timing of the sense amplifier enable signal sae when it is divided into eight. The width Δt_sae is reduced to approximately 1/8 when compared with FIG. Specifically, as shown on the left of Fig. 18, when divided into eight, the fluctuation range of the generation timing of the sense amplifier enable signal sae is Δt_sae = t_sae × 1/8 × 8% t_sae × 1%, which is an extremely small value. It will be reduced.

Specifically, the total generation timing of the SRAM sense amplifier enable signal sae according to the first embodiment of the present invention shown in FIG. 3 by connecting each replica bit line rpfbt divided into eight parts in series with each inverter INV. The fluctuation range ΣΔt_sae is determined. The 8th replica bit line rplbt and the 8th replica bit line rplbt from the fluctuation width Δt_sae of the 1st generation timing due to the 1st series connection between the 1st replica bit line rpfbt and the 1st inverter INV. Up to the fluctuation width Δt_sae of the eighth generation timing by the eighth series connection with the inverter INV, each fluctuation width Δt_sae is substantially normally distributed from the positive fluctuation value to the negative fluctuation value value. That is, the fluctuation width ΣΔt_sae of the total generation timing in the case of 8 divisions is ΣΔt_sae = Δt_sae × 8 t_sae × 3%. The fluctuation range of the total generation timing of the sense amplifier enable signal sae shown on the left of FIG. 18 in SRAM when the replica bit line (RBL) of the first embodiment of the present invention shown in FIG. 3 is divided into eight ΣΔt_sae. It is possible to reduce t_sae × 3% to less than half of t_sae × 8% of the generation timing fluctuation width Δt_sae shown in FIG. 17 in SRAM examined by the present inventors prior to the present invention in FIG. Become.

[Embodiment 2] Embodiment 2 of the present invention relates to the layout of the SRAM inverters INV0 and INV1 and the replica bit line precharge transistors PCH0 and PCH1 shown in FIG. 3 according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of SRAM according to the second embodiment of the present invention.

FIG. 5 shows in detail the internal configuration of the SRAM word driver (WD) according to the first embodiment of the present invention shown in FIG. Word driver (WD) is a plurality of CMOS word drivers ..., (K-1, CMOS_Drv), (K, CMOS_Drv), (K + 1, CMOS_Drv), (K + 2, CMOS_Drv), ... Including, the output terminal of the CMOS word driver (K-1, CMOS_Drv) is connected to the word line wl [K-1], and the output terminal of the CMOS word driver (K, CMOS_Drv) is connected to the word line wl [K]. The output terminal of the CMOS word driver (K + 1, CMOS_Drv) is connected to the word line wl [K + 1], and the output terminal of the CMOS word driver (K + 2, CMOS_Drv) is connected to the word line wl [K + 2]. Has been done. A plurality of SRAM / memory cells (MEMCELL) are connected to a plurality of word lines wl [K-1], wl [K], wl [K + 1], and wl [K + 1]. The first replica bit line (rplbt [0]) to which the first dummy memory cell (DMYCELL) is connected is connected to the input terminal of the first inverter INV0, and the output of this first inverter INV0. The terminal is connected to the second replica word line (rplbt [0]) to which the second precharge transistor PCH1 and the second replica memory cell (RPL CELL) are connected.

FIG. 6 is a diagram showing a planar layout of a device when the SRAM according to the first embodiment of the present invention shown in FIG. 5 is formed on a chip of a semiconductor integrated circuit.

FIG. 6 shows an N-type well region 61 and a P-type well region 62 for CMOS devices.

Four CMOS word drivers in the N-type well area 61 ..., (K-1, CMOS_Drv), (K, CMOS_Drv), (K + 1, CMOS_Drv), (K + 2, CMOS_Drv) ,. Four P-channel MOS transistors are formed. These four P-channel MOS transistors include a gate electrode with a channel length of L and a source / drain impurity region (S, D) with a channel width of Wp, and the second and third are formed inside the N-type well region 61. An N-type well substrate feeding contact region 611 is formed between the P-channel MOS transistors. For example, the power supply voltage V is connected to the N-type well board power supply contact region 611 via the metal wiring._DDHigh level voltage such as is supplied. Two P-channel MOS transistors 612 and 613 are formed to the right of the N-type well board feeding contact area 611, one transistor 612 is used as the second precharge transistor PCH1 and the other transistor is the first inverter. It is used as a P-channel MOS transistor that constitutes INV0. The layout height of the N-type well board feeding contact area 611 is set to be substantially the same as the layout height of the two P-channel MOS transistors 612 and 613. Further, the total layout width of the N-type well substrate feeding contact region 611 and the two P-channel MOS transistors 612 and 613 is set to be substantially equal to the channel width Wp of the P-channel MOS transistor.

Four CMOS word drivers in the P-well area 62 ..., (K-1, CMOS_Drv), (K, CMOS_Drv), (K + 1, CMOS_Drv), (K + 2, CMOS_Drv) ,. Four N-channel MOS transistors are formed. These four N-channel MOS transistors include a gate electrode with a channel length of L and a source / drain impurity region (S, D) with a channel width of Wn, and the second and third are formed inside the P-type well region 62. A P-type well substrate feeding contact region 621 is formed between the N-channel MOS transistors. A low level voltage such as a ground potential GND is supplied to the P-type well board feeding contact region 621 via metal wiring. One N-channel MOS transistor 622 is formed to the left of the P-type well board feeding contact region 621, and this transistor 622 is used as an N-channel MOS transistor constituting the first inverter INV0. The layout height of the P-type well board feeding contact area 621 is set to be substantially the same as the layout height of one N-channel MOS transistor 622. Further, the sum of the layout widths of the P-type well substrate feeding contact region 621 and one N-channel MOS transistor 622 is set to be substantially equal to the channel width Wn of the N-channel MOS transistor.

[Embodiment 3] In the third embodiment of the present invention, the inverters INV0, INV1 and the precharge transistors PCH0 and PCH1 of the replica bit line rlpbt [0] and [1] included in the SRAM of the first embodiment of the present invention are stored in the SRAM memory. It is formed using cell MEMCELL, replica memory cell RPLCELL, and dummy memory cell DMYCELL.

FIG. 7 is a diagram showing a configuration of SRAM according to the third embodiment of the present invention.

The inverters INV0 and INV1 included in the SRAM of the first embodiment of the present invention shown in FIG. 3 are replaced with the inverter cell (INVCELL) 701 of the SRAM of the third embodiment of the present invention shown in FIG. 7, and are shown in FIG. The precharge transistors PCH0 and PCH1 included in the SRAM of the first embodiment of the present invention are replaced with the precharge cell (PCHCELL) 702 of the SRAM of the third embodiment of the present invention shown in FIG. The SRAM of the third embodiment of the present invention shown in FIG. 7 is a dummy memory cell (DMYCELL) 703 and a replica memory cell (RPCELL), similarly to the SRAM of the first embodiment of the present invention shown in FIG. Includes 704 and.

FIG. 8 is a diagram showing the configuration of the SRAM inverter cell (INVCELL) 701 according to the third embodiment of the present invention shown in FIG.

The inverter cell (INVCELL) 701 shown in FIG. 8 is a SRAM memory cell (MEMCELL), a replica memory cell (RPCELL), and a dummy memory cell (DMYCELL) included in the SRAM of the first embodiment of the present invention shown in FIG. Similarly, it contains two P-channel MOS transistors pll80, plr80 and four N-channel MOS transistors npl80, ndl80, ndr80, npr80. In the inverter cell (INVCELL) 701 shown in FIG. 8, the input signal of the replica bit line rbpbt [0] is inverted by the CMOS inverter composed of the P-channel MOS transistor npr80 and the N-channel MOS transistor ndr80, and the replica word The line signal rplwl [1] is generated. The drive capability of the inverter cell (INVCELL) 701 shown in FIG. 8 can also be adjusted by the number of memory cells connected in parallel.

FIG. 9 is a diagram showing a configuration of a SRAM precharge cell (PCHCELL) 702 according to the third embodiment of the present invention shown in FIG.

The precharge cell (PCHCELL) 702 shown in FIG. 9 is a SRAM memory cell (MEMCELL), a replica memory cell (RPLCELL), and a dummy memory cell (dummy memory cell) included in the SRAM of the first embodiment of the present invention shown in FIG. Similar to DMYCELL), it includes two P-channel MOS transistors pll90, plr90 and four N-channel MOS transistors npl90, ndl90, ndr90, npr90. In the precharge cell (PCHCELL) 702 shown in FIG. 9, the replica word line signal rplwl [0] as an input signal is supplied to the gate of the P channel MOS transistor pll90, so that the replica bit line is supplied from the drain of the transistor pll90. The output signal of rplbt [0] is generated. When the replica word line signal rplwl [0] is low level, the P channel MOS transistor pll90 is turned on and the potential of the replica bit line rplbt [0] is the power supply voltage V._DDIt is precharged to the high level of. When the replica word line signal rplwl [0] is at a high level, the P channel MOS transistor pll90 is turned off and the replica bit line rplbt [0] is discharged to the ground potential GND by the replica memory cell (RPLCELL). Will be done. Further, the precharge drive capability of the precharge cell (PCHCELL) 702 shown in FIG. 9 can be adjusted by the number of memory cells connected in parallel.

[Embodiment 4] Embodiment 4 of the present invention is a replica bit line rpfbt by changing the connection state of the transistor node of the dummy memory cell (DMYCELL) 703 included in the SRAM of the third embodiment of the present invention shown in FIG. It adjusts the load capacity of [0] and [1].

FIG. 10 is a diagram showing a configuration of a dummy memory cell (DMYCELL) 703 included in the SRAM according to the fourth embodiment of the present invention.

The dummy memory cell (DMYCELL) 703 shown in FIG. 10 includes two P-channel MOS transistors pll100 and plr100 and four N-channel MOS transistors npl100, ndl100, ndr100 and npr100. In the dummy memory cell (DMYCELL) 703 shown in FIG. 10, in addition to the drain of the N-channel MOS transistor npll100, the drain of the N-channel MOS transistor nprl100 is connected to the replica bit line rbpbt [0] to perform a replica. -It is possible to increase the load capacitance of the bit line rpfbt [0].

FIG. 11 is also a diagram showing a configuration of a dummy memory cell (DMYCELL) 703 included in the SRAM according to the fourth embodiment of the present invention.

The dummy memory cell (DMYCELL) 703 shown in FIG. 11 includes two P-channel MOS transistors pll110 and plr110 and four N-channel MOS transistors npl110, ndl110, ndr110 and npr110. In the dummy memory cell (DMYCELL) 703 shown in FIG. 11, the replica bit is connected to the replica bit line rpfbt [0] in common by the drain and source of the N-channel MOS transistor npl110 by the cell internal wiring L703. It is possible to increase the load capacitance of the line rpfbt [0].

FIG. 12 is also a diagram showing a configuration of a dummy memory cell (DMYCELL) 703 included in the SRAM according to the fourth embodiment of the present invention.

The dummy memory cell (DMYCELL) 703 shown in FIG. 12 includes two P-channel MOS transistors pll120 and plr120 and four N-channel MOS transistors npl120, ndl120, ndr120 and npr120. In the dummy memory cell (DMYCELL) 703 shown in FIG. 12, the gate capacitances of the two N-channel MOS transistors npl120 and npr120 are connected to the replica bit line rpfbt [0] to connect the replica bit line rpfbt [0]. ], The load capacity can be increased.

FIG. 13 is also a diagram showing a configuration of a dummy memory cell (DMYCELL) 703 included in the SRAM according to the fourth embodiment of the present invention.

The dummy memory cell (DMYCELL) 703 shown in FIG. 13 includes two P-channel MOS transistors pll150 and plr150 and four N-channel MOS transistors npl150, ndl150, ndr150 and npr150. In the dummy memory cell (DMYCELL) 703 shown in FIG. 13, the gate capacitance of the P-channel MOS transistor pll150 and the gate capacitance of the N-channel MOS transistor ndl150 and the source / drain of the P-channel MOS transistor plr150 are connected to the replica bit line rpfbt [0]. By connecting with the capacitance, it is possible to increase the load capacitance of the replica bit line rbpbt [0].

The configurations of the dummy memory cells (DMYCELL) 703 of FIGS. 10 to 13 described above can be used in combination with each other depending on the situation.

[Embodiment 5] In the fifth embodiment of the present invention, the influence of the leakage current of the dummy memory cell is reflected in the pull-out delay of the replica bit line.

FIG. 14 is a diagram showing a configuration of a part of dummy memory cells (DMYCELL) 703 included in the SRAM according to the fifth embodiment of the present invention.

Inside all of the plurality of dummy memory cells (DMYCELL) included in the SRAM according to the first embodiment of the present invention shown in FIG. 3, a CMOS inverter composed of a P-channel MOS transistor P11 and an N-channel MOS transistor N11. High level power supply voltage V at the input terminal_DDIs supplied, and the output terminal of this CMOS inverter is maintained at the ground potential GND. Since the N-channel MOS transistor N12 as all transfer transistors of multiple dummy memory cells (DMYCELL) is turned off by the ground potential GND, the replica bit lines rpfbt [0] and rpfbt [1] have multiple precharge charges. It is discharged to the ground potential GND via a plurality of transfer transistors N12 inside all of the dummy memory cells (DMYCELL) of.

On the other hand, inside a part of the dummy memory cell (DMYCELL) 703 included in the SRAM according to the fifth embodiment of the present invention shown in FIG. 14, the other P-channel MOS transistor plr140 and the other N-channel MOS transistor ndr140. High-level power supply voltage V at the input terminal of the other CMOS inverter configured by_DDIs supplied, and the output terminal of the other CMOS inverter is maintained at the ground potential GND. Therefore, a ground potential GND is supplied to the input terminal of one CMOS inverter composed of one P-channel MOS transistor pll140 and one N-channel MOS transistor ndl140, and the output terminal of this CMOS inverter has a high level power supply voltage V._DDIs maintained at. As a result, inside some of the dummy memory cells (DMYCELL) 703 shown in FIG. 14, the replica bit lines rbpbt [0] and rpfbt [1] are generated by the leakage current of the transfer N-channel MOS transistor N12 in the off state. High level power supply voltage V_DDCharged towards. Therefore, the discharge of replica bit lines rbpbt [0], rpfbt [1] by other dummy memory cells (DMYCELL) and the replica bit lines rlpbt [0], rlpbt of some dummy memory cells (DMYCELL) 703. Depending on the difference in charging capacity of [1], it is possible to adjust the pull-out delay amount of the replica bit lines rbpbt [0] and rlpbt [1].

[Embodiment 6] Embodiment 6 of the present invention relates to a system on-chip (SoC) system LSI including SRAM of Embodiments 1 to 5 of the present invention shown in FIGS. 3 to 14 as internal memory.

FIG. 15 is a diagram showing a configuration of a system LSI according to the sixth embodiment of the present invention.

The semiconductor chip 150 of the system on-chip (SoC) system LSI shown in FIG. 15 has a central processing network (CPU) 151, 152, 153 and a two-dimensional image signal processing engine 154, 3 as an intellectual property right (IP) core. It includes a dimensional image signal processing engine 155, a moving image processing engine 156, an audio signal processing unit 157, a liquid crystal display controller 158, and an interface controller 159.

Each of the IP cores 151 to 159 integrated in the semiconductor chip 150 shown in FIG. 15 includes a built-in SRAM inside the IP cores 151 to 159. Each IP core 151 to 159 has various internal SRAM storage capacities depending on its function and performance. At that time, the SRAM of the first to fifth embodiments of the present invention shown in FIGS. 3 to 14 described above can be adopted as the built-in SRAM having an extremely large storage capacity. Further, the semiconductor chip 150 shown in FIG. 15 can include a large-capacity shared built-in SRAM shared and used by a plurality of IP cores 151 to 159. A compiled RAM (CRAM) design method can be used to design these large-capacity built-in SRAMs and built-in SRAMs with various storage capacities.

FIG. 16 is a diagram illustrating a method for designing a compiled RAM (CRAM) used for designing a built-in SRAM built in a semiconductor chip 150 of a system LSI according to a sixth embodiment of the present invention.

The memory compiler 160 is a design tool on a computer such as an engineering workstation, and the electronic data 161 of the basic memory device structure of the built-in SRAM and the input data 162 for the built-in SRAM of various storage capacities are the memory compiler 160. Is supplied to. The input data 162 includes placement component data, circuit component data, library data, and placement connection data of various built-in SRAMs.

The memory compiler 160 generates the output data 163 of the automatically designed built-in SRAM from the electronic data 161 of the supplied memory device structure and the input data 162 for the built-in SRAM. The output data 163 includes layout data, circuit data, memory library data, and netlist data.

In particular, the memory compiler 160 of the compiled RAM design method of the sixth embodiment of the present invention shown in FIG. 16 determines the appropriate sense amplifier enable signal generation timing for each of the automatically designed built-in SRAMs with various storage capacities. It is configured to output.

That is, in the output data 163 automatically generated from the memory compiler 160, the number of divisions of the replica bit line, the number of replica memory cells connected to each divided replica bit line, the number of dummy memory cells, etc. It contains moderation information regarding the generation timing of the sense amplifier enable signal of.

The invention made by the present inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

For example, the built-in memory built into the semiconductor integrated circuit device according to the embodiment of the present invention is not limited to SRAM, but is not limited to SRAM, but is DRAM (Dynamic Random Access Memory) or EEPROM (Electrically Erasable / Writable Read Only). It can be applied to non-volatile memory such as memory) or batch erase type flash memory.

Further, the present invention can be applied to a semiconductor memory integrated circuit device having a dedicated function only for a semiconductor memory of a non-volatile memory such as DRAM, EEPROM, and flash memory, in addition to a system LSI called a system on chip (SoC). It is possible.

<figref num="1">FIG. 1 is a diagram showing a configuration of an SRAM using a replica bit line, which was examined by the present inventors based on the technique described in Non-Patent Document 1 prior to the present invention.</figref><figref num="2">FIG. 2 is a waveform diagram of each part of the SRAM shown in FIG. 1 for explaining the operation of the SRAM shown in FIG. ()</figref><figref num="3">FIG. 3 is a diagram showing a configuration of an SRAM using a replica bit line according to the first embodiment of the present invention.</figref><figref num="4">FIG. 4 is a waveform diagram of each part of the SRAM shown in FIG. 3 for explaining the operation of the SRAM according to the first embodiment of the present invention shown in FIG.</figref><figref num="5">FIG. 5 is a diagram showing a configuration of SRAM according to the second embodiment of the present invention.</figref><figref num="6">FIG. 6 is a diagram showing a planar layout of a device when the SRAM according to the second embodiment of the present invention shown in FIG. 5 is formed on a chip of a semiconductor integrated circuit.</figref><figref num="7">FIG. 7 is a diagram showing a configuration of SRAM according to the third embodiment of the present invention.</figref><figref num="8">FIG. 8 is a diagram showing the configuration of the SRAM inverter cell according to the third embodiment of the present invention shown in FIG.</figref><figref num="9">FIG. 9 is a diagram showing a configuration of a SRAM precharge cell according to the third embodiment of the present invention shown in FIG.</figref><figref num="10">FIG. 10 is a diagram showing a configuration of a dummy memory cell included in the SRAM according to the fourth embodiment of the present invention.</figref><figref num="11">FIG. 11 is also a diagram showing a configuration of a dummy memory cell included in the SRAM according to the fourth embodiment of the present invention.</figref><figref num="12">FIG. 12 is also a diagram showing a configuration of a part of dummy memory cells included in the SRAM according to the fourth embodiment of the present invention.</figref><figref num="13">FIG. 13 is a plan view of a silicon chip showing the layout of various devices constituting the semiconductor integrated circuit according to one embodiment of the present invention shown in FIG.</figref><figref num="14">FIG. 14 is a diagram showing a configuration of a dummy memory cell included in the SRAM according to the fifth embodiment of the present invention.</figref><figref num="15">FIG. 15 is a diagram showing a configuration of a system LSI according to the sixth embodiment of the present invention.</figref><figref num="16">FIG. 16 is a diagram illustrating a method for designing a compiled RAM used for designing the built-in SRAM built in the semiconductor chip 150 of the system LSI according to the sixth embodiment of the present invention.</figref><figref num="17">FIG. 17 shows the delay variation of the replica bit line of the SRAM using the replica bit line and the local logical threshold value of the inverter, which were examined by the present inventors prior to the present invention described in FIGS. 1 and 2. It is a figure which shows the state of the fluctuation of the generation timing of a sense amplifier enable signal due to the fluctuation.</figref><figref num="18">FIG. 18 shows the variation in the generation timing of the sense amplifier enable signal due to the delay variation of the replica bit line of the SRAM and the local variation of the logical threshold value of the inverter according to the first embodiment of the present invention described in FIGS. 3 and 4. It is a figure which shows the state of.</figref>

WD word driver CNTL decode control circuit wl [0] ~ wl [n] word line bt [0], bb [0] ~ bt [m], bb [m] Bit line rplwl [0], rplwl [1] replica wordline rplbt [0], rplbt [1] replica bit lines MEMCELL SRAM / Memory Cell RPLCELL replica memory cell DMYCELL dummy memory cell PCH0, PCH1 precharge transistor INV0, INV1 inverter BUF buffer SA sense amplifier CLK clock a [0] ~ a [h] address signal dec [0] ~ dec [j] decoder signal sae sense amplifier enable signal q [0] ~ q [m] Read data