Ferroelectric memory

The present invention relates to a ferroelectric memory and is used, for example, for a refresh operation in a ferroelectric memory.

The ferroelectric memory is a semiconductor memory in which a ferroelectric capacitor is a component of a memory cell. A memory cell in a ferroelectric memory generally consists of a ferroelectric capacitor and a cell transistor.

The ferroelectric memory is usually provided with wiring such as a word wire, a bit wire, and a plate wire. In a ferroelectric memory, when the word line and the plate line do not have a one-to-one correspondence, the accumulation of electric charge in the node between the ferroelectric capacitor and the cell transistor becomes a problem. The accumulated charge and its leak cause a decrease in the reliability of the ferroelectric memory.

In a conventional ferroelectric memory, as a countermeasure to this problem, a refresh operation in which a word line is turned on and an electric charge is discharged is periodically performed. However, when performing the refresh operation, the plate wire and the bit wire need to have the same potential. Therefore, in the past, the refresh operation could not be performed in a situation where access for reading / writing is frequently performed.

In addition, Patent Document 1 describes a data read operation of reading binary data from a selected cell, an inverse data writing operation of writing data having a logic level opposite to that of the read binary data to the selected cell, and the read. An example of a ferroelectric memory in which the same data writing operation of writing data of the same logic level as the binary data to the selected cell again as a series of refreshing operations is described.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-11665</text></patcit>

<p> An object of the present invention is to improve the efficiency of refresh operation in a ferroelectric memory.</p>

<p> One aspect of the present invention is, for example, having a plurality of memory cells, arranging a plurality of word lines, a plurality of bit lines, and a plurality of plate lines, and each plate line has two or more word lines. The corresponding memory cell array, the access control circuit that performs the access operation to the selected cell selected from the memory cells, and the refresh operation of the refresh cell selected from the memory cells are performed in the access operation. A refresh control circuit performed in the background is provided, and in the refresh control circuit, the plate wire connected to the selected cell and the bit wire connected to the selected cell have the same potential after the access operation. It is a ferroelectric memory characterized in that the refresh operation is sometimes performed.</p>

<p> According to the present invention, it is possible to improve the efficiency of the refresh operation in the ferroelectric memory.</p>

Embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic diagram showing a circuit configuration of the ferroelectric memory 101 of the first embodiment. The ferroelectric memory 101 of FIG. 1 includes a memory cell array 111, a sense amplifier 112, and a drive circuit 113. The drive circuit 113 is an example of the access control circuit and the refresh control circuit of the present invention.

The memory cell array 111 has a plurality of memory cells 121. FIG. 1 shows the first memory cell 121 as an example of the memory cell 121.₁And the second memory cell 121₂Is shown. As shown in FIG. 1, each memory cell 121 has one ferroelectric capacitor 131 and one cell transistor 132.

Further, a plurality of word lines, a plurality of bit lines, and a plurality of plate lines are arranged in the memory cell array 111. In Figure 1, the first and second word lines WL are examples of such word lines, bit lines, and plate lines.₁And WL₂And the first and second bit lines BL₁And BL₂And the plate wire PL are shown.

In Figure 1, WL₁, WL₂Are the first memory cells 121, respectively₁, Second memory cell 121₂It is connected to the. Also, BL₁, BL₂Also each of the first memory cells 121₁, Second memory cell 121₂It is connected to the. On the other hand, PL is the first memory cell 121.₁And second memory cell 121₂Connected to both, WL₁And WL₂Corresponds to both. As described above, in the present embodiment, each plate line does not have a one-to-one correspondence with the word line, but corresponds to two or more word lines.

In each memory cell 121 of FIG. 1, the ferroelectric capacitor 131 and the cell transistor 132 are connected in series. One electrode of the ferroelectric capacitor 131 is connected to the plate wire and the other electrode is connected to the cell transistor 132. Further, one of the source and drain of the cell transistor 132 is connected to the ferroelectric capacitor 131, and the other is connected to the bit wire. Further, the gate of the cell transistor 132 is connected to the word line.

In FIG. 1, the word line and the plate line extend in the first direction, and the bit line extends in the second direction. The first direction is the vertical direction of the paper here, and the second direction is the horizontal direction of the paper here. Each memory cell 121 in FIG. 1 is provided near the intersection of one word line and one bit line.

As described above, the ferroelectric memory 101 of FIG. 1 is further provided with a sense amplifier 112 and a drive circuit 113. The sense amplifier 112 is a circuit that reads out the stored data of the selected cell by detecting and amplifying the potential change of the bit line. The drive circuit 113 is a circuit that performs an access operation to the selected cell and a refresh operation of the refresh cell.

During the access operation, a cell to be accessed is selected from the memory cells 121, and the access operation to the cell (selected cell) is performed. Then, at the time of reading, the stored data is read from the cell. When reading data from a selected cell, the sense amplifier 112 detects the potential change of the bit line connected to the selected cell. On the other hand, during the refresh operation, a cell to be refreshed is selected from the memory cells 121, and the cell (refresh cell) is refreshed.

FIG. 2 is a timing chart for explaining the access operation and the refresh operation of the ferroelectric memory 101 of FIG. Figure 2 shows the first memory cell 121 to be accessed.₁It is a waveform diagram in the case of.

The ferroelectric memory 101 is a first memory cell 121.₁When reading stored data from, WL₁Set both the potential of and the potential of PL to H (high) (S1, S2). As a result, BL₁The potential of is increased (S3).

At this time, the first memory cell 121₁If the stored data of is "0", BL₁The potential of is slightly increased (S3A). On the other hand, the first memory cell 121₁If the stored data of is "1", BL₁The potential of is greatly increased (S3B). Sense amplifier 112 is BL₁By detecting and amplifying the potential of the first memory cell 121₁Read the stored data of.

Next, the ferroelectric memory 101 is the first memory cell 121.₁Rewrite to (S4). The ferroelectric memory 101 is BL when the rewrite data is "0".₁Potential of grounding potential V_SSDrop it in (S4A). On the other hand, the ferroelectric memory 101 is BL when the rewrite data is "1".₁Further raise the potential of (S4B).

In this way, the ferroelectric memory 101 is the first memory cell 121 by the processing of S1 to S4.₁Perform an access operation to. In FIG. 2, the access operation is a data read operation (including a rewrite operation). Then, when the rewrite data is "1", the ferroelectric memory 101 is BL after the end of the access operation.₁Potential of grounding potential V_SSDrop it in (S5).

The potential of PL is the ground potential V at the stage of S4._SSDropped in. Therefore, in the ferroelectric memory 101, PL and BL at the time of S5.₁And have the same potential.

The ferroelectric memory 101 performs the processing of S1'to S5'in the same manner as the processing of S1 to S5 at the next access operation. In Figure 2, the period from S5 to S1'is indicated by T. PL and BL during period T₁Have the same potential.

In the present embodiment, the refresh operation is performed during this period T. Figure 2 shows the second memory cell 121 to be refreshed.₂It is a waveform diagram in the case of. Ferroelectric memory 101 is WL in period T₂The potential of is set to H (high) (S6). As a result, the second memory cell 121₂Then, the charge accumulated in the node between the capacitor 131 and the transistor 132 is released. In FIG. 1, the node is indicated by A.

As described above, in the present embodiment, the refresh operation is performed when the plate wire and the bit wire connected to the selected cell have the same potential after the access operation. That is, the refresh operation is performed during the period T shown in FIG.

Thereby, in the present embodiment, the refresh operation can be performed in the background of the access operation without interrupting the access operation. This is because the refresh operation is performed during the period T, which is the free time of the access operation.

Therefore, in the present embodiment, the refresh operation is performed during the period T, so that the refresh operation is performed in the background of the access operation. As a result, in the present embodiment, the refresh operation can be performed without adversely affecting the performance of the access operation.

Further, in the present embodiment, since the refresh operation is performed during the period T which is the free time of the access operation, the refresh operation can be performed even in a situation where reading and writing are frequently performed.

Further, in the present embodiment, the refresh operation is performed during the period between one access operation and the next access operation. Therefore, in the present embodiment, it is possible to perform one refresh operation for each access operation. Therefore, in the present embodiment, it is possible to increase the number of refreshes as the number of accesses increases. In general, charge accumulation occurs at each access operation, so the more frequently the access operation, the more frequently the refresh operation needs to be performed. Therefore, in the present embodiment, in order to deal with such a situation, an efficient refresh operation can be realized by increasing the number of refreshes according to the increase in the number of accesses.

In FIG. 2, the selected cell is the first memory cell 121.₁The refresh cell is the second memory cell 121.₂It has become. Therefore, in FIG. 2, the refresh cell is a non-selected cell connected to the same plate line as the selected cell.

In the present embodiment, the refresh cell can be randomly selected from, for example, the memory cell 121. However, in this case, the refresh cell may be a selected cell or a non-selected cell connected to a plate line different from the selected cell. However, since the refresh operation of this embodiment can be applied to these cells, no problem occurs.

However, when the refresh cell is a non-selected cell connected to a plate line different from the selected cell, the executable period of the refresh operation can be set wider than the period T. Such a setting will be described in the embodiment described later.

In Fig. 2, the refresh operation is BL.₁The potential of is the ground potential V_SSIt is done immediately after being dropped in, but it may be done at other times.

As described above, in the present embodiment, the refresh operation is performed when the plate wire and the bit wire connected to the selected cell have the same potential after the access operation, and the row is performed in the background of the access operation. It is said. Thereby, in the present embodiment, the refresh operation can be made more efficient.

(Comparison example) FIG. 3 is a timing chart for explaining the access operation and the refresh operation of the ferroelectric memory of the comparative example. In the ferroelectric memory, a refresh operation in which a word line is turned on and an electric charge is discharged is periodically performed. When performing the refresh operation, the plate wire and the bit wire need to have the same potential. In FIG. 3, when the potential of the plate wire PL is L (low), the plate wire PL and the bit wire are set to the same potential. Then, the refresh operation of turning on the word line and discharging the electric charge is performed under this setting.

In this case, it is difficult to perform the refresh operation in a situation where access for reading / writing occurs frequently. FIG. 3 shows the potential of node A in FIG. 1 and the refresh time T._RIt is shown. If the number of refreshes is small, as shown in FIG. 3, the potential of node A becomes unstable due to charge accumulation.

On the other hand, according to the first embodiment, the refresh operation can be performed even in a situation where reading and writing are frequently performed. Therefore, the problem shown in FIG. 3 is solved.

Hereinafter, the ferroelectric memory 101 of the second to fifth embodiments will be described. The second to fifth embodiments are modifications of the first embodiment, and the second to fifth embodiments will be described focusing on the differences from the first embodiment.

(Second Embodiment) FIG. 4 is a schematic diagram showing the circuit configuration of the ferroelectric memory 101 of the second embodiment. FIG. 4 shows the first and second memory cells 121.₁And 121₂In addition to the third memory cell 121₃It is shown. Third memory cell 121₃Is the third word line WL₃And the first and second bit lines BL₁And BL₂3rd bit line different from BL₃Is connected to. Third memory cell 121₃Is further connected to a plate wire PL'different from the plate wire PL.

FIG. 5 is a timing chart for explaining the access operation and the refresh operation of the ferroelectric memory 101 of FIG. FIG. 5 shows the first memory cell 121 to be accessed.₁It is a waveform diagram in the case of.

In the present embodiment, when the refresh cell (refresh target cell) is a memory cell 121 connected to the same plate line as the selected cell (access target cell), the refresh operation of FIG. 2 is performed. Figure 2 shows the second memory cell 121 to be refreshed.₂It is a waveform diagram in the case of.

On the other hand, in the present embodiment, when the refresh cell (refresh target cell) is a memory cell 121 connected to a plate line different from the selected cell (access target cell), the refresh operation shown in FIG. 5 can be performed. Is. In Figure 5, the refresh target is the third memory cell 121.₃It is a waveform diagram in the case of.

In FIG. 2, as described above, the refresh operation of the cell to be refreshed is performed when the plate line and the bit line connected to the cell to be accessed have the same potential after the access operation to the cell to be accessed. It is (S6). That is, the refresh operation is performed during the period T shown in FIG.

On the other hand, in FIG. 5, the refresh operation of the cell to be refreshed is performed when the plate wire and the bit wire connected to the cell to be accessed have the same potential or not at the same potential (S6). That is, in FIG. 5, the refresh operation may be performed after the plate wire and the bit wire have the same potential, or may be performed before the potential becomes the same. This is because the cell to be refreshed is connected to a plate wire different from the cell to be accessed. Further, in FIG. 5, the refresh operation may be performed at the same time when the word line connected to the access target cell is turned on to realize a complete background operation.

In FIGS. 2 and 5, the refresh operation of the cell to be refreshed is performed when the plate wire and the bit wire connected to the cell to be refreshed have the same potential. Further, the refresh operation of FIG. 5 is connected to a plate wire different from the plate wire PL, and the bit wire BL₁And BL₂Applies to memory cells 121 connected to different bit lines.

As described above, in the present embodiment, when the refresh cell is connected to a plate wire different from the selected cell, the refresh operation can be performed not only after the access operation but also during the access operation. The present embodiment has an advantage that the degree of freedom in setting the execution timing of the refresh operation is high.

On the other hand, the refresh operation may be performed during the period T regardless of which plate wire the refresh cell is connected to. Such processing has an advantage that the execution timing of the refresh operation can be unified regardless of which plate wire the refresh cell is connected to.

(Third Embodiment) FIG. 6 is a schematic diagram showing the circuit configuration of the ferroelectric memory 101 of the third embodiment. The ferroelectric memory 101 of the present embodiment includes the circuit shown in FIG. 6 in addition to the circuit shown in FIG.

As shown in FIG. 6, the ferroelectric memory 101 of the present embodiment includes a counter 201, a selector 202, and a decoder 203. The counter 201 is an example of the address generation circuit of the present invention. The counter 201, the selector 202, and the decoder 203 are provided in the drive circuit 113 of FIG.

In the present embodiment, the address of the refresh cell is generated independently of the address of the selected cell. The reason is to refresh all memory cells 121 without bias. Further, it is desirable that the refresh operation is performed on all the memory cells 121 when a predetermined time has elapsed.

The circuit of FIG. 6 is an example of a circuit for performing such a refresh operation.

In FIG. 6, the refresh cell address is generated by counter 201. The counter 201 is connected to all the plate wires in the memory cell array 111, and generates the address of the refresh cell by counting the number of potential fluctuations of these plate wires. As a result, in the present embodiment, the address of the refresh cell changes for each access operation.

Further, the counter 201 is an m-ary counter when the number of word lines in the memory cell array 111 is m (m is an integer of 2 or more). As a result, in the present embodiment, all m word lines can be refreshed by m access operations, and each memory cell 121 can be easily refreshed without bias.

As shown in FIG. 6, the selector 202 has an address signal ADD and a refresh address signal ADD._RIs entered. The address signal ADD is a signal indicating the address of the selected cell, and is used during the access operation. Refresh address signal ADD_RIs a signal indicating the address of the refresh cell, and is used during the refresh operation. Refresh address signal ADD_RIs generated and output by the counter 201.

Further, a select signal SEL that specifies an address signal to be selected is input to the selector 202. When the selector 202 receives the select signal to select the ADD, the selector 202 selects and outputs the ADD, and the ADD_RWhen a select signal to select is received, ADD_RIs selected and output. In the present embodiment, by providing the selector 202, the decoder 203 can be used for both the access operation and the refresh operation.

The address signal selected by the selector 202 is input to the decoder 203. When the ADD is input, the decoder 203 turns on the word line indicated by the ADD. As a result, the memory cell 121 connected to the word line becomes the access target. On the other hand, the decoder 203 is ADD._RIs entered, ADD_RTurn on the word line indicated by. As a result, the memory cell 121 connected to the word line becomes the refresh target.

As described above, in the present embodiment, the address of the refresh cell is generated independently of the address of the selected cell. As a result, the refresh operation can be performed evenly for each memory cell 121. Further, in the present embodiment, the refresh cell address is generated by the counter 201. This makes it possible to realize a refresh operation with less bias with a relatively simple circuit configuration.

(Fourth Embodiment) FIG. 7 is a timing chart for explaining the access operation and the refresh operation of the ferroelectric memory 101 of the fourth embodiment. The ferroelectric memory 101 of the present embodiment has the circuit configurations shown in FIGS. 1 and 6.

FIG. 7A shows the potential change of the plate line PL. This is the same as the potential change of the plate line PL in FIG. FIG. 7B represents the address signal ADD. Here, the selected cell is the word line WL₁First memory cell 121 connected to₁Suppose that

The signal SEN shown in FIG. 7C represents the drive signal of the sense amplifier 112. The sense amplifier 112 becomes active when the drive signal SEN is H (high), and performs detection and amplification. On the other hand, the sense amplifier 112 becomes inactive when the drive signal SEN is L (low), and stops detection and amplification.

In the ferroelectric memory 101, when the drive signal SEN becomes L, the sense amplifier 112 becomes inactive. Then, in the ferroelectric memory 101, when the sense amplifier 112 becomes inactive, the potential of the bit line connected to the selected cell becomes the ground potential V as shown in S5 of FIG._SSDropped in.

Therefore, in the present embodiment, when the drive signal SEN becomes L, the select signal SEL is set to H and the address signal is changed from ADD to ADD._RSwitch to (Fig. 7D). In the present embodiment, such control enables the refresh operation to be performed during the period T shown in FIG. Here, the refresh cell is the word line WL₂Second memory cell 121 connected to₂Suppose that Figure 7E shows the word line WL as the select signal SEL changes to H.₂Is shown to be turned on.

As described above, in the present embodiment, the refresh operation is performed when the sense amplifier 112 is inactive. In the present embodiment, such control enables the refresh operation to be performed during the period T.

(Fifth Embodiment) FIG. 8 is a timing chart for explaining the access operation and the refresh operation of the ferroelectric memory 101 of the fifth embodiment. The ferroelectric memory 101 of the present embodiment has the circuit configurations shown in FIGS. 1 and 6.

The access operation in FIG. 2 is a plate wire drive type, whereas the access operation in FIG. 8 is a bit line drive type.

The ferroelectric memory 101 of the present embodiment is the first memory cell 121.₁When reading stored data from, BL₁Raise the potential of (S11), then WL₁The potential of is set to H (S12). As a result, BL₁The potential of is lowered (S13).

At this time, the first memory cell 121₁If the stored data of is "0", BL₁The potential of is greatly reduced (S13A). On the other hand, the first memory cell 121₁If the stored data of is "1", BL₁The potential of is slightly lowered (S13B). Sense amplifier 112 is BL₁By detecting and amplifying the potential of the first memory cell 121₁Read the stored data of.

Next, the ferroelectric memory 101 is the first memory cell 121.₁Rewrite to (S14). The ferroelectric memory 101 is BL when the rewrite data is "0".₁Potential of grounding potential V_SSDrop it in (S14A). On the other hand, the ferroelectric memory 101 is BL when the rewrite data is "1".₁Raise the potential of (S14B) again. At the time of the rewriting, the potential of PL is set to H (S15).

As described above, the ferroelectric memory 101 is the first memory cell 121 by the processing of S11 to S15.₁Perform an access operation to. In FIG. 8, the access operation is a data read operation (including a rewrite operation). Then, when the rewrite data is "1", the ferroelectric memory 101 is BL after the end of the access operation.₁Potential of grounding potential V_SSDrop it in (S16). Also, the potential of PL is also the ground potential V._SSDropped in. Therefore, in the ferroelectric memory 101, PL and BL at the time of S16.₁And have the same potential.

The ferroelectric memory 101 performs the processing of S11'to S16' in the same manner as the processing of S11 to S16 at the next access operation. In FIG. 8, the period from S16 to S11'is indicated by T. PL and BL during period T₁Have the same potential.

In the present embodiment, as in the first embodiment, the refresh operation is performed during this period T. Ferroelectric memory 101 is WL in period T₂The potential of is set to H (S17). As a result, the second memory cell 121₂Then, the charge accumulated in the node between the capacitor 131 and the transistor 132 is released. In FIG. 1, the node is indicated by A.

As described above, according to the present embodiment, the same refresh operation as that of the first embodiment can be executed in the bit-wire driven type ferroelectric memory 101.

Although examples of specific embodiments of the present invention have been described above with reference to the first to fifth embodiments, the present invention is not limited to these embodiments.

<figref num="1">It is a schematic diagram which shows the circuit structure of the ferroelectric memory of 1st Embodiment.</figref><figref num="2">It is a timing chart for demonstrating the access operation and refresh operation of the ferroelectric memory of 1st Embodiment.</figref><figref num="3">It is a timing chart for demonstrating the access operation and refresh operation of the ferroelectric memory of the comparative example.</figref><figref num="4">It is a schematic diagram which shows the circuit structure of the ferroelectric memory of 2nd Embodiment.</figref><figref num="5">It is a timing chart for demonstrating the access operation and refresh operation of the ferroelectric memory of the 2nd Embodiment.</figref><figref num="6">It is a schematic diagram which shows the circuit structure of the ferroelectric memory of 3rd Embodiment.</figref><figref num="7">It is a timing chart for demonstrating the access operation and refresh operation of the ferroelectric memory of 4th Embodiment.</figref><figref num="8">It is a timing chart for demonstrating access operation and refresh operation of the ferroelectric memory of 5th Embodiment.</figref>

Code description

101 Ferroelectric memory 111 Memory cell array 112 sense amplifier 113 drive circuit 121 memory cells 131 Ferroelectric Capacitor 132 cell transistor 201 counter 202 Selector 203 decoder