Memory device

The present invention relates to a memory device including an error detection and correction circuit.

In a large-capacity memory such as resistance change RAM (ReRAM), the stored contents are corrupted due to various causes such as during data retention. In particular, the physical mechanism used as the data holding state is susceptible to disturbance, and the error rate will increase as the memory capacity increases and the manufacturing process becomes finer in the future. Therefore, it is an important technique to mount an error detection and correction circuit on-chip in the memory.

Galois finite field GF (2)ⁿ) Is used, and when performing error correction of 2 bits or more in an ECC system using BCH code (BCH-ECC system), a method of sequentially substituting finite field elements to find the solution of the error position search equation is used. If it is used, the calculation time becomes enormous, and even when it is on-chip, the read / write performance of the memory is significantly reduced. Therefore, an ECC circuit that does not sacrifice memory performance is desired regardless of such sequential search.

In particular, ReRAM is suitable for miniaturization, and at the same time, it can form a crosspoint cell and is easy to stack. Therefore, a large-capacity file memory is expected to be used as a successor candidate for a NAND flash memory. However, the resistance-changing substance used as the memory cell of ReRAM does not show stable resistance change unless a strong voltage is applied once, so it is necessary to devise to realize high-speed data transfer while maintaining reliability.

A technique for mounting an ECC circuit in a memory chip or in a memory controller that controls the memory chip is shown in, for example, Patent Document 1.

In a memory equipped with an ECC circuit, a technique for refreshing a data bit and an ECC inspection bit in order to improve data reliability is shown in, for example, Patent Document 2.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-173289</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2006-527447</text></patcit>

<p> An object of the present invention is to provide a memory device that realizes high-speed data transfer while ensuring data reliability by incorporating an error detection and correction circuit.</p>

<p> The memory device according to one aspect of the present invention is Memory cell array and An error detection and correction circuit that detects and corrects errors in the read data of the memory cell array, and The number of data bits provided for temporarily storing the read data and the write data of the memory cell array is set to an integral multiple of the number of data bits including the check bit at the time of error detection and correction processing by the error detection and correction circuit. Equipped with a buffer register The write data stored in the buffer register from the outside is encoded through the error detection and correction circuit, overwritten with the check bit in the buffer register, and then transferred and written to the memory cell array. The data read from the memory cell array is stored in the buffer register together with the check bit, then decoded through the error detection and correction circuit, overwritten in the buffer register as correct read data, and then output to the outside. It is characterized by that.</p><p> A memory device according to another aspect of the present invention Memory cell array and An error detection and correction circuit that detects and corrects errors in the read data of the memory cell array, and The number of data bits provided for temporarily storing the read data and the write data of the memory cell array is set to an integral multiple of the number of data bits including the check bit during the error detection and correction processing by the error detection and correction circuit. Equipped with two buffer registers Burst transfer of read or write data to and from the outside by one of the two buffer registers and read or write via the error detection and correction circuit between the memory cell array by the other of the two buffer registers. Internal data transfer is alternated It is characterized by that.</p>

<p> According to the present invention, it is possible to provide a memory device that realizes high-speed data transfer while ensuring data reliability by incorporating an error detection and correction circuit.</p>

In the following embodiment, a configuration of a memory system capable of high-speed data transfer while ensuring reliability even if a resistance changing substance of a memory cell causes a data storage error is shown, and the timing and sequence of high-speed data transfer are shown. It is specified and shown that a large-capacity high-speed file memory can be realized.

The technical elements of the embodiments can be summarized as follows.

-The memory system is equipped with a buffer register that reads and writes data in synchronization with the clock and an ECC circuit that detects and corrects data errors. The number of data bits in the buffer register is the parallel read data from the memory cell array by the ECC circuit. Is set to an integral multiple of the number of data bits including the check bit when performing error detection and correction processing.

-When reading data, the data read from the cell array is decoded through the ECC circuit, held in the buffer register as error-corrected data, and burst-transferred and output.

-When writing data, burst transfer the data written from the outside to the buffer register and hold it, then encode the data through the ECC circuit, overwrite the buffer register as error-correctable code data, and write this to the cell array. Transfer write.

-The buffer register alternately repeats "internal data transfer", which is data transfer with the memory cell array via the ECC circuit, and "external data transfer", which is transfer of read / write data to and from the external terminal, and reads out. Regardless of writing, before the external data transfer, the operation of holding the data in the buffer register in advance by the internal data transfer is performed.

-Equipped with two buffer registers, it performs an interleave operation of burst transfer, which is an external data transfer, and while one is performing external data transfer by burst transfer, the other is in the internal data transfer state. ..

-It has an ECC refresh mode in which the memory cell array data is error-corrected via the ECC circuit, read into the buffer register, and the retained data is rewritten and transferred to the memory cell array without going through the ECC circuit to refresh the cell array data.

-When burst transfer, which is external data transfer from the buffer register, is interrupted, data transfer control is performed to start a new data transfer operation based on the signal indicating the internal data transfer status.

-ECC refresh is performed based on the number of internal data transfers.

-The memory cell array is configured as a three-dimensional cell array in which a plurality of layers of cell array mats are stacked using, for example, a resistance-changing memory cell. Data transfer to the outside via the buffer register is performed in a series of clock bursts, and at least a signal indicating the input start cycle of a command or address, a series of signals specifying the operation mode, burst data and its start address are specified. It has an interface for a series of signals to specify, a series of signals to specify the address of the layer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a 3D cell array block 1 in which memory cells are three-dimensionally arranged and a control circuit 2 formed on the underlying semiconductor substrate. The word line WL and the bit line BL, which are the selection signal lines of the 3D cell array block 1, are vertical wiring regions provided on the four sides of the cell array block and are connected to the base control circuit 2.

In order to construct an actual file memory, such a cell array block 1 is further arranged in a matrix, and the details will be described later.

The unit layer (that is, matte) of the cell array block 1 is shown by an equivalent circuit as shown in FIG. 2, and the resistance change type memory cell MC is arranged at each cross point of the word line WL and the bit line BL. The memory cell MC is composed of a diode Di and a variable resistance element VR connected in series. Here, the anode side signal line of the diode Di is defined as a bit line BL, and the cathode side signal line is defined as a word line WL.

The control circuit 2 has bit line decoder / multiplexer circuits 21a and 21b corresponding to both ends of the bit line. That is, the bit wires drawn on the substrate at both ends of the cell array block 1 are selected by these bit wire decoders / multiplexers 21a and 21b according to the address signal and command from the outside, the potential is set, and the sense amplifier is passed through the buses 22a and 22b. Input to circuit 23.

At the time of reading, as will be described later, a current sense type sense amplifier senses data by comparing the cell current and the reference current. At the time of writing, the sense amplifier circuit 23 and the decoder / multiplexer circuits 21a and 21b supply an appropriate writing voltage and current to the selected cell.

Word line decoders / drivers 24a and 24b are located at both ends of the control circuit 2 in the word line direction. That is, the word lines drawn on the board at both ends of the cell array block 1 enter these word line decoders / drivers 24a and 24b, and the word line level is selectively set according to an external address or a command.

In this example, the bus areas 22a and 22b for exchanging data with the outside are set in the gap provided between the bit line decoder / multiplexer circuits 21a and 21b and the cell array block 1. Therefore, the bit line passes over the bus regions 22a and 22b from the bit line decoder / multiplexer circuits 21a and 21b until it reaches the cell array block 1.

The bit line signal is sent to the sense amplifier circuit 23 provided on the substrate directly under the cell array via the bus regions 22a and 22b, where the sense amplification or writing is converted into a writing voltage or current according to the data. The sense amplifier circuit 23 exchanges data with the outside of the cell array block via the bus regions 22a and 22b.

FIG. 3 shows the detailed configuration of the sense system circuit in relation to the word line and the bit line in the mat.

The reference cell RMC fixes a specific bit line in the mat as a reference bit line RBL and uses the one connected to the reference bit line RBL. In the figure, one bit line BL of the information cell MC is shown, but in reality, one reference bit line BL is selected in pairs for a plurality of bit lines. Both are in the same mat and the sense system is closed by the mat.

All cells connected to the reference bit line RBL, that is, the reference cell RMC, are set to the low resistance set state, which is the cell state after forming, after being selected as the reference bit line RBL. No settings other than the set state are made for this. That is, when writing occurs in the information cell MC, the word line WL common to the information bit line BL and the reference bit line RBL is selected, so that the reference bit line RBL is written in the set state at the same time.

That is, the set state is refreshed on the reference cell RMC of the reference bit line RBL, assuming that the set state is always written at the time of writing. By this operation, the reference cell RMC is always in a stable set state, and the reference level at the time of reading the cell data of the bit line BL can be secured.

In the following, the low resistance set state of the memory cell is referred to as data 1, and the high resistance reset state is referred to as data 0.

The cell current of the information cell MC flowing through the bit line BL and the reference current of the reference cell RMC flowing through the reference bit line RBL enter the two inputs IN and / IN of the sense amplifier (SA) 31 via the local buses LB and RLB. .. As will be described later, the actual reference current becomes a sense amplifier input by reducing the amount of the current by about 1/10 by the current mirror circuit.

Explaining the specific circuit operation of FIG. 3, when the word line WL is selected, the word line switch transistor MN1 driven by the decoding signal from the low decoding is turned on and connected to Vss. When the bit line BL and the reference bit line RBL are selected, the column decoder and the bit line switch transistors MN2 and MN3 controlled by the output of the reference column decoder are turned on and connected to the local data buses LB and RLB, respectively. .. These local buses LB and RLB are connected to the input IN and / IN of the sense amplifier SA.

The word line selection transistor MN1 is selected at the L level of the signal from the decoder, and its on-resistance is controlled by the level Vm given to the gate. The level of this voltage Vm is changed according to forming, "1" writing, "0" writing and reading.

In the bit line BL selection transistor MN2, the signal from the decoder is selected at the L level, and its on-resistance is controlled by the level Vg given to the gate. The level of this voltage Vg is changed according to forming, "1" writing, "0" and reading.

The selection transistor MN3 of the reference bit line RBL is selected at a gate level higher than Vdd + Vt at the time of writing and at a gate level of Vread at the time of reading. Vt is the threshold voltage.

A write control circuit 32 is provided as a level generation circuit for the control voltages Vg and Vm of the above selection transistors. The details will be described later.

The NMOS transistors MP1 and MP2 connected to the local buses LB and RLB are controlled by the signal / Write = L at the time of writing, and the local buses LB and RLB are set to the power supply level Vdd.

FIG. 4 shows a configuration example of the sense amplifier (SA) 31, which is a current comparison type sense amplifier that compares minute cell currents of 100 nA or less at high speed. The basic configuration of this sense amplifier has already been patented and published (Japanese Patent Application No. 2004-093387).

In the sense amplifier 31, the first current path 41 in which the MIMO transistors M0, M8, the NMOS transistors M10, the MIMO transistors M2, and the NMOS transistor M4 are connected in series between Vdd and Vss, and the MOSFETs M1, M9, and the NMOS transistors The second current path 42 in which the M11, the MOSFET transistor M3, and the NMOS transistor M5 are connected in series is formed symmetrically.

The sources of the MOSFET transistors M2 and M3 are connected to the input nodes IN and / IN, respectively, but the current mirror circuits 43 and 44 are interposed between them. The current mirror 44 provided on the input node / IN side of the reference bit line RBL is composed of MOSFET transistors M15 and M16 whose dimensional ratio is set to 1:10, and 1/10 of the current flowing through the reference cell RMC is It actually flows to the sense amplifier as a "reference current".

The current mirror 43 on the IN side of the input node is a dummy for ensuring symmetry with the input node / IN side, and the dimensional ratio of the NMOS transistors M13 and M14 is 10:10. That is, the cell current of the selected cell MC flowing to the input node IN is supplied to the sense amplifier as it is.

These current mirrors 43 and 44 are connected to the power supply Vdd via the MOSFET transistors M14 and M17 activated by the activation signal / accREAD.

The connection node of the MOSFET M2 and the NMOS transistor M4 of the first current path 41 becomes one output node OUT, and the connection node of the MOSFET M3 and the NMOS transistor M5 of the second current path 42 becomes the other output node / OUT Become.

The gates of the MOSFETs M0, M2 and the NMOS transistors M4 of the first current path 41 are commonly connected to one output node / OUT, and the gates of the MOSFETs M1, M3 and the NMOS transistors M5 of the second current path 42 are the other. It is commonly connected to the output node OUT of, and constitutes a CMOS latch. That is, the CMOS inverter forming the first current path 41 and the CMOS inverter forming the second current path 42 are cross-connected with input and output to form a latch.

MOSFET transistors M8 and M9 are activation transistors, and the gate is controlled by the activation signal / ACT. The NMOS transistors M10 and M11 are current control elements of current paths 41 and 42, and the gate is controlled by the signal vLTC to determine the sense amplifier current.

The gates of the MOSFETs M4 and M5 that make up the CMOS latch are connected to the drains of the MOSFETs M6 and M7 driven by the sense signal / SE, respectively. These NMOS transistors M6 and M7 are turned on during / SE = H to keep the CMOS latched MOSFET transistors M4 and M5 off.

That is, the current flowing through the current paths 41 and 42 due to the activation signal / ACT = L flows to Vss via the NMOS transistors M7 and M6, respectively, until / SE becomes L. Then, after the cell current is introduced, when / SE = L is sensed, the NMOS transistors M6 and M7 are turned off to cut off the pass current, and the drain voltage difference between them is positively feedback amplified by the CMOS latch. become.

The operation of the sense amplifier SA of this embodiment will be described with reference to FIG. When the sense signal / SE is H, the NMOS transistors M6 and M7 are on, and the output nodes OUT and / OUT are kept at the L level. When the activation signal / ACT becomes L, a current flows through the current paths 41 and 42. Then, when the cell current capture signal / accREAD becomes L and current injection is started into the bit line and reference bit line connected to the input nodes IN and / IN, the cell current and the reference current (1 of the reference cell current) are started. A small voltage difference is generated in the drains of the NMOS transistors M6 and M7 according to the difference of 10) (hereinafter referred to as the cell current difference).

When the sense signal / SE becomes L after an appropriate time ΔT that reflects the cell current difference, the NMOS transistors M6 and M7 are turned off, and the positive feedback operation of the latch circuit that amplifies the drain voltage difference causes it. , One of the NMOS transistors M4 and M5 is on and the other is off. That is, when the NMOS transistors M6 and M7 transition from on to off, the timing shift based on the cell current difference is converted into their drain voltage, which is positive feedback amplified.

In the transistor pairs M10 and M11, the gate signal vLTC is set to a low level VRR at the initial stage to suppress conductance, the sense amplifier current from the power supply Vdd is throttled, and the cell current difference supplied via the pairs M12 and M13. Is more strongly reflected in the state of the sense amplifier. When the balance of the sense amplifier is lost due to the cell data current difference due to the initial sense of the sense amplifier, the gate signal vLTC is changed from VRR to VPP higher than Vdd, the power supply voltage is supplied to the sense amplifier, and the output is fully swung to Vdd. Let me. At this time, the signal / accREAD is started and the supply of the cell current to the sense amplifier is cut off.

Since the variation of the miniaturized pair transistor is caused by the fluctuation of the manufacturing process, it is preferable that the current paths 41 and 42 are connected in series of many elements as shown in FIG. 4 because the variation is offset. Therefore, the M0-M1 pair, M8-M9 pair, and M10-M11 form the space between the input node and the power supply Vdd.

In particular, the N-channel transistor pair M10-M11 suppresses the influence of variations between the P-channel transistor pairs M0-M1 and the pair M8-M9, which form a feedback loop for the operation of the sense amplifier SA. That is, the conductance of the N-channel transistor is suppressed, the potential of the drain and source of the P-channel transistor closer to the power supply Vdd is raised, and the conductance of the P-channel transistor is raised. That is, the conductance of the P channel and the N channel acts in the direction of suppressing the influence of the respective variations.

The time difference between the signal / accREAD shutdown and the sense operation start signal / SE shutdown ΔT waits until the cell current injection after the / accREAD shutdown is completed and the input current sufficiently reflects the cell current. Will be adjusted so that

FIG. 6 shows the configuration of the write control circuit 32. The power supplied to the circuit is a power supply voltage Vdd sufficient to generate the cell set voltage Vset, a boosted power supply voltage Vpp higher than this, Vg_reset, Vread, Vt + ε and Vss lower than Vdd. The magnitude relationship is Vss &lt;Vt + ε &lt;Vread &lt;Vg_reset &lt;Vdd &lt;Vpp.

The signal supplied to the write control circuit 32 is / Write and the information data data to be written to the cell, and the output is the power supply level of Vg and Vm. This circuit is a circuit that generates the required power supply level from the data data according to the operation mode of the memory, and has a MOSFET flip-flop FF that changes the state according to the data. The MOSFETs MP21 and MP22 controlled by the flip-flop FF output the power supply voltages Vpp and Vg_reset at the time of setting and reset, respectively, and their outputs are output to the Vg node via the MOSFET transistor MP23.

On the control signal Vm side, a driver DRV11 that outputs Vdd and Vt + ε at the time of reset and at the time of setting, respectively, and a MOSFET transistor MP24 that transfers the output are arranged.

The MOSFET transistors MP23 and MP24 are turned on by being controlled by the signal / Write = L at the time of writing (at the time of setting or resetting). At the time of reading, the NMOS transistors MN21 and MN22 are turned on by the signal / Write = H, and the reading voltage Vread is given to the Vg and Vm nodes.

In FIG. 7, the levels of the control signals Vm and Vg at the time of reset (when writing 0), at the time of setting (when writing 1), and at the time of reading are summarized in a table. The cell forming mode is the same as Set, where Vm gives Vt + ε and Vg gives Vpp.

FIG. 8 shows the relationship between the sense amplifier and the data bus in the control circuit 2. The unit layer that constitutes the cell array block 1, that is, the size of the mat, is a cell matrix of 4 [Mb] composed of 4k word lines WL and 1k bit lines BL, and this is the unit of the smallest cell group. It becomes. In the area of the sense amplifier circuit 23, four sense amplifiers SA1-SA4 are provided, and the bit lines are connected to each of the two from both ends of the matte bit line through the bit line decoder / multiplexer circuits 21a and 21b. Will be done. That is, when one word line WL is selected by the word line driver 24a or 24b, two bit lines BL are selected from both sides, and four cells are accessed.

Address signal lines that select word line WL or bit line BL and data lines that are selected and connected from bit line BL run on buses 22a and 22b. Bit line decoder / multiplexer circuits 21a and 21b and word line drivers 24a and 24b A pre-decoder 25a-25d that selectively drives a word line driver is arranged in the intersection region of the above.

The entire memory array is configured by further arranging a plurality of array block 1s shown in FIG. 1 in two dimensions. For convenience of displaying the entire cell array of this memory chip, the following is a 16 [Mb] block display in which four 4 [Mb] cell array blocks are grouped together, and 68 [Mb] in which four 4 [Mb] cell array blocks are grouped together. Introduce cell array unit display.

FIG. 9 shows one 16 [Mb] cell array block B, which is a combination of four 4 [Mb] cell array blocks b0-b3. At this time, the buses running through the bit line decoder / multiplexer circuit of each cell array block are 34 bits each on the upper and lower sides.

Further, as shown in FIG. 10, four 16 [Mb] cell array blocks B (B0 to B3), each of which is a group of four 4 [Mb] cell array blocks b, and one 4 [Mb] cell array block b. Arranged in the data bus direction, a cell array unit CA of 68 [Mb] per unit mat is constructed.

The cell array unit CA is composed of 17 4 [Mb] cell array blocks b, and since each cell array block outputs 2-bit data on one side, a 34-bit bus runs up and down. A 136-bit or 68-bit bus further runs at one end of the cell array unit CA, and buses from each cell array block are selectively connected to this bus via a bus gate.

FIG. 11 is an example of a memory chip configuration having a memory core 100 of 8 [Gb] + 832 [Mb] per unit mat, which is configured by using the above-mentioned cell array unit display. This configuration example is for the x16IO type, which reads and writes 16-bit data in parallel. Here, it is assumed that the memory chip is equipped with an ECC circuit 112 capable of error correction up to 4 bits.

This ECC circuit 112 is a finite field GF (2).¹⁰) Is BCH-ECC, the number of data bits is 552 (the number of information bits is 512 + the number of check bits is 40), and the above-mentioned memory capacity component 832 [Mb] means each mat capacity for check bits. are doing. The details of the ECC circuit 112 will be described later.

As shown in FIG. 11, the memory core 100 is configured by arranging eight cell array units composed of mats having a 68 [Mb] configuration in the X direction and 16 in the Y direction. However, 4 [Mb] cell array blocks are added to the cell array units at both ends in the X direction in order to match the number of read / write data in relation to the ECC circuit 112. As a result, with one layer of mat, 68 [Mb] x 16 x 8 + 4 [Mb] x 32 = 8 [Gb] + 832 [Mb], and assuming that the number of mats stacked is m, 8 [Gb] x m + The capacity is 832 [Mb] x m.

In this example, one layer of the entire memory mat is selected and a quarter of the memory mat is divided. That is, the cell array region surrounded by the broken line in the figure is assumed to be activated at the same time, and the inside of the memory chip is activated as evenly as possible.

The data read and written collectively to and from the cell array is an integral multiple of the number of processing data bits 512 + 40 of the ECC circuit 112. Specifically, in this example, (512 [b] + 40 [b]) x 4 = 2208. [b]. These data are transferred in parallel by the 136-bit bus from the cell array unit and the 144-bit bus at both ends of the chip. 128-bit data is exchanged with the outside of the chip for each IO, and this data transfer unit is hereinafter referred to as burst.

The buffer register 111 temporarily holds the data for burst, and the number of data bits is M times the number of processing data bits (including check bits) of the ECC circuit (M is an integer), and 128 for each IO. +40 = 168-bit buffer. Data is transferred between the buffer register 111 and the ECC circuit 112 in M times of time division, encoding (writing) or decoding (reading) is performed, and the code data is overwritten in the buffer register 111. Transferred to an external or memory cell array.

Actually, two buffer registers 111 are provided as described later, and by interleaving and using them, gapless data can be read and written to and from the outside of the chip. Its transfer rate is a data cycle of 25 [ns] and 40 [Mbs] per IO. As a memory chip, it achieves a data transfer rate of 80 [Mbyte / s].

FIG. 12 shows a configuration example of a memory chip having the same capacity as that of FIG. 11 in the case of × 8 IO. The array of cell array units of the memory core 100 is the same as the example in FIG. 11, and one layer is 8 [Gb] + 832 [Mb], and the total capacity is 8 [Gb] × m + 832 [M, where m is the number of layers. Mb] × m.

In this example, one layer of the entire memory mat is selected, and one-eighth division operation is performed in it. That is, it is simultaneously activated when the cell array portion surrounded by the broken line is accessed. The data that is collectively read and written to and from the cell array is (512 [b] + 40 [b]) x 4 = 2208 [b], and these data are the 68-bit bus from the cell array unit and 72 at both ends of the chip. It is transferred by the bit bus by two parallel transfers. 128-bit data is exchanged with the outside of the chip for each IO, and this data transfer unit is hereinafter referred to as burst.

The buffer register 111 temporarily holds the data for burst, and the number of data bits is M times the number of processing data bits (including check bits) of the ECC circuit (M is an integer), and 128+ per IO. 40 = 168-bit buffer. Data is exchanged between the buffer register 111 and the ECC circuit 112 in M time divisions, encoding or decoding is performed, and the code data is overwritten by the buffer register 111 and transferred to an external or memory cell array. To.

Two buffer registers 111 are provided, and interleaving and using them is the same as the above example. Its transfer rate is a data cycle of 25 [ns] and 40 [Mbs] per IO. As a memory chip, it achieves a data transfer rate of 40 [Mbyte / s].

As shown in FIG. 13, a buffer register 111 is provided between the memory core 100 and the ECC circuit 112, and two of the registers are read or written data transfer (this) to and from the memory core 100. While performing internal transfer (hereinafter referred to as internal transfer), the other performs read or write data transfer (hereinafter referred to as external transfer) with the external terminal IO, that is, an interleave operation is performed.

As described above, the ECC circuit 112 corrects 4-bit errors. To briefly explain this, the ECC circuit 112 includes an encoding unit ENC as shown in FIG. 14 and a decoding unit DEC as shown in FIG. It is composed.

The encoding unit ENC generates check bits based on the information polynomial f (x) whose coefficients represent data. That is, the coefficient a of the information polynomial f (x) represented by the equation 1_4n~ a_h-1Assign information bits to. [Number 1] f (x) = a_h-1x^h-1-4n+ a_h-2x^h-2-4n+ ...... + a_{4n + 2}x²+ a_{4n + 1}x + a_4n And four primitive irreducible polynomials m₁(x), m₃(x), m₅(x), m₇Code generation using (x) Polynomial g (x) = m₁(x) m₃(x) m₅(x) m₇A polynomial f (x) x that generates (x) and starts from the 4nth order⁴ⁿIs divided by g (x) to obtain the remainder r (x) as shown in Equation 2. [Number 2] f (x) x⁴ⁿ= q (x) g (x) + r (x) r (x) = b_4n-1x^4n-1+ b_4n-2x^4n-2+ ...... + b₁x + b₀ Coefficient b of this remainder polynomial r (x)_4n-1~ b₀Becomes the check bit and the information bit a_h-1~ a_4nConsists of the data bits stored in memory with. Specifically, in this embodiment, the finite field GF (2) is considered in consideration of the error correction rate and the like.¹⁰) Is used to realize the ECC system of BCH code, and 512 bits are used as the information bit and 40 bits are used as the check bit.

The data read from the memory is the polynomial ν (x) represented by the following equation 3. [Number 3] ν (x) = f (x) x⁴ⁿ+ r (x) + e (x) = q (x) g (x) + e (x) That is, the error that occurs in the read data is represented by the error polynomial e (x) of order h-1. The decoding unit DEC finds this error polynomial e (x).

As the first step, in the syndrome calculation unit SC, the read data polynomial ν (x) is set to the irreducible polynomial m.₁(x), m₃(x), m₅(x), m₇Find the syndrome polynomial, which is the remainder polynomial divided by (x). Then, based on the obtained syndrome, the error position search unit ES calculates the error position. If the 4-bit error is next to i, j, k, l, then the error polynomial is e (x) = xⁱ+ x^j+ x^k+ x^lTherefore, finding this order is the error position search.

The error position search unit ES outputs a signal "no error" to that effect when there is no error, and outputs a signal "non correctable" to that effect when there is an error of 4 bits or more. Output. The obtained error bit can be corrected by the error correction unit EC to obtain correct data.

In order to realize such an ECC circuit with the smallest possible circuit scale and high-speed operation, it is important to reduce the calculation scale of the error position search unit ES to the following. In practice, a circuit is used by examining the exclusive conditions for finding solutions for 2-bit errors, 3-bit errors, and 4-bit errors, and using the common circuit in the system in a time-division manner based on the results. The scale can be effectively reduced, but the detailed explanation is omitted.

Next, the data transfer, that is, the internal transfer between the buffer register 111 and the memory core 100 will be described in detail.

First, write data transfer (Wdt), in which write data stored in a buffer register is transferred to a memory cell array by burst transfer, will be described with reference to FIGS. 16 and 17.

FIG. 16 shows the case of the × 8 IO configuration. In this case, the burst per IO is 128 bits, which is eight and 1024 bit write data is stored in the buffer register. As the buffer register, it has two registers REG1 and REG2 of 552 bits, which is a total of 512 information bits and 40 check bits of the ECC circuit. That is, 1024-bit write data is stored in registers REG1 and REG2 by 512 bits by a burst of 128 cycles.

Since ECC processing is performed every 512 bits of data, the data in the registers REG1 and REG2 is sent to the encoding section ENC of the ECC circuit 122 in two time divisions and encoded, and the encoded data is the generated check bit. Overwrites the same registers REG1 and REG2 with (40 bits).

The encoding time is 50 [ns], and it takes 50 [ns] x 2 = 100 [ns] to encode all the write data. The data code overwritten in the buffer registers REG1 and REG2 is transferred to the cell array and written in a time of about 2 [μs].

FIG. 17 shows the case of the × 16 IO configuration. In this case, the burst per IO is still 128 bits, which is 16, so the write data is stored in the 2048-bit buffer register. As buffer registers, four registers REG1 to REG4 with a 512-bit + 40-bit configuration are prepared, and 512 bits are stored in each of these in a burst of 128 cycles.

The write data stored in these buffer registers is also time-division-encoded for ECC coding, and 40-bit check bits are added to overwrite each of them in the same buffer register.

The encoding process is for every 512 bits of data, and assuming that the encoding time is 50 [ns], it takes 50 [ns] x 4 = 200 [ns] to encode all the write data. The data code overwritten in the buffer register is transferred to the cell array and written in a time of about 2 [μs].

Next, with reference to FIGS. 18 and 19, a read data transfer (Rdt) that reads the data in the memory cell array, transfers the data to the buffer register, and outputs the data to the outside by burst transfer will be described.

FIG. 18 shows the case of the × 8 IO configuration. In this case, 128-bit burst data code (512 bits + 40 bits) x 2 per IO is read and transferred from the cell array to the two buffer registers REG1 and REG2. At this stage, the data has not passed through the ECC circuit. This data transfer requires 100 [ns] of time.

Then, the data code of the buffer registers REG1 and REG2 is transferred to the decoding part of the ECC circuit by time division, the decoding process for the burst of × 8 is performed twice, and the corrected data is the original register REG1 respectively. Overwrite, REG2.

The time required for ECC decoding is 200 [ns], and since this is repeated twice, the decoding process is completed in 400 [ns] time, and finally the error-corrected data and check bits are stored in the buffer registers REG1 and REG2. Is retained. The data part of this buffer register is burst-transferred and sequentially output to IO.

FIG. 19 shows the case of × 16 IO. In this case, the read data code (512 bits + 40 bits) × 4 for a burst of 128 bits per IO is transferred from the cell array to the four buffer registers REG1 to REG4. This data transfer requires 100 [ns] of time. The data code read into the buffer register is sequentially transferred to the decoding unit of the ECC circuit, and is overwritten in the original register as data whose error has been corrected by the decoding process.

Decoding processing is data processing for bursts of × 16 four times by time division. The time required for one decoding process is 200 [ns], and since this is repeated four times, all decoding processing is completed in 800 [ns] time, and finally the error is corrected in the buffer registers REG1 to REG4. Data and check bits are retained. The data part of this buffer register is burst-transferred and sequentially output to IO.

Next, the interleaved transfer operation of the internal transfer and the external transfer by the two buffer registers will be specifically described with reference to FIG.

The first thing to note is that the buffer register that performs external transfer in synchronization with the clock should hold the data of the corresponding address in advance regardless of reading or writing. This is natural for reading, but even in the case of writing, data is read in advance in the buffer register to be written, and the write data is overwritten with respect to this. By using such a method, the data of the burst address is retained against the mask input of the data or the cancellation of writing in the middle of the burst, and the consistency of the data is maintained.

The work of storing the burst address data in the buffer register in advance is performed for the buffer register on the back side of the two buffer registers that actually perform burst transfer in preparation for the next burst.

In FIG. 20, the buffer register REG-A is actually performing burst transfer (external transfer), and internal transfer, that is, write data transfer (Wdt) is performed in the other buffer register REG-B within the burst cycle. ) And read data transfer (Rdt) are performed.

It should be noted that there are cases where the write data transfer Wdt is involved and cases where it is not accompanied, but this is the difference between whether or not the Wdt operation is performed in the data transfer sequence with the cell array. In other transfer methods, the write data transfer Wdt may always be performed. This is because the data stored in the buffer register is guaranteed to be error-free by the result of error correction in the ECC circuit in the case of reading, and the written data is correct in the case of writing. Because it is guaranteed.

By writing and transferring this data via the encoding section of the ECC circuit, it is possible to transfer an error-free data code to the cell array in both reading and writing. This is equivalent to refreshing the data in the cell array. This is a concept that is only possible when the ECC circuit intervenes in the middle of data transfer between the cell array and the data register.

In the burst cycle, after the write data transfer Wdt from the register REG-B to the cell array, the data at the address to be the next burst is read from the cell array to the register REG-B, data transfer Rdt is performed, and the data is stored as error-corrected data. To do. Since these Wdt and Rdt are completed during the burst cycle to prepare for the next burst, if the read cycle time tRC and write cycle time tWC of the burst cycle are 25 [ns], the burst will consist of 128 cycles, so 25 [ns. ] × 128 = 3.2 [μs] must complete these transfers.

The time required for each transfer is shown earlier, but with × 8IO, Wdt takes 2.1 [μs] and Rdt takes 500 [ns], so a total of 2.6 [μs] is required at a minimum. With × 16 IO, Wdt takes 2.2 [μs] and Rdt takes 900 [ns], so a total of 3.1 [μs] is required at a minimum. Since both are shorter than the burst cycle time of 3.2 [μs], there is no contradiction between the data transfer of the external transfer and the data transfer of the internal transfer.

Next, the details of the data transfer timing specification in the burst cycle will be described. Specifically, an example of timing specifications for data transfer in which read and write data bursts coexist and timing specifications for command signals will be described.

In FIG. 21, two buffer registers REG-A and REG-B alternately perform burst transfer, and during the burst transfer, the other register writes data to and from the cell array Wdt and the next burst. Indicates that read data transfer Rdt is performed in preparation for transfer.

With reference to FIG. 22, a timing specification for enabling such data transfer will be described. Before a new data burst begins, you need to decide whether the data burst is read or write. It is also necessary to enter the address of the data burst. Regarding the method of capturing a command using a command start signal as described below, there is already a patent proposal by the present inventors (for example, USP6,185,150).

As shown in FIG. 22, the timing of the command start signal that determines the clock cycle for capturing the command is defined with reference to the clock rise t0 at the burst data switching timing. There are two ways to do this.

The first is the setup time tCS of the command start signal from the rising edge t0 of the clock.^*And tCH corresponding to the duration of the command signal^*It is a method to specify. At this time, it is necessary to read the data and prepare it in the buffer register by data transfer Rdt for the next data burst. The transfer time for batch read transfer for that purpose is about 500 [ns] for x8IO and about 900 [ns] for x16IO, so tCS^*It is necessary to set a time longer than this time.

However, if the setup time is too long, it becomes difficult to set it, and the timing of receiving commands cannot be set accurately. Therefore, as the second method, there is a method of defining the timing from the clock edge t0 based on the number of clocks.

That is, the clock m cycles before the rising edge t0 of the clock that switches the data burst is specified, and the rising and falling timings tCS and tCH of the command start signal from the rising edge are specified as shown in FIG. Specifically, it is necessary that m × tCK is 500 ns or 900 ns or more, where the clock period is tCK. If tCK = 25ns, m will be 20 or 36 or more.

This command start signal causes the command acquisition such as the read or write mode and address of the next data burst cycle to be started.

The timing of clock CK and data is determined by the data access time tAC from each clock edge when reading data. It is also possible to give the clock a clock latency. In the figure, the rising edge of the clock is used as the reference, but DDR specifications that also use the falling side are also possible. For writing, the input data may be retained while it is determined by the setup time tDS and hold time tDH from the rising edge of the clock.

Although FIG. 21 does not show whether the data burst is a read data burst or a write data burst, there are four mode relationships between the data bursts. That is, when the read data burst continues (RR), when the write data burst continues (WW), when the read data burst is followed by the write data burst (RW), and when the write data burst is followed by the read data burst. There are four cases (WR). Each will be described below.

Mode RR is a continuous sequence of reads, with no data output clock jumps between data bursts.

Mode WW is a continuous sequence of writes, and like RR, there is no data input clock jump.

Mode RW is a sequence that switches from a read data burst to a write data burst. In this case, the regulation for the clock edge of the data differs between reading and writing, and since the data precedes the clock edge in writing, it is necessary to shift the relationship between the data and the clock at the time of switching. That is, since the read data burst before the timing t0 may overlap with the next write data burst, the input of the burst data is started after n clock cycles (n 1) from t0. The actual write data burst cycle starts from the clock after this n cycles.

Mode WR is a sequence for switching from a write data burst to a read data burst, and the timing of the edge of the data and the clock shifts toward the delay when switching, so there is no contradiction in the relationship between the data and the clock without special consideration. .. That is, n = 0 may be used.

In the method of performing ECC refresh for the read burst, the write data transfer Wdt is always performed at the timing when the buffer register is switched. If ECC refresh is not performed, transfer is performed only at the time of switching after a write data burst. Read data transfer Rdt shall start data transfer from the cell array to the buffer register as soon as the burst address is determined by the command, so that this Rdt is always performed regardless of whether the next burst is write or read. To do.

In Fig. 22, the clock cycle tCK is defined as the clock cycle tCK from the rising edge of the clock CK to the next rising edge. However, considering the double data rate (DDR), the meaning of the clock cycle is defined as the clock edge, which is the standard for determining the timing of clock data or commands. Can be defined between. That is, in DDR, it is defined by the rising and falling edges of the clock.

When reading and writing data in a burst cycle with the outside of the memory, that is, in the case of external transfer, since the length of 128 cycles is considered as a burst here, it often happens that the burst transfer is not completed and ends in the middle. It seems that. At this time, a method of maintaining the consistency between the data in the memory array and the data to be read / written will be described.

The burst transfer may end in the middle of an interrupt, which starts by switching a new burst cycle from the middle, or a stop, which stops the burst transfer and ends the memory access.

FIG. 23 shows the case of burst cycle interrupts. It is assumed that an interrupt command is input as shown in the figure in a clock cycle in the middle of performing burst transfer "burstA" using the buffer register REG-A. The details of setting this command will be described later.

Until an interrupt occurs, if "burstA" is a write burst, the data from outside the memory will be read by overwriting the data in the buffer register REG-A, so the data in register REG-A after the clock cycle in which the interrupt occurred will be read. The burst data to which the data is written remains the corrected data via the ECC circuit. That is, the data is not overwritten as in the data writing mask operation described later.

When writing the data of the overwritten register REG-A to the cell array, the write data transfer Wdt must be performed as the code data encoded through the ECC circuit. During burst transfer at register REG-A, at register REG-B, write data transfer Wdt (or write data transfer that does not pass through the ECC circuit may occur, which is Wdt.^*And. The same applies hereinafter) and read data transfer Rdt is performed.

Therefore, it is Wdt or Wdt in register REG-B that can start a new burst transfer "burstB" after an interrupt.^*Is over and the Rdt of the new burst address is done. At the same time as a new burst "burstB" is started, Wdt or Wdt from the register REG-A on the previously interrupted "burstA" side^*Make a transfer.

If the burst "burstA" is a read burst, the burst read of the data read and transferred to the register REG-A is only interrupted until an interrupt occurs, and the data in the REG-A is decoded by the ECC circuit. Since the data is error-corrected, there is no need to re-encode this data when writing it back to the cell array. That is, it is sufficient to match the check bit of REG-A and write it back, and this is the write data transfer Wdt that does not pass through the ECC circuit.^*Will be.

FIG. 24 shows the case where the burst cycle is interrupted. It is assumed that an end command is entered in the middle of the burst cycle in the buffer register REG-A as shown in the figure. Until the interruption occurs, if this burst "burstA" is a write burst, the data from outside the memory will be read by overwriting the data in register REG-A. The data in register REG-A after the clock cycle in which the interruption occurred is the read data in which the burst data to which the data is written is corrected via ECC.

That is, in this case as well, the data is not overwritten as in the data writing mask operation described later. When writing the data of the overwritten register REG-A to the cell array, write transfer Wdt must be performed as code data encoded through the ECC circuit. This Wdt transfer can be started by Wdt (or Wdt) in register REG-B.^*) Is finished, and after the transfer of REG-B is finished, Wdt transfer will be performed from the register REG-A of the interrupted "burstA".

If the burst "burstA" is a read burst, the burst read of the data read and transferred to the register REG-A is only interrupted until the interruption occurs, and the data in the register REG-A is error-corrected by the ECC circuit. Since it is the data, it is not necessary to re-encode it when writing it back to the cell array. Therefore, in this case, the write data transfer is Wdt.^*Will be.

Wdt or Wdt from buffer register REG-A^*Is the actual end of memory access.

In the case of an interrupt, a new burst cycle is started after the data preparation is completed by data transfer, and this clock cycle is determined not by the outside but by the memory system. Since there is a clock cycle gap in the data transfer between the memory and the outside, it is also necessary to output a signal indicating the internal data transfer status from the memory side, and this signal can be used as a signal to determine the start of a new burst cycle. To do so.

ECC may or may not be applied to the write data transfer Wdt, and this is also related to ECC refresh, which will be described later, so the outline will be described here.

ECC refresh is an operation of holding error-corrected data in a register and writing it to a cell array to refresh the held data in order to eliminate the cumulative error of the accessed burst data. It is based on the assumption that the data held in the register, including the write burst, is correct. If it is a read burst, the data is decoded through the ECC circuit in the cell array, so it is correct including the check bit. If it is a write burst, the data is overwritten, so the check bit cannot be used and it is necessary to newly encode. ..

In the burst cycle, two buffer registers are used in parallel, one performs data transfer with the outside and the other performs data transfer with the cell array, but the write data transfer Wdt from the register to the cell array is described above. As can be seen from the above, there are two cases depending on whether the data held in the register is used in the read burst or the write burst.

FIG. 25 shows a case where the buffer register REG-A performs a read burst (burst A) and then the buffer register REG-B performs a write transfer to the cell array behind the write burst cycle (burst B). At this time, since the write data transfer behind burstB is the correct code data including the check bit without encoding, it can be written back to the cell array without passing through the ECC circuit. This is the write data transfer Wdt without ECC^*Is.

It was explained earlier that the ECC circuit encoding takes about 100 [ns] for x8IO and about 200 [ns] for x16IO. Therefore, the write data transfer can be executed in a transfer time shorter by this time. Of course, if it is troublesome to determine the type of burst, you can perform normal write data transfer Wdt and re-encode.

FIG. 26 shows a case where a write burst (burstA) is performed in the buffer register REG-A and then a write transfer to the cell array is performed behind the burst (burstB) in the buffer register REG-B. At this time, the data in register REG-A is overwritten at least in part by burstA. Encoding is always required to create a check bit for this new data, and in the next write burst cycle (burstB), the normal write data transfer Wdt through the ECC circuit will be performed.

Write transfer Wdt or Wdt^*The burst data of the cell array immediately after the above is the state with the fewest errors, so to speak, the data is refreshed. After that, the number of error bits increases due to various disturbs while being held in the memory cell array, so ECC that reads back to the buffer register by read transfer again before the number of errors exceeds the range that can be corrected by ECC. It is preferable to refresh. The details of this ECC refresh will be described later.

Next, the details of the burst cycle interrupt timing specification will be described with reference to FIG. 27. The command start signal CE that indicates the start of command acceptance is the time tCS from the edge of the clock cycle where you want to start a new burst (which coincides with the start of a new data transfer cycle).^*Alternatively, the time tCS from the clock edge specified by the number of cycles m is set. In the case of burst interruption instead of interrupt, there is no new burst cycle, so there is no provision for this. The number of cycles m and the like are the same as those shown earlier in the explanation of the burst switching specifications.

The command code is accepted from the clock next to the clock cycle that received the command start signal CE, but for the data of the burst currently in progress, the command code is next to the cycle in which it is determined whether the command code is interrupt or stop. Data transfer between the buffer register and the outside is stopped from the cycle. This regulation is k cycles from the setting cycle of the command start signal CE. In the case of this embodiment, the command code is set to 3 bits, and k is set to be larger than 4.

The command start signal CE setting cycle is defined based on the time when you want to start a new data transfer cycle, but depending on the timing when CE is inserted, data transfer with the ongoing cell array is completed at the same time as the burst that receives an interrupt or interruption. It may not be possible. Therefore, the signals DTX_A and DTX_B indicating the internal data transfer status are output from the memory side to the outside.

That is, DTX_A is 1 during the period during which the buffer register REG-A can transfer internal data, and DTX_B = 1 during the period during which the buffer register REG-B can transfer internal data. When the data transfer between the register and the cell array is completed, the signal switching timing is synchronized with the clock and is performed at the same tAC timing as the data output.

Since the data transfer of the buffer registers REG-A and REG-B is performed alternately, it is also possible to use DTX_A and DTX_B as one signal and "1" or "0" of this signal to indicate the transfer usage period of one of them. it can. The new data transfer cycle (new burst cycle) is after the next clock cycle in which DTX_A and DTX_B change.

In the case of burst cycle interruption, new data transfer is completed after DTX_A or DTX_B is switched, and the data transfer operation of the memory ends after waiting for the timing when these signals are switched again, and the data held in the memory cell array. The consistency of the data exchanged with the outside is maintained.

To examine the details of ECC refresh, the method of data transfer between the cell array and the buffer register is reorganized here. I mentioned earlier that the data in the buffer register always represents the correct data. Whether or not the check bit register part, which is a part of the buffer register, corresponds to the correct data depends on the sequence of operations.

FIG. 28 shows how the burst cycles burstA and burstB are interleaved by using the two buffer registers REG-A and REG-B. The burst data transfer status can be monitored by the signals DTX_A and DTX_B.

For write data transfer performed behind the burst transfer, transfer (Wdt) that holds the data encoded in the buffer register via the encoding part of the ECC circuit and writes it to the cell array, and the transfer (Wdt) that writes this to the cell array, and the encoding part of the ECC circuit are not passed. Transfer to write the write data of the buffer register to the cell array (Wdt)^*). Read data transfer (Rdt) is a case where error-corrected read code data is held in a buffer register through an ECC circuit and output.

Wdt and Wdt^*Which of the above is used is determined by the history of whether the burst cycle before transfer was read or write.

As shown in FIG. 28, internal transfer (Wdt B or Wdt) is performed at register REG-B while burst transfer is performed at register REG-A.^*B, and Rdt B) can be performed, and while burst transfer is performed in register REG-B, internal transfer (Wdt A or Wdt) is performed in register REG-A.^*A, and Rdt A) can be performed.

Now, on the premise of real-time ECC, it is possible to refresh the cell using these internal transfers and correct the error that the cell receives due to the disturb. Since ECC decoding is performed during read data transfer (Rdt) to the buffer register, the data in the buffer register is always written back and transferred in the next burst cycle for the accessed burst address. Wdt^*To do. That is, after the write burst, the Wdt passes through the encode part of the ECC circuit, and after the read burst, the Wdt does not pass through the encode part.^*And.

For other burst addresses in the access cell block, if a write or read transfer is performed in the same cell block, the standby cell in the mat of the cell block also receives an electrically thermal register, so it is sent to the cell array block. Read data transfer Rdt is performed by cyclically changing the burst address within the same cell array block at regular intervals of burst cycle access, and data is written via the buffer register Data transfer Wdt^*Write back with.

This refresh burst address generation is performed by (a) an auto method that counts the number of burst accesses to the cell array block and changes the refresh burst address cyclically at regular intervals, and (b) an external method that the memory automatically performs. It is conceivable that the controller looks at the situation and responds with a command and an address.

For auto ECC refresh, control of command ECC refresh can be introduced into the chip, and a signal indicating that the burst cycle is a refresh burst can be output externally. Only the command ECC refresh that can correspond to is described.

FIG. 29 shows an example in which a burst cycle in register REG-A is set as Refresh Burst Cycle based on the burst sequence of FIG. 28. The burst cycle is continued, and when the refresh condition of a certain cell array block is satisfied, the refresh burst address of this cell array block is given to the memory from the controller to perform refreshing.

That is, as shown in the figure, a refresh command "Ref command" and a refresh address "Ref.Add." Are given at an appropriate timing t10, and read data transfer (Rdt A) is performed to the buffer register REG-A.

After this Rdt, error-corrected data and check bits are held in the buffer register REG-A, so write-back transfer (Wdt) from this register REG-A to the same refresh address in the next burst cycle.^*A) is performed to end the refresh cycle. Within the refresh burst cycle, issue a read / write command (W / R command) for the next burst cycle (timing t11) and resume access.

In the present embodiment, the burst cycle consists of 128 cycles, and if one cycle is 25 [ns], data cannot be exchanged in the ECC refresh cycle during 3.2 [μs]. There is no exchange of data via IO in the refresh cycle, so there is no need to wait for 128 clock cycles.

Therefore, the refresh data transfer gap can be reduced as much as possible by using an interrupt that can start the next burst cycle as soon as the internal data transfer is completed. In Fig. 29, in order to show this, when setting the W / R command in the refresh cycle, "interrupt" is shown in parentheses to indicate that the interrupt command is good.

Figure 30 shows an example of setting a Mask Write burst cycle. Here, the burst cycle of register REG-A is used as the mask write cycle.

In a write burst, you may want to rewrite only some data. Mask writing corresponds to this request. That is, in the case of a write burst, the data of the burst address of the write destination is ECC-corrected and transferred by Rdt to the buffer register REG-A. Therefore, in the burst clock cycle that does not require data rewriting, the write data from the outside is registered. Mask so that it does not overwrite. For that purpose, a mask signal "MASK" for specifying the clock cycle to be masked is required.

FIG. 30 shows an example of timing regulation of the mask signal MASK. If the mask signal is started and set according to the data write cycle to the buffer register, the data in that cycle is not transferred to the buffer register. That is, the data acquisition at the clock edge where the mask signal is MASK = H is invalidated, and the data is not overwritten in the buffer register.

Mask signal setup and hold times tS and tH are defined from the same clock edge as the data, as shown in the figure.

The internal write data transfer in the burst cycle following the mask write burst cycle becomes the write data transfer Wdt via the ECC circuit, and the code data is newly generated and written and transferred.

FIG. 31 is a specification of Repeat Write transfer in which the same data is written to the same burst address as the previous burst cycle. When holding data using a cell with a resistance-changing substance, to improve the reliability of the state holding of the cell without using a method such as ECC refresh, firmly set the low resistance state and the high resistance state. Must be set. In addition, depending on the quality of the cell array, there are some marginal ones in which the reliability of the holding characteristics cannot be sufficiently obtained unless the resistance value is set persistently .

Therefore, it is necessary to have a specification of repeated writing in which the same data is written to the same burst address several times in succession. That is, it is a command specification because the write data transfer Wdt from the buffer register is repeated in order to write the same data to the cell multiple times.

In the repeated write cycle shown in FIG. 31 and the next cycle, the replacement of the buffer register of the internal data transfer is different from the usual one. In a repetitive write cycle, Wdt if the repetitive burst cycle is a read^*For writing, Wdt is performed from register REG-B, and new cycle data read Rdt is performed to buffer register REG-A.

Wdt or Wdt of repeated burst cycle^*After that, the data in the buffer register REG-B, including the check bits, is encoded by the ECC circuit. Therefore, the internal data transfer performed from the register REG-B again in this new cycle is Wdt.^*This transfer overwrites the cell data.

That is, since the transfer data in the buffer register is ECC-encoded by Rdt or Wdt, the code data including the check bit is already correct. The data in this buffer register is repeatedly written to the cell array by the Wdt command "Rep.W command".^*Forward.

By this repeated writing, it is possible to reduce the number of defective writings to the correctable number or less.

In the next burst cycle in which the repeat write command is set, the buffer register is not replaced, so the exchange of data with the outside is blocked. This burst cycle does not require 128 cycles and can move on to the next operation once the internal transfer is complete. Therefore, the command to start a new burst cycle can use an interrupt to start a new burst cycle as soon as the transfer is completed. In the figure, to show this, when setting the command in the refresh cycle, "interrupt" is shown in parentheses to indicate that the interrupt command is fine.

Further, in the iterative cycle, the internal data transfer is different from the normal one, and the write transfer and the read transfer are performed for different buffer registers, so that the signals DTX_A and DTX_B change as shown in the figure.

FIG. 32 shows the specifications of a Repeat Read burst cycle that performs a burst read of the same buffer register as the previous burst cycle. That is, it is a command specification for burst access to the same buffer register multiple times in succession, and is set by repeatedly inputting the read command "Rep.R command" as shown in the figure.

In the case of a repeated read burst after a write burst, the data written in the buffer register is immediately read from the buffer register. The difference from the repeated writing in FIG. 31 is that the internal data transfer is not repeated. This is because the same buffer register, register REG-B in the example of FIG. 32, performs external data transfer and internal data transfer at the same time. Of course, simultaneous transfer from the same buffer register is not impossible, so the specification may be a specification in which internal data transfer is added to the specification for repeated writing.

If the internal data transfer is not performed in the repeat cycle, the internal data transfer in the next burst cycle is Wdt depending on whether the read burst or the write burst is repeated when transferring data from the buffer register.^*Or Wdt. That is, in the case of a read burst, the correct data including the check bit is already held in the buffer register, so the write transfer Wdt without encoding^*Well, if it is a write burst, a new check bit must be created, so it becomes a write transfer Wdt with encoding.

In addition, the iterative cycle involves burst output of data and uses 128 cycles to the full, so it does not interrupt unless there is a particular need.

Fig. 33 and Fig. 34 summarize the rules for timing such as command and burst address acquisition, and the relationship between input signals. As a related patent, there is Japanese Patent Application No. 10-337114 (US6,185,150B1) related to the command start signal CE here. In addition, the example here shows a method that uses only the rising edge of the clock CK as a reference, but the same timing as DDR that uses both the rising and falling edges of the clock or uses complementary clocks of opposite phase together. Is not mentioned because it is easy to specify.

The cycle following the clock cycle in which the command start signal CE is H is the command and address input cycle. Since the CE timing setting has already been described, only the tS and tH specifications for the clock edge are shown here. All input signal specifications are the same for the clock edge, and this timing specification is used. The CE receiver is active every clock cycle and becomes inactive for a period of time when CE = H is detected. Other receivers are active only for this period of time.

The signal R / W indicates whether the next new burst cycle is read (R) or write (W). The command signal CMD is a 3-bit code signal in 3 cycles, and the operation modes are Normal, Interrupt, and End (as shown in the table of Fig. 34) according to the bit information c0, c1, and c2. It is specified as Stop, Refresh, Repeat. The individual operating modes have already been described.

The signals Add_0 to Add_7 are the address of the burst, the start address of the burst cycle, and the address bit information of which layer to select, and 40 bits are input in 5 cycles. The cycle of each bit and the position of the signal are as shown in the waveform diagram of FIG. 33, and an example of the correspondence between each bit and each address is shown on the side of the figure.

Since the burst also includes the address of the cell array block, the address information of the mat layer may be added to this, but the number of layers of the mat layer can be easily changed during the manufacturing process, and the number of bits accompanies this. Since it changes, it is separated as an address bit.

The signals related to memory control, that is, the signals other than the power supply input to the chip pin, are summarized as follows.

CK: Basic clock that controls memory synchronously. In DDR, it is conceivable to input the clock CKB complementary to this together, or to input / output the strobe signal DQS of the input / output data to the chip.

CE: A command start signal that activates a command or address receiver or decoder in this state with only one receiver working so that the signal receiver and decoder do not work every cycle and consume power.

R / W: A signal that selects between read (R) and write (W) data transfer modes.

Add_0 ~ Add_7: A signal that time-divides the address bits A0 to A39.

IO0 ~ IO8 or IO0 ~ IO15: Data input / output.

DTX_A, DTX_B: Internal status signal that informs the outside of the data transfer status of the two buffer registers inside the chip.

According to the embodiment described above, it is possible to obtain a large-capacity file memory capable of high-speed data transfer while ensuring data reliability by ECC.

<figref num="1">It is a figure which shows the cell array block and its base control circuit configuration by embodiment.</figref><figref num="2">It is a figure which shows the cell array equivalent circuit in the cell array block.</figref><figref num="3">It is also a figure which shows the sense system.</figref><figref num="4">It is also a figure which shows the structure of the current detection type sense amplifier.</figref><figref num="5">It is a figure which shows the operation waveform of the same sense amplifier.</figref><figref num="6">Similarly, it is a figure which shows the structure of the write control circuit.</figref><figref num="7">It is a figure which shows the signal level of a write control circuit.</figref><figref num="8">It is a figure which shows the relationship between a 4Mb cell array block, a sense amplifier, and a data bus.</figref><figref num="9">It is a figure which shows the block display of 4Mb × 4.</figref><figref num="10">It is a figure which shows the cell array unit display of 68Mb / mat.</figref><figref num="11">It is a figure which shows the file memory configuration example 1 of (8Gb + 832Mb) × m.</figref><figref num="12">It is a figure which shows the file memory configuration example 2 of (8Gb + 832Mb) × m.</figref><figref num="13">It is a figure which shows the block display of the memory configuration example 1 and 2.</figref><figref num="14">It is a figure which shows the structure of the encoding part ENC of the ECC circuit.</figref><figref num="15">It is a figure which shows the structure of the decoding part DEC of the ECC circuit.</figref><figref num="16">It is a figure for demonstrating the write data transfer in the case of × 8IO.</figref><figref num="17">It is a figure for demonstrating the write data transfer in the case of × 16 IO.</figref><figref num="18">It is a figure for demonstrating the read data transfer in the case of × 8IO.</figref><figref num="19">It is a figure for demonstrating read data transfer in the case of × 16 IO.</figref><figref num="20">It is a figure for demonstrating the external data transfer and the internal data transfer by two buffer registers.</figref><figref num="21">It is a figure for demonstrating the interleaving operation of burst data transfer.</figref><figref num="22">Similarly, it is a figure which shows the timing specification of burst data transfer.</figref><figref num="23">It is a figure for demonstrating the interrupt operation of a burst cycle.</figref><figref num="24">It is a figure for demonstrating the forced termination operation of a burst cycle.</figref><figref num="25">It is a figure which shows the example which performs the write data transfer which does not pass through an ECC circuit after a read burst.</figref><figref num="26">It is a figure which shows the example which performs the write data transfer through an ECC circuit after a write burst.</figref><figref num="27">It is a figure for demonstrating the timing specification of interrupt processing in a burst cycle.</figref><figref num="28">It is a figure which shows the interleaving operation of a burst cycle by two buffer registers.</figref><figref num="29">It is a figure which shows the example which set the refresh burst cycle in the sequence of burst transfer.</figref><figref num="30">It is a figure which shows the example which set the mask write burst cycle in the sequence of burst transfer.</figref><figref num="31">It is a figure which shows the example which set the iterative write cycle in the sequence of burst transfer.</figref><figref num="32">It is a figure which shows the example which set the repeated read cycle in the sequence of burst transfer.</figref><figref num="33">It is a figure for demonstrating the timing rule of command and burst address acquisition.</figref><figref num="34">Similarly, it is a figure which shows the data bit setting example of a command.</figref>

Code description

1 ... cell array block, 2 ... control circuit, 31 ... sense amplifier, 32 ... write control circuit, 100 ... memory core, 111 ... buffer register, 112 ... ECC circuit, ENC ... encoding part, DEC ... decoding part, REG1-REG4 ... buffer register, REG-A, REG-B ... 2 system buffer register. Write data transfer through Wdt ... ECC, Wdt^*... write data transfer without ECC, Rdt ... read data transfer.