Dynamic type semiconductor memory device and refresh control method thereof

The present invention relates to a dynamic semiconductor storage circuit, and more particularly to a dynamic semiconductor storage device including a self-refresh circuit and a refresh control method thereof.

As is well known in the art, dynamic random access memory (hereinafter also abbreviated as "DRAM") is a dynamic in which one memory cell is composed of one switching transistor and one data storage capacitor. It is a type semiconductor storage device. Therefore, DRAM is widely used as a semiconductor memory suitable for high integration in a semiconductor substrate.

In DRAM, since the data signal is held by the capacitor, a "refresh operation" of periodically amplifying and rewriting the data signal stored in the capacitor is required. In other words, the charge charged in the capacitor is gradually discharged by the leak current, and eventually the data disappears. Therefore, it is necessary to rewrite (refresh) the memory cell at regular intervals. This fixed time is called the "refresh interval".

In DRAM, the address of a memory cell is indicated by row × column, and when specifying an address via the address bus, the address signal is not sent at once. The address and the column address are sent separately. At this time, the control signal when passing the row address bit to the DRAM via the address bus is called the row address strobe signal / RAS, and the control signal when passing the column address bit to the DRAM is called the column address strobe signal. Called signal / CAS. Then, normally, the row address strobe signal / RAS is output with respect to the output of the row address, and the column address strobe signal / CAS is output with respect to the output of the column address.

In the refresh operation, for example, by outputting the row address strobe signal / RAS while issuing the column address strobe signal / CAS to the DRAM, the memory cell of the row (word line) selected (specified) by the row address is output. Everything is refreshed at the same time. At the timing as described above, each time the column address strobe signal / CAS and the row address strobe signal / RAS are input, the rows are moved in sequence and the memory cells are refreshed in order.

Normally, this one-cycle refresh operation is performed during the period from when the row address (refresh address) for refresh is given from the refresh address counter to when the row address strobe signal / RAS is started up. This period is called the "refresh period". Normally, the refresh period is followed by the normal operating period. The period obtained by adding the normal operation period to the refresh period is the above-mentioned "refresh interval".

Most DRAMs in recent years have a function capable of performing a refresh operation without requiring external refresh control. This function is commonly referred to as the "self-refresh function". That is, the self-refresh function employs a method in which not only the refresh address but also the row address strobe signal / RAS is generated inside the chip. This method is called a "self-refresh method". In the self-refresh method, a refresh request signal is automatically generated by an internal refresh timer, and a RAS signal is automatically generated inside the chip to refresh the memory cell array.

The refresh cycle corresponds to the length of time from one row refreshed once in the memory cell array to the next refreshed time.

Various dynamic semiconductor storage devices having such a self-refresh function have been conventionally proposed.

For example, Japanese Patent Application Laid-Open No. 6-124587 (Patent Document 1) discloses an improved dynamic random access memory (DRAM) having a self-refresh mode. In the DRAM disclosed in Patent Document 1, centralized refresh using a refresh clock signal having a short period is performed for all rows in the memory cell array during the first period and / or the last period of the self-refresh period. ..

Further, Japanese Patent Application Laid-Open No. 9-7367 (Patent Document 2) discloses a DRAM refresh device capable of shortening the time required for the transition from the auto mode to the self mode and reducing the power consumption.

On the other hand, in order to operate a semiconductor integrated circuit at a low voltage, there is known a technique for reducing an increase in standby current (standby current) that occurs when a transistor threshold value is lowered. Such a technique is called a Sub threshold current reduction circuit (SCRC) in this field. Such SCRC is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-210976 (Patent Document 3).

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 6-124587 (Fig. 1, paragraphs 0029 to 0030)</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 9-7367 (Figs. 1-3, paragraphs 0014, 0024)</text></patcit><patcit num="3"><text>Japanese Patent Application Laid-Open No. 5-210976</text></patcit>

<p> Conventionally, DRAMs used in mobile devices such as mobile phones have been required to have a low-voltage operating power supply circuit and low power consumption. Under such a requirement, a sub-threshold current reduction circuit (SCRC) was applied to the command decoder, row system control bottleneck, column system control circuit, etc. in order to reduce the current during standby. However, among these circuits, the row system control circuit also operates during the self-refresh operation. Then, the row control circuit activates the word lines one by one in order to refresh the memory cells connected to the word lines. At this time, in the conventional DRAM, the row system control circuit is activated from the standby state, activates only one word line to refresh the memory cell, and the row system control circuit is put into the standby state each time the refresh is completed. I was back. Therefore, the standby time (standby time) and the active time (operation time) are periodically switched each time the word line is refreshed line by line. As a result, in the conventional DRAM, the self-refresh current is rather reduced due to the charging / discharging of the sub-threshold current reduction circuit (SCRC) by switching the activation (operating state) / deactivating (standby state) of the row system control circuit. There was a problem that it could not be done.</p>

<p> The dynamic semiconductor storage device of the present invention is a dynamic semiconductor storage device provided with a line system control circuit to which a sub-threshold current reduction circuit having a standby state and an active state is applied, and releases the standby state in the self-refresh mode. To activate the row control circuit, continuously activate N word lines (N is an integer of 2 or more) to refresh the memory cell, and then put it in the standby state to deactivate the row control circuit. It has a control circuit.</p><p> The refresh control method of the present invention is a refresh control method for controlling the self-refresh operation of a dynamic semiconductor storage device provided with a line system control circuit to which a sub-threshold current reduction circuit having a standby state and an active state is applied. In the refresh mode, the standby state is released, the line system control circuit is activated, N word lines (N is an integer of 2 or more) are continuously activated to refresh the memory cell, and then the standby state is performed. To deactivate the line control circuit.</p>

<p> At the time of self-refresh, N word lines are refreshed together and then the standby mode is entered, so the number of switching between active and standby is reduced, and the line system control circuit (sub-threshold current reduction in standby state) is reduced. The number of charge / discharge cycles due to switching (applying the circuit) can be reduced, and the current consumption can be reduced.</p>

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

A dynamic semiconductor storage device to which the refresh control method according to the present invention is applied will be described with reference to FIG. The dynamic semiconductor storage device includes a DRAM circuit 100 and an SCRC control signal generation circuit 200.

The DRAM circuit 100 includes a memory cell array 110, a command + row system control circuit SCRC area 120, and a column system control circuit SCRC area 130.

The SCRC driver of the command + row system control circuit SCRC area 120 and the column system control circuit SCRC area 130 is controlled by the SCRC control signal generation circuit 200. The details of the self-refresh control circuit 201 included in the SCRC control signal generation circuit 200 will be described later with reference to FIG.

The sub-threshold current reduction circuit (SCRC) is used in the command + row system control circuit SCRC area 120 and the column system control circuit SCRC area 130 other than the SCRC control signal generation circuit 200. The details of the sub-threshold current reduction circuit (SCRC) will be described in detail later with reference to FIG.

The SCRC control signal generation circuit 200 receives the row activation signal ROW ACTIVE and the self-refresh period signal SELFREF described later from the command + row system control circuit SCRC region 120. In response to the row activation signal ROW ACTIVE and the self-refresh period signal SELFREF, the SCRC control signal generation circuit 200 sends a command + row system control circuit SCRC control signal and a column system control circuit SCRC control signal to the command + row system, respectively. It is sent to the control circuit SCRC area 120 and the column system control circuit SCRC area 130.

The SCRC control signal generation circuit 200 includes a self-refresh control circuit (reference numeral 201 in FIG. 4) of the DRAM circuit 100 as described later.

Since the column system control circuit SCRC area 130 does not operate during self-refresh, the column system control circuit SCRC area 130 is in the standby state by the column system control circuit SCRC control signal (ACTIVE-C and its inverting signal / ACTIVE-C). It has become. On the other hand, during self-refresh, the command + line system control circuit SCRC area 120 operates, so the command + line system control circuit SCRC area 120 is turned on / off by the command + line system control circuit SCRC control signal as described later. To do.

The memory cell array 110 is a memory cell in which a large number of memory cells for storing 1 bit are arranged in a matrix in the row direction and the column direction. The row address (X address) or column address (Y address) to be accessed by the memory cell array 110 is specified by the address signal supplied from the outside.

The command + line system control circuit SCRC area 120 includes a command decoder 122, an X address buffer (line address buffer) 124, an X decoder / sense amplifier driver (line decoder / sense amplifier driver) 126, and a line control circuit 128. It is configured to prepare. In this command + line system control circuit SCRC area 120, the above-mentioned part excluding the command decoder 122 is referred to as a line system control circuit.

The command decoder 122 determines the control command defined based on the combination pattern of the command + line system control circuit SCRC control signal, and sends a control signal corresponding to the operation content to each part. The command + line system control circuit SCRC control signal will be described later with reference to FIG.

The X address buffer (row address buffer) 124 holds the X address (row address) specified by the address signal. The X decoder / sense amplifier driver (row decoder / sense amplifier driver) 126 is controlled by the row control circuit 128 that receives the output control signal of the command decoder 122, etc., and corresponds to the specified X address (row address). Select the word line and activate the sense amplifier located on the column side.

The column system control circuit SCRC area 130 includes a Y address buffer (column address buffer) 132 and a Y decoder (column decorator) 134.

The Y address buffer (column address buffer) 132 holds the Y address (column address) specified by the address signal. The Y decorator (column decoder) 134 selects one bit line corresponding to the specified Y address (column address).

FIG. 2 is a circuit diagram showing an example of a sub-threshold current reduction circuit (SCRC) 300 used in the peripheral circuit of the DRAM circuit 100 shown in FIG.

The sub-threshold current reduction circuit (SCRC) 300 shown in FIG. 2 describes its basic configuration and operation, and does not necessarily include the above command + row system control circuit SCRC region 120 and column system control circuit. The configuration of the SCRC region 130 is not limited to the configuration shown in FIG.

The illustrated sub-threshold current reduction circuit (SCRC) 300 comprises a logic portion 310, a first switch circuit 320, and a second switch circuit 330.

The first switch circuit 320 and the second switch circuit 330 are collectively referred to as an SCRC driver.

The sub-threshold current reduction circuit (SCRC) 300 is connected to the first and second power lines VDD and VSS and the first and second separate line VDD2 and VSS2. The first power supply voltage VDD supplied to the first power supply line VDD is higher than the second power supply voltage VSS supplied to the second power supply line VSS. That is, VDD&gt; VSS. Further, the first power supply voltage VDD is supplied to the first separate power supply line VDD2 via the first switch circuit 320, and the first power supply voltage VDD2 is supplied to the second separate power supply line VSS2 via the second switch circuit 330. The configuration is such that the second power supply voltage VSS is supplied. Then, during standby (standby), the first switch circuit 320 and the second switch circuit 330 (SCRC driver) are turned off, and the first power supply voltage VDD is supplied to the first separate power supply line VDD2. And the supply of the second power supply voltage VSS to the second separate power supply line VSS2 is cut off.

The logic portion 310 in the figure is a circuit in which the first to fourth CMOS inverter circuits 311, 312, 313, and 314 are connected in cascade. Each of the first to fourth CMOS inverter circuits 311 to 314 is composed of a p-channel MOS transistor and an n-channel MOS transistor. A Low Vth transistor (low threshold transistor) is used as the transistor constituting the logic portion 310.

The first switch circuit 320 is connected between the first power supply line VDD and the first separate power supply line VDD2. The first switch circuit 320 in the figure is composed of a p-channel MOS transistor. An inverting active signal / ACTIVE is supplied to the gate of this p-channel MOS transistor. The symbol / represents an inverted signal, and / ACTIVE means that it is an inverted signal of ACTIVE. The source of this p-channel MOS transistor is connected to the first power line VDD, and the drain is connected to the first separate power line VDD2.

The second switch circuit 330 is connected between the second power supply line VSS and the second separate power supply line VSS2. The second switch circuit 330 in the figure is composed of an n-channel MOS transistor. An active signal ACTIVE is supplied to the gate of this n-channel MOS transistor. The source of this n-channel MOS transistor is connected to the second power line VSS, and the drain is connected to the second separate power line VSS2.

In the sub-threshold current reduction circuit (SCRC) 300 shown in FIG. 2, the first switch circuit 320 is composed of p-channel MOS transistors, and the second switch circuit 330 is composed of n-channel MOS transistors. , The first switch circuit 320 may be composed of an n-channel MOS transistor, and the second switch circuit 330 may be composed of a p-channel MOS transistor. In this case, the active signal ACTIVE is supplied to the first switch circuit 320, and the inverting active signal / ACTIVE is supplied to the second switch circuit 330.

Normal Vth transistors (normal threshold transistors) are used as the transistors that make up the first and second switch circuits 320 and 330 (SCRC driver).

As shown in FIG. 2, the source of the p-channel MOS transistors of the first and third CMOS inverter circuits 311 and 313 is connected to the first power line VDD, and the second and fourth CMOS inverter circuits 312 and 314. The source of the p-channel MOS transistor is connected to the first separate power supply line VDD2. Further, the source of the n-channel MOS transistors of the second and fourth CMOS inverter circuits 312 and 314 is connected to the second power supply line VSS, and the n-channel MOS transistors of the first and third CMOS inverter circuits 311 and 313 are connected. The source is connected to the second separate power line VSS2.

It is assumed that each node of the logic portion 310 is as shown in FIG. 2 during standby (standby). That is, the input of the first CMOS inverter circuit 311 is at the logical "L" level, the output of the first CMOS inverter circuit 311 (the input of the second CMOS inverter circuit 312) is at the logical "H" level, and the second CMOS inverter. The output of circuit 312 (input of the third CMOS inverter circuit 313) is at the logical L level, and the output of the third CMOS inverter circuit 313 (input of the fourth CMOS inverter circuit 314) is at the logical H level. And.

In this case, as shown in FIG. 2, transistors to be turned off alternate. In the Low Vth transistor, leakage current flows even if Vgs = 0V. As a result, the transistor to be turned off is not completely turned off, and the standby current flows.

Therefore, in the sub-threshold current reduction circuit (SCRC) 300, as shown in Fig. 2, the source of the transistor to be turned off is connected to another power supply line (VDD2, VSS2), and this is cut off by the Normal Vth transistor during standby. As a result, the standby current is reduced.

By the way, at the time of activation (active), it is necessary to connect the first separate power supply line VDD2 to the first power supply line VDD and the second separate power line VSS2 to the second power supply line VSS. Therefore, the inverting active signal / ACTIVE is set to the logical "L" level, the first switch circuit 320 connecting the first power line VDD and the first separate power line VDD2 is turned on, and the active signal ACTIVE is logically set to "L". At the H level, the second switch circuit 330 that connects the second power line VSS and the second separate power line VSS2 is turned on.

If the size of the transistors of the first and second switch circuits 320 and 330 (SCRC driver) is not about 1/3 of the total size of the transistors of the logic part 310 of Low Vth, due to the voltage drop in this transistor part. , The operation of the logic part 310 becomes slow. Therefore, if switching between standby (standby) and active (active) occurs frequently, the charge / discharge current of the gate of this transistor becomes large, and by applying the sub-threshold current reduction circuit (SCRC) 300, On the contrary, there is a problem that the current consumption increases.

In particular, as the first power supply voltage VDD supplied to the first power supply line VDD becomes lower, the level of the active signal ACTIVE at the time of activation is boosted by a pump above the first power supply voltage VDD, or at the time of activation. The level of the inverted active signal / ACTIVE is generated by the pump so that the voltage is negative from the second power supply voltage VSS supplied to the second power supply line VSS. In such cases, this problem becomes even more pronounced as extra power is required to generate the high or negative voltage.

In order to reduce the self-refresh current of the DRAM circuit 100, consider the case where the sub-threshold current reduction circuit (SCRC) 300 as shown in FIG. 2 is applied to the DRAM circuit 100.

Here, in order to facilitate the understanding of the present invention, the operation of the conventional DRAM circuit will be described with reference to FIG. In FIG. 3, CKE is an externally input clock enable signal, WL is a timing signal output by the row control circuit to select the word line of the memory cell array 110 according to the row address, and ACTIVE is the sub-threshold current reduction. An active signal that activates circuit (SCRC) 300.

As described above, in the conventional DRAM circuit that requires low power consumption, as shown in FIG. 3, the self-refresh operation is periodically performed line by word line. Therefore, the sub-threshold current reduction circuit (SCRC) 300 also periodically switches between the standby state and the active state by the active signal ACTIVE that changes line by word. As a result, in the conventional DRAM circuit, there is a problem that the self-refresh current cannot be reduced by the charge / discharge current at the time of switching of the line system control circuit to which the sub-threshold current reduction circuit (SCRC) 300 is applied.

Next, the self-refresh control circuit 201 that constitutes a part of the SCRC control signal generation circuit 200 shown in FIG. 1 will be described with reference to FIG. FIG. 4 is a circuit diagram showing a configuration example of the self-refresh control circuit 201, and has a characteristic configuration of the present invention.

As described above, the command + line system control circuit SCRC control signal is supplied to the command decorator 122 of the DRAM circuit 100. Specifically, this command + line system control circuit SCRC control signal is the active signal ACTIVE of FIG. 5 and its inverting active signal / ACTIVE, which will be described later. Further, the command decoder 122 has a clock signal CLK, a clock enable signal CKE, a chip select signal / CS, a row address strobe signal / RAS, and a column address stroll signal / CAS (hereinafter, these signals are commanded). (Sometimes collectively referred to as a signal) is supplied. The command decorator 122 determines a command based on the current state (mode) of the dynamic semiconductor storage device and these command signals input from the outside, and sends a corresponding control signal to each unit. When the current state (mode) of the dynamic semiconductor storage device is in the standby state and the command decoder 122 determines that the above command signal input is a self-refresh command, the command decoder 122 determines the command result signal ACT and the self-refresh period signal SELFREF. And output. The self-refresh period signal SELFREF is a signal indicating a self-refresh period.

The command decoder 122 and the line control circuit 128 in FIG. 4 form a part of the command + line system control circuit SCRC area 120 in FIG. Then, the row control circuit 128 receives an external signal and responds to the decoding result signal ACT sent from the command decoder 122 or the internal activation signal ACTS generated by the self-refresh control circuit 201, as will be described later. Outputs the row activation signal ROW ACTIVE and the refresh end signal REFEND. The row activation signal ROW ACTIVE is a signal that becomes a logic H during the refresh operation. The refresh end signal REFEND is a signal output when the DRAM circuit 100 finishes refreshing one line and can accept the next refresh command.

As will be described in detail later, the self-refresh control circuit 201 activates the command + line system control circuit SCRC region 120 configured by applying the sub-memory current reduction circuit (SCRC) 300 (Fig. 2) in the self-refresh mode. After refreshing the memory cells by continuously activating N word lines (N is an integer of 2 or more), the command + line system control circuit SCRC area 120 to which the sub-threshold current reduction circuit (SCRC) 300 is applied. It is equipped with a refresh control means for deactivating. In the illustrated example, N is equal to 4.

More specifically, the self-refresh control circuit 201 includes a first inverter circuit 202, a long-cycle timer 204, a first OR circuit 206, a counter 208, an AND circuit 210, and a second OR circuit 212. It is configured to include a second inverter circuit 214.

When the self-refresh command is input while the current state (mode) of the dynamic semiconductor storage device is in the standby state, the self-refresh period signal SELREF is output as logic H from the command decoder 122. That is, during the self-refresh mode period, the self-refresh period signal SELFREF becomes logical H. Then, the first inverter circuit 202 inverts the self-refresh period signal SELFREF and outputs the inverted self-refresh period signal / SELFREF.

The long-period timer 204 responds to the inverting self-refresh period signal / SELFREF and generates a refresh request signal REFREQ at regular intervals after the self-refresh mode entry. That is, the long-period timer 204 functions as a timer for determining the period of the active signal ACTIVE and its inverted active signal / ACTIVE in the self-refresh mode.

The first OR circuit 206 takes the logical sum of the refresh request signal REFREQ and the refresh end signal REFEND, and outputs the refresh logical sum signal REFOR as the first logical sum result signal.

The counter 208 is activated by the inverting self-refresh period signal / SELFREF, from the time when the refresh request signal REFREQ becomes the logical H level until the refresh end signal REFEND is input three times ((N-1) times). , It is a circuit that outputs the selection signal SELFP which becomes the logic "H". In other words, the counter 208 counts the refresh logical sum signal REFOR while the self-refresh period signal SELREF indicates the self-refresh period, and the logical H level selection signal SELFP until the count value reaches N. Is output.

That is, the combination of the first OR circuit 206 and the counter 208 counts the refresh request signal REFREQ and the refresh end signal REFEND while the self-refresh period signal SELREF indicates the self-refresh period, and the count value is calculated. It works as a selection signal output circuit that outputs the selection signal SELFP until it reaches N.

The AND circuit 210 takes the logical product of the selection signal SELFP and the refresh logical sum signal REFOR, and generates the internal activation signal ACTS as the logical product result signal. That is, while the selection signal SELFP is logic H, the AND circuit 210 generates an internal activation signal ACTS by the refresh request signal REFREQ or the refresh end signal REFEND. The row control circuit 128 is controlled by this internal activation signal ACTS, and the DRAM circuit 100 refreshes N rows (4 rows).

That is, the AND circuit 210 has an internal activity for continuously activating N word lines to refresh the memory cell by the refresh request signal REFREQ and the refresh end signal REFEND while the selection signal SELFP is being output. It works as an internal activation circuit generated as a conversion signal ACTS.

The second OR circuit 212 ORs the row activation signal ROW ACTIVE, the inverted self-refresh period signal / SELFREF, and the selection signal SELFP, and outputs the active signal ACTIVE as the second logical sum result signal. Therefore, the inverted self-refresh period signal / SELFREF or the selection signal SELFP or the row activation signal ROWACTIVE is at the logical H level, and the active signal ACTIVE is at the logical H level. This active signal ACTIVE is one of the switching signals for switching between standby and active by turning on / off the SCRC driver of the sub-threshold current reduction circuit (SCRC) 300 (Fig. 2) in the DRAM circuit 100. That is, the active signal ACTIVE is a switching signal for switching between the standby state and the active state of the command + line system control circuit SCRC area 120 shown in FIG.

The second inverter circuit 214 inverts the active signal ACTIVE and outputs the inverted active signal / ACTIVE as a complementary signal of the switching signal.

Therefore, the combination of the first inverter circuit 202, the second OR circuit 212, and the second inverter circuit 214 is sub-thresholded in response to the self-refresh period signal SELFREF, the row activation signal ROW ACTIVE, and the selection signal SELF P. Command + line system control circuit to which the current reduction circuit (SCRC) 300 (Fig. 2) is applied Operates as a standby / active switching circuit that generates a switching signal to switch between standby and active in the SCRC area 120.

As described above, the combination of the first inverter circuit 202, the first OR circuit 206, the counter 208, the AND circuit 210, the second OR circuit 212, and the second inverter circuit 214 is in the self-refresh mode. Command + line system control circuit to which the sub-threshold current reduction circuit (SCRC) (Fig. 2) is applied. After activating the SCRC area 120 and activating N word lines continuously to refresh the memory cell, the sub-threshold current Command + line system control circuit to which the reduction circuit (SCRC) (Fig. 2) is applied. It works as a refresh control means to deactivate the SCRC area 120. This refresh control means deactivates the command + line control circuit SCRC region 120 to which the subthreshold current reduction circuit (SCRC) (Fig. 2) is applied in synchronization with the end of selection of N consecutively selected word lines. To become.

In the illustrated example, the number N of word lines continuously selected is 4, but this number N can be easily changed to an arbitrary value by changing the configuration (count number) of the counter 208. Can be done.

FIG. 5 is a time chart showing an example of the operation of the self-refresh control circuit 201 shown in FIG. It can be seen that the internal activation signal ACTS is pulsed four times while the active signal ACTIVE is at the logical H level. That is, four lines are refreshed for one active.

FIG. 6 is a time chart for explaining the operation of the DRAM circuit 100. In FIG. 6, CKE is a clock enable signal input from the outside, WL is a timing signal output by the row control circuit 128 to select the word line of the memory cell array 110 according to the row address, and ACTIVE is the SCRC driver. This is an active signal that activates the command + line system control circuit SCRC region 120, which is turned on and the sub-threshold current reduction circuit (SCRC) 300 (Fig. 2) is applied. The timing signal WL corresponds to the internal activation signal ACTS shown in FIG.

As is clear from FIG. 6, in the present embodiment, four lines are refreshed and then switched during standby. As a result, the number of switching of the active signal ACTIVE is reduced, and the charge / discharge current (self-refresh current) of the sub-threshold current reduction circuit (SCRC) 300 (Fig. 2) applied to the command + line system control circuit SCRC area 120 itself is reduced. , Reduced to 1/4 of the conventional one.

In general, when the clock enable signal CKE reaches the logical H level, the self-refresh control circuit exits the self-refresh operation. Even in the self-refresh control circuit 201 of the present embodiment, the self-refresh operation is not continued until the 4-line refresh is completed, but is refreshed when the clock enable signal CKE reaches the logical H level. When the line refresh is finished, the self-refresh operation is exited. Therefore, since the timing at which the self-refresh control circuit 201 exits the self-refresh operation is the same as that of the conventional product, the usability seen from the outside is the same as that of the conventional product.

Next, the optimum number of self-refresh lines (word lines) N will be described. In N-line units, the frequency of switching between activation / deactivation of the command + line system control circuit SCRC area 120 to which the sub-threshold current reduction circuit (SCRC) 300 (Fig. 2) is applied is 1 / N. The control current (a part of the self-refresh current) of the command + line system control circuit SCRC area 120 to which the sub-threshold current reduction circuit (SCRC) 300 (Fig. 2) is applied becomes 1 / N. Therefore, the larger N is, the more advantageous it is. However, at the time of self-refresh, there are some customers who reduce the power consumption by narrowing down the capacity of power supply ICs such as mobile phones. Therefore, if the burst length (the period during which the active signal ACTIVE is at the logical H level) is too long, the capacity of the power supply becomes insufficient, and there is a possibility of malfunction in refresh. Under these circumstances, the optimum number of self-refresh lines (word lines) N is about 4 to 8.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and changes can be made without departing from the gist (subject) of the present invention. Is. For example, in the above-described embodiment, the self-refresh control circuit 201 is composed of a long-period timer 204, a selection signal output circuit, a standby / active switching circuit, and an internal activation circuit, but is limited to such a configuration. Of course, it is not done.

<figref num="1">It is a block diagram which shows the structure of the dynamic type semiconductor storage device to which the refresh control method which concerns on this invention is applied.</figref><figref num="2">This circuit shows an example of a sub-threshold current reduction circuit (SCRC) used in the peripheral circuit of the DRAM circuit shown in FIG.</figref><figref num="3">It is a time chart for explaining the operation of the conventional DRAM circuit.</figref><figref num="4">It is a circuit diagram which shows the structural example of the self-refresh control circuit included in the SCRC control signal generation circuit shown in FIG.</figref><figref num="5">It is a time chart which shows an example of the operation of the self-refresh control circuit included in the SCRC control signal generation circuit shown in FIG.</figref><figref num="6">It is a time chart for demonstrating the operation of the DRAM circuit by one Embodiment of this invention.</figref>

Code description

100 RDAM circuit 110 memory cell array 120 Command + line system control circuit SCRC area 122 Command Decorator 124 X address buffer (row address buffer) 126 X Decoder / Sense Amplifier Driver (Line Decoder / Sense Amplifier Driver) 128 line control circuit 130 column system control circuit SCRC area 132 Y address buffer (column address buffer) 134 Y Decorator (Column Decoder) 200 SCRC control signal generation circuit 201 Self-refresh control circuit 202 1st inverter circuit 204 Long-period timer 206 1st OR circuit 208 counter 210 AND circuit 212 Second OR circuit 214 Second inverter circuit 300 Sub-threshold current reduction circuit (SCRC) 310 logic part 311 ~ 314 CMOS inverter circuit 320 1st switch circuit 330 Second switch circuit